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1	/*
2	* i386 CPUID, CPU class, definitions, models
3	*
4	* Copyright (c) 2003 Fabrice Bellard
5	*
6	* This library is free software; you can redistribute it and/or
7	* modify it under the terms of the GNU Lesser General Public
8	* License as published by the Free Software Foundation; either
9	* version 2.1 of the License, or (at your option) any later version.
10	*
11	* This library is distributed in the hope that it will be useful,
12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14	* Lesser General Public License for more details.
15	*
16	* You should have received a copy of the GNU Lesser General Public
17	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
18	*/
19
20	#include "qemu/osdep.h"
21	#include "qemu/units.h"
22	#include "qemu/cutils.h"
23	#include "qemu/qemu-print.h"
24	#include "qemu/hw-version.h"
25	#include "cpu.h"
26	#include "tcg/helper-tcg.h"
27	#include "exec/translation-block.h"
28	#include "system/hvf.h"
29	#include "system/mshv.h"
30	#include "system/whpx.h"
31	#include "whpx/whpx-i386.h"
32	#include "hvf/hvf-i386.h"
33	#include "kvm/kvm_i386.h"
34	#include "kvm/tdx.h"
35	#include "sev.h"
36	#include "qapi/error.h"
37	#include "qemu/error-report.h"
38	#include "qapi/qapi-visit-machine.h"
39	#include "standard-headers/asm-x86/kvm_para.h"
40	#include "hw/core/qdev-properties.h"
41	#include "hw/i386/topology.h"
42	#include "exec/watchpoint.h"
43	#ifndef CONFIG_USER_ONLY
44	#include "confidential-guest.h"
45	#include "monitor/hmp.h"
46	#include "system/reset.h"
47	#include "qapi/qapi-commands-machine.h"
48	#include "system/address-spaces.h"
49	#include "hw/core/boards.h"
50	#include "hw/i386/sgx-epc.h"
51	#endif
52	#include "system/qtest.h"
53	#include "tcg/tcg-cpu.h"
54
55	#include "disas/capstone.h"
56	#include "cpu-internal.h"
57
58	static void x86_cpu_realizefn(DeviceState dev, Error *errp);
59	static void x86_cpu_get_supported_cpuid(uint32_t func, uint32_t index,
60	uint32_t eax, uint32_t ebx,
61	uint32_t ecx, uint32_t edx);
62
63	/* Helpers for building CPUID[2] descriptors: */
64
65	struct CPUID2CacheDescriptorInfo {
66	enum CacheType type;
67	int level;
68	int size;
69	int line_size;
70	int associativity;
71	};
72
73	/*
74	* Known CPUID 2 cache descriptors.
75	* TLB, prefetch and sectored cache related descriptors are not included.
76	* From Intel SDM Volume 2A, CPUID instruction
77	*/
78	struct CPUID2CacheDescriptorInfo cpuid2_cache_descriptors[] = {
79	[0x06] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 8 * KiB,
80	.associativity = 4, .line_size = 32, },
81	[0x08] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 16 * KiB,
82	.associativity = 4, .line_size = 32, },
83	[0x09] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB,
84	.associativity = 4, .line_size = 64, },
85	[0x0A] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB,
86	.associativity = 2, .line_size = 32, },
87	[0x0C] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
88	.associativity = 4, .line_size = 32, },
89	[0x0D] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
90	.associativity = 4, .line_size = 64, },
91	[0x0E] = { .level = 1, .type = DATA_CACHE, .size = 24 * KiB,
92	.associativity = 6, .line_size = 64, },
93	[0x1D] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB,
94	.associativity = 2, .line_size = 64, },
95	[0x21] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
96	.associativity = 8, .line_size = 64, },
97	/*
98	* lines per sector is not supported cpuid2_cache_descriptor(),
99	* so descriptors 0x22, 0x23 are not included
100	*/
101	[0x24] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
102	.associativity = 16, .line_size = 64, },
103	/*
104	* lines per sector is not supported cpuid2_cache_descriptor(),
105	* so descriptors 0x25, 0x29 are not included
106	*/
107	[0x2C] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB,
108	.associativity = 8, .line_size = 64, },
109	[0x30] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB,
110	.associativity = 8, .line_size = 64, },
111	/*
112	* Newer Intel CPUs (having the cores without L3, e.g., Intel MTL, ARL)
113	* use CPUID 0x4 leaf to describe cache topology, by encoding CPUID 0x2
114	* leaf with 0xFF. For older CPUs (without 0x4 leaf), it's also valid
115	* to just ignore L3's code if there's no L3.
116	*
117	* This already covers all the cases in QEMU, so code 0x40 is not
118	* included.
119	*/
120	[0x41] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB,
121	.associativity = 4, .line_size = 32, },
122	[0x42] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
123	.associativity = 4, .line_size = 32, },
124	[0x43] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
125	.associativity = 4, .line_size = 32, },
126	[0x44] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
127	.associativity = 4, .line_size = 32, },
128	[0x45] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
129	.associativity = 4, .line_size = 32, },
130	[0x46] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB,
131	.associativity = 4, .line_size = 64, },
132	[0x47] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
133	.associativity = 8, .line_size = 64, },
134	[0x48] = { .level = 2, .type = UNIFIED_CACHE, .size = 3 * MiB,
135	.associativity = 12, .line_size = 64, },
136	/*
137	* Descriptor 0x49 has 2 cases:
138	* - 2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size.
139	* - 3rd-level cache: 4MB, 16-way set associative, 64-byte line size
140	* (Intel Xeon processor MP, Family 0FH, Model 06H).
141	*
142	* When it represents L3, then it depends on CPU family/model. Fortunately,
143	* the legacy cache/CPU models don't have such special L3. So, just add it
144	* to represent the general L2 case.
145	*/
146	[0x49] = { .level = 2, .type = UNIFIED_CACHE, .size = 4 * MiB,
147	.associativity = 16, .line_size = 64, },
148	[0x4A] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB,
149	.associativity = 12, .line_size = 64, },
150	[0x4B] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
151	.associativity = 16, .line_size = 64, },
152	[0x4C] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB,
153	.associativity = 12, .line_size = 64, },
154	[0x4D] = { .level = 3, .type = UNIFIED_CACHE, .size = 16 * MiB,
155	.associativity = 16, .line_size = 64, },
156	[0x4E] = { .level = 2, .type = UNIFIED_CACHE, .size = 6 * MiB,
157	.associativity = 24, .line_size = 64, },
158	[0x60] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
159	.associativity = 8, .line_size = 64, },
160	[0x66] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB,
161	.associativity = 4, .line_size = 64, },
162	[0x67] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
163	.associativity = 4, .line_size = 64, },
164	[0x68] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB,
165	.associativity = 4, .line_size = 64, },
166	[0x78] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
167	.associativity = 4, .line_size = 64, },
168	/*
169	* lines per sector is not supported cpuid2_cache_descriptor(),
170	* so descriptors 0x79, 0x7A, 0x7B, 0x7C are not included.
171	*/
172	[0x7D] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
173	.associativity = 8, .line_size = 64, },
174	[0x7F] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
175	.associativity = 2, .line_size = 64, },
176	[0x80] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
177	.associativity = 8, .line_size = 64, },
178	[0x82] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
179	.associativity = 8, .line_size = 32, },
180	[0x83] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
181	.associativity = 8, .line_size = 32, },
182	[0x84] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
183	.associativity = 8, .line_size = 32, },
184	[0x85] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
185	.associativity = 8, .line_size = 32, },
186	[0x86] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
187	.associativity = 4, .line_size = 64, },
188	[0x87] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
189	.associativity = 8, .line_size = 64, },
190	[0xD0] = { .level = 3, .type = UNIFIED_CACHE, .size = 512 * KiB,
191	.associativity = 4, .line_size = 64, },
192	[0xD1] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB,
193	.associativity = 4, .line_size = 64, },
194	[0xD2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB,
195	.associativity = 4, .line_size = 64, },
196	[0xD6] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB,
197	.associativity = 8, .line_size = 64, },
198	[0xD7] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB,
199	.associativity = 8, .line_size = 64, },
200	[0xD8] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB,
201	.associativity = 8, .line_size = 64, },
202	[0xDC] = { .level = 3, .type = UNIFIED_CACHE, .size = 1.5 * MiB,
203	.associativity = 12, .line_size = 64, },
204	[0xDD] = { .level = 3, .type = UNIFIED_CACHE, .size = 3 * MiB,
205	.associativity = 12, .line_size = 64, },
206	[0xDE] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB,
207	.associativity = 12, .line_size = 64, },
208	[0xE2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB,
209	.associativity = 16, .line_size = 64, },
210	[0xE3] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB,
211	.associativity = 16, .line_size = 64, },
212	[0xE4] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
213	.associativity = 16, .line_size = 64, },
214	[0xEA] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB,
215	.associativity = 24, .line_size = 64, },
216	[0xEB] = { .level = 3, .type = UNIFIED_CACHE, .size = 18 * MiB,
217	.associativity = 24, .line_size = 64, },
218	[0xEC] = { .level = 3, .type = UNIFIED_CACHE, .size = 24 * MiB,
219	.associativity = 24, .line_size = 64, },
220	};
221
222	/*
223	* "CPUID leaf 2 does not report cache descriptor information,
224	* use CPUID leaf 4 to query cache parameters"
225	*/
226	#define CACHE_DESCRIPTOR_UNAVAILABLE 0xFF
227
228	/*
229	* Return a CPUID 2 cache descriptor for a given cache.
230	* If no known descriptor is found, return CACHE_DESCRIPTOR_UNAVAILABLE
231	*/
232	static uint8_t cpuid2_cache_descriptor(CPUCacheInfo cache, bool unmacthed)
233	{
234	int i;
235
236	assert(cache->size > 0);
237	assert(cache->level > 0);
238	assert(cache->line_size > 0);
239	assert(cache->associativity > 0);
240	for (i = 0; i < ARRAY_SIZE(cpuid2_cache_descriptors); i++) {
241	struct CPUID2CacheDescriptorInfo *d = &cpuid2_cache_descriptors[i];
242	if (d->level == cache->level && d->type == cache->type &&
243	d->size == cache->size && d->line_size == cache->line_size &&
244	d->associativity == cache->associativity) {
245	return i;
246	}
247	}
248
249	*unmacthed \|= true;
250	return CACHE_DESCRIPTOR_UNAVAILABLE;
251	}
252
253	static const CPUCaches legacy_intel_cpuid2_cache_info;
254
255	/* Encode cache info for CPUID[2] */
256	static void encode_cache_cpuid2(X86CPU *cpu,
257	const CPUCaches *caches,
258	uint32_t eax, uint32_t ebx,
259	uint32_t ecx, uint32_t edx)
260	{
261	CPUX86State *env = &cpu->env;
262	int l1d, l1i, l2, l3;
263	bool unmatched = false;
264
265	eax = 1; / Number of CPUID[EAX=2] calls required */
266	ebx = ecx = *edx = 0;
267
268	l1d = cpuid2_cache_descriptor(caches->l1d_cache, &unmatched);
269	l1i = cpuid2_cache_descriptor(caches->l1i_cache, &unmatched);
270	l2 = cpuid2_cache_descriptor(caches->l2_cache, &unmatched);
271	l3 = cpuid2_cache_descriptor(caches->l3_cache, &unmatched);
272
273	if (!cpu->consistent_cache \|\|
274	(env->cpuid_min_level < 0x4 && !unmatched)) {
275	/*
276	* Though SDM defines code 0x40 for cases with no L2 or L3. It's
277	* also valid to just ignore l3's code if there's no l2.
278	*/
279	if (cpu->enable_l3_cache) {
280	*ecx = l3;
281	}
282	*edx = (l1d << 16) \| (l1i << 8) \| l2;
283	} else {
284	*ecx = 0;
285	*edx = CACHE_DESCRIPTOR_UNAVAILABLE;
286	}
287	}
288
289	/* CPUID Leaf 4 constants: */
290
291	/* EAX: */
292	#define CACHE_TYPE_D 1
293	#define CACHE_TYPE_I 2
294	#define CACHE_TYPE_UNIFIED 3
295
296	#define CACHE_LEVEL(l) (l << 5)
297
298	#define CACHE_SELF_INIT_LEVEL (1 << 8)
299
300	/* EDX: */
301	#define CACHE_NO_INVD_SHARING (1 << 0)
302	#define CACHE_INCLUSIVE (1 << 1)
303	#define CACHE_COMPLEX_IDX (1 << 2)
304
305	/* Encode CacheType for CPUID[4].EAX */
306	#define CACHE_TYPE(t) (((t) == DATA_CACHE) ? CACHE_TYPE_D : \
307	((t) == INSTRUCTION_CACHE) ? CACHE_TYPE_I : \
308	((t) == UNIFIED_CACHE) ? CACHE_TYPE_UNIFIED : \
309	0 /* Invalid value */)
310
311	static uint32_t apicid_offset_by_topo_level(X86CPUTopoInfo *topo_info,
312	enum CpuTopologyLevel topo_level)
313	{
314	switch (topo_level) {
315	case CPU_TOPOLOGY_LEVEL_THREAD:
316	return 0;
317	case CPU_TOPOLOGY_LEVEL_CORE:
318	return apicid_core_offset(topo_info);
319	case CPU_TOPOLOGY_LEVEL_MODULE:
320	return apicid_module_offset(topo_info);
321	case CPU_TOPOLOGY_LEVEL_DIE:
322	return apicid_die_offset(topo_info);
323	case CPU_TOPOLOGY_LEVEL_SOCKET:
324	return apicid_pkg_offset(topo_info);
325	default:
326	g_assert_not_reached();
327	}
328	return 0;
329	}
330
331	static uint32_t max_thread_ids_for_cache(X86CPUTopoInfo *topo_info,
332	enum CpuTopologyLevel share_level)
333	{
334	return (1 << apicid_offset_by_topo_level(topo_info, share_level)) - 1;
335	}
336
337	static uint32_t max_core_ids_in_package(X86CPUTopoInfo *topo_info)
338	{
339	uint32_t num_cores = 1 << (apicid_pkg_offset(topo_info) -
340	apicid_core_offset(topo_info));
341	return num_cores - 1;
342	}
343
344	/* Encode cache info for CPUID[4] */
345	static void encode_cache_cpuid4(CPUCacheInfo *cache,
346	X86CPUTopoInfo *topo_info,
347	uint32_t eax, uint32_t ebx,
348	uint32_t ecx, uint32_t edx)
349	{
350	assert(cache->size == cache->line_size * cache->associativity *
351	cache->partitions * cache->sets);
352
353	/*
354	* The following fields have bit-width limitations, so consider the
355	* maximum values to avoid overflow:
356	* Bits 25-14: maximum 4095.
357	* Bits 31-26: maximum 63.
358	*/
359	*eax = CACHE_TYPE(cache->type) \|
360	CACHE_LEVEL(cache->level) \|
361	(cache->self_init ? CACHE_SELF_INIT_LEVEL : 0) \|
362	(MIN(max_core_ids_in_package(topo_info), 63) << 26) \|
363	(MIN(max_thread_ids_for_cache(topo_info, cache->share_level), 4095) << 14);
364
365	assert(cache->line_size > 0);
366	assert(cache->partitions > 0);
367	assert(cache->associativity > 0);
368	/* We don't implement fully-associative caches */
369	assert(cache->associativity < cache->sets);
370	*ebx = (cache->line_size - 1) \|
371	((cache->partitions - 1) << 12) \|
372	((cache->associativity - 1) << 22);
373
374	assert(cache->sets > 0);
375	*ecx = cache->sets - 1;
376
377	*edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) \|
378	(cache->inclusive ? CACHE_INCLUSIVE : 0) \|
379	(cache->complex_indexing ? CACHE_COMPLEX_IDX : 0);
380	}
381
382	static uint32_t num_threads_by_topo_level(X86CPUTopoInfo *topo_info,
383	enum CpuTopologyLevel topo_level)
384	{
385	switch (topo_level) {
386	case CPU_TOPOLOGY_LEVEL_THREAD:
387	return 1;
388	case CPU_TOPOLOGY_LEVEL_CORE:
389	return topo_info->threads_per_core;
390	case CPU_TOPOLOGY_LEVEL_MODULE:
391	return x86_threads_per_module(topo_info);
392	case CPU_TOPOLOGY_LEVEL_DIE:
393	return x86_threads_per_die(topo_info);
394	case CPU_TOPOLOGY_LEVEL_SOCKET:
395	return x86_threads_per_pkg(topo_info);
396	default:
397	g_assert_not_reached();
398	}
399	return 0;
400	}
401
402	static uint32_t cpuid1f_topo_type(enum CpuTopologyLevel topo_level)
403	{
404	switch (topo_level) {
405	case CPU_TOPOLOGY_LEVEL_INVALID:
406	return CPUID_1F_ECX_TOPO_LEVEL_INVALID;
407	case CPU_TOPOLOGY_LEVEL_THREAD:
408	return CPUID_1F_ECX_TOPO_LEVEL_SMT;
409	case CPU_TOPOLOGY_LEVEL_CORE:
410	return CPUID_1F_ECX_TOPO_LEVEL_CORE;
411	case CPU_TOPOLOGY_LEVEL_MODULE:
412	return CPUID_1F_ECX_TOPO_LEVEL_MODULE;
413	case CPU_TOPOLOGY_LEVEL_DIE:
414	return CPUID_1F_ECX_TOPO_LEVEL_DIE;
415	default:
416	/* Other types are not supported in QEMU. */
417	g_assert_not_reached();
418	}
419	return 0;
420	}
421
422	static void encode_topo_cpuid1f(CPUX86State *env, uint32_t count,
423	X86CPUTopoInfo *topo_info,
424	uint32_t eax, uint32_t ebx,
425	uint32_t ecx, uint32_t edx)
426	{
427	X86CPU *cpu = env_archcpu(env);
428	unsigned long level, base_level, next_level;
429	uint32_t num_threads_next_level, offset_next_level;
430
431	assert(count <= CPU_TOPOLOGY_LEVEL_SOCKET);
432
433	/*
434	* Find the No.(count + 1) topology level in avail_cpu_topo bitmap.
435	* The search starts from bit 0 (CPU_TOPOLOGY_LEVEL_THREAD).
436	*/
437	level = CPU_TOPOLOGY_LEVEL_THREAD;
438	base_level = level;
439	for (int i = 0; i <= count; i++) {
440	level = find_next_bit(env->avail_cpu_topo,
441	CPU_TOPOLOGY_LEVEL_SOCKET,
442	base_level);
443
444	/*
445	* CPUID[0x1f] doesn't explicitly encode the package level,
446	* and it just encodes the invalid level (all fields are 0)
447	* into the last subleaf of 0x1f.
448	*/
449	if (level == CPU_TOPOLOGY_LEVEL_SOCKET) {
450	level = CPU_TOPOLOGY_LEVEL_INVALID;
451	break;
452	}
453	/* Search the next level. */
454	base_level = level + 1;
455	}
456
457	if (level == CPU_TOPOLOGY_LEVEL_INVALID) {
458	num_threads_next_level = 0;
459	offset_next_level = 0;
460	} else {
461	next_level = find_next_bit(env->avail_cpu_topo,
462	CPU_TOPOLOGY_LEVEL_SOCKET,
463	level + 1);
464	num_threads_next_level = num_threads_by_topo_level(topo_info,
465	next_level);
466	offset_next_level = apicid_offset_by_topo_level(topo_info,
467	next_level);
468	}
469
470	*eax = offset_next_level;
471	/* The count (bits 15-00) doesn't need to be reliable. */
472	*ebx = num_threads_next_level & 0xffff;
473	*ecx = (count & 0xff) \| (cpuid1f_topo_type(level) << 8);
474	*edx = cpu->apic_id;
475
476	assert(!(*eax & ~0x1f));
477	}
478
479	/* Encode cache info for CPUID[0x80000005].ECX or CPUID[0x80000005].EDX */
480	static uint32_t encode_cache_cpuid80000005(CPUCacheInfo *cache)
481	{
482	assert(cache->size % 1024 == 0);
483	assert(cache->associativity > 0);
484	assert(cache->line_size > 0);
485	return ((cache->size / 1024) << 24) \| (cache->associativity << 16) \|
486	(cache->lines_per_tag << 8) \| (cache->line_size);
487	}
488
489	#define ASSOC_FULL 0xFF
490
491	/* x86 associativity encoding used on CPUID Leaf 0x80000006: */
492	#define X86_ENC_ASSOC(a) (a <= 1 ? a : \
493	a == 2 ? 0x2 : \
494	a == 4 ? 0x4 : \
495	a == 8 ? 0x6 : \
496	a == 16 ? 0x8 : \
497	a == 32 ? 0xA : \
498	a == 48 ? 0xB : \
499	a == 64 ? 0xC : \
500	a == 96 ? 0xD : \
501	a == 128 ? 0xE : \
502	a == ASSOC_FULL ? 0xF : \
503	0 /* invalid value */)
504
505	/*
506	* Encode cache info for CPUID[0x80000006].ECX and CPUID[0x80000006].EDX
507	* @l3 can be NULL.
508	*/
509	static void encode_cache_cpuid80000006(CPUCacheInfo *l2,
510	CPUCacheInfo *l3,
511	uint32_t ecx, uint32_t edx)
512	{
513	assert(l2->size % 1024 == 0);
514	assert(l2->associativity > 0);
515	assert(l2->line_size > 0);
516	*ecx = ((l2->size / 1024) << 16) \|
517	(X86_ENC_ASSOC(l2->associativity) << 12) \|
518	(l2->lines_per_tag << 8) \| (l2->line_size);
519
520	/* For Intel, EDX is reserved. */
521	if (l3) {
522	assert(l3->size % (512 * 1024) == 0);
523	assert(l3->associativity > 0);
524	assert(l3->line_size > 0);
525	edx = ((l3->size / (512 1024)) << 18) \|
526	(X86_ENC_ASSOC(l3->associativity) << 12) \|
527	(l3->lines_per_tag << 8) \| (l3->line_size);
528	} else {
529	*edx = 0;
530	}
531	}
532
533	/* Encode cache info for CPUID[8000001D] */
534	static void encode_cache_cpuid8000001d(CPUCacheInfo *cache,
535	X86CPUTopoInfo *topo_info,
536	uint32_t eax, uint32_t ebx,
537	uint32_t ecx, uint32_t edx)
538	{
539	assert(cache->size == cache->line_size * cache->associativity *
540	cache->partitions * cache->sets);
541
542	*eax = CACHE_TYPE(cache->type) \| CACHE_LEVEL(cache->level) \|
543	(cache->self_init ? CACHE_SELF_INIT_LEVEL : 0);
544	/* Bits 25:14 - NumSharingCache: maximum 4095. */
545	*eax \|= MIN(max_thread_ids_for_cache(topo_info, cache->share_level), 4095) << 14;
546
547	assert(cache->line_size > 0);
548	assert(cache->partitions > 0);
549	assert(cache->associativity > 0);
550	/* We don't implement fully-associative caches */
551	assert(cache->associativity < cache->sets);
552	*ebx = (cache->line_size - 1) \|
553	((cache->partitions - 1) << 12) \|
554	((cache->associativity - 1) << 22);
555
556	assert(cache->sets > 0);
557	*ecx = cache->sets - 1;
558
559	*edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) \|
560	(cache->inclusive ? CACHE_INCLUSIVE : 0) \|
561	(cache->complex_indexing ? CACHE_COMPLEX_IDX : 0);
562	}
563
564	/* Encode cache info for CPUID[8000001E] */
565	static void encode_topo_cpuid8000001e(X86CPU cpu, X86CPUTopoInfo topo_info,
566	uint32_t eax, uint32_t ebx,
567	uint32_t ecx, uint32_t edx)
568	{
569	X86CPUTopoIDs topo_ids;
570
571	x86_topo_ids_from_apicid(cpu->apic_id, topo_info, &topo_ids);
572
573	*eax = cpu->apic_id;
574
575	/*
576	* CPUID_Fn8000001E_EBX [Core Identifiers] (CoreId)
577	* Read-only. Reset: 0000_XXXXh.
578	* See Core::X86::Cpuid::ExtApicId.
579	* Core::X86::Cpuid::CoreId_lthree[1:0]_core[3:0]_thread[1:0];
580	* Bits Description
581	* 31:16 Reserved.
582	* 15:8 ThreadsPerCore: threads per core. Read-only. Reset: XXh.
583	* The number of threads per core is ThreadsPerCore+1.
584	* 7:0 CoreId: core ID. Read-only. Reset: XXh.
585	*
586	* NOTE: CoreId is already part of apic_id. Just use it. We can
587	* use all the 8 bits to represent the core_id here.
588	*/
589	*ebx = ((topo_info->threads_per_core - 1) << 8) \| (topo_ids.core_id & 0xFF);
590
591	/*
592	* CPUID_Fn8000001E_ECX [Node Identifiers] (NodeId)
593	* Read-only. Reset: 0000_0XXXh.
594	* Core::X86::Cpuid::NodeId_lthree[1:0]_core[3:0]_thread[1:0];
595	* Bits Description
596	* 31:11 Reserved.
597	* 10:8 NodesPerProcessor: Node per processor. Read-only. Reset: XXXb.
598	* ValidValues:
599	* Value Description
600	* 0h 1 node per processor.
601	* 7h-1h Reserved.
602	* 7:0 NodeId: Node ID. Read-only. Reset: XXh.
603	*
604	* NOTE: Hardware reserves 3 bits for number of nodes per processor.
605	* But users can create more nodes than the actual hardware can
606	* support. To genaralize we can use all the upper 8 bits for nodes.
607	* NodeId is combination of node and socket_id which is already decoded
608	* in apic_id. Just use it by shifting.
609	*/
610	if (cpu->legacy_multi_node) {
611	*ecx = ((topo_info->dies_per_pkg - 1) << 8) \|
612	((cpu->apic_id >> apicid_die_offset(topo_info)) & 0xFF);
613	} else {
614	*ecx = (cpu->apic_id >> apicid_pkg_offset(topo_info)) & 0xFF;
615	}
616
617	*edx = 0;
618	}
619
620	/*
621	* Definitions of the hardcoded cache entries we expose:
622	* These are legacy cache values. If there is a need to change any
623	* of these values please use builtin_x86_defs
624	*/
625	static const CPUCaches legacy_amd_cache_info = {
626	.l1d_cache = &(CPUCacheInfo) {
627	.type = DATA_CACHE,
628	.level = 1,
629	.size = 64 * KiB,
630	.self_init = 1,
631	.line_size = 64,
632	.associativity = 2,
633	.sets = 512,
634	.partitions = 1,
635	.lines_per_tag = 1,
636	.no_invd_sharing = true,
637	.share_level = CPU_TOPOLOGY_LEVEL_CORE,
638	},
639	.l1i_cache = &(CPUCacheInfo) {
640	.type = INSTRUCTION_CACHE,
641	.level = 1,
642	.size = 64 * KiB,
643	.self_init = 1,
644	.line_size = 64,
645	.associativity = 2,
646	.sets = 512,
647	.partitions = 1,
648	.lines_per_tag = 1,
649	.no_invd_sharing = true,
650	.share_level = CPU_TOPOLOGY_LEVEL_CORE,
651	},
652	.l2_cache = &(CPUCacheInfo) {
653	.type = UNIFIED_CACHE,
654	.level = 2,
655	.size = 512 * KiB,
656	.line_size = 64,
657	.lines_per_tag = 1,
658	.associativity = 16,
659	.sets = 512,
660	.partitions = 1,
661	.share_level = CPU_TOPOLOGY_LEVEL_CORE,
662	},
663	.l3_cache = &(CPUCacheInfo) {
664	.type = UNIFIED_CACHE,
665	.level = 3,
666	.size = 16 * MiB,
667	.line_size = 64,
668	.associativity = 16,
669	.sets = 16384,
670	.partitions = 1,
671	.lines_per_tag = 1,
672	.self_init = true,
673	.inclusive = true,
674	.complex_indexing = true,
675	.share_level = CPU_TOPOLOGY_LEVEL_DIE,
676	},
677	};
678
679	/*
680	* Only used for the CPU models with CPUID level < 4.
681	* These CPUs (CPUID level < 4) only use CPUID leaf 2 to present
682	* cache information.
683	*
684	* Note: This cache model is just a default one, and is not
685	* guaranteed to match real hardwares.
686	*/
687	static const CPUCaches legacy_intel_cpuid2_cache_info = {
688	.l1d_cache = &(CPUCacheInfo) {
689	.type = DATA_CACHE,
690	.level = 1,
691	.size = 32 * KiB,
692	.self_init = 1,
693	.line_size = 64,
694	.associativity = 8,
695	.sets = 64,
696	.partitions = 1,
697	.no_invd_sharing = true,
698	.share_level = CPU_TOPOLOGY_LEVEL_CORE,
699	},
700	.l1i_cache = &(CPUCacheInfo) {
701	.type = INSTRUCTION_CACHE,
702	.level = 1,
703	.size = 32 * KiB,
704	.self_init = 1,
705	.line_size = 64,
706	.associativity = 8,
707	.sets = 64,
708	.partitions = 1,
709	.no_invd_sharing = true,
710	.share_level = CPU_TOPOLOGY_LEVEL_CORE,
711	},
712	.l2_cache = &(CPUCacheInfo) {
713	.type = UNIFIED_CACHE,
714	.level = 2,
715	.size = 2 * MiB,
716	.self_init = 1,
717	.line_size = 64,
718	.associativity = 8,
719	.sets = 4096,
720	.partitions = 1,
721	.no_invd_sharing = true,
722	.share_level = CPU_TOPOLOGY_LEVEL_CORE,
723	},
724	.l3_cache = &(CPUCacheInfo) {
725	.type = UNIFIED_CACHE,
726	.level = 3,
727	.size = 16 * MiB,
728	.line_size = 64,
729	.associativity = 16,
730	.sets = 16384,
731	.partitions = 1,
732	.lines_per_tag = 1,
733	.self_init = true,
734	.inclusive = true,
735	.complex_indexing = true,
736	.share_level = CPU_TOPOLOGY_LEVEL_DIE,
737	},
738	};
739
740	static const CPUCaches legacy_intel_cache_info = {
741	.l1d_cache = &(CPUCacheInfo) {
742	.type = DATA_CACHE,
743	.level = 1,
744	.size = 32 * KiB,
745	.self_init = 1,
746	.line_size = 64,
747	.associativity = 8,
748	.sets = 64,
749	.partitions = 1,
750	.no_invd_sharing = true,
751	.share_level = CPU_TOPOLOGY_LEVEL_CORE,
752	},
753	.l1i_cache = &(CPUCacheInfo) {
754	.type = INSTRUCTION_CACHE,
755	.level = 1,
756	.size = 32 * KiB,
757	.self_init = 1,
758	.line_size = 64,
759	.associativity = 8,
760	.sets = 64,
761	.partitions = 1,
762	.no_invd_sharing = true,
763	.share_level = CPU_TOPOLOGY_LEVEL_CORE,
764	},
765	.l2_cache = &(CPUCacheInfo) {
766	.type = UNIFIED_CACHE,
767	.level = 2,
768	.size = 4 * MiB,
769	.self_init = 1,
770	.line_size = 64,
771	.associativity = 16,
772	.sets = 4096,
773	.partitions = 1,
774	.no_invd_sharing = true,
775	.share_level = CPU_TOPOLOGY_LEVEL_CORE,
776	},
777	.l3_cache = &(CPUCacheInfo) {
778	.type = UNIFIED_CACHE,
779	.level = 3,
780	.size = 16 * MiB,
781	.line_size = 64,
782	.associativity = 16,
783	.sets = 16384,
784	.partitions = 1,
785	.lines_per_tag = 1,
786	.self_init = true,
787	.inclusive = true,
788	.complex_indexing = true,
789	.share_level = CPU_TOPOLOGY_LEVEL_DIE,
790	},
791	};
792
793	/* TLB definitions: */
794
795	#define L1_DTLB_2M_ASSOC 1
796	#define L1_DTLB_2M_ENTRIES 255
797	#define L1_DTLB_4K_ASSOC 1
798	#define L1_DTLB_4K_ENTRIES 255
799
800	#define L1_ITLB_2M_ASSOC 1
801	#define L1_ITLB_2M_ENTRIES 255
802	#define L1_ITLB_4K_ASSOC 1
803	#define L1_ITLB_4K_ENTRIES 255
804
805	#define L2_DTLB_2M_ASSOC 0 /* disabled */
806	#define L2_DTLB_2M_ENTRIES 0 /* disabled */
807	#define L2_DTLB_4K_ASSOC 4
808	#define L2_DTLB_4K_ENTRIES 512
809
810	#define L2_ITLB_2M_ASSOC 0 /* disabled */
811	#define L2_ITLB_2M_ENTRIES 0 /* disabled */
812	#define L2_ITLB_4K_ASSOC 4
813	#define L2_ITLB_4K_ENTRIES 512
814
815	/* CPUID Leaf 0x14 constants: */
816	#define INTEL_PT_MAX_SUBLEAF 0x1
817	/*
818	* bit[00]: IA32_RTIT_CTL.CR3 filter can be set to 1 and IA32_RTIT_CR3_MATCH
819	* MSR can be accessed;
820	* bit[01]: Support Configurable PSB and Cycle-Accurate Mode;
821	* bit[02]: Support IP Filtering, TraceStop filtering, and preservation
822	* of Intel PT MSRs across warm reset;
823	* bit[03]: Support MTC timing packet and suppression of COFI-based packets;
824	*/
825	#define INTEL_PT_MINIMAL_EBX 0xf
826	/*
827	* bit[00]: Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1 and
828	* IA32_RTIT_OUTPUT_BASE and IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be
829	* accessed;
830	* bit[01]: ToPA tables can hold any number of output entries, up to the
831	* maximum allowed by the MaskOrTableOffset field of
832	* IA32_RTIT_OUTPUT_MASK_PTRS;
833	* bit[02]: Support Single-Range Output scheme;
834	*/
835	#define INTEL_PT_MINIMAL_ECX 0x7
836	/* generated packets which contain IP payloads have LIP values */
837	#define INTEL_PT_IP_LIP (1 << 31)
838	#define INTEL_PT_ADDR_RANGES_NUM 0x2 /* Number of configurable address ranges */
839	#define INTEL_PT_ADDR_RANGES_NUM_MASK 0x3
840	#define INTEL_PT_MTC_BITMAP (0x0249 << 16) /* Support ART(0,3,6,9) */
841	#define INTEL_PT_CYCLE_BITMAP 0x1fff /* Support 0,2^(0~11) */
842	#define INTEL_PT_PSB_BITMAP (0x003f << 16) /* Support 2K,4K,8K,16K,32K,64K */
843
844	/* CPUID Leaf 0x1D constants: */
845	#define INTEL_AMX_TILE_MAX_SUBLEAF 0x1
846	#define INTEL_AMX_TOTAL_TILE_BYTES 0x2000
847	#define INTEL_AMX_BYTES_PER_TILE 0x400
848	#define INTEL_AMX_BYTES_PER_ROW 0x40
849	#define INTEL_AMX_TILE_MAX_NAMES 0x8
850	#define INTEL_AMX_TILE_MAX_ROWS 0x10
851
852	/* CPUID Leaf 0x1E constants: */
853	#define INTEL_AMX_TMUL_MAX_K 0x10
854	#define INTEL_AMX_TMUL_MAX_N 0x40
855
856	void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
857	uint32_t vendor2, uint32_t vendor3)
858	{
859	int i;
860	for (i = 0; i < 4; i++) {
861	dst[i] = vendor1 >> (8 * i);
862	dst[i + 4] = vendor2 >> (8 * i);
863	dst[i + 8] = vendor3 >> (8 * i);
864	}
865	dst[CPUID_VENDOR_SZ] = '\0';
866	}
867
868	#define I486_FEATURES (CPUID_FP87 \| CPUID_VME \| CPUID_PSE)
869	#define PENTIUM_FEATURES (I486_FEATURES \| CPUID_DE \| CPUID_TSC \| \
870	CPUID_MSR \| CPUID_MCE \| CPUID_CX8 \| CPUID_MMX \| CPUID_APIC)
871	#define PENTIUM2_FEATURES (PENTIUM_FEATURES \| CPUID_PAE \| CPUID_SEP \| \
872	CPUID_MTRR \| CPUID_PGE \| CPUID_MCA \| CPUID_CMOV \| CPUID_PAT \| \
873	CPUID_PSE36 \| CPUID_FXSR)
874	#define PENTIUM3_FEATURES (PENTIUM2_FEATURES \| CPUID_SSE)
875	#define PPRO_FEATURES (CPUID_FP87 \| CPUID_DE \| CPUID_PSE \| CPUID_TSC \| \
876	CPUID_MSR \| CPUID_MCE \| CPUID_CX8 \| CPUID_PGE \| CPUID_CMOV \| \
877	CPUID_PAT \| CPUID_FXSR \| CPUID_MMX \| CPUID_SSE \| CPUID_SSE2 \| \
878	CPUID_PAE \| CPUID_SEP \| CPUID_APIC)
879
880	#define TCG_FEATURES (CPUID_FP87 \| CPUID_PSE \| CPUID_TSC \| CPUID_MSR \| \
881	CPUID_PAE \| CPUID_MCE \| CPUID_CX8 \| CPUID_APIC \| CPUID_SEP \| \
882	CPUID_MTRR \| CPUID_PGE \| CPUID_MCA \| CPUID_CMOV \| CPUID_PAT \| \
883	CPUID_PSE36 \| CPUID_CLFLUSH \| CPUID_ACPI \| CPUID_MMX \| \
884	CPUID_FXSR \| CPUID_SSE \| CPUID_SSE2 \| CPUID_SS \| CPUID_DE \| \
885	CPUID_HT)
886	/* partly implemented:
887	CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */
888	/* missing:
889	CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_TM, CPUID_PBE */
890
891	/*
892	* Kernel-only features that can be shown to usermode programs even if
893	* they aren't actually supported by TCG, because qemu-user only runs
894	* in CPL=3; remove them if they are ever implemented for system emulation.
895	*/
896	#if defined CONFIG_USER_ONLY
897	#define CPUID_EXT_KERNEL_FEATURES \
898	(CPUID_EXT_PCID \| CPUID_EXT_TSC_DEADLINE_TIMER)
899	#else
900	#define CPUID_EXT_KERNEL_FEATURES 0
901	#endif
902	#define TCG_EXT_FEATURES (CPUID_EXT_SSE3 \| CPUID_EXT_PCLMULQDQ \| \
903	CPUID_EXT_MONITOR \| CPUID_EXT_SSSE3 \| CPUID_EXT_CX16 \| \
904	CPUID_EXT_SSE41 \| CPUID_EXT_SSE42 \| CPUID_EXT_POPCNT \| \
905	CPUID_EXT_XSAVE \| /* CPUID_EXT_OSXSAVE is dynamic */ \
906	CPUID_EXT_MOVBE \| CPUID_EXT_AES \| CPUID_EXT_HYPERVISOR \| \
907	CPUID_EXT_RDRAND \| CPUID_EXT_AVX \| CPUID_EXT_F16C \| \
908	CPUID_EXT_FMA \| CPUID_EXT_X2APIC \| CPUID_EXT_KERNEL_FEATURES)
909	/* missing:
910	CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
911	CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID,
912	CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
913	CPUID_EXT_TSC_DEADLINE_TIMER
914	*/
915
916	#ifdef TARGET_X86_64
917	#define TCG_EXT2_X86_64_FEATURES CPUID_EXT2_LM
918	#else
919	#define TCG_EXT2_X86_64_FEATURES 0
920	#endif
921
922	/*
923	* CPUID_*_KERNEL_FEATURES denotes bits and features that are not usable
924	* in usermode or by 32-bit programs. Those are added to supported
925	* TCG features unconditionally in user-mode emulation mode. This may
926	* indeed seem strange or incorrect, but it works because code running
927	* under usermode emulation cannot access them.
928	*
929	* Even for long mode, qemu-i386 is not running "a userspace program on a
930	* 32-bit CPU"; it's running "a userspace program with a 32-bit code segment"
931	* and therefore using the 32-bit ABI; the CPU itself might be 64-bit
932	* but again the difference is only visible in kernel mode.
933	*/
934	#if defined CONFIG_LINUX_USER
935	#define CPUID_EXT2_KERNEL_FEATURES (CPUID_EXT2_LM \| CPUID_EXT2_FFXSR)
936	#elif defined CONFIG_USER_ONLY
937	/* FIXME: Long mode not yet supported for i386 bsd-user */
938	#define CPUID_EXT2_KERNEL_FEATURES CPUID_EXT2_FFXSR
939	#else
940	#define CPUID_EXT2_KERNEL_FEATURES 0
941	#endif
942
943	#define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) \| \
944	CPUID_EXT2_NX \| CPUID_EXT2_MMXEXT \| CPUID_EXT2_RDTSCP \| \
945	CPUID_EXT2_3DNOW \| CPUID_EXT2_3DNOWEXT \| CPUID_EXT2_PDPE1GB \| \
946	CPUID_EXT2_SYSCALL \| TCG_EXT2_X86_64_FEATURES \| \
947	CPUID_EXT2_KERNEL_FEATURES)
948
949	#if defined CONFIG_USER_ONLY
950	#define CPUID_EXT3_KERNEL_FEATURES CPUID_EXT3_OSVW
951	#else
952	#define CPUID_EXT3_KERNEL_FEATURES 0
953	#endif
954
955	#define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM \| CPUID_EXT3_SVM \| \
956	CPUID_EXT3_CR8LEG \| CPUID_EXT3_ABM \| CPUID_EXT3_SSE4A \| \
957	CPUID_EXT3_3DNOWPREFETCH \| CPUID_EXT3_KERNEL_FEATURES \| \
958	CPUID_EXT3_CMP_LEG)
959
960	#define TCG_EXT4_FEATURES 0
961
962	#if defined CONFIG_USER_ONLY
963	#define CPUID_SVM_KERNEL_FEATURES (CPUID_SVM_NRIPSAVE \| CPUID_SVM_VNMI)
964	#else
965	#define CPUID_SVM_KERNEL_FEATURES 0
966	#endif
967	#define TCG_SVM_FEATURES (CPUID_SVM_NPT \| CPUID_SVM_VGIF \| \
968	CPUID_SVM_SVME_ADDR_CHK \| CPUID_SVM_KERNEL_FEATURES)
969
970	#define TCG_KVM_FEATURES 0
971
972	#if defined CONFIG_USER_ONLY
973	#define CPUID_7_0_EBX_KERNEL_FEATURES CPUID_7_0_EBX_INVPCID
974	#else
975	#define CPUID_7_0_EBX_KERNEL_FEATURES 0
976	#endif
977	#define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP \| CPUID_7_0_EBX_SMAP \| \
978	CPUID_7_0_EBX_BMI1 \| CPUID_7_0_EBX_BMI2 \| CPUID_7_0_EBX_ADX \| \
979	CPUID_7_0_EBX_CLFLUSHOPT \| \
980	CPUID_7_0_EBX_CLWB \| CPUID_7_0_EBX_MPX \| CPUID_7_0_EBX_FSGSBASE \| \
981	CPUID_7_0_EBX_ERMS \| CPUID_7_0_EBX_AVX2 \| CPUID_7_0_EBX_RDSEED \| \
982	CPUID_7_0_EBX_SHA_NI \| CPUID_7_0_EBX_KERNEL_FEATURES)
983	/* missing:
984	CPUID_7_0_EBX_HLE
985	CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM */
986
987	#if !defined CONFIG_USER_ONLY \|\| defined CONFIG_LINUX
988	#define TCG_7_0_ECX_RDPID CPUID_7_0_ECX_RDPID
989	#else
990	#define TCG_7_0_ECX_RDPID 0
991	#endif
992	#define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_UMIP \| CPUID_7_0_ECX_PKU \| \
993	/* CPUID_7_0_ECX_OSPKE is dynamic */ \
994	CPUID_7_0_ECX_LA57 \| CPUID_7_0_ECX_PKS \| CPUID_7_0_ECX_VAES \| \
995	TCG_7_0_ECX_RDPID)
996
997	#if defined CONFIG_USER_ONLY
998	#define CPUID_7_0_EDX_KERNEL_FEATURES (CPUID_7_0_EDX_SPEC_CTRL \| \
999	CPUID_7_0_EDX_ARCH_CAPABILITIES \| CPUID_7_0_EDX_SPEC_CTRL_SSBD)
1000	#else
1001	#define CPUID_7_0_EDX_KERNEL_FEATURES 0
1002	#endif
1003	#define TCG_7_0_EDX_FEATURES (CPUID_7_0_EDX_FSRM \| CPUID_7_0_EDX_KERNEL_FEATURES)
1004
1005	#define TCG_7_1_EAX_FEATURES (CPUID_7_1_EAX_FZRM \| CPUID_7_1_EAX_FSRS \| \
1006	CPUID_7_1_EAX_FSRC \| CPUID_7_1_EAX_CMPCCXADD)
1007	#define TCG_7_1_ECX_FEATURES 0
1008	#define TCG_7_1_EDX_FEATURES 0
1009	#define TCG_7_2_EDX_FEATURES 0
1010	#define TCG_APM_FEATURES 0
1011	#define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT
1012	#define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT \| CPUID_XSAVE_XGETBV1)
1013	/* missing:
1014	CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */
1015	#define TCG_14_0_ECX_FEATURES 0
1016	#define TCG_SGX_12_0_EAX_FEATURES 0
1017	#define TCG_SGX_12_0_EBX_FEATURES 0
1018	#define TCG_SGX_12_1_EAX_FEATURES 0
1019	#define TCG_24_0_EBX_FEATURES 0
1020	#define TCG_29_0_EBX_FEATURES 0
1021	#define TCG_1E_1_EAX_FEATURES 0
1022	#define TCG_24_1_ECX_FEATURES 0
1023
1024	#if defined CONFIG_USER_ONLY
1025	#define CPUID_8000_0008_EBX_KERNEL_FEATURES (CPUID_8000_0008_EBX_IBPB \| \
1026	CPUID_8000_0008_EBX_IBRS \| CPUID_8000_0008_EBX_STIBP \| \
1027	CPUID_8000_0008_EBX_STIBP_ALWAYS_ON \| CPUID_8000_0008_EBX_AMD_SSBD \| \
1028	CPUID_8000_0008_EBX_AMD_PSFD)
1029	#else
1030	#define CPUID_8000_0008_EBX_KERNEL_FEATURES 0
1031	#endif
1032
1033	#define TCG_8000_0008_EBX (CPUID_8000_0008_EBX_XSAVEERPTR \| \
1034	CPUID_8000_0008_EBX_WBNOINVD \| CPUID_8000_0008_EBX_KERNEL_FEATURES)
1035
1036	#if defined CONFIG_USER_ONLY
1037	#define CPUID_8000_0021_EAX_KERNEL_FEATURES CPUID_8000_0021_EAX_AUTO_IBRS
1038	#else
1039	#define CPUID_8000_0021_EAX_KERNEL_FEATURES 0
1040	#endif
1041
1042	#define TCG_8000_0021_EAX_FEATURES ( \
1043	CPUID_8000_0021_EAX_NO_NESTED_DATA_BP \| \
1044	CPUID_8000_0021_EAX_NULL_SEL_CLR_BASE \| \
1045	CPUID_8000_0021_EAX_KERNEL_FEATURES)
1046
1047	FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
1048	[FEAT_1_EDX] = {
1049	.type = CPUID_FEATURE_WORD,
1050	.feat_names = {
1051	"fpu", "vme", "de", "pse",
1052	"tsc", "msr", "pae", "mce",
1053	"cx8", "apic", NULL, "sep",
1054	"mtrr", "pge", "mca", "cmov",
1055	"pat", "pse36", "pn" /* Intel psn /, "clflush" / Intel clfsh */,
1056	NULL, "ds" /* Intel dts */, "acpi", "mmx",
1057	"fxsr", "sse", "sse2", "ss",
1058	"ht" /* Intel htt */, "tm", "ia64", "pbe",
1059	},
1060	.cpuid = {.eax = 1, .reg = R_EDX, },
1061	.tcg_features = TCG_FEATURES,
1062	.no_autoenable_flags = CPUID_HT,
1063	},
1064	[FEAT_1_ECX] = {
1065	.type = CPUID_FEATURE_WORD,
1066	.feat_names = {
1067	"pni" /* Intel,AMD sse3 */, "pclmulqdq", "dtes64", "monitor",
1068	"ds-cpl", "vmx", "smx", "est",
1069	"tm2", "ssse3", "cid", NULL,
1070	"fma", "cx16", "xtpr", "pdcm",
1071	NULL, "pcid", "dca", "sse4.1",
1072	"sse4.2", "x2apic", "movbe", "popcnt",
1073	"tsc-deadline", "aes", "xsave", NULL /* osxsave */,
1074	"avx", "f16c", "rdrand", "hypervisor",
1075	},
1076	.cpuid = { .eax = 1, .reg = R_ECX, },
1077	.tcg_features = TCG_EXT_FEATURES,
1078	},
1079	/* Feature names that are already defined on feature_name[] but
1080	* are set on CPUID[8000_0001].EDX on AMD CPUs don't have their
1081	* names on feat_names below. They are copied automatically
1082	* to features[FEAT_8000_0001_EDX] if and only if CPU vendor is AMD.
1083	*/
1084	[FEAT_8000_0001_EDX] = {
1085	.type = CPUID_FEATURE_WORD,
1086	.feat_names = {
1087	NULL /* fpu /, NULL / vme /, NULL / de /, NULL / pse */,
1088	NULL /* tsc /, NULL / msr /, NULL / pae /, NULL / mce */,
1089	NULL /* cx8 /, NULL / apic */, NULL, "syscall",
1090	NULL /* mtrr /, NULL / pge /, NULL / mca /, NULL / cmov */,
1091	NULL /* pat /, NULL / pse36 /, NULL, NULL / Linux mp */,
1092	"nx", NULL, "mmxext", NULL /* mmx */,
1093	NULL /* fxsr */, "fxsr-opt", "pdpe1gb", "rdtscp",
1094	NULL, "lm", "3dnowext", "3dnow",
1095	},
1096	.cpuid = { .eax = 0x80000001, .reg = R_EDX, },
1097	.tcg_features = TCG_EXT2_FEATURES,
1098	},
1099	[FEAT_8000_0001_ECX] = {
1100	.type = CPUID_FEATURE_WORD,
1101	.feat_names = {
1102	"lahf-lm", "cmp-legacy", "svm", "extapic",
1103	"cr8legacy", "abm", "sse4a", "misalignsse",
1104	"3dnowprefetch", "osvw", "ibs", "xop",
1105	"skinit", "wdt", NULL, "lwp",
1106	"fma4", "tce", NULL, "nodeid-msr",
1107	NULL, "tbm", "topoext", "perfctr-core",
1108	"perfctr-nb", NULL, NULL, NULL,
1109	NULL, NULL, NULL, NULL,
1110	},
1111	.cpuid = { .eax = 0x80000001, .reg = R_ECX, },
1112	.tcg_features = TCG_EXT3_FEATURES,
1113	/*
1114	* TOPOEXT is always allowed but can't be enabled blindly by
1115	* "-cpu host", as it requires consistent cache topology info
1116	* to be provided so it doesn't confuse guests.
1117	*/
1118	.no_autoenable_flags = CPUID_EXT3_TOPOEXT,
1119	},
1120	[FEAT_C000_0001_EDX] = {
1121	.type = CPUID_FEATURE_WORD,
1122	.feat_names = {
1123	NULL, NULL, "xstore", "xstore-en",
1124	NULL, NULL, "xcrypt", "xcrypt-en",
1125	"ace2", "ace2-en", "phe", "phe-en",
1126	"pmm", "pmm-en", NULL, NULL,
1127	NULL, NULL, NULL, NULL,
1128	NULL, NULL, NULL, NULL,
1129	NULL, NULL, NULL, NULL,
1130	NULL, NULL, NULL, NULL,
1131	},
1132	.cpuid = { .eax = 0xC0000001, .reg = R_EDX, },
1133	.tcg_features = TCG_EXT4_FEATURES,
1134	},
1135	[FEAT_KVM] = {
1136	.type = CPUID_FEATURE_WORD,
1137	.feat_names = {
1138	"kvmclock", "kvm-nopiodelay", "kvm-mmu", "kvmclock",
1139	"kvm-asyncpf", "kvm-steal-time", "kvm-pv-eoi", "kvm-pv-unhalt",
1140	NULL, "kvm-pv-tlb-flush", "kvm-asyncpf-vmexit", "kvm-pv-ipi",
1141	"kvm-poll-control", "kvm-pv-sched-yield", "kvm-asyncpf-int", "kvm-msi-ext-dest-id",
1142	NULL, NULL, NULL, NULL,
1143	NULL, NULL, NULL, NULL,
1144	"kvmclock-stable-bit", NULL, NULL, NULL,
1145	NULL, NULL, NULL, NULL,
1146	},
1147	.cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EAX, },
1148	.tcg_features = TCG_KVM_FEATURES,
1149	},
1150	[FEAT_KVM_HINTS] = {
1151	.type = CPUID_FEATURE_WORD,
1152	.feat_names = {
1153	"kvm-hint-dedicated", NULL, NULL, NULL,
1154	NULL, NULL, NULL, NULL,
1155	NULL, NULL, NULL, NULL,
1156	NULL, NULL, NULL, NULL,
1157	NULL, NULL, NULL, NULL,
1158	NULL, NULL, NULL, NULL,
1159	NULL, NULL, NULL, NULL,
1160	NULL, NULL, NULL, NULL,
1161	},
1162	.cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EDX, },
1163	.tcg_features = TCG_KVM_FEATURES,
1164	/*
1165	* KVM hints aren't auto-enabled by -cpu host, they need to be
1166	* explicitly enabled in the command-line.
1167	*/
1168	.no_autoenable_flags = ~0U,
1169	},
1170	[FEAT_SVM] = {
1171	.type = CPUID_FEATURE_WORD,
1172	.feat_names = {
1173	"npt", "lbrv", "svm-lock", "nrip-save",
1174	"tsc-scale", "vmcb-clean", "flushbyasid", "decodeassists",
1175	NULL, NULL, "pause-filter", NULL,
1176	"pfthreshold", "avic", NULL, "v-vmsave-vmload",
1177	"vgif", "gmet", NULL, NULL,
1178	NULL, NULL, NULL, NULL,
1179	NULL, "vnmi", NULL, NULL,
1180	"svme-addr-chk", NULL, NULL, NULL,
1181	},
1182	.cpuid = { .eax = 0x8000000A, .reg = R_EDX, },
1183	.tcg_features = TCG_SVM_FEATURES,
1184	},
1185	[FEAT_7_0_EBX] = {
1186	.type = CPUID_FEATURE_WORD,
1187	.feat_names = {
1188	"fsgsbase", "tsc-adjust", "sgx", "bmi1",
1189	"hle", "avx2", "fdp-excptn-only", "smep",
1190	"bmi2", "erms", "invpcid", "rtm",
1191	NULL, "zero-fcs-fds", "mpx", NULL,
1192	"avx512f", "avx512dq", "rdseed", "adx",
1193	"smap", "avx512ifma", "pcommit", "clflushopt",
1194	"clwb", "intel-pt", "avx512pf", "avx512er",
1195	"avx512cd", "sha-ni", "avx512bw", "avx512vl",
1196	},
1197	.cpuid = {
1198	.eax = 7,
1199	.needs_ecx = true, .ecx = 0,
1200	.reg = R_EBX,
1201	},
1202	.tcg_features = TCG_7_0_EBX_FEATURES,
1203	},
1204	[FEAT_7_0_ECX] = {
1205	.type = CPUID_FEATURE_WORD,
1206	.feat_names = {
1207	NULL, "avx512vbmi", "umip", "pku",
1208	NULL /* ospke */, "waitpkg", "avx512vbmi2", "cet-ss",
1209	"gfni", "vaes", "vpclmulqdq", "avx512vnni",
1210	"avx512bitalg", NULL, "avx512-vpopcntdq", NULL,
1211	"la57", NULL, NULL, NULL,
1212	NULL, NULL, "rdpid", NULL,
1213	"bus-lock-detect", "cldemote", NULL, "movdiri",
1214	"movdir64b", NULL, "sgxlc", "pks",
1215	},
1216	.cpuid = {
1217	.eax = 7,
1218	.needs_ecx = true, .ecx = 0,
1219	.reg = R_ECX,
1220	},
1221	.tcg_features = TCG_7_0_ECX_FEATURES,
1222	},
1223	[FEAT_7_0_EDX] = {
1224	.type = CPUID_FEATURE_WORD,
1225	.feat_names = {
1226	NULL, NULL, "avx512-4vnniw", "avx512-4fmaps",
1227	"fsrm", NULL, NULL, NULL,
1228	"avx512-vp2intersect", NULL, "md-clear", NULL,
1229	NULL, NULL, "serialize", NULL,
1230	"tsx-ldtrk", NULL, NULL /* pconfig */, "arch-lbr",
1231	"cet-ibt", NULL, "amx-bf16", "avx512-fp16",
1232	"amx-tile", "amx-int8", "spec-ctrl", "stibp",
1233	"flush-l1d", "arch-capabilities", "core-capability", "ssbd",
1234	},
1235	.cpuid = {
1236	.eax = 7,
1237	.needs_ecx = true, .ecx = 0,
1238	.reg = R_EDX,
1239	},
1240	.tcg_features = TCG_7_0_EDX_FEATURES,
1241	},
1242	[FEAT_7_1_EAX] = {
1243	.type = CPUID_FEATURE_WORD,
1244	.feat_names = {
1245	"sha512", "sm3", "sm4", NULL,
1246	"avx-vnni", "avx512-bf16", NULL, "cmpccxadd",
1247	NULL, NULL, "fzrm", "fsrs",
1248	"fsrc", NULL, NULL, NULL,
1249	NULL, "fred", "lkgs", "wrmsrns",
1250	NULL, "amx-fp16", NULL, "avx-ifma",
1251	NULL, NULL, "lam", NULL,
1252	NULL, NULL, NULL, "movrs",
1253	},
1254	.cpuid = {
1255	.eax = 7,
1256	.needs_ecx = true, .ecx = 1,
1257	.reg = R_EAX,
1258	},
1259	.tcg_features = TCG_7_1_EAX_FEATURES,
1260	},
1261	[FEAT_7_1_ECX] = {
1262	.type = CPUID_FEATURE_WORD,
1263	.feat_names = {
1264	NULL, NULL, NULL, NULL,
1265	NULL, "msr-imm", NULL, NULL,
1266	NULL, NULL, NULL, NULL,
1267	NULL, NULL, NULL, NULL,
1268	NULL, NULL, NULL, NULL,
1269	NULL, NULL, NULL, NULL,
1270	NULL, NULL, NULL, NULL,
1271	NULL, NULL, NULL, NULL,
1272	},
1273	.cpuid = {
1274	.eax = 7,
1275	.needs_ecx = true, .ecx = 1,
1276	.reg = R_ECX,
1277	},
1278	.tcg_features = TCG_7_1_ECX_FEATURES,
1279	},
1280	[FEAT_7_1_EDX] = {
1281	.type = CPUID_FEATURE_WORD,
1282	.feat_names = {
1283	NULL, NULL, NULL, NULL,
1284	"avx-vnni-int8", "avx-ne-convert", NULL, NULL,
1285	"amx-complex", NULL, "avx-vnni-int16", NULL,
1286	NULL, NULL, "prefetchiti", NULL,
1287	NULL, NULL, NULL, "avx10",
1288	NULL, "apxf", NULL, NULL,
1289	NULL, NULL, NULL, NULL,
1290	NULL, NULL, NULL, NULL,
1291	},
1292	.cpuid = {
1293	.eax = 7,
1294	.needs_ecx = true, .ecx = 1,
1295	.reg = R_EDX,
1296	},
1297	.tcg_features = TCG_7_1_EDX_FEATURES,
1298	},
1299	[FEAT_7_2_EDX] = {
1300	.type = CPUID_FEATURE_WORD,
1301	.feat_names = {
1302	"intel-psfd", "ipred-ctrl", "rrsba-ctrl", "ddpd-u",
1303	"bhi-ctrl", "mcdt-no", NULL, NULL,
1304	NULL, NULL, NULL, NULL,
1305	NULL, NULL, NULL, NULL,
1306	NULL, NULL, NULL, NULL,
1307	NULL, NULL, NULL, NULL,
1308	NULL, NULL, NULL, NULL,
1309	NULL, NULL, NULL, NULL,
1310	},
1311	.cpuid = {
1312	.eax = 7,
1313	.needs_ecx = true, .ecx = 2,
1314	.reg = R_EDX,
1315	},
1316	.tcg_features = TCG_7_2_EDX_FEATURES,
1317	},
1318	[FEAT_1E_1_EAX] = {
1319	.type = CPUID_FEATURE_WORD,
1320	.feat_names = {
1321	"amx-int8-alias", "amx-bf16-alias", "amx-complex-alias", "amx-fp16-alias",
1322	"amx-fp8", NULL, "amx-tf32", "amx-avx512",
1323	"amx-movrs", NULL, NULL, NULL,
1324	NULL, NULL, NULL, NULL,
1325	NULL, NULL, NULL, NULL,
1326	NULL, NULL, NULL, NULL,
1327	NULL, NULL, NULL, NULL,
1328	NULL, NULL, NULL, NULL,
1329	},
1330	.cpuid = {
1331	.eax = 0x1e,
1332	.needs_ecx = true, .ecx = 1,
1333	.reg = R_EAX,
1334	},
1335	.tcg_features = TCG_1E_1_EAX_FEATURES,
1336	},
1337	[FEAT_24_0_EBX] = {
1338	.type = CPUID_FEATURE_WORD,
1339	.feat_names = {
1340	[16] = "avx10-128",
1341	[17] = "avx10-256",
1342	[18] = "avx10-512",
1343	},
1344	.cpuid = {
1345	.eax = 0x24,
1346	.needs_ecx = true, .ecx = 0,
1347	.reg = R_EBX,
1348	},
1349	.tcg_features = TCG_24_0_EBX_FEATURES,
1350	},
1351	[FEAT_29_0_EBX] = {
1352	.type = CPUID_FEATURE_WORD,
1353	.feat_names = {
1354	"apx-nci-ndd-nf", NULL, NULL, NULL,
1355	NULL, NULL, NULL, NULL,
1356	NULL, NULL, NULL, NULL,
1357	NULL, NULL, NULL, NULL,
1358	NULL, NULL, NULL, NULL,
1359	NULL, NULL, NULL, NULL,
1360	NULL, NULL, NULL, NULL,
1361	NULL, NULL, NULL, NULL,
1362	},
1363	.cpuid = {
1364	.eax = 0x29,
1365	.needs_ecx = true, .ecx = 0,
1366	.reg = R_EBX,
1367	},
1368	.tcg_features = TCG_29_0_EBX_FEATURES,
1369	},
1370	[FEAT_24_1_ECX] = {
1371	.type = CPUID_FEATURE_WORD,
1372	.feat_names = {
1373	[2] = "avx10-vnni-int",
1374	},
1375	.cpuid = {
1376	.eax = 0x24,
1377	.needs_ecx = true, .ecx = 1,
1378	.reg = R_ECX,
1379	},
1380	.tcg_features = TCG_24_1_ECX_FEATURES,
1381	},
1382	[FEAT_8000_0007_EDX] = {
1383	.type = CPUID_FEATURE_WORD,
1384	.feat_names = {
1385	NULL, NULL, NULL, NULL,
1386	NULL, NULL, NULL, NULL,
1387	"invtsc", NULL, NULL, NULL,
1388	NULL, NULL, NULL, NULL,
1389	NULL, NULL, NULL, NULL,
1390	NULL, NULL, NULL, NULL,
1391	NULL, NULL, NULL, NULL,
1392	NULL, NULL, NULL, NULL,
1393	},
1394	.cpuid = { .eax = 0x80000007, .reg = R_EDX, },
1395	.tcg_features = TCG_APM_FEATURES,
1396	.unmigratable_flags = CPUID_APM_INVTSC,
1397	},
1398	[FEAT_8000_0007_EBX] = {
1399	.type = CPUID_FEATURE_WORD,
1400	.feat_names = {
1401	"overflow-recov", "succor", NULL, NULL,
1402	NULL, NULL, NULL, NULL,
1403	NULL, NULL, NULL, NULL,
1404	NULL, NULL, NULL, NULL,
1405	NULL, NULL, NULL, NULL,
1406	NULL, NULL, NULL, NULL,
1407	NULL, NULL, NULL, NULL,
1408	NULL, NULL, NULL, NULL,
1409	},
1410	.cpuid = { .eax = 0x80000007, .reg = R_EBX, },
1411	.tcg_features = 0,
1412	.unmigratable_flags = 0,
1413	},
1414	[FEAT_8000_0008_EBX] = {
1415	.type = CPUID_FEATURE_WORD,
1416	.feat_names = {
1417	"clzero", NULL, "xsaveerptr", NULL,
1418	NULL, NULL, NULL, NULL,
1419	NULL, "wbnoinvd", NULL, NULL,
1420	"ibpb", NULL, "ibrs", "amd-stibp",
1421	NULL, "stibp-always-on", NULL, NULL,
1422	NULL, NULL, NULL, NULL,
1423	"amd-ssbd", "virt-ssbd", "amd-no-ssb", NULL,
1424	"amd-psfd", NULL, NULL, NULL,
1425	},
1426	.cpuid = { .eax = 0x80000008, .reg = R_EBX, },
1427	.tcg_features = TCG_8000_0008_EBX,
1428	.unmigratable_flags = 0,
1429	},
1430	[FEAT_8000_0021_EAX] = {
1431	.type = CPUID_FEATURE_WORD,
1432	.feat_names = {
1433	"no-nested-data-bp", "fs-gs-base-ns", "lfence-always-serializing", NULL,
1434	NULL, "verw-clear", "null-sel-clr-base", NULL,
1435	"auto-ibrs", NULL, NULL, NULL,
1436	NULL, NULL, NULL, NULL,
1437	NULL, NULL, NULL, NULL,
1438	"prefetchi", NULL, NULL, NULL,
1439	"eraps", NULL, NULL, "sbpb",
1440	"ibpb-brtype", "srso-no", "srso-user-kernel-no", NULL,
1441	},
1442	.cpuid = { .eax = 0x80000021, .reg = R_EAX, },
1443	.tcg_features = TCG_8000_0021_EAX_FEATURES,
1444	.unmigratable_flags = 0,
1445	},
1446	[FEAT_8000_0021_EBX] = {
1447	.type = CPUID_FEATURE_WORD,
1448	.cpuid = { .eax = 0x80000021, .reg = R_EBX, },
1449	.tcg_features = 0,
1450	.unmigratable_flags = 0,
1451	},
1452	[FEAT_8000_0021_ECX] = {
1453	.type = CPUID_FEATURE_WORD,
1454	.feat_names = {
1455	NULL, "tsa-sq-no", "tsa-l1-no", NULL,
1456	NULL, NULL, NULL, NULL,
1457	NULL, NULL, NULL, NULL,
1458	NULL, NULL, NULL, NULL,
1459	NULL, NULL, NULL, NULL,
1460	NULL, NULL, NULL, NULL,
1461	NULL, NULL, NULL, NULL,
1462	NULL, NULL, NULL, NULL,
1463	},
1464	.cpuid = { .eax = 0x80000021, .reg = R_ECX, },
1465	.tcg_features = 0,
1466	.unmigratable_flags = 0,
1467	},
1468	[FEAT_8000_0022_EAX] = {
1469	.type = CPUID_FEATURE_WORD,
1470	.feat_names = {
1471	"perfmon-v2", NULL, NULL, NULL,
1472	NULL, NULL, NULL, NULL,
1473	NULL, NULL, NULL, NULL,
1474	NULL, NULL, NULL, NULL,
1475	NULL, NULL, NULL, NULL,
1476	NULL, NULL, NULL, NULL,
1477	NULL, NULL, NULL, NULL,
1478	NULL, NULL, NULL, NULL,
1479	},
1480	.cpuid = { .eax = 0x80000022, .reg = R_EAX, },
1481	.tcg_features = 0,
1482	.unmigratable_flags = 0,
1483	},
1484	[FEAT_XSAVE] = {
1485	.type = CPUID_FEATURE_WORD,
1486	.feat_names = {
1487	"xsaveopt", "xsavec", "xgetbv1", "xsaves",
1488	"xfd", NULL, NULL, NULL,
1489	NULL, NULL, NULL, NULL,
1490	NULL, NULL, NULL, NULL,
1491	NULL, NULL, NULL, NULL,
1492	NULL, NULL, NULL, NULL,
1493	NULL, NULL, NULL, NULL,
1494	NULL, NULL, NULL, NULL,
1495	},
1496	.cpuid = {
1497	.eax = 0xd,
1498	.needs_ecx = true, .ecx = 1,
1499	.reg = R_EAX,
1500	},
1501	.tcg_features = TCG_XSAVE_FEATURES,
1502	},
1503	[FEAT_XSAVE_XSS_LO] = {
1504	.type = CPUID_FEATURE_WORD,
1505	.feat_names = {
1506	NULL, NULL, NULL, NULL,
1507	NULL, NULL, NULL, NULL,
1508	NULL, NULL, NULL, NULL,
1509	NULL, NULL, NULL, NULL,
1510	NULL, NULL, NULL, NULL,
1511	NULL, NULL, NULL, NULL,
1512	NULL, NULL, NULL, NULL,
1513	NULL, NULL, NULL, NULL,
1514	},
1515	.cpuid = {
1516	.eax = 0xD,
1517	.needs_ecx = true,
1518	.ecx = 1,
1519	.reg = R_ECX,
1520	},
1521	.migratable_flags = XSTATE_CET_U_MASK \| XSTATE_CET_S_MASK \|
1522	XSTATE_ARCH_LBR_MASK,
1523	},
1524	[FEAT_XSAVE_XSS_HI] = {
1525	.type = CPUID_FEATURE_WORD,
1526	.cpuid = {
1527	.eax = 0xD,
1528	.needs_ecx = true,
1529	.ecx = 1,
1530	.reg = R_EDX
1531	},
1532	},
1533	[FEAT_6_EAX] = {
1534	.type = CPUID_FEATURE_WORD,
1535	.feat_names = {
1536	NULL, NULL, "arat", NULL,
1537	NULL, NULL, NULL, NULL,
1538	NULL, NULL, NULL, NULL,
1539	NULL, NULL, NULL, NULL,
1540	NULL, NULL, NULL, NULL,
1541	NULL, NULL, NULL, NULL,
1542	NULL, NULL, NULL, NULL,
1543	NULL, NULL, NULL, NULL,
1544	},
1545	.cpuid = { .eax = 6, .reg = R_EAX, },
1546	.tcg_features = TCG_6_EAX_FEATURES,
1547	},
1548	[FEAT_XSAVE_XCR0_LO] = {
1549	.type = CPUID_FEATURE_WORD,
1550	.cpuid = {
1551	.eax = 0xD,
1552	.needs_ecx = true, .ecx = 0,
1553	.reg = R_EAX,
1554	},
1555	.tcg_features = XSTATE_FP_MASK \| XSTATE_SSE_MASK \|
1556	XSTATE_YMM_MASK \| XSTATE_BNDREGS_MASK \| XSTATE_BNDCSR_MASK \|
1557	XSTATE_PKRU_MASK,
1558	.migratable_flags = XSTATE_FP_MASK \| XSTATE_SSE_MASK \|
1559	XSTATE_YMM_MASK \| XSTATE_BNDREGS_MASK \| XSTATE_BNDCSR_MASK \|
1560	XSTATE_OPMASK_MASK \| XSTATE_ZMM_Hi256_MASK \| XSTATE_Hi16_ZMM_MASK \|
1561	XSTATE_PKRU_MASK \| XSTATE_XTILE_CFG_MASK \| XSTATE_XTILE_DATA_MASK \|
1562	XSTATE_APX_MASK,
1563	},
1564	[FEAT_XSAVE_XCR0_HI] = {
1565	.type = CPUID_FEATURE_WORD,
1566	.cpuid = {
1567	.eax = 0xD,
1568	.needs_ecx = true, .ecx = 0,
1569	.reg = R_EDX,
1570	},
1571	.tcg_features = 0U,
1572	},
1573	/Below are MSR exposed features/
1574	[FEAT_ARCH_CAPABILITIES] = {
1575	.type = MSR_FEATURE_WORD,
1576	.feat_names = {
1577	"rdctl-no", "ibrs-all", "rsba", "skip-l1dfl-vmentry",
1578	"ssb-no", "mds-no", "pschange-mc-no", "tsx-ctrl",
1579	"taa-no", NULL, NULL, NULL,
1580	NULL, "sbdr-ssdp-no", "fbsdp-no", "psdp-no",
1581	NULL, "fb-clear", NULL, NULL,
1582	"bhi-no", NULL, NULL, NULL,
1583	"pbrsb-no", NULL, "gds-no", "rfds-no",
1584	"rfds-clear", NULL, NULL, NULL,
1585	NULL, NULL, NULL, NULL,
1586	NULL, NULL, NULL, NULL,
1587	NULL, NULL, NULL, NULL,
1588	NULL, NULL, NULL, NULL,
1589	NULL, NULL, NULL, NULL,
1590	NULL, NULL, NULL, NULL,
1591	NULL, NULL, NULL, NULL,
1592	NULL, NULL, "its-no", NULL,
1593	},
1594	.msr = {
1595	.index = MSR_IA32_ARCH_CAPABILITIES,
1596	},
1597	/*
1598	* FEAT_ARCH_CAPABILITIES only affects a read-only MSR, which
1599	* cannot be read from user mode. Therefore, it has no impact
1600	> on any user-mode operation, and warnings about unsupported
1601	* features do not matter.
1602	*/
1603	.tcg_features = ~0U,
1604	},
1605	[FEAT_CORE_CAPABILITY] = {
1606	.type = MSR_FEATURE_WORD,
1607	.feat_names = {
1608	NULL, NULL, NULL, NULL,
1609	NULL, "split-lock-detect", NULL, NULL,
1610	NULL, NULL, NULL, NULL,
1611	NULL, NULL, NULL, NULL,
1612	NULL, NULL, NULL, NULL,
1613	NULL, NULL, NULL, NULL,
1614	NULL, NULL, NULL, NULL,
1615	NULL, NULL, NULL, NULL,
1616	},
1617	.msr = {
1618	.index = MSR_IA32_CORE_CAPABILITY,
1619	},
1620	},
1621	[FEAT_PERF_CAPABILITIES] = {
1622	.type = MSR_FEATURE_WORD,
1623	.feat_names = {
1624	NULL, NULL, NULL, NULL,
1625	NULL, NULL, NULL, NULL,
1626	NULL, NULL, NULL, NULL,
1627	NULL, "full-width-write", NULL, NULL,
1628	NULL, NULL, NULL, NULL,
1629	NULL, NULL, NULL, NULL,
1630	NULL, NULL, NULL, NULL,
1631	NULL, NULL, NULL, NULL,
1632	},
1633	.msr = {
1634	.index = MSR_IA32_PERF_CAPABILITIES,
1635	},
1636	},
1637
1638	[FEAT_VMX_PROCBASED_CTLS] = {
1639	.type = MSR_FEATURE_WORD,
1640	.feat_names = {
1641	NULL, NULL, "vmx-vintr-pending", "vmx-tsc-offset",
1642	NULL, NULL, NULL, "vmx-hlt-exit",
1643	NULL, "vmx-invlpg-exit", "vmx-mwait-exit", "vmx-rdpmc-exit",
1644	"vmx-rdtsc-exit", NULL, NULL, "vmx-cr3-load-noexit",
1645	"vmx-cr3-store-noexit", NULL, NULL, "vmx-cr8-load-exit",
1646	"vmx-cr8-store-exit", "vmx-flexpriority", "vmx-vnmi-pending", "vmx-movdr-exit",
1647	"vmx-io-exit", "vmx-io-bitmap", NULL, "vmx-mtf",
1648	"vmx-msr-bitmap", "vmx-monitor-exit", "vmx-pause-exit", "vmx-secondary-ctls",
1649	},
1650	.msr = {
1651	.index = MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1652	}
1653	},
1654
1655	[FEAT_VMX_SECONDARY_CTLS] = {
1656	.type = MSR_FEATURE_WORD,
1657	.feat_names = {
1658	"vmx-apicv-xapic", "vmx-ept", "vmx-desc-exit", "vmx-rdtscp-exit",
1659	"vmx-apicv-x2apic", "vmx-vpid", "vmx-wbinvd-exit", "vmx-unrestricted-guest",
1660	"vmx-apicv-register", "vmx-apicv-vid", "vmx-ple", "vmx-rdrand-exit",
1661	"vmx-invpcid-exit", "vmx-vmfunc", "vmx-shadow-vmcs", "vmx-encls-exit",
1662	"vmx-rdseed-exit", "vmx-pml", NULL, NULL,
1663	"vmx-xsaves", NULL, "vmx-mbec", NULL,
1664	NULL, "vmx-tsc-scaling", "vmx-enable-user-wait-pause", NULL,
1665	NULL, NULL, NULL, NULL,
1666	},
1667	.msr = {
1668	.index = MSR_IA32_VMX_PROCBASED_CTLS2,
1669	}
1670	},
1671
1672	[FEAT_VMX_PINBASED_CTLS] = {
1673	.type = MSR_FEATURE_WORD,
1674	.feat_names = {
1675	"vmx-intr-exit", NULL, NULL, "vmx-nmi-exit",
1676	NULL, "vmx-vnmi", "vmx-preemption-timer", "vmx-posted-intr",
1677	NULL, NULL, NULL, NULL,
1678	NULL, NULL, NULL, NULL,
1679	NULL, NULL, NULL, NULL,
1680	NULL, NULL, NULL, NULL,
1681	NULL, NULL, NULL, NULL,
1682	NULL, NULL, NULL, NULL,
1683	},
1684	.msr = {
1685	.index = MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1686	}
1687	},
1688
1689	[FEAT_VMX_EXIT_CTLS] = {
1690	.type = MSR_FEATURE_WORD,
1691	/*
1692	* VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE is copied from
1693	* the LM CPUID bit.
1694	*/
1695	.feat_names = {
1696	NULL, NULL, "vmx-exit-nosave-debugctl", NULL,
1697	NULL, NULL, NULL, NULL,
1698	NULL, NULL /* vmx-exit-host-addr-space-size */, NULL, NULL,
1699	"vmx-exit-load-perf-global-ctrl", NULL, NULL, "vmx-exit-ack-intr",
1700	NULL, NULL, "vmx-exit-save-pat", "vmx-exit-load-pat",
1701	"vmx-exit-save-efer", "vmx-exit-load-efer",
1702	"vmx-exit-save-preemption-timer", "vmx-exit-clear-bndcfgs",
1703	NULL, "vmx-exit-clear-rtit-ctl", NULL, NULL,
1704	"vmx-exit-save-cet", "vmx-exit-load-pkrs", NULL, "vmx-exit-secondary-ctls",
1705	},
1706	.msr = {
1707	.index = MSR_IA32_VMX_TRUE_EXIT_CTLS,
1708	}
1709	},
1710
1711	[FEAT_VMX_ENTRY_CTLS] = {
1712	.type = MSR_FEATURE_WORD,
1713	.feat_names = {
1714	NULL, NULL, "vmx-entry-noload-debugctl", NULL,
1715	NULL, NULL, NULL, NULL,
1716	NULL, "vmx-entry-ia32e-mode", NULL, NULL,
1717	NULL, "vmx-entry-load-perf-global-ctrl", "vmx-entry-load-pat", "vmx-entry-load-efer",
1718	"vmx-entry-load-bndcfgs", NULL, "vmx-entry-load-rtit-ctl", NULL,
1719	"vmx-entry-load-cet", NULL, "vmx-entry-load-pkrs", "vmx-entry-load-fred",
1720	NULL, NULL, NULL, NULL,
1721	NULL, NULL, NULL, NULL,
1722	},
1723	.msr = {
1724	.index = MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1725	}
1726	},
1727
1728	[FEAT_VMX_MISC] = {
1729	.type = MSR_FEATURE_WORD,
1730	.feat_names = {
1731	NULL, NULL, NULL, NULL,
1732	NULL, "vmx-store-lma", "vmx-activity-hlt", "vmx-activity-shutdown",
1733	"vmx-activity-wait-sipi", NULL, NULL, NULL,
1734	NULL, NULL, NULL, NULL,
1735	NULL, NULL, NULL, NULL,
1736	NULL, NULL, NULL, NULL,
1737	NULL, NULL, NULL, NULL,
1738	NULL, "vmx-vmwrite-vmexit-fields", "vmx-zero-len-inject", NULL,
1739	},
1740	.msr = {
1741	.index = MSR_IA32_VMX_MISC,
1742	}
1743	},
1744
1745	[FEAT_VMX_EPT_VPID_CAPS] = {
1746	.type = MSR_FEATURE_WORD,
1747	.feat_names = {
1748	"vmx-ept-execonly", NULL, NULL, NULL,
1749	NULL, NULL, "vmx-page-walk-4", "vmx-page-walk-5",
1750	NULL, NULL, NULL, NULL,
1751	NULL, NULL, NULL, NULL,
1752	"vmx-ept-2mb", "vmx-ept-1gb", NULL, NULL,
1753	"vmx-invept", "vmx-eptad", "vmx-ept-advanced-exitinfo", NULL,
1754	NULL, "vmx-invept-single-context", "vmx-invept-all-context", NULL,
1755	NULL, NULL, NULL, NULL,
1756	"vmx-invvpid", NULL, NULL, NULL,
1757	NULL, NULL, NULL, NULL,
1758	"vmx-invvpid-single-addr", "vmx-invept-single-context",
1759	"vmx-invvpid-all-context", "vmx-invept-single-context-noglobals",
1760	NULL, NULL, NULL, NULL,
1761	NULL, NULL, NULL, NULL,
1762	NULL, NULL, NULL, NULL,
1763	NULL, NULL, NULL, NULL,
1764	NULL, NULL, NULL, NULL,
1765	},
1766	.msr = {
1767	.index = MSR_IA32_VMX_EPT_VPID_CAP,
1768	}
1769	},
1770
1771	[FEAT_VMX_BASIC] = {
1772	.type = MSR_FEATURE_WORD,
1773	.feat_names = {
1774	[54] = "vmx-ins-outs",
1775	[55] = "vmx-true-ctls",
1776	[56] = "vmx-any-errcode",
1777	[58] = "vmx-nested-exception",
1778	},
1779	.msr = {
1780	.index = MSR_IA32_VMX_BASIC,
1781	},
1782	/* Just to be safe - we don't support setting the MSEG version field. */
1783	.no_autoenable_flags = MSR_VMX_BASIC_DUAL_MONITOR,
1784	},
1785
1786	[FEAT_VMX_VMFUNC] = {
1787	.type = MSR_FEATURE_WORD,
1788	.feat_names = {
1789	[0] = "vmx-eptp-switching",
1790	},
1791	.msr = {
1792	.index = MSR_IA32_VMX_VMFUNC,
1793	}
1794	},
1795
1796	[FEAT_14_0_ECX] = {
1797	.type = CPUID_FEATURE_WORD,
1798	.feat_names = {
1799	NULL, NULL, NULL, NULL,
1800	NULL, NULL, NULL, NULL,
1801	NULL, NULL, NULL, NULL,
1802	NULL, NULL, NULL, NULL,
1803	NULL, NULL, NULL, NULL,
1804	NULL, NULL, NULL, NULL,
1805	NULL, NULL, NULL, NULL,
1806	NULL, NULL, NULL, "intel-pt-lip",
1807	},
1808	.cpuid = {
1809	.eax = 0x14,
1810	.needs_ecx = true, .ecx = 0,
1811	.reg = R_ECX,
1812	},
1813	.tcg_features = TCG_14_0_ECX_FEATURES,
1814	},
1815
1816	[FEAT_SGX_12_0_EAX] = {
1817	.type = CPUID_FEATURE_WORD,
1818	.feat_names = {
1819	"sgx1", "sgx2", NULL, NULL,
1820	NULL, NULL, NULL, NULL,
1821	NULL, NULL, NULL, "sgx-edeccssa",
1822	NULL, NULL, NULL, NULL,
1823	NULL, NULL, NULL, NULL,
1824	NULL, NULL, NULL, NULL,
1825	NULL, NULL, NULL, NULL,
1826	NULL, NULL, NULL, NULL,
1827	},
1828	.cpuid = {
1829	.eax = 0x12,
1830	.needs_ecx = true, .ecx = 0,
1831	.reg = R_EAX,
1832	},
1833	.tcg_features = TCG_SGX_12_0_EAX_FEATURES,
1834	},
1835
1836	[FEAT_SGX_12_0_EBX] = {
1837	.type = CPUID_FEATURE_WORD,
1838	.feat_names = {
1839	"sgx-exinfo" , NULL, NULL, NULL,
1840	NULL, NULL, NULL, NULL,
1841	NULL, NULL, NULL, NULL,
1842	NULL, NULL, NULL, NULL,
1843	NULL, NULL, NULL, NULL,
1844	NULL, NULL, NULL, NULL,
1845	NULL, NULL, NULL, NULL,
1846	NULL, NULL, NULL, NULL,
1847	},
1848	.cpuid = {
1849	.eax = 0x12,
1850	.needs_ecx = true, .ecx = 0,
1851	.reg = R_EBX,
1852	},
1853	.tcg_features = TCG_SGX_12_0_EBX_FEATURES,
1854	},
1855
1856	[FEAT_SGX_12_1_EAX] = {
1857	.type = CPUID_FEATURE_WORD,
1858	.feat_names = {
1859	NULL, "sgx-debug", "sgx-mode64", NULL,
1860	"sgx-provisionkey", "sgx-tokenkey", NULL, "sgx-kss",
1861	NULL, NULL, "sgx-aex-notify", NULL,
1862	NULL, NULL, NULL, NULL,
1863	NULL, NULL, NULL, NULL,
1864	NULL, NULL, NULL, NULL,
1865	NULL, NULL, NULL, NULL,
1866	NULL, NULL, NULL, NULL,
1867	},
1868	.cpuid = {
1869	.eax = 0x12,
1870	.needs_ecx = true, .ecx = 1,
1871	.reg = R_EAX,
1872	},
1873	.tcg_features = TCG_SGX_12_1_EAX_FEATURES,
1874	},
1875	};
1876
1877	bool is_feature_word_cpuid(uint32_t feature, uint32_t index, int reg)
1878	{
1879	FeatureWordInfo *wi;
1880	FeatureWord w;
1881
1882	for (w = 0; w < FEATURE_WORDS; w++) {
1883	wi = &feature_word_info[w];
1884	if (wi->type == CPUID_FEATURE_WORD && wi->cpuid.eax == feature &&
1885	(!wi->cpuid.needs_ecx \|\| wi->cpuid.ecx == index) &&
1886	wi->cpuid.reg == reg) {
1887	return true;
1888	}
1889	}
1890	return false;
1891	}
1892
1893	static FeatureDep feature_dependencies[] = {
1894	{
1895	.from = { FEAT_7_0_EDX, CPUID_7_0_EDX_ARCH_CAPABILITIES },
1896	.to = { FEAT_ARCH_CAPABILITIES, ~0ull },
1897	},
1898	{
1899	.from = { FEAT_7_0_EDX, CPUID_7_0_EDX_CORE_CAPABILITY },
1900	.to = { FEAT_CORE_CAPABILITY, ~0ull },
1901	},
1902	{
1903	.from = { FEAT_1_ECX, CPUID_EXT_PDCM },
1904	.to = { FEAT_PERF_CAPABILITIES, ~0ull },
1905	},
1906	{
1907	.from = { FEAT_1_ECX, CPUID_EXT_VMX },
1908	.to = { FEAT_VMX_PROCBASED_CTLS, ~0ull },
1909	},
1910	{
1911	.from = { FEAT_1_ECX, CPUID_EXT_VMX },
1912	.to = { FEAT_VMX_PINBASED_CTLS, ~0ull },
1913	},
1914	{
1915	.from = { FEAT_1_ECX, CPUID_EXT_VMX },
1916	.to = { FEAT_VMX_EXIT_CTLS, ~0ull },
1917	},
1918	{
1919	.from = { FEAT_1_ECX, CPUID_EXT_VMX },
1920	.to = { FEAT_VMX_ENTRY_CTLS, ~0ull },
1921	},
1922	{
1923	.from = { FEAT_1_ECX, CPUID_EXT_VMX },
1924	.to = { FEAT_VMX_MISC, ~0ull },
1925	},
1926	{
1927	.from = { FEAT_1_ECX, CPUID_EXT_VMX },
1928	.to = { FEAT_VMX_BASIC, ~0ull },
1929	},
1930	{
1931	.from = { FEAT_8000_0001_EDX, CPUID_EXT2_LM },
1932	.to = { FEAT_VMX_ENTRY_CTLS, VMX_VM_ENTRY_IA32E_MODE },
1933	},
1934	{
1935	.from = { FEAT_VMX_PROCBASED_CTLS, VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS },
1936	.to = { FEAT_VMX_SECONDARY_CTLS, ~0ull },
1937	},
1938	{
1939	.from = { FEAT_XSAVE, CPUID_XSAVE_XSAVES },
1940	.to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_XSAVES },
1941	},
1942	{
1943	.from = { FEAT_1_ECX, CPUID_EXT_RDRAND },
1944	.to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDRAND_EXITING },
1945	},
1946	{
1947	.from = { FEAT_7_0_EBX, CPUID_7_0_EBX_INVPCID },
1948	.to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_INVPCID },
1949	},
1950	{
1951	.from = { FEAT_7_0_EBX, CPUID_7_0_EBX_MPX },
1952	.to = { FEAT_VMX_EXIT_CTLS, VMX_VM_EXIT_CLEAR_BNDCFGS },
1953	},
1954	{
1955	.from = { FEAT_7_0_EBX, CPUID_7_0_EBX_MPX },
1956	.to = { FEAT_VMX_ENTRY_CTLS, VMX_VM_ENTRY_LOAD_BNDCFGS },
1957	},
1958	{
1959	.from = { FEAT_7_0_EBX, CPUID_7_0_EBX_RDSEED },
1960	.to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDSEED_EXITING },
1961	},
1962	{
1963	.from = { FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT },
1964	.to = { FEAT_14_0_ECX, ~0ull },
1965	},
1966	{
1967	.from = { FEAT_8000_0001_EDX, CPUID_EXT2_RDTSCP },
1968	.to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDTSCP },
1969	},
1970	{
1971	.from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_EPT },
1972	.to = { FEAT_VMX_EPT_VPID_CAPS, 0xffffffffull },
1973	},
1974	{
1975	.from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_EPT },
1976	.to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST },
1977	},
1978	{
1979	.from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_EPT },
1980	.to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_MODE_BASED_EPT_EXEC },
1981	},
1982	{
1983	.from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_VPID },
1984	.to = { FEAT_VMX_EPT_VPID_CAPS, 0xffffffffull << 32 },
1985	},
1986	{
1987	.from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_VMFUNC },
1988	.to = { FEAT_VMX_VMFUNC, ~0ull },
1989	},
1990	{
1991	.from = { FEAT_8000_0001_ECX, CPUID_EXT3_SVM },
1992	.to = { FEAT_SVM, ~0ull },
1993	},
1994	{
1995	.from = { FEAT_7_0_ECX, CPUID_7_0_ECX_WAITPKG },
1996	.to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_USER_WAIT_PAUSE },
1997	},
1998	{
1999	.from = { FEAT_8000_0001_EDX, CPUID_EXT2_LM },
2000	.to = { FEAT_7_1_EAX, CPUID_7_1_EAX_FRED },
2001	},
2002	{
2003	.from = { FEAT_7_1_EAX, CPUID_7_1_EAX_LKGS },
2004	.to = { FEAT_7_1_EAX, CPUID_7_1_EAX_FRED },
2005	},
2006	{
2007	.from = { FEAT_7_0_EBX, CPUID_7_0_EBX_SGX },
2008	.to = { FEAT_7_0_ECX, CPUID_7_0_ECX_SGX_LC },
2009	},
2010	{
2011	.from = { FEAT_7_0_EBX, CPUID_7_0_EBX_SGX },
2012	.to = { FEAT_SGX_12_0_EAX, ~0ull },
2013	},
2014	{
2015	.from = { FEAT_7_0_EBX, CPUID_7_0_EBX_SGX },
2016	.to = { FEAT_SGX_12_0_EBX, ~0ull },
2017	},
2018	{
2019	.from = { FEAT_7_0_EBX, CPUID_7_0_EBX_SGX },
2020	.to = { FEAT_SGX_12_1_EAX, ~0ull },
2021	},
2022	{
2023	.from = { FEAT_24_0_EBX, CPUID_24_0_EBX_AVX10_128 },
2024	.to = { FEAT_24_0_EBX, CPUID_24_0_EBX_AVX10_256 },
2025	},
2026	{
2027	.from = { FEAT_24_0_EBX, CPUID_24_0_EBX_AVX10_256 },
2028	.to = { FEAT_24_0_EBX, CPUID_24_0_EBX_AVX10_512 },
2029	},
2030	{
2031	.from = { FEAT_24_0_EBX, CPUID_24_0_EBX_AVX10_VL_MASK },
2032	.to = { FEAT_7_1_EDX, CPUID_7_1_EDX_AVX10 },
2033	},
2034	{
2035	.from = { FEAT_7_1_EDX, CPUID_7_1_EDX_AVX10 },
2036	.to = { FEAT_24_0_EBX, ~0ull },
2037	},
2038	{
2039	.from = { FEAT_7_1_EDX, CPUID_7_1_EDX_APXF },
2040	.to = { FEAT_29_0_EBX, ~0ull },
2041	},
2042
2043	{
2044	.from = { FEAT_7_1_EDX, CPUID_7_1_EDX_AVX10 },
2045	.to = { FEAT_24_1_ECX, ~0ull },
2046	},
2047	{
2048	.from = { FEAT_7_1_EAX, CPUID_7_1_EAX_FRED },
2049	.to = { FEAT_VMX_ENTRY_CTLS, VMX_VM_ENTRY_LOAD_IA32_FRED },
2050	},
2051	};
2052
2053	typedef struct X86RegisterInfo32 {
2054	/* Name of register */
2055	const char *name;
2056	/* QAPI enum value register */
2057	X86CPURegister32 qapi_enum;
2058	} X86RegisterInfo32;
2059
2060	#define REGISTER(reg) \
2061	[R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg }
2062	static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = {
2063	REGISTER(EAX),
2064	REGISTER(ECX),
2065	REGISTER(EDX),
2066	REGISTER(EBX),
2067	REGISTER(ESP),
2068	REGISTER(EBP),
2069	REGISTER(ESI),
2070	REGISTER(EDI),
2071	};
2072	#undef REGISTER
2073
2074	ExtSaveArea x86_ext_save_areas[XSAVE_STATE_AREA_COUNT] = {
2075	[XSTATE_FP_BIT] = {
2076	/* x87 FP state component is always enabled if XSAVE is supported */
2077	.size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader),
2078	.features = {
2079	{ FEAT_1_ECX, CPUID_EXT_XSAVE },
2080	},
2081	},
2082	[XSTATE_SSE_BIT] = {
2083	/* SSE state component is always enabled if XSAVE is supported */
2084	.size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader),
2085	.features = {
2086	{ FEAT_1_ECX, CPUID_EXT_XSAVE },
2087	},
2088	},
2089	[XSTATE_YMM_BIT] = {
2090	.size = sizeof(XSaveAVX),
2091	.features = {
2092	{ FEAT_1_ECX, CPUID_EXT_AVX },
2093	},
2094	},
2095	[XSTATE_BNDREGS_BIT] = {
2096	.size = sizeof(XSaveBNDREG),
2097	.features = {
2098	{ FEAT_7_0_EBX, CPUID_7_0_EBX_MPX },
2099	},
2100	},
2101	[XSTATE_BNDCSR_BIT] = {
2102	.size = sizeof(XSaveBNDCSR),
2103	.features = {
2104	{ FEAT_7_0_EBX, CPUID_7_0_EBX_MPX },
2105	},
2106	},
2107	[XSTATE_OPMASK_BIT] = {
2108	.size = sizeof(XSaveOpmask),
2109	.features = {
2110	{ FEAT_7_0_EBX, CPUID_7_0_EBX_AVX512F },
2111	{ FEAT_7_1_EDX, CPUID_7_1_EDX_AVX10 },
2112	},
2113	},
2114	[XSTATE_ZMM_Hi256_BIT] = {
2115	.size = sizeof(XSaveZMM_Hi256),
2116	.features = {
2117	{ FEAT_7_0_EBX, CPUID_7_0_EBX_AVX512F },
2118	{ FEAT_7_1_EDX, CPUID_7_1_EDX_AVX10 },
2119	},
2120	},
2121	[XSTATE_Hi16_ZMM_BIT] = {
2122	.size = sizeof(XSaveHi16_ZMM),
2123	.features = {
2124	{ FEAT_7_0_EBX, CPUID_7_0_EBX_AVX512F },
2125	{ FEAT_7_1_EDX, CPUID_7_1_EDX_AVX10 },
2126	},
2127	},
2128	[XSTATE_PKRU_BIT] = {
2129	.size = sizeof(XSavePKRU),
2130	.features = {
2131	{ FEAT_7_0_ECX, CPUID_7_0_ECX_PKU },
2132	},
2133	},
2134	[XSTATE_CET_U_BIT] = {
2135	.size = sizeof(XSaveCETU),
2136	.features = {
2137	{ FEAT_7_0_ECX, CPUID_7_0_ECX_CET_SHSTK },
2138	{ FEAT_7_0_EDX, CPUID_7_0_EDX_CET_IBT },
2139	},
2140	},
2141	[XSTATE_CET_S_BIT] = {
2142	.size = sizeof(XSaveCETS),
2143	.features = {
2144	{ FEAT_7_0_ECX, CPUID_7_0_ECX_CET_SHSTK },
2145	{ FEAT_7_0_EDX, CPUID_7_0_EDX_CET_IBT },
2146	},
2147	},
2148	[XSTATE_ARCH_LBR_BIT] = {
2149	.size = sizeof(XSaveArchLBR),
2150	.features = {
2151	{ FEAT_7_0_EDX, CPUID_7_0_EDX_ARCH_LBR },
2152	},
2153	},
2154	[XSTATE_XTILE_CFG_BIT] = {
2155	.size = sizeof(XSaveXTILECFG),
2156	.features = {
2157	{ FEAT_7_0_EDX, CPUID_7_0_EDX_AMX_TILE },
2158	},
2159	},
2160	[XSTATE_XTILE_DATA_BIT] = {
2161	.size = sizeof(XSaveXTILEDATA),
2162	.features = {
2163	{ FEAT_7_0_EDX, CPUID_7_0_EDX_AMX_TILE },
2164	},
2165	},
2166	[XSTATE_APX_BIT] = {
2167	.size = sizeof(XSaveAPX),
2168	.features = {
2169	{ FEAT_7_1_EDX, CPUID_7_1_EDX_APXF },
2170	},
2171	},
2172	};
2173
2174	uint32_t xsave_area_size(uint64_t mask, bool compacted)
2175	{
2176	uint64_t ret = x86_ext_save_areas[0].size;
2177	const ExtSaveArea *esa;
2178	uint32_t offset = 0;
2179	int i;
2180
2181	for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
2182	esa = &x86_ext_save_areas[i];
2183	if ((mask >> i) & 1) {
2184	offset = compacted ? ret : esa->offset;
2185	ret = MAX(ret, offset + esa->size);
2186	}
2187	}
2188	return ret;
2189	}
2190
2191	static inline bool accel_uses_host_cpuid(void)
2192	{
2193	return !tcg_enabled() && !qtest_enabled();
2194	}
2195
2196	static inline uint64_t x86_cpu_xsave_xcr0_components(X86CPU *cpu)
2197	{
2198	return ((uint64_t)cpu->env.features[FEAT_XSAVE_XCR0_HI]) << 32 \|
2199	cpu->env.features[FEAT_XSAVE_XCR0_LO];
2200	}
2201
2202	/* Return name of 32-bit register, from a R_* constant */
2203	static const char *get_register_name_32(unsigned int reg)
2204	{
2205	if (reg >= CPU_NB_REGS32) {
2206	return NULL;
2207	}
2208	return x86_reg_info_32[reg].name;
2209	}
2210
2211	static inline uint64_t x86_cpu_xsave_xss_components(X86CPU *cpu)
2212	{
2213	return ((uint64_t)cpu->env.features[FEAT_XSAVE_XSS_HI]) << 32 \|
2214	cpu->env.features[FEAT_XSAVE_XSS_LO];
2215	}
2216
2217	/*
2218	* Returns the set of feature flags that are supported and migratable by
2219	* QEMU, for a given FeatureWord.
2220	*/
2221	static uint64_t x86_cpu_get_migratable_flags(X86CPU *cpu, FeatureWord w)
2222	{
2223	FeatureWordInfo *wi = &feature_word_info[w];
2224	CPUX86State *env = &cpu->env;
2225	uint64_t r = 0;
2226	int i;
2227
2228	for (i = 0; i < 64; i++) {
2229	uint64_t f = 1ULL << i;
2230
2231	/*
2232	* If the feature name is known, it is implicitly considered migratable,
2233	* unless it is explicitly set in unmigratable_flags.
2234	*
2235	* TODO: Make the behavior of x86_cpu_enable_xsave_components() align
2236	* with migratable_flags masking.
2237	*/
2238	if ((wi->migratable_flags & f) \|\|
2239	(wi->feat_names[i] && !(wi->unmigratable_flags & f))) {
2240	r \|= f;
2241	}
2242	}
2243
2244	/* when tsc-khz is set explicitly, invtsc is migratable */
2245	if ((w == FEAT_8000_0007_EDX) && env->user_tsc_khz) {
2246	r \|= CPUID_APM_INVTSC;
2247	}
2248
2249	return r;
2250	}
2251
2252	void host_cpuid(uint32_t function, uint32_t count,
2253	uint32_t eax, uint32_t ebx, uint32_t ecx, uint32_t edx)
2254	{
2255	uint32_t vec[4];
2256
2257	#ifdef __x86_64__
2258	asm volatile("cpuid"
2259	: "=a"(vec[0]), "=b"(vec[1]),
2260	"=c"(vec[2]), "=d"(vec[3])
2261	: "0"(function), "c"(count) : "cc");
2262	#else
2263	abort();
2264	#endif
2265
2266	if (eax)
2267	*eax = vec[0];
2268	if (ebx)
2269	*ebx = vec[1];
2270	if (ecx)
2271	*ecx = vec[2];
2272	if (edx)
2273	*edx = vec[3];
2274	}
2275
2276	/* CPU class name definitions: */
2277
2278	/* Return type name for a given CPU model name
2279	* Caller is responsible for freeing the returned string.
2280	*/
2281	static char x86_cpu_type_name(const char model_name)
2282	{
2283	return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name);
2284	}
2285
2286	static ObjectClass x86_cpu_class_by_name(const char cpu_model)
2287	{
2288	g_autofree char *typename = x86_cpu_type_name(cpu_model);
2289	return object_class_by_name(typename);
2290	}
2291
2292	static char x86_cpu_class_get_model_name(X86CPUClass cc)
2293	{
2294	const char *class_name = object_class_get_name(OBJECT_CLASS(cc));
2295	assert(g_str_has_suffix(class_name, X86_CPU_TYPE_SUFFIX));
2296	return cpu_model_from_type(class_name);
2297	}
2298
2299	typedef struct X86CPUVersionDefinition {
2300	X86CPUVersion version;
2301	const char *alias;
2302	const char *note;
2303	PropValue *props;
2304	const CPUCaches *const cache_info;
2305	} X86CPUVersionDefinition;
2306
2307	/* Base definition for a CPU model */
2308	typedef struct X86CPUDefinition {
2309	const char *name;
2310	uint32_t level;
2311	uint32_t xlevel;
2312	/* vendor is zero-terminated, 12 character ASCII string */
2313	char vendor[CPUID_VENDOR_SZ + 1];
2314	int family;
2315	int model;
2316	int stepping;
2317	uint8_t avx10_version;
2318	/*
2319	* Whether to present CPUID 0x1f by default.
2320	* If true, encode CPU topology in 0x1f leaf even if there's no
2321	* extended topology levels.
2322	*/
2323	bool cpuid_0x1f;
2324	FeatureWordArray features;
2325	const char *model_id;
2326	const CPUCaches *const cache_info;
2327	/*
2328	* Definitions for alternative versions of CPU model.
2329	* List is terminated by item with version == 0.
2330	* If NULL, version 1 will be registered automatically.
2331	*/
2332	const X86CPUVersionDefinition *versions;
2333	const char *deprecation_note;
2334	} X86CPUDefinition;
2335
2336	/* Reference to a specific CPU model version */
2337	struct X86CPUModel {
2338	/* Base CPU definition */
2339	const X86CPUDefinition *cpudef;
2340	/* CPU model version */
2341	X86CPUVersion version;
2342	const char *note;
2343	/*
2344	* If true, this is an alias CPU model.
2345	* This matters only for "-cpu help" and query-cpu-definitions
2346	*/
2347	bool is_alias;
2348	};
2349
2350	/* Get full model name for CPU version */
2351	static char x86_cpu_versioned_model_name(const X86CPUDefinition cpudef,
2352	X86CPUVersion version)
2353	{
2354	assert(version > 0);
2355	return g_strdup_printf("%s-v%d", cpudef->name, (int)version);
2356	}
2357
2358	static const X86CPUVersionDefinition *
2359	x86_cpu_def_get_versions(const X86CPUDefinition *def)
2360	{
2361	/* When X86CPUDefinition::versions is NULL, we register only v1 */
2362	static const X86CPUVersionDefinition default_version_list[] = {
2363	{ 1 },
2364	{ /* end of list */ }
2365	};
2366
2367	return def->versions ?: default_version_list;
2368	}
2369
2370	/* CPUID 0x24.0x0 (EAX, EBX, ECX, EDX) and 0x24.0x1 (EAX, EBX, ECX, EDX) */
2371	#define AVX10_FEATURE_WORDS 8
2372
2373	typedef struct AVX10VersionDefinition {
2374	const char *name;
2375	/* AVX10 version */
2376	uint8_t version;
2377	/* AVX10 (CPUID 0x24) maximum supported sub-leaf. */
2378	uint8_t max_subleaf;
2379	FeatureMask *features;
2380	} AVX10VersionDefinition;
2381
2382	static const AVX10VersionDefinition builtin_avx10_defs[] = {
2383	{
2384	.name = "avx10.1",
2385	.version = 1,
2386	.max_subleaf = 0,
2387	.features = (FeatureMask[]) {
2388	{ FEAT_7_1_EDX, CPUID_7_1_EDX_AVX10 },
2389	{ FEAT_24_0_EBX, CPUID_24_0_EBX_AVX10_VL_MASK },
2390	{ /* end of list */ }
2391	}
2392	},
2393	{
2394	.name = "avx10.2",
2395	.version = 2,
2396	.max_subleaf = 1,
2397	.features = (FeatureMask[]) {
2398	{ FEAT_24_1_ECX, CPUID_24_1_ECX_AVX10_VNNI_INT },
2399	{ /* end of list */ }
2400	}
2401	},
2402	};
2403
2404	static const CPUCaches epyc_cache_info = {
2405	.l1d_cache = &(CPUCacheInfo) {
2406	.type = DATA_CACHE,
2407	.level = 1,
2408	.size = 32 * KiB,
2409	.line_size = 64,
2410	.associativity = 8,
2411	.partitions = 1,
2412	.sets = 64,
2413	.lines_per_tag = 1,
2414	.self_init = 1,
2415	.no_invd_sharing = true,
2416	.share_level = CPU_TOPOLOGY_LEVEL_CORE,
2417	},
2418	.l1i_cache = &(CPUCacheInfo) {
2419	.type = INSTRUCTION_CACHE,
2420	.level = 1,
2421	.size = 64 * KiB,
2422	.line_size = 64,
2423	.associativity = 4,
2424	.partitions = 1,
2425	.sets = 256,
2426	.lines_per_tag = 1,
2427	.self_init = 1,
2428	.no_invd_sharing = true,
2429	.share_level = CPU_TOPOLOGY_LEVEL_CORE,
2430	},
2431	.l2_cache = &(CPUCacheInfo) {
2432	.type = UNIFIED_CACHE,
2433	.level = 2,
2434	.size = 512 * KiB,
2435	.line_size = 64,
2436	.associativity = 8,
2437	.partitions = 1,
2438	.sets = 1024,
2439	.lines_per_tag = 1,
2440	.share_level = CPU_TOPOLOGY_LEVEL_CORE,
2441	},
2442	.l3_cache = &(CPUCacheInfo) {
2443	.type = UNIFIED_CACHE,
2444	.level = 3,
2445	.size = 8 * MiB,
2446	.line_size = 64,
2447	.associativity = 16,
2448	.partitions = 1,
2449	.sets = 8192,
2450	.lines_per_tag = 1,
2451	.self_init = true,
2452	.inclusive = true,
2453	.complex_indexing = true,
2454	.share_level = CPU_TOPOLOGY_LEVEL_DIE,
2455	},
2456	};
2457
2458	static CPUCaches epyc_v4_cache_info = {
2459	.l1d_cache = &(CPUCacheInfo) {
2460	.type = DATA_CACHE,
2461	.level = 1,
2462	.size = 32 * KiB,
2463	.line_size = 64,
2464	.associativity = 8,
2465	.partitions = 1,
2466	.sets = 64,
2467	.lines_per_tag = 1,
2468	.self_init = 1,
2469	.no_invd_sharing = true,
2470	.share_level = CPU_TOPOLOGY_LEVEL_CORE,
2471	},
2472	.l1i_cache = &(CPUCacheInfo) {
2473	.type = INSTRUCTION_CACHE,
2474	.level = 1,
2475	.size = 64 * KiB,
2476	.line_size = 64,
2477	.associativity = 4,
2478	.partitions = 1,
2479	.sets = 256,
2480	.lines_per_tag = 1,
2481	.self_init = 1,
2482	.no_invd_sharing = true,
2483	.share_level = CPU_TOPOLOGY_LEVEL_CORE,
2484	},
2485	.l2_cache = &(CPUCacheInfo) {
2486	.type = UNIFIED_CACHE,
2487	.level = 2,
2488	.size = 512 * KiB,
2489	.line_size = 64,
2490	.associativity = 8,
2491	.partitions = 1,
2492	.sets = 1024,
2493	.lines_per_tag = 1,
2494	.share_level = CPU_TOPOLOGY_LEVEL_CORE,
2495	},
2496	.l3_cache = &(CPUCacheInfo) {
2497	.type = UNIFIED_CACHE,
2498	.level = 3,
2499	.size = 8 * MiB,
2500	.line_size = 64,
2501	.associativity = 16,
2502	.partitions = 1,
2503	.sets = 8192,
2504	.lines_per_tag = 1,
2505	.self_init = true,
2506	.inclusive = true,
2507	.complex_indexing = false,
2508	.share_level = CPU_TOPOLOGY_LEVEL_DIE,
2509	},
2510	};
2511
2512	static CPUCaches epyc_v5_cache_info = {
2513	.l1d_cache = &(CPUCacheInfo) {
2514	.type = DATA_CACHE,
2515	.level = 1,
2516	.size = 32 * KiB,
2517	.line_size = 64,
2518	.associativity = 8,
2519	.partitions = 1,
2520	.sets = 64,
2521	.lines_per_tag = 1,
2522	.self_init = true,
2523	.share_level = CPU_TOPOLOGY_LEVEL_CORE,
2524	},
2525	.l1i_cache = &(CPUCacheInfo) {
2526	.type = INSTRUCTION_CACHE,
2527	.level = 1,
2528	.size = 64 * KiB,
2529	.line_size = 64,
2530	.associativity = 4,
2531	.partitions = 1,
2532	.sets = 256,
2533	.lines_per_tag = 1,
2534	.self_init = true,
2535	.share_level = CPU_TOPOLOGY_LEVEL_CORE,
2536	},
2537	.l2_cache = &(CPUCacheInfo) {
2538	.type = UNIFIED_CACHE,
2539	.level = 2,
2540	.size = 512 * KiB,
2541	.line_size = 64,
2542	.associativity = 8,
2543	.partitions = 1,
2544	.sets = 1024,
2545	.lines_per_tag = 1,
2546	.self_init = true,
2547	.inclusive = true,
2548	.share_level = CPU_TOPOLOGY_LEVEL_CORE,
2549	},
2550	.l3_cache = &(CPUCacheInfo) {
2551	.type = UNIFIED_CACHE,
2552	.level = 3,
2553	.size = 8 * MiB,
2554	.line_size = 64,
2555	.associativity = 16,
2556	.partitions = 1,
2557	.sets = 8192,
2558	.lines_per_tag = 1,
2559	.self_init = true,
2560	.no_invd_sharing = true,
2561	.complex_indexing = false,
2562	.share_level = CPU_TOPOLOGY_LEVEL_DIE,
2563	},
2564	};
2565
2566	static const CPUCaches epyc_rome_cache_info = {
2567	.l1d_cache = &(CPUCacheInfo) {
2568	.type = DATA_CACHE,
2569	.level = 1,
2570	.size = 32 * KiB,
2571	.line_size = 64,
2572	.associativity = 8,
2573	.partitions = 1,
2574	.sets = 64,
2575	.lines_per_tag = 1,
2576	.self_init = 1,
2577	.no_invd_sharing = true,
2578	.share_level = CPU_TOPOLOGY_LEVEL_CORE,
2579	},
2580	.l1i_cache = &(CPUCacheInfo) {
2581	.type = INSTRUCTION_CACHE,
2582	.level = 1,
2583	.size = 32 * KiB,
2584	.line_size = 64,
2585	.associativity = 8,
2586	.partitions = 1,
2587	.sets = 64,
2588	.lines_per_tag = 1,
2589	.self_init = 1,
2590	.no_invd_sharing = true,
2591	.share_level = CPU_TOPOLOGY_LEVEL_CORE,
2592	},
2593	.l2_cache = &(CPUCacheInfo) {
2594	.type = UNIFIED_CACHE,
2595	.level = 2,
2596	.size = 512 * KiB,
2597	.line_size = 64,
2598	.associativity = 8,
2599	.partitions = 1,
2600	.sets = 1024,
2601	.lines_per_tag = 1,
2602	.share_level = CPU_TOPOLOGY_LEVEL_CORE,
2603	},
2604	.l3_cache = &(CPUCacheInfo) {
2605	.type = UNIFIED_CACHE,
2606	.level = 3,
2607	.size = 16 * MiB,
2608	.line_size = 64,
2609	.associativity = 16,
2610	.partitions = 1,
2611	.sets = 16384,
2612	.lines_per_tag = 1,
2613	.self_init = true,
2614	.inclusive = true,
2615	.complex_indexing = true,
2616	.share_level = CPU_TOPOLOGY_LEVEL_DIE,
2617	},
2618	};
2619
2620	static const CPUCaches epyc_rome_v3_cache_info = {
2621	.l1d_cache = &(CPUCacheInfo) {
2622	.type = DATA_CACHE,
2623	.level = 1,
2624	.size = 32 * KiB,
2625	.line_size = 64,
2626	.associativity = 8,
2627	.partitions = 1,
2628	.sets = 64,
2629	.lines_per_tag = 1,
2630	.self_init = 1,
2631	.no_invd_sharing = true,
2632	.share_level = CPU_TOPOLOGY_LEVEL_CORE,
2633	},
2634	.l1i_cache = &(CPUCacheInfo) {
2635	.type = INSTRUCTION_CACHE,
2636	.level = 1,
2637	.size = 32 * KiB,
2638	.line_size = 64,
2639	.associativity = 8,
2640	.partitions = 1,
2641	.sets = 64,
2642	.lines_per_tag = 1,
2643	.self_init = 1,
2644	.no_invd_sharing = true,
2645	.share_level = CPU_TOPOLOGY_LEVEL_CORE,
2646	},
2647	.l2_cache = &(CPUCacheInfo) {
2648	.type = UNIFIED_CACHE,
2649	.level = 2,
2650	.size = 512 * KiB,
2651	.line_size = 64,
2652	.associativity = 8,
2653	.partitions = 1,
2654	.sets = 1024,
2655	.lines_per_tag = 1,
2656	.share_level = CPU_TOPOLOGY_LEVEL_CORE,
2657	},
2658	.l3_cache = &(CPUCacheInfo) {
2659	.type = UNIFIED_CACHE,
2660	.level = 3,
2661	.size = 16 * MiB,
2662	.line_size = 64,
2663	.associativity = 16,
2664	.partitions = 1,
2665	.sets = 16384,
2666	.lines_per_tag = 1,
2667	.self_init = true,
2668	.inclusive = true,
2669	.complex_indexing = false,
2670	.share_level = CPU_TOPOLOGY_LEVEL_DIE,
2671	},
2672	};
2673
2674	static const CPUCaches epyc_rome_v5_cache_info = {
2675	.l1d_cache = &(CPUCacheInfo) {
2676	.type = DATA_CACHE,
2677	.level = 1,
2678	.size = 32 * KiB,
2679	.line_size = 64,
2680	.associativity = 8,
2681	.partitions = 1,
2682	.sets = 64,
2683	.lines_per_tag = 1,
2684	.self_init = true,
2685	.share_level = CPU_TOPOLOGY_LEVEL_CORE,
2686	},
2687	.l1i_cache = &(CPUCacheInfo) {
2688	.type = INSTRUCTION_CACHE,
2689	.level = 1,
2690	.size = 32 * KiB,
2691	.line_size = 64,
2692	.associativity = 8,
2693	.partitions = 1,
2694	.sets = 64,
2695	.lines_per_tag = 1,
2696	.self_init = true,
2697	.share_level = CPU_TOPOLOGY_LEVEL_CORE,
2698	},
2699	.l2_cache = &(CPUCacheInfo) {
2700	.type = UNIFIED_CACHE,
2701	.level = 2,
2702	.size = 512 * KiB,
2703	.line_size = 64,
2704	.associativity = 8,
2705	.partitions = 1,
2706	.sets = 1024,
2707	.lines_per_tag = 1,
2708	.self_init = true,
2709	.inclusive = true,
2710	.share_level = CPU_TOPOLOGY_LEVEL_CORE,
2711	},
2712	.l3_cache = &(CPUCacheInfo) {
2713	.type = UNIFIED_CACHE,
2714	.level = 3,
2715	.size = 16 * MiB,
2716	.line_size = 64,
2717	.associativity = 16,
2718	.partitions = 1,
2719	.sets = 16384,
2720	.lines_per_tag = 1,
2721	.self_init = true,
2722	.no_invd_sharing = true,
2723	.complex_indexing = false,
2724	.share_level = CPU_TOPOLOGY_LEVEL_DIE,
2725	},
2726	};
2727
2728	static const CPUCaches epyc_milan_cache_info = {
2729	.l1d_cache = &(CPUCacheInfo) {
2730	.type = DATA_CACHE,
2731	.level = 1,
2732	.size = 32 * KiB,
2733	.line_size = 64,
2734	.associativity = 8,
2735	.partitions = 1,
2736	.sets = 64,
2737	.lines_per_tag = 1,
2738	.self_init = 1,
2739	.no_invd_sharing = true,
2740	.share_level = CPU_TOPOLOGY_LEVEL_CORE,
2741	},
2742	.l1i_cache = &(CPUCacheInfo) {
2743	.type = INSTRUCTION_CACHE,
2744	.level = 1,
2745	.size = 32 * KiB,
2746	.line_size = 64,
2747	.associativity = 8,
2748	.partitions = 1,
2749	.sets = 64,
2750	.lines_per_tag = 1,
2751	.self_init = 1,
2752	.no_invd_sharing = true,
2753	.share_level = CPU_TOPOLOGY_LEVEL_CORE,
2754	},
2755	.l2_cache = &(CPUCacheInfo) {
2756	.type = UNIFIED_CACHE,
2757	.level = 2,
2758	.size = 512 * KiB,
2759	.line_size = 64,
2760	.associativity = 8,
2761	.partitions = 1,
2762	.sets = 1024,
2763	.lines_per_tag = 1,
2764	.share_level = CPU_TOPOLOGY_LEVEL_CORE,
2765	},
2766	.l3_cache = &(CPUCacheInfo) {
2767	.type = UNIFIED_CACHE,
2768	.level = 3,
2769	.size = 32 * MiB,
2770	.line_size = 64,
2771	.associativity = 16,
2772	.partitions = 1,
2773	.sets = 32768,
2774	.lines_per_tag = 1,
2775	.self_init = true,
2776	.inclusive = true,
2777	.complex_indexing = true,
2778	.share_level = CPU_TOPOLOGY_LEVEL_DIE,
2779	},
2780	};
2781
2782	static const CPUCaches epyc_milan_v2_cache_info = {
2783	.l1d_cache = &(CPUCacheInfo) {
2784	.type = DATA_CACHE,
2785	.level = 1,
2786	.size = 32 * KiB,
2787	.line_size = 64,
2788	.associativity = 8,
2789	.partitions = 1,
2790	.sets = 64,
2791	.lines_per_tag = 1,
2792	.self_init = 1,
2793	.no_invd_sharing = true,
2794	.share_level = CPU_TOPOLOGY_LEVEL_CORE,
2795	},
2796	.l1i_cache = &(CPUCacheInfo) {
2797	.type = INSTRUCTION_CACHE,
2798	.level = 1,
2799	.size = 32 * KiB,
2800	.line_size = 64,
2801	.associativity = 8,
2802	.partitions = 1,
2803	.sets = 64,
2804	.lines_per_tag = 1,
2805	.self_init = 1,
2806	.no_invd_sharing = true,
2807	.share_level = CPU_TOPOLOGY_LEVEL_CORE,
2808	},
2809	.l2_cache = &(CPUCacheInfo) {
2810	.type = UNIFIED_CACHE,
2811	.level = 2,
2812	.size = 512 * KiB,
2813	.line_size = 64,
2814	.associativity = 8,
2815	.partitions = 1,
2816	.sets = 1024,
2817	.lines_per_tag = 1,
2818	.share_level = CPU_TOPOLOGY_LEVEL_CORE,
2819	},
2820	.l3_cache = &(CPUCacheInfo) {
2821	.type = UNIFIED_CACHE,
2822	.level = 3,
2823	.size = 32 * MiB,
2824	.line_size = 64,
2825	.associativity = 16,
2826	.partitions = 1,
2827	.sets = 32768,
2828	.lines_per_tag = 1,
2829	.self_init = true,
2830	.inclusive = true,
2831	.complex_indexing = false,
2832	.share_level = CPU_TOPOLOGY_LEVEL_DIE,
2833	},
2834	};
2835
2836	static const CPUCaches epyc_milan_v3_cache_info = {
2837	.l1d_cache = &(CPUCacheInfo) {
2838	.type = DATA_CACHE,
2839	.level = 1,
2840	.size = 32 * KiB,
2841	.line_size = 64,
2842	.associativity = 8,
2843	.partitions = 1,
2844	.sets = 64,
2845	.lines_per_tag = 1,
2846	.self_init = true,
2847	.share_level = CPU_TOPOLOGY_LEVEL_CORE,
2848	},
2849	.l1i_cache = &(CPUCacheInfo) {
2850	.type = INSTRUCTION_CACHE,
2851	.level = 1,
2852	.size = 32 * KiB,
2853	.line_size = 64,
2854	.associativity = 8,
2855	.partitions = 1,
2856	.sets = 64,
2857	.lines_per_tag = 1,
2858	.self_init = true,
2859	.share_level = CPU_TOPOLOGY_LEVEL_CORE,
2860	},
2861	.l2_cache = &(CPUCacheInfo) {
2862	.type = UNIFIED_CACHE,
2863	.level = 2,
2864	.size = 512 * KiB,
2865	.line_size = 64,
2866	.associativity = 8,
2867	.partitions = 1,
2868	.sets = 1024,
2869	.lines_per_tag = 1,
2870	.self_init = true,
2871	.inclusive = true,
2872	.share_level = CPU_TOPOLOGY_LEVEL_CORE,
2873	},
2874	.l3_cache = &(CPUCacheInfo) {
2875	.type = UNIFIED_CACHE,
2876	.level = 3,
2877	.size = 32 * MiB,
2878	.line_size = 64,
2879	.associativity = 16,
2880	.partitions = 1,
2881	.sets = 32768,
2882	.lines_per_tag = 1,
2883	.self_init = true,
2884	.no_invd_sharing = true,
2885	.complex_indexing = false,
2886	.share_level = CPU_TOPOLOGY_LEVEL_DIE,
2887	},
2888	};
2889
2890	static const CPUCaches epyc_genoa_cache_info = {
2891	.l1d_cache = &(CPUCacheInfo) {
2892	.type = DATA_CACHE,
2893	.level = 1,
2894	.size = 32 * KiB,
2895	.line_size = 64,
2896	.associativity = 8,
2897	.partitions = 1,
2898	.sets = 64,
2899	.lines_per_tag = 1,
2900	.self_init = 1,
2901	.no_invd_sharing = true,
2902	.share_level = CPU_TOPOLOGY_LEVEL_CORE,
2903	},
2904	.l1i_cache = &(CPUCacheInfo) {
2905	.type = INSTRUCTION_CACHE,
2906	.level = 1,
2907	.size = 32 * KiB,
2908	.line_size = 64,
2909	.associativity = 8,
2910	.partitions = 1,
2911	.sets = 64,
2912	.lines_per_tag = 1,
2913	.self_init = 1,
2914	.no_invd_sharing = true,
2915	.share_level = CPU_TOPOLOGY_LEVEL_CORE,
2916	},
2917	.l2_cache = &(CPUCacheInfo) {
2918	.type = UNIFIED_CACHE,
2919	.level = 2,
2920	.size = 1 * MiB,
2921	.line_size = 64,
2922	.associativity = 8,
2923	.partitions = 1,
2924	.sets = 2048,
2925	.lines_per_tag = 1,
2926	.share_level = CPU_TOPOLOGY_LEVEL_CORE,
2927	},
2928	.l3_cache = &(CPUCacheInfo) {
2929	.type = UNIFIED_CACHE,
2930	.level = 3,
2931	.size = 32 * MiB,
2932	.line_size = 64,
2933	.associativity = 16,
2934	.partitions = 1,
2935	.sets = 32768,
2936	.lines_per_tag = 1,
2937	.self_init = true,
2938	.inclusive = true,
2939	.complex_indexing = false,
2940	.share_level = CPU_TOPOLOGY_LEVEL_DIE,
2941	},
2942	};
2943
2944	static const CPUCaches epyc_genoa_v2_cache_info = {
2945	.l1d_cache = &(CPUCacheInfo) {
2946	.type = DATA_CACHE,
2947	.level = 1,
2948	.size = 32 * KiB,
2949	.line_size = 64,
2950	.associativity = 8,
2951	.partitions = 1,
2952	.sets = 64,
2953	.lines_per_tag = 1,
2954	.self_init = true,
2955	.share_level = CPU_TOPOLOGY_LEVEL_CORE,
2956	},
2957	.l1i_cache = &(CPUCacheInfo) {
2958	.type = INSTRUCTION_CACHE,
2959	.level = 1,
2960	.size = 32 * KiB,
2961	.line_size = 64,
2962	.associativity = 8,
2963	.partitions = 1,
2964	.sets = 64,
2965	.lines_per_tag = 1,
2966	.self_init = true,
2967	.share_level = CPU_TOPOLOGY_LEVEL_CORE,
2968	},
2969	.l2_cache = &(CPUCacheInfo) {
2970	.type = UNIFIED_CACHE,
2971	.level = 2,
2972	.size = 1 * MiB,
2973	.line_size = 64,
2974	.associativity = 8,
2975	.partitions = 1,
2976	.sets = 2048,
2977	.lines_per_tag = 1,
2978	.self_init = true,
2979	.inclusive = true,
2980	.share_level = CPU_TOPOLOGY_LEVEL_CORE,
2981	},
2982	.l3_cache = &(CPUCacheInfo) {
2983	.type = UNIFIED_CACHE,
2984	.level = 3,
2985	.size = 32 * MiB,
2986	.line_size = 64,
2987	.associativity = 16,
2988	.partitions = 1,
2989	.sets = 32768,
2990	.lines_per_tag = 1,
2991	.self_init = true,
2992	.no_invd_sharing = true,
2993	.complex_indexing = false,
2994	.share_level = CPU_TOPOLOGY_LEVEL_DIE,
2995	},
2996	};
2997
2998	static const CPUCaches epyc_turin_cache_info = {
2999	.l1d_cache = &(CPUCacheInfo) {
3000	.type = DATA_CACHE,
3001	.level = 1,
3002	.size = 48 * KiB,
3003	.line_size = 64,
3004	.associativity = 12,
3005	.partitions = 1,
3006	.sets = 64,
3007	.lines_per_tag = 1,
3008	.self_init = true,
3009	.share_level = CPU_TOPOLOGY_LEVEL_CORE,
3010	},
3011	.l1i_cache = &(CPUCacheInfo) {
3012	.type = INSTRUCTION_CACHE,
3013	.level = 1,
3014	.size = 32 * KiB,
3015	.line_size = 64,
3016	.associativity = 8,
3017	.partitions = 1,
3018	.sets = 64,
3019	.lines_per_tag = 1,
3020	.self_init = true,
3021	.share_level = CPU_TOPOLOGY_LEVEL_CORE,
3022	},
3023	.l2_cache = &(CPUCacheInfo) {
3024	.type = UNIFIED_CACHE,
3025	.level = 2,
3026	.size = 1 * MiB,
3027	.line_size = 64,
3028	.associativity = 16,
3029	.partitions = 1,
3030	.sets = 1024,
3031	.lines_per_tag = 1,
3032	.self_init = true,
3033	.inclusive = true,
3034	.share_level = CPU_TOPOLOGY_LEVEL_CORE,
3035	},
3036	.l3_cache = &(CPUCacheInfo) {
3037	.type = UNIFIED_CACHE,
3038	.level = 3,
3039	.size = 32 * MiB,
3040	.line_size = 64,
3041	.associativity = 16,
3042	.partitions = 1,
3043	.sets = 32768,
3044	.lines_per_tag = 1,
3045	.self_init = true,
3046	.no_invd_sharing = true,
3047	.complex_indexing = false,
3048	.share_level = CPU_TOPOLOGY_LEVEL_DIE,
3049	}
3050	};
3051
3052	static const CPUCaches xeon_spr_cache_info = {
3053	.l1d_cache = &(CPUCacheInfo) {
3054	/* CPUID 0x4.0x0.EAX */
3055	.type = DATA_CACHE,
3056	.level = 1,
3057	.self_init = true,
3058
3059	/* CPUID 0x4.0x0.EBX */
3060	.line_size = 64,
3061	.partitions = 1,
3062	.associativity = 12,
3063
3064	/* CPUID 0x4.0x0.ECX */
3065	.sets = 64,
3066
3067	/* CPUID 0x4.0x0.EDX */
3068	.no_invd_sharing = false,
3069	.inclusive = false,
3070	.complex_indexing = false,
3071
3072	.size = 48 * KiB,
3073	.share_level = CPU_TOPOLOGY_LEVEL_CORE,
3074	},
3075	.l1i_cache = &(CPUCacheInfo) {
3076	/* CPUID 0x4.0x1.EAX */
3077	.type = INSTRUCTION_CACHE,
3078	.level = 1,
3079	.self_init = true,
3080
3081	/* CPUID 0x4.0x1.EBX */
3082	.line_size = 64,
3083	.partitions = 1,
3084	.associativity = 8,
3085
3086	/* CPUID 0x4.0x1.ECX */
3087	.sets = 64,
3088
3089	/* CPUID 0x4.0x1.EDX */
3090	.no_invd_sharing = false,
3091	.inclusive = false,
3092	.complex_indexing = false,
3093
3094	.size = 32 * KiB,
3095	.share_level = CPU_TOPOLOGY_LEVEL_CORE,
3096	},
3097	.l2_cache = &(CPUCacheInfo) {
3098	/* CPUID 0x4.0x2.EAX */
3099	.type = UNIFIED_CACHE,
3100	.level = 2,
3101	.self_init = true,
3102
3103	/* CPUID 0x4.0x2.EBX */
3104	.line_size = 64,
3105	.partitions = 1,
3106	.associativity = 16,
3107
3108	/* CPUID 0x4.0x2.ECX */
3109	.sets = 2048,
3110
3111	/* CPUID 0x4.0x2.EDX */
3112	.no_invd_sharing = false,
3113	.inclusive = false,
3114	.complex_indexing = false,
3115
3116	.size = 2 * MiB,
3117	.share_level = CPU_TOPOLOGY_LEVEL_CORE,
3118	},
3119	.l3_cache = &(CPUCacheInfo) {
3120	/* CPUID 0x4.0x3.EAX */
3121	.type = UNIFIED_CACHE,
3122	.level = 3,
3123	.self_init = true,
3124
3125	/* CPUID 0x4.0x3.EBX */
3126	.line_size = 64,
3127	.partitions = 1,
3128	.associativity = 15,
3129
3130	/* CPUID 0x4.0x3.ECX */
3131	.sets = 65536,
3132
3133	/* CPUID 0x4.0x3.EDX */
3134	.no_invd_sharing = false,
3135	.inclusive = false,
3136	.complex_indexing = true,
3137
3138	.size = 60 * MiB,
3139	.share_level = CPU_TOPOLOGY_LEVEL_SOCKET,
3140	},
3141	};
3142
3143	static const CPUCaches xeon_gnr_cache_info = {
3144	.l1d_cache = &(CPUCacheInfo) {
3145	/* CPUID 0x4.0x0.EAX */
3146	.type = DATA_CACHE,
3147	.level = 1,
3148	.self_init = true,
3149
3150	/* CPUID 0x4.0x0.EBX */
3151	.line_size = 64,
3152	.partitions = 1,
3153	.associativity = 12,
3154
3155	/* CPUID 0x4.0x0.ECX */
3156	.sets = 64,
3157
3158	/* CPUID 0x4.0x0.EDX */
3159	.no_invd_sharing = false,
3160	.inclusive = false,
3161	.complex_indexing = false,
3162
3163	.size = 48 * KiB,
3164	.share_level = CPU_TOPOLOGY_LEVEL_CORE,
3165	},
3166	.l1i_cache = &(CPUCacheInfo) {
3167	/* CPUID 0x4.0x1.EAX */
3168	.type = INSTRUCTION_CACHE,
3169	.level = 1,
3170	.self_init = true,
3171
3172	/* CPUID 0x4.0x1.EBX */
3173	.line_size = 64,
3174	.partitions = 1,
3175	.associativity = 16,
3176
3177	/* CPUID 0x4.0x1.ECX */
3178	.sets = 64,
3179
3180	/* CPUID 0x4.0x1.EDX */
3181	.no_invd_sharing = false,
3182	.inclusive = false,
3183	.complex_indexing = false,
3184
3185	.size = 64 * KiB,
3186	.share_level = CPU_TOPOLOGY_LEVEL_CORE,
3187	},
3188	.l2_cache = &(CPUCacheInfo) {
3189	/* CPUID 0x4.0x2.EAX */
3190	.type = UNIFIED_CACHE,
3191	.level = 2,
3192	.self_init = true,
3193
3194	/* CPUID 0x4.0x2.EBX */
3195	.line_size = 64,
3196	.partitions = 1,
3197	.associativity = 16,
3198
3199	/* CPUID 0x4.0x2.ECX */
3200	.sets = 2048,
3201
3202	/* CPUID 0x4.0x2.EDX */
3203	.no_invd_sharing = false,
3204	.inclusive = false,
3205	.complex_indexing = false,
3206
3207	.size = 2 * MiB,
3208	.share_level = CPU_TOPOLOGY_LEVEL_CORE,
3209	},
3210	.l3_cache = &(CPUCacheInfo) {
3211	/* CPUID 0x4.0x3.EAX */
3212	.type = UNIFIED_CACHE,
3213	.level = 3,
3214	.self_init = true,
3215
3216	/* CPUID 0x4.0x3.EBX */
3217	.line_size = 64,
3218	.partitions = 1,
3219	.associativity = 16,
3220
3221	/* CPUID 0x4.0x3.ECX */
3222	.sets = 294912,
3223
3224	/* CPUID 0x4.0x3.EDX */
3225	.no_invd_sharing = false,
3226	.inclusive = false,
3227	.complex_indexing = true,
3228
3229	.size = 288 * MiB,
3230	.share_level = CPU_TOPOLOGY_LEVEL_SOCKET,
3231	},
3232	};
3233
3234	static const CPUCaches xeon_srf_cache_info = {
3235	.l1d_cache = &(CPUCacheInfo) {
3236	/* CPUID 0x4.0x0.EAX */
3237	.type = DATA_CACHE,
3238	.level = 1,
3239	.self_init = true,
3240
3241	/* CPUID 0x4.0x0.EBX */
3242	.line_size = 64,
3243	.partitions = 1,
3244	.associativity = 8,
3245
3246	/* CPUID 0x4.0x0.ECX */
3247	.sets = 64,
3248
3249	/* CPUID 0x4.0x0.EDX */
3250	.no_invd_sharing = false,
3251	.inclusive = false,
3252	.complex_indexing = false,
3253
3254	.size = 32 * KiB,
3255	.share_level = CPU_TOPOLOGY_LEVEL_CORE,
3256	},
3257	.l1i_cache = &(CPUCacheInfo) {
3258	/* CPUID 0x4.0x1.EAX */
3259	.type = INSTRUCTION_CACHE,
3260	.level = 1,
3261	.self_init = true,
3262
3263	/* CPUID 0x4.0x1.EBX */
3264	.line_size = 64,
3265	.partitions = 1,
3266	.associativity = 8,
3267
3268	/* CPUID 0x4.0x1.ECX */
3269	.sets = 128,
3270
3271	/* CPUID 0x4.0x1.EDX */
3272	.no_invd_sharing = false,
3273	.inclusive = false,
3274	.complex_indexing = false,
3275
3276	.size = 64 * KiB,
3277	.share_level = CPU_TOPOLOGY_LEVEL_CORE,
3278	},
3279	.l2_cache = &(CPUCacheInfo) {
3280	/* CPUID 0x4.0x2.EAX */
3281	.type = UNIFIED_CACHE,
3282	.level = 2,
3283	.self_init = true,
3284
3285	/* CPUID 0x4.0x2.EBX */
3286	.line_size = 64,
3287	.partitions = 1,
3288	.associativity = 16,
3289
3290	/* CPUID 0x4.0x2.ECX */
3291	.sets = 4096,
3292
3293	/* CPUID 0x4.0x2.EDX */
3294	.no_invd_sharing = false,
3295	.inclusive = false,
3296	.complex_indexing = false,
3297
3298	.size = 4 * MiB,
3299	.share_level = CPU_TOPOLOGY_LEVEL_MODULE,
3300	},
3301	.l3_cache = &(CPUCacheInfo) {
3302	/* CPUID 0x4.0x3.EAX */
3303	.type = UNIFIED_CACHE,
3304	.level = 3,
3305	.self_init = true,
3306
3307	/* CPUID 0x4.0x3.EBX */
3308	.line_size = 64,
3309	.partitions = 1,
3310	.associativity = 12,
3311
3312	/* CPUID 0x4.0x3.ECX */
3313	.sets = 147456,
3314
3315	/* CPUID 0x4.0x3.EDX */
3316	.no_invd_sharing = false,
3317	.inclusive = false,
3318	.complex_indexing = true,
3319
3320	.size = 108 * MiB,
3321	.share_level = CPU_TOPOLOGY_LEVEL_SOCKET,
3322	},
3323	};
3324
3325	static const CPUCaches xeon_cwf_cache_info = {
3326	.l1d_cache = &(CPUCacheInfo) {
3327	/* CPUID 0x4.0x0.EAX */
3328	.type = DATA_CACHE,
3329	.level = 1,
3330	.self_init = true,
3331
3332	/* CPUID 0x4.0x0.EBX */
3333	.line_size = 64,
3334	.partitions = 1,
3335	.associativity = 8,
3336
3337	/* CPUID 0x4.0x0.ECX */
3338	.sets = 64,
3339
3340	/* CPUID 0x4.0x0.EDX */
3341	.no_invd_sharing = false,
3342	.inclusive = false,
3343	.complex_indexing = false,
3344
3345	.size = 32 * KiB,
3346	.share_level = CPU_TOPOLOGY_LEVEL_CORE,
3347	},
3348	.l1i_cache = &(CPUCacheInfo) {
3349	/* CPUID 0x4.0x1.EAX */
3350	.type = INSTRUCTION_CACHE,
3351	.level = 1,
3352	.self_init = true,
3353
3354	/* CPUID 0x4.0x1.EBX */
3355	.line_size = 64,
3356	.partitions = 1,
3357	.associativity = 8,
3358
3359	/* CPUID 0x4.0x1.ECX */
3360	.sets = 128,
3361
3362	/* CPUID 0x4.0x1.EDX */
3363	.no_invd_sharing = false,
3364	.inclusive = false,
3365	.complex_indexing = false,
3366
3367	.size = 64 * KiB,
3368	.share_level = CPU_TOPOLOGY_LEVEL_CORE,
3369	},
3370	.l2_cache = &(CPUCacheInfo) {
3371	/* CPUID 0x4.0x2.EAX */
3372	.type = UNIFIED_CACHE,
3373	.level = 2,
3374	.self_init = true,
3375
3376	/* CPUID 0x4.0x2.EBX */
3377	.line_size = 64,
3378	.partitions = 1,
3379	.associativity = 16,
3380
3381	/* CPUID 0x4.0x2.ECX */
3382	.sets = 4096,
3383
3384	/* CPUID 0x4.0x2.EDX */
3385	.no_invd_sharing = false,
3386	.inclusive = false,
3387	.complex_indexing = false,
3388
3389	.size = 4 * MiB,
3390	.share_level = CPU_TOPOLOGY_LEVEL_MODULE,
3391	},
3392	.l3_cache = &(CPUCacheInfo) {
3393	/* CPUID 0x4.0x3.EAX */
3394	.type = UNIFIED_CACHE,
3395	.level = 3,
3396	.self_init = true,
3397
3398	/* CPUID 0x4.0x3.EBX */
3399	.line_size = 64,
3400	.partitions = 1,
3401	.associativity = 16,
3402
3403	/* CPUID 0x4.0x3.ECX */
3404	.sets = 540672,
3405
3406	/* CPUID 0x4.0x3.EDX */
3407	.no_invd_sharing = false,
3408	.inclusive = false,
3409	.complex_indexing = true,
3410
3411	.size = 528 * MiB,
3412	.share_level = CPU_TOPOLOGY_LEVEL_SOCKET,
3413	},
3414	};
3415
3416	static const CPUCaches yongfeng_cache_info = {
3417	.l1d_cache = &(CPUCacheInfo) {
3418	/* CPUID 0x4.0x0.EAX */
3419	.type = DATA_CACHE,
3420	.level = 1,
3421	.self_init = true,
3422
3423	/* CPUID 0x4.0x0.EBX */
3424	.line_size = 64,
3425	.partitions = 1,
3426	.associativity = 8,
3427
3428	/* CPUID 0x4.0x0.ECX */
3429	.sets = 64,
3430
3431	/* CPUID 0x4.0x0.EDX */
3432	.no_invd_sharing = false,
3433	.inclusive = false,
3434	.complex_indexing = false,
3435
3436	/* CPUID 0x80000005.ECX */
3437	.lines_per_tag = 1,
3438	.size = 32 * KiB,
3439
3440	.share_level = CPU_TOPOLOGY_LEVEL_CORE,
3441	},
3442	.l1i_cache = &(CPUCacheInfo) {
3443	/* CPUID 0x4.0x1.EAX */
3444	.type = INSTRUCTION_CACHE,
3445	.level = 1,
3446	.self_init = true,
3447
3448	/* CPUID 0x4.0x1.EBX */
3449	.line_size = 64,
3450	.partitions = 1,
3451	.associativity = 16,
3452
3453	/* CPUID 0x4.0x1.ECX */
3454	.sets = 64,
3455
3456	/* CPUID 0x4.0x1.EDX */
3457	.no_invd_sharing = false,
3458	.inclusive = false,
3459	.complex_indexing = false,
3460
3461	/* CPUID 0x80000005.EDX */
3462	.lines_per_tag = 1,
3463	.size = 64 * KiB,
3464
3465	.share_level = CPU_TOPOLOGY_LEVEL_CORE,
3466	},
3467	.l2_cache = &(CPUCacheInfo) {
3468	/* CPUID 0x4.0x2.EAX */
3469	.type = UNIFIED_CACHE,
3470	.level = 2,
3471	.self_init = true,
3472
3473	/* CPUID 0x4.0x2.EBX */
3474	.line_size = 64,
3475	.partitions = 1,
3476	.associativity = 8,
3477
3478	/* CPUID 0x4.0x2.ECX */
3479	.sets = 512,
3480
3481	/* CPUID 0x4.0x2.EDX */
3482	.no_invd_sharing = false,
3483	.inclusive = true,
3484	.complex_indexing = false,
3485
3486	/* CPUID 0x80000006.ECX */
3487	.size = 256 * KiB,
3488
3489	.share_level = CPU_TOPOLOGY_LEVEL_CORE,
3490	},
3491	.l3_cache = &(CPUCacheInfo) {
3492	/* CPUID 0x4.0x3.EAX */
3493	.type = UNIFIED_CACHE,
3494	.level = 3,
3495	.self_init = true,
3496
3497	/* CPUID 0x4.0x3.EBX */
3498	.line_size = 64,
3499	.partitions = 1,
3500	.associativity = 16,
3501
3502	/* CPUID 0x4.0x3.ECX */
3503	.sets = 8192,
3504
3505	/* CPUID 0x4.0x3.EDX */
3506	.no_invd_sharing = true,
3507	.inclusive = true,
3508	.complex_indexing = false,
3509
3510	.size = 8 * MiB,
3511	.share_level = CPU_TOPOLOGY_LEVEL_DIE,
3512	},
3513	};
3514
3515	/* The following VMX features are not supported by KVM and are left out in the
3516	* CPU definitions:
3517	*
3518	* Dual-monitor support (all processors)
3519	* Entry to SMM
3520	* Deactivate dual-monitor treatment
3521	* Number of CR3-target values
3522	* Shutdown activity state
3523	* Wait-for-SIPI activity state
3524	* PAUSE-loop exiting (Westmere and newer)
3525	* EPT-violation #VE (Broadwell and newer)
3526	* Inject event with insn length=0 (Skylake and newer)
3527	* Conceal non-root operation from PT
3528	* Conceal VM exits from PT
3529	* Conceal VM entries from PT
3530	* Enable ENCLS exiting
3531	* Mode-based execute control (XS/XU)
3532	* TSC scaling (Skylake Server and newer)
3533	* GPA translation for PT (IceLake and newer)
3534	* User wait and pause
3535	* ENCLV exiting
3536	* Load IA32_RTIT_CTL
3537	* Clear IA32_RTIT_CTL
3538	* Advanced VM-exit information for EPT violations
3539	* Sub-page write permissions
3540	* PT in VMX operation
3541	*/
3542
3543	static const X86CPUDefinition builtin_x86_defs[] = {
3544	{
3545	.name = "qemu64",
3546	.level = 0xd,
3547	.vendor = CPUID_VENDOR_AMD,
3548	.family = 15,
3549	.model = 107,
3550	.stepping = 1,
3551	.features[FEAT_1_EDX] =
3552	PPRO_FEATURES \|
3553	CPUID_MTRR \| CPUID_CLFLUSH \| CPUID_MCA \|
3554	CPUID_PSE36,
3555	.features[FEAT_1_ECX] =
3556	CPUID_EXT_SSE3 \| CPUID_EXT_CX16,
3557	.features[FEAT_8000_0001_EDX] =
3558	CPUID_EXT2_LM \| CPUID_EXT2_SYSCALL \| CPUID_EXT2_NX,
3559	.features[FEAT_8000_0001_ECX] =
3560	CPUID_EXT3_LAHF_LM \| CPUID_EXT3_SVM,
3561	.xlevel = 0x8000000A,
3562	.model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
3563	},
3564	{
3565	.name = "phenom",
3566	.level = 5,
3567	.vendor = CPUID_VENDOR_AMD,
3568	.family = 16,
3569	.model = 2,
3570	.stepping = 3,
3571	/* Missing: CPUID_HT */
3572	.features[FEAT_1_EDX] =
3573	PPRO_FEATURES \|
3574	CPUID_MTRR \| CPUID_CLFLUSH \| CPUID_MCA \|
3575	CPUID_PSE36 \| CPUID_VME,
3576	.features[FEAT_1_ECX] =
3577	CPUID_EXT_SSE3 \| CPUID_EXT_MONITOR \| CPUID_EXT_CX16 \|
3578	CPUID_EXT_POPCNT,
3579	.features[FEAT_8000_0001_EDX] =
3580	CPUID_EXT2_LM \| CPUID_EXT2_SYSCALL \| CPUID_EXT2_NX \|
3581	CPUID_EXT2_3DNOW \| CPUID_EXT2_3DNOWEXT \| CPUID_EXT2_MMXEXT \|
3582	CPUID_EXT2_FFXSR \| CPUID_EXT2_PDPE1GB \| CPUID_EXT2_RDTSCP,
3583	/* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
3584	CPUID_EXT3_CR8LEG,
3585	CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
3586	CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
3587	.features[FEAT_8000_0001_ECX] =
3588	CPUID_EXT3_LAHF_LM \| CPUID_EXT3_SVM \|
3589	CPUID_EXT3_ABM \| CPUID_EXT3_SSE4A,
3590	/* Missing: CPUID_SVM_LBRV */
3591	.features[FEAT_SVM] =
3592	CPUID_SVM_NPT,
3593	.xlevel = 0x8000001A,
3594	.model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
3595	},
3596	{
3597	.name = "core2duo",
3598	.level = 10,
3599	.vendor = CPUID_VENDOR_INTEL,
3600	.family = 6,
3601	.model = 15,
3602	.stepping = 11,
3603	/* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
3604	.features[FEAT_1_EDX] =
3605	PPRO_FEATURES \|
3606	CPUID_MTRR \| CPUID_CLFLUSH \| CPUID_MCA \|
3607	CPUID_PSE36 \| CPUID_VME \| CPUID_ACPI \| CPUID_SS,
3608	/* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST,
3609	* CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */
3610	.features[FEAT_1_ECX] =
3611	CPUID_EXT_SSE3 \| CPUID_EXT_MONITOR \| CPUID_EXT_SSSE3 \|
3612	CPUID_EXT_CX16,
3613	.features[FEAT_8000_0001_EDX] =
3614	CPUID_EXT2_LM \| CPUID_EXT2_SYSCALL \| CPUID_EXT2_NX,
3615	.features[FEAT_8000_0001_ECX] =
3616	CPUID_EXT3_LAHF_LM,
3617	.features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS,
3618	.features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
3619	.features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
3620	.features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
3621	.features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK \|
3622	VMX_PIN_BASED_NMI_EXITING \| VMX_PIN_BASED_VIRTUAL_NMIS,
3623	.features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING \|
3624	VMX_CPU_BASED_USE_TSC_OFFSETING \| VMX_CPU_BASED_HLT_EXITING \|
3625	VMX_CPU_BASED_INVLPG_EXITING \| VMX_CPU_BASED_MWAIT_EXITING \|
3626	VMX_CPU_BASED_RDPMC_EXITING \| VMX_CPU_BASED_RDTSC_EXITING \|
3627	VMX_CPU_BASED_CR8_LOAD_EXITING \| VMX_CPU_BASED_CR8_STORE_EXITING \|
3628	VMX_CPU_BASED_TPR_SHADOW \| VMX_CPU_BASED_MOV_DR_EXITING \|
3629	VMX_CPU_BASED_UNCOND_IO_EXITING \| VMX_CPU_BASED_USE_IO_BITMAPS \|
3630	VMX_CPU_BASED_MONITOR_EXITING \| VMX_CPU_BASED_PAUSE_EXITING \|
3631	VMX_CPU_BASED_VIRTUAL_NMI_PENDING \| VMX_CPU_BASED_USE_MSR_BITMAPS \|
3632	VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3633	.features[FEAT_VMX_SECONDARY_CTLS] =
3634	VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES,
3635	.xlevel = 0x80000008,
3636	.model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
3637	},
3638	{
3639	.name = "kvm64",
3640	.level = 0xd,
3641	.vendor = CPUID_VENDOR_INTEL,
3642	.family = 15,
3643	.model = 6,
3644	.stepping = 1,
3645	/* Missing: CPUID_HT */
3646	.features[FEAT_1_EDX] =
3647	PPRO_FEATURES \| CPUID_VME \|
3648	CPUID_MTRR \| CPUID_CLFLUSH \| CPUID_MCA \|
3649	CPUID_PSE36,
3650	/* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
3651	.features[FEAT_1_ECX] =
3652	CPUID_EXT_SSE3 \| CPUID_EXT_CX16,
3653	/* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
3654	.features[FEAT_8000_0001_EDX] =
3655	CPUID_EXT2_LM \| CPUID_EXT2_SYSCALL \| CPUID_EXT2_NX,
3656	/* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
3657	CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
3658	CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
3659	CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
3660	.features[FEAT_8000_0001_ECX] =
3661	0,
3662	/* VMX features from Cedar Mill/Prescott */
3663	.features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
3664	.features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
3665	.features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
3666	.features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK \|
3667	VMX_PIN_BASED_NMI_EXITING,
3668	.features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING \|
3669	VMX_CPU_BASED_USE_TSC_OFFSETING \| VMX_CPU_BASED_HLT_EXITING \|
3670	VMX_CPU_BASED_INVLPG_EXITING \| VMX_CPU_BASED_MWAIT_EXITING \|
3671	VMX_CPU_BASED_RDPMC_EXITING \| VMX_CPU_BASED_RDTSC_EXITING \|
3672	VMX_CPU_BASED_CR8_LOAD_EXITING \| VMX_CPU_BASED_CR8_STORE_EXITING \|
3673	VMX_CPU_BASED_TPR_SHADOW \| VMX_CPU_BASED_MOV_DR_EXITING \|
3674	VMX_CPU_BASED_UNCOND_IO_EXITING \| VMX_CPU_BASED_USE_IO_BITMAPS \|
3675	VMX_CPU_BASED_MONITOR_EXITING \| VMX_CPU_BASED_PAUSE_EXITING,
3676	.xlevel = 0x80000008,
3677	.model_id = "Common KVM processor"
3678	},
3679	{
3680	.name = "qemu32",
3681	.level = 4,
3682	.vendor = CPUID_VENDOR_INTEL,
3683	.family = 6,
3684	.model = 6,
3685	.stepping = 3,
3686	.features[FEAT_1_EDX] =
3687	PPRO_FEATURES,
3688	.features[FEAT_1_ECX] =
3689	CPUID_EXT_SSE3,
3690	.xlevel = 0x80000004,
3691	.model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
3692	},
3693	{
3694	.name = "kvm32",
3695	.level = 5,
3696	.vendor = CPUID_VENDOR_INTEL,
3697	.family = 15,
3698	.model = 6,
3699	.stepping = 1,
3700	.features[FEAT_1_EDX] =
3701	PPRO_FEATURES \| CPUID_VME \|
3702	CPUID_MTRR \| CPUID_CLFLUSH \| CPUID_MCA \| CPUID_PSE36,
3703	.features[FEAT_1_ECX] =
3704	CPUID_EXT_SSE3,
3705	.features[FEAT_8000_0001_ECX] =
3706	0,
3707	/* VMX features from Yonah */
3708	.features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
3709	.features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
3710	.features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
3711	.features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK \|
3712	VMX_PIN_BASED_NMI_EXITING,
3713	.features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING \|
3714	VMX_CPU_BASED_USE_TSC_OFFSETING \| VMX_CPU_BASED_HLT_EXITING \|
3715	VMX_CPU_BASED_INVLPG_EXITING \| VMX_CPU_BASED_MWAIT_EXITING \|
3716	VMX_CPU_BASED_RDPMC_EXITING \| VMX_CPU_BASED_RDTSC_EXITING \|
3717	VMX_CPU_BASED_MOV_DR_EXITING \| VMX_CPU_BASED_UNCOND_IO_EXITING \|
3718	VMX_CPU_BASED_USE_IO_BITMAPS \| VMX_CPU_BASED_MONITOR_EXITING \|
3719	VMX_CPU_BASED_PAUSE_EXITING \| VMX_CPU_BASED_USE_MSR_BITMAPS,
3720	.xlevel = 0x80000008,
3721	.model_id = "Common 32-bit KVM processor"
3722	},
3723	{
3724	.name = "coreduo",
3725	.level = 10,
3726	.vendor = CPUID_VENDOR_INTEL,
3727	.family = 6,
3728	.model = 14,
3729	.stepping = 8,
3730	/* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
3731	.features[FEAT_1_EDX] =
3732	PPRO_FEATURES \| CPUID_VME \|
3733	CPUID_MTRR \| CPUID_CLFLUSH \| CPUID_MCA \| CPUID_ACPI \|
3734	CPUID_SS,
3735	/* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR,
3736	* CPUID_EXT_PDCM, CPUID_EXT_VMX */
3737	.features[FEAT_1_ECX] =
3738	CPUID_EXT_SSE3 \| CPUID_EXT_MONITOR,
3739	.features[FEAT_8000_0001_EDX] =
3740	CPUID_EXT2_NX,
3741	.features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
3742	.features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
3743	.features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
3744	.features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK \|
3745	VMX_PIN_BASED_NMI_EXITING,
3746	.features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING \|
3747	VMX_CPU_BASED_USE_TSC_OFFSETING \| VMX_CPU_BASED_HLT_EXITING \|
3748	VMX_CPU_BASED_INVLPG_EXITING \| VMX_CPU_BASED_MWAIT_EXITING \|
3749	VMX_CPU_BASED_RDPMC_EXITING \| VMX_CPU_BASED_RDTSC_EXITING \|
3750	VMX_CPU_BASED_MOV_DR_EXITING \| VMX_CPU_BASED_UNCOND_IO_EXITING \|
3751	VMX_CPU_BASED_USE_IO_BITMAPS \| VMX_CPU_BASED_MONITOR_EXITING \|
3752	VMX_CPU_BASED_PAUSE_EXITING \| VMX_CPU_BASED_USE_MSR_BITMAPS,
3753	.xlevel = 0x80000008,
3754	.model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
3755	},
3756	{
3757	.name = "486",
3758	.level = 1,
3759	.vendor = CPUID_VENDOR_INTEL,
3760	.family = 4,
3761	.model = 8,
3762	.stepping = 0,
3763	.features[FEAT_1_EDX] =
3764	I486_FEATURES,
3765	.xlevel = 0,
3766	.model_id = "",
3767	.cache_info = &legacy_intel_cpuid2_cache_info,
3768	},
3769	{
3770	.name = "pentium",
3771	.level = 1,
3772	.vendor = CPUID_VENDOR_INTEL,
3773	.family = 5,
3774	.model = 4,
3775	.stepping = 3,
3776	.features[FEAT_1_EDX] =
3777	PENTIUM_FEATURES,
3778	.xlevel = 0,
3779	.model_id = "",
3780	.cache_info = &legacy_intel_cpuid2_cache_info,
3781	},
3782	{
3783	.name = "pentium2",
3784	.level = 2,
3785	.vendor = CPUID_VENDOR_INTEL,
3786	.family = 6,
3787	.model = 5,
3788	.stepping = 2,
3789	.features[FEAT_1_EDX] =
3790	PENTIUM2_FEATURES,
3791	.xlevel = 0,
3792	.model_id = "",
3793	.cache_info = &legacy_intel_cpuid2_cache_info,
3794	},
3795	{
3796	.name = "pentium3",
3797	.level = 3,
3798	.vendor = CPUID_VENDOR_INTEL,
3799	.family = 6,
3800	.model = 7,
3801	.stepping = 3,
3802	.features[FEAT_1_EDX] =
3803	PENTIUM3_FEATURES,
3804	.xlevel = 0,
3805	.model_id = "",
3806	.cache_info = &legacy_intel_cpuid2_cache_info,
3807	},
3808	{
3809	.name = "athlon",
3810	.level = 2,
3811	.vendor = CPUID_VENDOR_AMD,
3812	.family = 6,
3813	.model = 2,
3814	.stepping = 3,
3815	.features[FEAT_1_EDX] =
3816	PPRO_FEATURES \| CPUID_PSE36 \| CPUID_VME \| CPUID_MTRR \|
3817	CPUID_MCA,
3818	.features[FEAT_8000_0001_EDX] =
3819	CPUID_EXT2_MMXEXT \| CPUID_EXT2_3DNOW \| CPUID_EXT2_3DNOWEXT,
3820	.xlevel = 0x80000008,
3821	.model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
3822	},
3823	{
3824	.name = "n270",
3825	.level = 10,
3826	.vendor = CPUID_VENDOR_INTEL,
3827	.family = 6,
3828	.model = 28,
3829	.stepping = 2,
3830	/* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
3831	.features[FEAT_1_EDX] =
3832	PPRO_FEATURES \|
3833	CPUID_MTRR \| CPUID_CLFLUSH \| CPUID_MCA \| CPUID_VME \|
3834	CPUID_ACPI \| CPUID_SS,
3835	/* Some CPUs got no CPUID_SEP */
3836	/* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2,
3837	* CPUID_EXT_XTPR */
3838	.features[FEAT_1_ECX] =
3839	CPUID_EXT_SSE3 \| CPUID_EXT_MONITOR \| CPUID_EXT_SSSE3 \|
3840	CPUID_EXT_MOVBE,
3841	.features[FEAT_8000_0001_EDX] =
3842	CPUID_EXT2_NX,
3843	.features[FEAT_8000_0001_ECX] =
3844	CPUID_EXT3_LAHF_LM,
3845	.xlevel = 0x80000008,
3846	.model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
3847	},
3848	{
3849	.name = "Conroe",
3850	.level = 10,
3851	.vendor = CPUID_VENDOR_INTEL,
3852	.family = 6,
3853	.model = 15,
3854	.stepping = 3,
3855	.features[FEAT_1_EDX] =
3856	CPUID_VME \| CPUID_SSE2 \| CPUID_SSE \| CPUID_FXSR \| CPUID_MMX \|
3857	CPUID_CLFLUSH \| CPUID_PSE36 \| CPUID_PAT \| CPUID_CMOV \| CPUID_MCA \|
3858	CPUID_PGE \| CPUID_MTRR \| CPUID_SEP \| CPUID_APIC \| CPUID_CX8 \|
3859	CPUID_MCE \| CPUID_PAE \| CPUID_MSR \| CPUID_TSC \| CPUID_PSE \|
3860	CPUID_DE \| CPUID_FP87,
3861	.features[FEAT_1_ECX] =
3862	CPUID_EXT_SSSE3 \| CPUID_EXT_SSE3,
3863	.features[FEAT_8000_0001_EDX] =
3864	CPUID_EXT2_LM \| CPUID_EXT2_NX \| CPUID_EXT2_SYSCALL,
3865	.features[FEAT_8000_0001_ECX] =
3866	CPUID_EXT3_LAHF_LM,
3867	.features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS,
3868	.features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
3869	.features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
3870	.features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
3871	.features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK \|
3872	VMX_PIN_BASED_NMI_EXITING \| VMX_PIN_BASED_VIRTUAL_NMIS,
3873	.features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING \|
3874	VMX_CPU_BASED_USE_TSC_OFFSETING \| VMX_CPU_BASED_HLT_EXITING \|
3875	VMX_CPU_BASED_INVLPG_EXITING \| VMX_CPU_BASED_MWAIT_EXITING \|
3876	VMX_CPU_BASED_RDPMC_EXITING \| VMX_CPU_BASED_RDTSC_EXITING \|
3877	VMX_CPU_BASED_CR8_LOAD_EXITING \| VMX_CPU_BASED_CR8_STORE_EXITING \|
3878	VMX_CPU_BASED_TPR_SHADOW \| VMX_CPU_BASED_MOV_DR_EXITING \|
3879	VMX_CPU_BASED_UNCOND_IO_EXITING \| VMX_CPU_BASED_USE_IO_BITMAPS \|
3880	VMX_CPU_BASED_MONITOR_EXITING \| VMX_CPU_BASED_PAUSE_EXITING \|
3881	VMX_CPU_BASED_VIRTUAL_NMI_PENDING \| VMX_CPU_BASED_USE_MSR_BITMAPS \|
3882	VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3883	.features[FEAT_VMX_SECONDARY_CTLS] =
3884	VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES,
3885	.xlevel = 0x80000008,
3886	.model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
3887	},
3888	{
3889	.name = "Penryn",
3890	.level = 10,
3891	.vendor = CPUID_VENDOR_INTEL,
3892	.family = 6,
3893	.model = 23,
3894	.stepping = 3,
3895	.features[FEAT_1_EDX] =
3896	CPUID_VME \| CPUID_SSE2 \| CPUID_SSE \| CPUID_FXSR \| CPUID_MMX \|
3897	CPUID_CLFLUSH \| CPUID_PSE36 \| CPUID_PAT \| CPUID_CMOV \| CPUID_MCA \|
3898	CPUID_PGE \| CPUID_MTRR \| CPUID_SEP \| CPUID_APIC \| CPUID_CX8 \|
3899	CPUID_MCE \| CPUID_PAE \| CPUID_MSR \| CPUID_TSC \| CPUID_PSE \|
3900	CPUID_DE \| CPUID_FP87,
3901	.features[FEAT_1_ECX] =
3902	CPUID_EXT_SSE41 \| CPUID_EXT_CX16 \| CPUID_EXT_SSSE3 \|
3903	CPUID_EXT_SSE3,
3904	.features[FEAT_8000_0001_EDX] =
3905	CPUID_EXT2_LM \| CPUID_EXT2_NX \| CPUID_EXT2_SYSCALL,
3906	.features[FEAT_8000_0001_ECX] =
3907	CPUID_EXT3_LAHF_LM,
3908	.features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS,
3909	.features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE \|
3910	VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
3911	.features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT \|
3912	VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
3913	.features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
3914	.features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK \|
3915	VMX_PIN_BASED_NMI_EXITING \| VMX_PIN_BASED_VIRTUAL_NMIS,
3916	.features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING \|
3917	VMX_CPU_BASED_USE_TSC_OFFSETING \| VMX_CPU_BASED_HLT_EXITING \|
3918	VMX_CPU_BASED_INVLPG_EXITING \| VMX_CPU_BASED_MWAIT_EXITING \|
3919	VMX_CPU_BASED_RDPMC_EXITING \| VMX_CPU_BASED_RDTSC_EXITING \|
3920	VMX_CPU_BASED_CR8_LOAD_EXITING \| VMX_CPU_BASED_CR8_STORE_EXITING \|
3921	VMX_CPU_BASED_TPR_SHADOW \| VMX_CPU_BASED_MOV_DR_EXITING \|
3922	VMX_CPU_BASED_UNCOND_IO_EXITING \| VMX_CPU_BASED_USE_IO_BITMAPS \|
3923	VMX_CPU_BASED_MONITOR_EXITING \| VMX_CPU_BASED_PAUSE_EXITING \|
3924	VMX_CPU_BASED_VIRTUAL_NMI_PENDING \| VMX_CPU_BASED_USE_MSR_BITMAPS \|
3925	VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3926	.features[FEAT_VMX_SECONDARY_CTLS] =
3927	VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES \|
3928	VMX_SECONDARY_EXEC_WBINVD_EXITING,
3929	.xlevel = 0x80000008,
3930	.model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
3931	},
3932	{
3933	.name = "Nehalem",
3934	.level = 11,
3935	.vendor = CPUID_VENDOR_INTEL,
3936	.family = 6,
3937	.model = 26,
3938	.stepping = 3,
3939	.features[FEAT_1_EDX] =
3940	CPUID_VME \| CPUID_SSE2 \| CPUID_SSE \| CPUID_FXSR \| CPUID_MMX \|
3941	CPUID_CLFLUSH \| CPUID_PSE36 \| CPUID_PAT \| CPUID_CMOV \| CPUID_MCA \|
3942	CPUID_PGE \| CPUID_MTRR \| CPUID_SEP \| CPUID_APIC \| CPUID_CX8 \|
3943	CPUID_MCE \| CPUID_PAE \| CPUID_MSR \| CPUID_TSC \| CPUID_PSE \|
3944	CPUID_DE \| CPUID_FP87,
3945	.features[FEAT_1_ECX] =
3946	CPUID_EXT_POPCNT \| CPUID_EXT_SSE42 \| CPUID_EXT_SSE41 \|
3947	CPUID_EXT_CX16 \| CPUID_EXT_SSSE3 \| CPUID_EXT_SSE3,
3948	.features[FEAT_8000_0001_EDX] =
3949	CPUID_EXT2_LM \| CPUID_EXT2_SYSCALL \| CPUID_EXT2_NX,
3950	.features[FEAT_8000_0001_ECX] =
3951	CPUID_EXT3_LAHF_LM,
3952	.features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS \|
3953	MSR_VMX_BASIC_TRUE_CTLS,
3954	.features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE \|
3955	VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL \| VMX_VM_ENTRY_LOAD_IA32_PAT \|
3956	VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS \| VMX_VM_ENTRY_LOAD_IA32_EFER,
3957	.features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY \|
3958	MSR_VMX_EPT_PAGE_WALK_LENGTH_4 \| MSR_VMX_EPT_WB \| MSR_VMX_EPT_2MB \|
3959	MSR_VMX_EPT_1GB \| MSR_VMX_EPT_INVEPT \|
3960	MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT \| MSR_VMX_EPT_INVEPT_ALL_CONTEXT \|
3961	MSR_VMX_EPT_INVVPID \| MSR_VMX_EPT_INVVPID_SINGLE_ADDR \|
3962	MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT \| MSR_VMX_EPT_INVVPID_ALL_CONTEXT \|
3963	MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
3964	.features[FEAT_VMX_EXIT_CTLS] =
3965	VMX_VM_EXIT_ACK_INTR_ON_EXIT \| VMX_VM_EXIT_SAVE_DEBUG_CONTROLS \|
3966	VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL \|
3967	VMX_VM_EXIT_LOAD_IA32_PAT \| VMX_VM_EXIT_LOAD_IA32_EFER \|
3968	VMX_VM_EXIT_SAVE_IA32_PAT \| VMX_VM_EXIT_SAVE_IA32_EFER \|
3969	VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
3970	.features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
3971	.features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK \|
3972	VMX_PIN_BASED_NMI_EXITING \| VMX_PIN_BASED_VIRTUAL_NMIS \|
3973	VMX_PIN_BASED_VMX_PREEMPTION_TIMER,
3974	.features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING \|
3975	VMX_CPU_BASED_USE_TSC_OFFSETING \| VMX_CPU_BASED_HLT_EXITING \|
3976	VMX_CPU_BASED_INVLPG_EXITING \| VMX_CPU_BASED_MWAIT_EXITING \|
3977	VMX_CPU_BASED_RDPMC_EXITING \| VMX_CPU_BASED_RDTSC_EXITING \|
3978	VMX_CPU_BASED_CR8_LOAD_EXITING \| VMX_CPU_BASED_CR8_STORE_EXITING \|
3979	VMX_CPU_BASED_TPR_SHADOW \| VMX_CPU_BASED_MOV_DR_EXITING \|
3980	VMX_CPU_BASED_UNCOND_IO_EXITING \| VMX_CPU_BASED_USE_IO_BITMAPS \|
3981	VMX_CPU_BASED_MONITOR_EXITING \| VMX_CPU_BASED_PAUSE_EXITING \|
3982	VMX_CPU_BASED_VIRTUAL_NMI_PENDING \| VMX_CPU_BASED_USE_MSR_BITMAPS \|
3983	VMX_CPU_BASED_CR3_LOAD_EXITING \| VMX_CPU_BASED_CR3_STORE_EXITING \|
3984	VMX_CPU_BASED_MONITOR_TRAP_FLAG \|
3985	VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3986	.features[FEAT_VMX_SECONDARY_CTLS] =
3987	VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES \|
3988	VMX_SECONDARY_EXEC_WBINVD_EXITING \| VMX_SECONDARY_EXEC_ENABLE_EPT \|
3989	VMX_SECONDARY_EXEC_DESC \| VMX_SECONDARY_EXEC_RDTSCP \|
3990	VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE \|
3991	VMX_SECONDARY_EXEC_ENABLE_VPID,
3992	.xlevel = 0x80000008,
3993	.model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
3994	.versions = (X86CPUVersionDefinition[]) {
3995	{ .version = 1 },
3996	{
3997	.version = 2,
3998	.alias = "Nehalem-IBRS",
3999	.props = (PropValue[]) {
4000	{ "spec-ctrl", "on" },
4001	{ "model-id",
4002	"Intel Core i7 9xx (Nehalem Core i7, IBRS update)" },
4003	{ /* end of list */ }
4004	}
4005	},
4006	{ /* end of list */ }
4007	}
4008	},
4009	{
4010	.name = "Westmere",
4011	.level = 11,
4012	.vendor = CPUID_VENDOR_INTEL,
4013	.family = 6,
4014	.model = 44,
4015	.stepping = 1,
4016	.features[FEAT_1_EDX] =
4017	CPUID_VME \| CPUID_SSE2 \| CPUID_SSE \| CPUID_FXSR \| CPUID_MMX \|
4018	CPUID_CLFLUSH \| CPUID_PSE36 \| CPUID_PAT \| CPUID_CMOV \| CPUID_MCA \|
4019	CPUID_PGE \| CPUID_MTRR \| CPUID_SEP \| CPUID_APIC \| CPUID_CX8 \|
4020	CPUID_MCE \| CPUID_PAE \| CPUID_MSR \| CPUID_TSC \| CPUID_PSE \|
4021	CPUID_DE \| CPUID_FP87,
4022	.features[FEAT_1_ECX] =
4023	CPUID_EXT_AES \| CPUID_EXT_POPCNT \| CPUID_EXT_SSE42 \|
4024	CPUID_EXT_SSE41 \| CPUID_EXT_CX16 \| CPUID_EXT_SSSE3 \|
4025	CPUID_EXT_PCLMULQDQ \| CPUID_EXT_SSE3,
4026	.features[FEAT_8000_0001_EDX] =
4027	CPUID_EXT2_LM \| CPUID_EXT2_SYSCALL \| CPUID_EXT2_NX,
4028	.features[FEAT_8000_0001_ECX] =
4029	CPUID_EXT3_LAHF_LM,
4030	.features[FEAT_6_EAX] =
4031	CPUID_6_EAX_ARAT,
4032	.features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS \|
4033	MSR_VMX_BASIC_TRUE_CTLS,
4034	.features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE \|
4035	VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL \| VMX_VM_ENTRY_LOAD_IA32_PAT \|
4036	VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS \| VMX_VM_ENTRY_LOAD_IA32_EFER,
4037	.features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY \|
4038	MSR_VMX_EPT_PAGE_WALK_LENGTH_4 \| MSR_VMX_EPT_WB \| MSR_VMX_EPT_2MB \|
4039	MSR_VMX_EPT_1GB \| MSR_VMX_EPT_INVEPT \|
4040	MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT \| MSR_VMX_EPT_INVEPT_ALL_CONTEXT \|
4041	MSR_VMX_EPT_INVVPID \| MSR_VMX_EPT_INVVPID_SINGLE_ADDR \|
4042	MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT \| MSR_VMX_EPT_INVVPID_ALL_CONTEXT \|
4043	MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
4044	.features[FEAT_VMX_EXIT_CTLS] =
4045	VMX_VM_EXIT_ACK_INTR_ON_EXIT \| VMX_VM_EXIT_SAVE_DEBUG_CONTROLS \|
4046	VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL \|
4047	VMX_VM_EXIT_LOAD_IA32_PAT \| VMX_VM_EXIT_LOAD_IA32_EFER \|
4048	VMX_VM_EXIT_SAVE_IA32_PAT \| VMX_VM_EXIT_SAVE_IA32_EFER \|
4049	VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
4050	.features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT \|
4051	MSR_VMX_MISC_STORE_LMA,
4052	.features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK \|
4053	VMX_PIN_BASED_NMI_EXITING \| VMX_PIN_BASED_VIRTUAL_NMIS \|
4054	VMX_PIN_BASED_VMX_PREEMPTION_TIMER,
4055	.features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING \|
4056	VMX_CPU_BASED_USE_TSC_OFFSETING \| VMX_CPU_BASED_HLT_EXITING \|
4057	VMX_CPU_BASED_INVLPG_EXITING \| VMX_CPU_BASED_MWAIT_EXITING \|
4058	VMX_CPU_BASED_RDPMC_EXITING \| VMX_CPU_BASED_RDTSC_EXITING \|
4059	VMX_CPU_BASED_CR8_LOAD_EXITING \| VMX_CPU_BASED_CR8_STORE_EXITING \|
4060	VMX_CPU_BASED_TPR_SHADOW \| VMX_CPU_BASED_MOV_DR_EXITING \|
4061	VMX_CPU_BASED_UNCOND_IO_EXITING \| VMX_CPU_BASED_USE_IO_BITMAPS \|
4062	VMX_CPU_BASED_MONITOR_EXITING \| VMX_CPU_BASED_PAUSE_EXITING \|
4063	VMX_CPU_BASED_VIRTUAL_NMI_PENDING \| VMX_CPU_BASED_USE_MSR_BITMAPS \|
4064	VMX_CPU_BASED_CR3_LOAD_EXITING \| VMX_CPU_BASED_CR3_STORE_EXITING \|
4065	VMX_CPU_BASED_MONITOR_TRAP_FLAG \|
4066	VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
4067	.features[FEAT_VMX_SECONDARY_CTLS] =
4068	VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES \|
4069	VMX_SECONDARY_EXEC_WBINVD_EXITING \| VMX_SECONDARY_EXEC_ENABLE_EPT \|
4070	VMX_SECONDARY_EXEC_DESC \| VMX_SECONDARY_EXEC_RDTSCP \|
4071	VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE \|
4072	VMX_SECONDARY_EXEC_ENABLE_VPID \| VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST,
4073	.xlevel = 0x80000008,
4074	.model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
4075	.versions = (X86CPUVersionDefinition[]) {
4076	{ .version = 1 },
4077	{
4078	.version = 2,
4079	.alias = "Westmere-IBRS",
4080	.props = (PropValue[]) {
4081	{ "spec-ctrl", "on" },
4082	{ "model-id",
4083	"Westmere E56xx/L56xx/X56xx (IBRS update)" },
4084	{ /* end of list */ }
4085	}
4086	},
4087	{ /* end of list */ }
4088	}
4089	},
4090	{
4091	.name = "SandyBridge",
4092	.level = 0xd,
4093	.vendor = CPUID_VENDOR_INTEL,
4094	.family = 6,
4095	.model = 42,
4096	.stepping = 1,
4097	.features[FEAT_1_EDX] =
4098	CPUID_VME \| CPUID_SSE2 \| CPUID_SSE \| CPUID_FXSR \| CPUID_MMX \|
4099	CPUID_CLFLUSH \| CPUID_PSE36 \| CPUID_PAT \| CPUID_CMOV \| CPUID_MCA \|
4100	CPUID_PGE \| CPUID_MTRR \| CPUID_SEP \| CPUID_APIC \| CPUID_CX8 \|
4101	CPUID_MCE \| CPUID_PAE \| CPUID_MSR \| CPUID_TSC \| CPUID_PSE \|
4102	CPUID_DE \| CPUID_FP87,
4103	.features[FEAT_1_ECX] =
4104	CPUID_EXT_AVX \| CPUID_EXT_XSAVE \| CPUID_EXT_AES \|
4105	CPUID_EXT_TSC_DEADLINE_TIMER \| CPUID_EXT_POPCNT \|
4106	CPUID_EXT_X2APIC \| CPUID_EXT_SSE42 \| CPUID_EXT_SSE41 \|
4107	CPUID_EXT_CX16 \| CPUID_EXT_SSSE3 \| CPUID_EXT_PCLMULQDQ \|
4108	CPUID_EXT_SSE3,
4109	.features[FEAT_8000_0001_EDX] =
4110	CPUID_EXT2_LM \| CPUID_EXT2_RDTSCP \| CPUID_EXT2_NX \|
4111	CPUID_EXT2_SYSCALL,
4112	.features[FEAT_8000_0001_ECX] =
4113	CPUID_EXT3_LAHF_LM,
4114	.features[FEAT_XSAVE] =
4115	CPUID_XSAVE_XSAVEOPT,
4116	.features[FEAT_6_EAX] =
4117	CPUID_6_EAX_ARAT,
4118	.features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS \|
4119	MSR_VMX_BASIC_TRUE_CTLS,
4120	.features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE \|
4121	VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL \| VMX_VM_ENTRY_LOAD_IA32_PAT \|
4122	VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS \| VMX_VM_ENTRY_LOAD_IA32_EFER,
4123	.features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY \|
4124	MSR_VMX_EPT_PAGE_WALK_LENGTH_4 \| MSR_VMX_EPT_WB \| MSR_VMX_EPT_2MB \|
4125	MSR_VMX_EPT_1GB \| MSR_VMX_EPT_INVEPT \|
4126	MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT \| MSR_VMX_EPT_INVEPT_ALL_CONTEXT \|
4127	MSR_VMX_EPT_INVVPID \| MSR_VMX_EPT_INVVPID_SINGLE_ADDR \|
4128	MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT \| MSR_VMX_EPT_INVVPID_ALL_CONTEXT \|
4129	MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
4130	.features[FEAT_VMX_EXIT_CTLS] =
4131	VMX_VM_EXIT_ACK_INTR_ON_EXIT \| VMX_VM_EXIT_SAVE_DEBUG_CONTROLS \|
4132	VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL \|
4133	VMX_VM_EXIT_LOAD_IA32_PAT \| VMX_VM_EXIT_LOAD_IA32_EFER \|
4134	VMX_VM_EXIT_SAVE_IA32_PAT \| VMX_VM_EXIT_SAVE_IA32_EFER \|
4135	VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
4136	.features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT \|
4137	MSR_VMX_MISC_STORE_LMA,
4138	.features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK \|
4139	VMX_PIN_BASED_NMI_EXITING \| VMX_PIN_BASED_VIRTUAL_NMIS \|
4140	VMX_PIN_BASED_VMX_PREEMPTION_TIMER,
4141	.features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING \|
4142	VMX_CPU_BASED_USE_TSC_OFFSETING \| VMX_CPU_BASED_HLT_EXITING \|
4143	VMX_CPU_BASED_INVLPG_EXITING \| VMX_CPU_BASED_MWAIT_EXITING \|
4144	VMX_CPU_BASED_RDPMC_EXITING \| VMX_CPU_BASED_RDTSC_EXITING \|
4145	VMX_CPU_BASED_CR8_LOAD_EXITING \| VMX_CPU_BASED_CR8_STORE_EXITING \|
4146	VMX_CPU_BASED_TPR_SHADOW \| VMX_CPU_BASED_MOV_DR_EXITING \|
4147	VMX_CPU_BASED_UNCOND_IO_EXITING \| VMX_CPU_BASED_USE_IO_BITMAPS \|
4148	VMX_CPU_BASED_MONITOR_EXITING \| VMX_CPU_BASED_PAUSE_EXITING \|
4149	VMX_CPU_BASED_VIRTUAL_NMI_PENDING \| VMX_CPU_BASED_USE_MSR_BITMAPS \|
4150	VMX_CPU_BASED_CR3_LOAD_EXITING \| VMX_CPU_BASED_CR3_STORE_EXITING \|
4151	VMX_CPU_BASED_MONITOR_TRAP_FLAG \|
4152	VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
4153	.features[FEAT_VMX_SECONDARY_CTLS] =
4154	VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES \|
4155	VMX_SECONDARY_EXEC_WBINVD_EXITING \| VMX_SECONDARY_EXEC_ENABLE_EPT \|
4156	VMX_SECONDARY_EXEC_DESC \| VMX_SECONDARY_EXEC_RDTSCP \|
4157	VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE \|
4158	VMX_SECONDARY_EXEC_ENABLE_VPID \| VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST,
4159	.xlevel = 0x80000008,
4160	.model_id = "Intel Xeon E312xx (Sandy Bridge)",
4161	.versions = (X86CPUVersionDefinition[]) {
4162	{ .version = 1 },
4163	{
4164	.version = 2,
4165	.alias = "SandyBridge-IBRS",
4166	.props = (PropValue[]) {
4167	{ "spec-ctrl", "on" },
4168	{ "model-id",
4169	"Intel Xeon E312xx (Sandy Bridge, IBRS update)" },
4170	{ /* end of list */ }
4171	}
4172	},
4173	{ /* end of list */ }
4174	}
4175	},
4176	{
4177	.name = "IvyBridge",
4178	.level = 0xd,
4179	.vendor = CPUID_VENDOR_INTEL,
4180	.family = 6,
4181	.model = 58,
4182	.stepping = 9,
4183	.features[FEAT_1_EDX] =
4184	CPUID_VME \| CPUID_SSE2 \| CPUID_SSE \| CPUID_FXSR \| CPUID_MMX \|
4185	CPUID_CLFLUSH \| CPUID_PSE36 \| CPUID_PAT \| CPUID_CMOV \| CPUID_MCA \|
4186	CPUID_PGE \| CPUID_MTRR \| CPUID_SEP \| CPUID_APIC \| CPUID_CX8 \|
4187	CPUID_MCE \| CPUID_PAE \| CPUID_MSR \| CPUID_TSC \| CPUID_PSE \|
4188	CPUID_DE \| CPUID_FP87,
4189	.features[FEAT_1_ECX] =
4190	CPUID_EXT_AVX \| CPUID_EXT_XSAVE \| CPUID_EXT_AES \|
4191	CPUID_EXT_TSC_DEADLINE_TIMER \| CPUID_EXT_POPCNT \|
4192	CPUID_EXT_X2APIC \| CPUID_EXT_SSE42 \| CPUID_EXT_SSE41 \|
4193	CPUID_EXT_CX16 \| CPUID_EXT_SSSE3 \| CPUID_EXT_PCLMULQDQ \|
4194	CPUID_EXT_SSE3 \| CPUID_EXT_F16C \| CPUID_EXT_RDRAND,
4195	.features[FEAT_7_0_EBX] =
4196	CPUID_7_0_EBX_FSGSBASE \| CPUID_7_0_EBX_SMEP \|
4197	CPUID_7_0_EBX_ERMS,
4198	.features[FEAT_8000_0001_EDX] =
4199	CPUID_EXT2_LM \| CPUID_EXT2_RDTSCP \| CPUID_EXT2_NX \|
4200	CPUID_EXT2_SYSCALL,
4201	.features[FEAT_8000_0001_ECX] =
4202	CPUID_EXT3_LAHF_LM,
4203	.features[FEAT_XSAVE] =
4204	CPUID_XSAVE_XSAVEOPT,
4205	.features[FEAT_6_EAX] =
4206	CPUID_6_EAX_ARAT,
4207	.features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS \|
4208	MSR_VMX_BASIC_TRUE_CTLS,
4209	.features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE \|
4210	VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL \| VMX_VM_ENTRY_LOAD_IA32_PAT \|
4211	VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS \| VMX_VM_ENTRY_LOAD_IA32_EFER,
4212	.features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY \|
4213	MSR_VMX_EPT_PAGE_WALK_LENGTH_4 \| MSR_VMX_EPT_WB \| MSR_VMX_EPT_2MB \|
4214	MSR_VMX_EPT_1GB \| MSR_VMX_EPT_INVEPT \|
4215	MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT \| MSR_VMX_EPT_INVEPT_ALL_CONTEXT \|
4216	MSR_VMX_EPT_INVVPID \| MSR_VMX_EPT_INVVPID_SINGLE_ADDR \|
4217	MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT \| MSR_VMX_EPT_INVVPID_ALL_CONTEXT \|
4218	MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
4219	.features[FEAT_VMX_EXIT_CTLS] =
4220	VMX_VM_EXIT_ACK_INTR_ON_EXIT \| VMX_VM_EXIT_SAVE_DEBUG_CONTROLS \|
4221	VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL \|
4222	VMX_VM_EXIT_LOAD_IA32_PAT \| VMX_VM_EXIT_LOAD_IA32_EFER \|
4223	VMX_VM_EXIT_SAVE_IA32_PAT \| VMX_VM_EXIT_SAVE_IA32_EFER \|
4224	VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
4225	.features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT \|
4226	MSR_VMX_MISC_STORE_LMA,
4227	.features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK \|
4228	VMX_PIN_BASED_NMI_EXITING \| VMX_PIN_BASED_VIRTUAL_NMIS \|
4229	VMX_PIN_BASED_VMX_PREEMPTION_TIMER \| VMX_PIN_BASED_POSTED_INTR,
4230	.features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING \|
4231	VMX_CPU_BASED_USE_TSC_OFFSETING \| VMX_CPU_BASED_HLT_EXITING \|
4232	VMX_CPU_BASED_INVLPG_EXITING \| VMX_CPU_BASED_MWAIT_EXITING \|
4233	VMX_CPU_BASED_RDPMC_EXITING \| VMX_CPU_BASED_RDTSC_EXITING \|
4234	VMX_CPU_BASED_CR8_LOAD_EXITING \| VMX_CPU_BASED_CR8_STORE_EXITING \|
4235	VMX_CPU_BASED_TPR_SHADOW \| VMX_CPU_BASED_MOV_DR_EXITING \|
4236	VMX_CPU_BASED_UNCOND_IO_EXITING \| VMX_CPU_BASED_USE_IO_BITMAPS \|
4237	VMX_CPU_BASED_MONITOR_EXITING \| VMX_CPU_BASED_PAUSE_EXITING \|
4238	VMX_CPU_BASED_VIRTUAL_NMI_PENDING \| VMX_CPU_BASED_USE_MSR_BITMAPS \|
4239	VMX_CPU_BASED_CR3_LOAD_EXITING \| VMX_CPU_BASED_CR3_STORE_EXITING \|
4240	VMX_CPU_BASED_MONITOR_TRAP_FLAG \|
4241	VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
4242	.features[FEAT_VMX_SECONDARY_CTLS] =
4243	VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES \|
4244	VMX_SECONDARY_EXEC_WBINVD_EXITING \| VMX_SECONDARY_EXEC_ENABLE_EPT \|
4245	VMX_SECONDARY_EXEC_DESC \| VMX_SECONDARY_EXEC_RDTSCP \|
4246	VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE \|
4247	VMX_SECONDARY_EXEC_ENABLE_VPID \| VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST \|
4248	VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT \|
4249	VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY \|
4250	VMX_SECONDARY_EXEC_RDRAND_EXITING,
4251	.xlevel = 0x80000008,
4252	.model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)",
4253	.versions = (X86CPUVersionDefinition[]) {
4254	{ .version = 1 },
4255	{
4256	.version = 2,
4257	.alias = "IvyBridge-IBRS",
4258	.props = (PropValue[]) {
4259	{ "spec-ctrl", "on" },
4260	{ "model-id",
4261	"Intel Xeon E3-12xx v2 (Ivy Bridge, IBRS)" },
4262	{ /* end of list */ }
4263	}
4264	},
4265	{ /* end of list */ }
4266	}
4267	},
4268	{
4269	.name = "Haswell",
4270	.level = 0xd,
4271	.vendor = CPUID_VENDOR_INTEL,
4272	.family = 6,
4273	.model = 60,
4274	.stepping = 4,
4275	.features[FEAT_1_EDX] =
4276	CPUID_VME \| CPUID_SSE2 \| CPUID_SSE \| CPUID_FXSR \| CPUID_MMX \|
4277	CPUID_CLFLUSH \| CPUID_PSE36 \| CPUID_PAT \| CPUID_CMOV \| CPUID_MCA \|
4278	CPUID_PGE \| CPUID_MTRR \| CPUID_SEP \| CPUID_APIC \| CPUID_CX8 \|
4279	CPUID_MCE \| CPUID_PAE \| CPUID_MSR \| CPUID_TSC \| CPUID_PSE \|
4280	CPUID_DE \| CPUID_FP87,
4281	.features[FEAT_1_ECX] =
4282	CPUID_EXT_AVX \| CPUID_EXT_XSAVE \| CPUID_EXT_AES \|
4283	CPUID_EXT_POPCNT \| CPUID_EXT_X2APIC \| CPUID_EXT_SSE42 \|
4284	CPUID_EXT_SSE41 \| CPUID_EXT_CX16 \| CPUID_EXT_SSSE3 \|
4285	CPUID_EXT_PCLMULQDQ \| CPUID_EXT_SSE3 \|
4286	CPUID_EXT_TSC_DEADLINE_TIMER \| CPUID_EXT_FMA \| CPUID_EXT_MOVBE \|
4287	CPUID_EXT_PCID \| CPUID_EXT_F16C \| CPUID_EXT_RDRAND,
4288	.features[FEAT_8000_0001_EDX] =
4289	CPUID_EXT2_LM \| CPUID_EXT2_RDTSCP \| CPUID_EXT2_NX \|
4290	CPUID_EXT2_SYSCALL,
4291	.features[FEAT_8000_0001_ECX] =
4292	CPUID_EXT3_ABM \| CPUID_EXT3_LAHF_LM,
4293	.features[FEAT_7_0_EBX] =
4294	CPUID_7_0_EBX_FSGSBASE \| CPUID_7_0_EBX_BMI1 \|
4295	CPUID_7_0_EBX_HLE \| CPUID_7_0_EBX_AVX2 \| CPUID_7_0_EBX_SMEP \|
4296	CPUID_7_0_EBX_BMI2 \| CPUID_7_0_EBX_ERMS \| CPUID_7_0_EBX_INVPCID \|
4297	CPUID_7_0_EBX_RTM,
4298	.features[FEAT_XSAVE] =
4299	CPUID_XSAVE_XSAVEOPT,
4300	.features[FEAT_6_EAX] =
4301	CPUID_6_EAX_ARAT,
4302	.features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS \|
4303	MSR_VMX_BASIC_TRUE_CTLS,
4304	.features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE \|
4305	VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL \| VMX_VM_ENTRY_LOAD_IA32_PAT \|
4306	VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS \| VMX_VM_ENTRY_LOAD_IA32_EFER,
4307	.features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY \|
4308	MSR_VMX_EPT_PAGE_WALK_LENGTH_4 \| MSR_VMX_EPT_WB \| MSR_VMX_EPT_2MB \|
4309	MSR_VMX_EPT_1GB \| MSR_VMX_EPT_INVEPT \|
4310	MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT \| MSR_VMX_EPT_INVEPT_ALL_CONTEXT \|
4311	MSR_VMX_EPT_INVVPID \| MSR_VMX_EPT_INVVPID_SINGLE_ADDR \|
4312	MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT \| MSR_VMX_EPT_INVVPID_ALL_CONTEXT \|
4313	MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS \| MSR_VMX_EPT_AD_BITS,
4314	.features[FEAT_VMX_EXIT_CTLS] =
4315	VMX_VM_EXIT_ACK_INTR_ON_EXIT \| VMX_VM_EXIT_SAVE_DEBUG_CONTROLS \|
4316	VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL \|
4317	VMX_VM_EXIT_LOAD_IA32_PAT \| VMX_VM_EXIT_LOAD_IA32_EFER \|
4318	VMX_VM_EXIT_SAVE_IA32_PAT \| VMX_VM_EXIT_SAVE_IA32_EFER \|
4319	VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
4320	.features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT \|
4321	MSR_VMX_MISC_STORE_LMA \| MSR_VMX_MISC_VMWRITE_VMEXIT,
4322	.features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK \|
4323	VMX_PIN_BASED_NMI_EXITING \| VMX_PIN_BASED_VIRTUAL_NMIS \|
4324	VMX_PIN_BASED_VMX_PREEMPTION_TIMER \| VMX_PIN_BASED_POSTED_INTR,
4325	.features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING \|
4326	VMX_CPU_BASED_USE_TSC_OFFSETING \| VMX_CPU_BASED_HLT_EXITING \|
4327	VMX_CPU_BASED_INVLPG_EXITING \| VMX_CPU_BASED_MWAIT_EXITING \|
4328	VMX_CPU_BASED_RDPMC_EXITING \| VMX_CPU_BASED_RDTSC_EXITING \|
4329	VMX_CPU_BASED_CR8_LOAD_EXITING \| VMX_CPU_BASED_CR8_STORE_EXITING \|
4330	VMX_CPU_BASED_TPR_SHADOW \| VMX_CPU_BASED_MOV_DR_EXITING \|
4331	VMX_CPU_BASED_UNCOND_IO_EXITING \| VMX_CPU_BASED_USE_IO_BITMAPS \|
4332	VMX_CPU_BASED_MONITOR_EXITING \| VMX_CPU_BASED_PAUSE_EXITING \|
4333	VMX_CPU_BASED_VIRTUAL_NMI_PENDING \| VMX_CPU_BASED_USE_MSR_BITMAPS \|
4334	VMX_CPU_BASED_CR3_LOAD_EXITING \| VMX_CPU_BASED_CR3_STORE_EXITING \|
4335	VMX_CPU_BASED_MONITOR_TRAP_FLAG \|
4336	VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
4337	.features[FEAT_VMX_SECONDARY_CTLS] =
4338	VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES \|
4339	VMX_SECONDARY_EXEC_WBINVD_EXITING \| VMX_SECONDARY_EXEC_ENABLE_EPT \|
4340	VMX_SECONDARY_EXEC_DESC \| VMX_SECONDARY_EXEC_RDTSCP \|
4341	VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE \|
4342	VMX_SECONDARY_EXEC_ENABLE_VPID \| VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST \|
4343	VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT \|
4344	VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY \|
4345	VMX_SECONDARY_EXEC_RDRAND_EXITING \| VMX_SECONDARY_EXEC_ENABLE_INVPCID \|
4346	VMX_SECONDARY_EXEC_ENABLE_VMFUNC \| VMX_SECONDARY_EXEC_SHADOW_VMCS,
4347	.features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
4348	.xlevel = 0x80000008,
4349	.model_id = "Intel Core Processor (Haswell)",
4350	.versions = (X86CPUVersionDefinition[]) {
4351	{ .version = 1 },
4352	{
4353	.version = 2,
4354	.alias = "Haswell-noTSX",
4355	.props = (PropValue[]) {
4356	{ "hle", "off" },
4357	{ "rtm", "off" },
4358	{ "stepping", "1" },
4359	{ "model-id", "Intel Core Processor (Haswell, no TSX)", },
4360	{ /* end of list */ }
4361	},
4362	},
4363	{
4364	.version = 3,
4365	.alias = "Haswell-IBRS",
4366	.props = (PropValue[]) {
4367	/* Restore TSX features removed by -v2 above */
4368	{ "hle", "on" },
4369	{ "rtm", "on" },
4370	/*
4371	* Haswell and Haswell-IBRS had stepping=4 in
4372	* QEMU 4.0 and older
4373	*/
4374	{ "stepping", "4" },
4375	{ "spec-ctrl", "on" },
4376	{ "model-id",
4377	"Intel Core Processor (Haswell, IBRS)" },
4378	{ /* end of list */ }
4379	}
4380	},
4381	{
4382	.version = 4,
4383	.alias = "Haswell-noTSX-IBRS",
4384	.props = (PropValue[]) {
4385	{ "hle", "off" },
4386	{ "rtm", "off" },
4387	/* spec-ctrl was already enabled by -v3 above */
4388	{ "stepping", "1" },
4389	{ "model-id",
4390	"Intel Core Processor (Haswell, no TSX, IBRS)" },
4391	{ /* end of list */ }
4392	}
4393	},
4394	{ /* end of list */ }
4395	}
4396	},
4397	{
4398	.name = "Broadwell",
4399	.level = 0xd,
4400	.vendor = CPUID_VENDOR_INTEL,
4401	.family = 6,
4402	.model = 61,
4403	.stepping = 2,
4404	.features[FEAT_1_EDX] =
4405	CPUID_VME \| CPUID_SSE2 \| CPUID_SSE \| CPUID_FXSR \| CPUID_MMX \|
4406	CPUID_CLFLUSH \| CPUID_PSE36 \| CPUID_PAT \| CPUID_CMOV \| CPUID_MCA \|
4407	CPUID_PGE \| CPUID_MTRR \| CPUID_SEP \| CPUID_APIC \| CPUID_CX8 \|
4408	CPUID_MCE \| CPUID_PAE \| CPUID_MSR \| CPUID_TSC \| CPUID_PSE \|
4409	CPUID_DE \| CPUID_FP87,
4410	.features[FEAT_1_ECX] =
4411	CPUID_EXT_AVX \| CPUID_EXT_XSAVE \| CPUID_EXT_AES \|
4412	CPUID_EXT_POPCNT \| CPUID_EXT_X2APIC \| CPUID_EXT_SSE42 \|
4413	CPUID_EXT_SSE41 \| CPUID_EXT_CX16 \| CPUID_EXT_SSSE3 \|
4414	CPUID_EXT_PCLMULQDQ \| CPUID_EXT_SSE3 \|
4415	CPUID_EXT_TSC_DEADLINE_TIMER \| CPUID_EXT_FMA \| CPUID_EXT_MOVBE \|
4416	CPUID_EXT_PCID \| CPUID_EXT_F16C \| CPUID_EXT_RDRAND,
4417	.features[FEAT_8000_0001_EDX] =
4418	CPUID_EXT2_LM \| CPUID_EXT2_RDTSCP \| CPUID_EXT2_NX \|
4419	CPUID_EXT2_SYSCALL,
4420	.features[FEAT_8000_0001_ECX] =
4421	CPUID_EXT3_ABM \| CPUID_EXT3_LAHF_LM \| CPUID_EXT3_3DNOWPREFETCH,
4422	.features[FEAT_7_0_EBX] =
4423	CPUID_7_0_EBX_FSGSBASE \| CPUID_7_0_EBX_BMI1 \|
4424	CPUID_7_0_EBX_HLE \| CPUID_7_0_EBX_AVX2 \| CPUID_7_0_EBX_SMEP \|
4425	CPUID_7_0_EBX_BMI2 \| CPUID_7_0_EBX_ERMS \| CPUID_7_0_EBX_INVPCID \|
4426	CPUID_7_0_EBX_RTM \| CPUID_7_0_EBX_RDSEED \| CPUID_7_0_EBX_ADX \|
4427	CPUID_7_0_EBX_SMAP,
4428	.features[FEAT_XSAVE] =
4429	CPUID_XSAVE_XSAVEOPT,
4430	.features[FEAT_6_EAX] =
4431	CPUID_6_EAX_ARAT,
4432	.features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS \|
4433	MSR_VMX_BASIC_TRUE_CTLS,
4434	.features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE \|
4435	VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL \| VMX_VM_ENTRY_LOAD_IA32_PAT \|
4436	VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS \| VMX_VM_ENTRY_LOAD_IA32_EFER,
4437	.features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY \|
4438	MSR_VMX_EPT_PAGE_WALK_LENGTH_4 \| MSR_VMX_EPT_WB \| MSR_VMX_EPT_2MB \|
4439	MSR_VMX_EPT_1GB \| MSR_VMX_EPT_INVEPT \|
4440	MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT \| MSR_VMX_EPT_INVEPT_ALL_CONTEXT \|
4441	MSR_VMX_EPT_INVVPID \| MSR_VMX_EPT_INVVPID_SINGLE_ADDR \|
4442	MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT \| MSR_VMX_EPT_INVVPID_ALL_CONTEXT \|
4443	MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS \| MSR_VMX_EPT_AD_BITS,
4444	.features[FEAT_VMX_EXIT_CTLS] =
4445	VMX_VM_EXIT_ACK_INTR_ON_EXIT \| VMX_VM_EXIT_SAVE_DEBUG_CONTROLS \|
4446	VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL \|
4447	VMX_VM_EXIT_LOAD_IA32_PAT \| VMX_VM_EXIT_LOAD_IA32_EFER \|
4448	VMX_VM_EXIT_SAVE_IA32_PAT \| VMX_VM_EXIT_SAVE_IA32_EFER \|
4449	VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
4450	.features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT \|
4451	MSR_VMX_MISC_STORE_LMA \| MSR_VMX_MISC_VMWRITE_VMEXIT,
4452	.features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK \|
4453	VMX_PIN_BASED_NMI_EXITING \| VMX_PIN_BASED_VIRTUAL_NMIS \|
4454	VMX_PIN_BASED_VMX_PREEMPTION_TIMER \| VMX_PIN_BASED_POSTED_INTR,
4455	.features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING \|
4456	VMX_CPU_BASED_USE_TSC_OFFSETING \| VMX_CPU_BASED_HLT_EXITING \|
4457	VMX_CPU_BASED_INVLPG_EXITING \| VMX_CPU_BASED_MWAIT_EXITING \|
4458	VMX_CPU_BASED_RDPMC_EXITING \| VMX_CPU_BASED_RDTSC_EXITING \|
4459	VMX_CPU_BASED_CR8_LOAD_EXITING \| VMX_CPU_BASED_CR8_STORE_EXITING \|
4460	VMX_CPU_BASED_TPR_SHADOW \| VMX_CPU_BASED_MOV_DR_EXITING \|
4461	VMX_CPU_BASED_UNCOND_IO_EXITING \| VMX_CPU_BASED_USE_IO_BITMAPS \|
4462	VMX_CPU_BASED_MONITOR_EXITING \| VMX_CPU_BASED_PAUSE_EXITING \|
4463	VMX_CPU_BASED_VIRTUAL_NMI_PENDING \| VMX_CPU_BASED_USE_MSR_BITMAPS \|
4464	VMX_CPU_BASED_CR3_LOAD_EXITING \| VMX_CPU_BASED_CR3_STORE_EXITING \|
4465	VMX_CPU_BASED_MONITOR_TRAP_FLAG \|
4466	VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
4467	.features[FEAT_VMX_SECONDARY_CTLS] =
4468	VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES \|
4469	VMX_SECONDARY_EXEC_WBINVD_EXITING \| VMX_SECONDARY_EXEC_ENABLE_EPT \|
4470	VMX_SECONDARY_EXEC_DESC \| VMX_SECONDARY_EXEC_RDTSCP \|
4471	VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE \|
4472	VMX_SECONDARY_EXEC_ENABLE_VPID \| VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST \|
4473	VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT \|
4474	VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY \|
4475	VMX_SECONDARY_EXEC_RDRAND_EXITING \| VMX_SECONDARY_EXEC_ENABLE_INVPCID \|
4476	VMX_SECONDARY_EXEC_ENABLE_VMFUNC \| VMX_SECONDARY_EXEC_SHADOW_VMCS \|
4477	VMX_SECONDARY_EXEC_RDSEED_EXITING \| VMX_SECONDARY_EXEC_ENABLE_PML,
4478	.features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
4479	.xlevel = 0x80000008,
4480	.model_id = "Intel Core Processor (Broadwell)",
4481	.versions = (X86CPUVersionDefinition[]) {
4482	{ .version = 1 },
4483	{
4484	.version = 2,
4485	.alias = "Broadwell-noTSX",
4486	.props = (PropValue[]) {
4487	{ "hle", "off" },
4488	{ "rtm", "off" },
4489	{ "model-id", "Intel Core Processor (Broadwell, no TSX)", },
4490	{ /* end of list */ }
4491	},
4492	},
4493	{
4494	.version = 3,
4495	.alias = "Broadwell-IBRS",
4496	.props = (PropValue[]) {
4497	/* Restore TSX features removed by -v2 above */
4498	{ "hle", "on" },
4499	{ "rtm", "on" },
4500	{ "spec-ctrl", "on" },
4501	{ "model-id",
4502	"Intel Core Processor (Broadwell, IBRS)" },
4503	{ /* end of list */ }
4504	}
4505	},
4506	{
4507	.version = 4,
4508	.alias = "Broadwell-noTSX-IBRS",
4509	.props = (PropValue[]) {
4510	{ "hle", "off" },
4511	{ "rtm", "off" },
4512	/* spec-ctrl was already enabled by -v3 above */
4513	{ "model-id",
4514	"Intel Core Processor (Broadwell, no TSX, IBRS)" },
4515	{ /* end of list */ }
4516	}
4517	},
4518	{ /* end of list */ }
4519	}
4520	},
4521	{
4522	.name = "Skylake-Client",
4523	.level = 0xd,
4524	.vendor = CPUID_VENDOR_INTEL,
4525	.family = 6,
4526	.model = 94,
4527	.stepping = 3,
4528	.features[FEAT_1_EDX] =
4529	CPUID_VME \| CPUID_SSE2 \| CPUID_SSE \| CPUID_FXSR \| CPUID_MMX \|
4530	CPUID_CLFLUSH \| CPUID_PSE36 \| CPUID_PAT \| CPUID_CMOV \| CPUID_MCA \|
4531	CPUID_PGE \| CPUID_MTRR \| CPUID_SEP \| CPUID_APIC \| CPUID_CX8 \|
4532	CPUID_MCE \| CPUID_PAE \| CPUID_MSR \| CPUID_TSC \| CPUID_PSE \|
4533	CPUID_DE \| CPUID_FP87,
4534	.features[FEAT_1_ECX] =
4535	CPUID_EXT_AVX \| CPUID_EXT_XSAVE \| CPUID_EXT_AES \|
4536	CPUID_EXT_POPCNT \| CPUID_EXT_X2APIC \| CPUID_EXT_SSE42 \|
4537	CPUID_EXT_SSE41 \| CPUID_EXT_CX16 \| CPUID_EXT_SSSE3 \|
4538	CPUID_EXT_PCLMULQDQ \| CPUID_EXT_SSE3 \|
4539	CPUID_EXT_TSC_DEADLINE_TIMER \| CPUID_EXT_FMA \| CPUID_EXT_MOVBE \|
4540	CPUID_EXT_PCID \| CPUID_EXT_F16C \| CPUID_EXT_RDRAND,
4541	.features[FEAT_8000_0001_EDX] =
4542	CPUID_EXT2_LM \| CPUID_EXT2_RDTSCP \| CPUID_EXT2_NX \|
4543	CPUID_EXT2_SYSCALL,
4544	.features[FEAT_8000_0001_ECX] =
4545	CPUID_EXT3_ABM \| CPUID_EXT3_LAHF_LM \| CPUID_EXT3_3DNOWPREFETCH,
4546	.features[FEAT_7_0_EBX] =
4547	CPUID_7_0_EBX_FSGSBASE \| CPUID_7_0_EBX_BMI1 \|
4548	CPUID_7_0_EBX_HLE \| CPUID_7_0_EBX_AVX2 \| CPUID_7_0_EBX_SMEP \|
4549	CPUID_7_0_EBX_BMI2 \| CPUID_7_0_EBX_ERMS \| CPUID_7_0_EBX_INVPCID \|
4550	CPUID_7_0_EBX_RTM \| CPUID_7_0_EBX_RDSEED \| CPUID_7_0_EBX_ADX \|
4551	CPUID_7_0_EBX_SMAP,
4552	/* XSAVES is added in version 4 */
4553	.features[FEAT_XSAVE] =
4554	CPUID_XSAVE_XSAVEOPT \| CPUID_XSAVE_XSAVEC \|
4555	CPUID_XSAVE_XGETBV1,
4556	.features[FEAT_6_EAX] =
4557	CPUID_6_EAX_ARAT,
4558	/* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
4559	.features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS \|
4560	MSR_VMX_BASIC_TRUE_CTLS,
4561	.features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE \|
4562	VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL \| VMX_VM_ENTRY_LOAD_IA32_PAT \|
4563	VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS \| VMX_VM_ENTRY_LOAD_IA32_EFER,
4564	.features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY \|
4565	MSR_VMX_EPT_PAGE_WALK_LENGTH_4 \| MSR_VMX_EPT_WB \| MSR_VMX_EPT_2MB \|
4566	MSR_VMX_EPT_1GB \| MSR_VMX_EPT_INVEPT \|
4567	MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT \| MSR_VMX_EPT_INVEPT_ALL_CONTEXT \|
4568	MSR_VMX_EPT_INVVPID \| MSR_VMX_EPT_INVVPID_SINGLE_ADDR \|
4569	MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT \| MSR_VMX_EPT_INVVPID_ALL_CONTEXT \|
4570	MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS \| MSR_VMX_EPT_AD_BITS,
4571	.features[FEAT_VMX_EXIT_CTLS] =
4572	VMX_VM_EXIT_ACK_INTR_ON_EXIT \| VMX_VM_EXIT_SAVE_DEBUG_CONTROLS \|
4573	VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL \|
4574	VMX_VM_EXIT_LOAD_IA32_PAT \| VMX_VM_EXIT_LOAD_IA32_EFER \|
4575	VMX_VM_EXIT_SAVE_IA32_PAT \| VMX_VM_EXIT_SAVE_IA32_EFER \|
4576	VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
4577	.features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT \|
4578	MSR_VMX_MISC_STORE_LMA \| MSR_VMX_MISC_VMWRITE_VMEXIT,
4579	.features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK \|
4580	VMX_PIN_BASED_NMI_EXITING \| VMX_PIN_BASED_VIRTUAL_NMIS \|
4581	VMX_PIN_BASED_VMX_PREEMPTION_TIMER,
4582	.features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING \|
4583	VMX_CPU_BASED_USE_TSC_OFFSETING \| VMX_CPU_BASED_HLT_EXITING \|
4584	VMX_CPU_BASED_INVLPG_EXITING \| VMX_CPU_BASED_MWAIT_EXITING \|
4585	VMX_CPU_BASED_RDPMC_EXITING \| VMX_CPU_BASED_RDTSC_EXITING \|
4586	VMX_CPU_BASED_CR8_LOAD_EXITING \| VMX_CPU_BASED_CR8_STORE_EXITING \|
4587	VMX_CPU_BASED_TPR_SHADOW \| VMX_CPU_BASED_MOV_DR_EXITING \|
4588	VMX_CPU_BASED_UNCOND_IO_EXITING \| VMX_CPU_BASED_USE_IO_BITMAPS \|
4589	VMX_CPU_BASED_MONITOR_EXITING \| VMX_CPU_BASED_PAUSE_EXITING \|
4590	VMX_CPU_BASED_VIRTUAL_NMI_PENDING \| VMX_CPU_BASED_USE_MSR_BITMAPS \|
4591	VMX_CPU_BASED_CR3_LOAD_EXITING \| VMX_CPU_BASED_CR3_STORE_EXITING \|
4592	VMX_CPU_BASED_MONITOR_TRAP_FLAG \|
4593	VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
4594	.features[FEAT_VMX_SECONDARY_CTLS] =
4595	VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES \|
4596	VMX_SECONDARY_EXEC_WBINVD_EXITING \| VMX_SECONDARY_EXEC_ENABLE_EPT \|
4597	VMX_SECONDARY_EXEC_DESC \| VMX_SECONDARY_EXEC_RDTSCP \|
4598	VMX_SECONDARY_EXEC_ENABLE_VPID \| VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST \|
4599	VMX_SECONDARY_EXEC_RDRAND_EXITING \| VMX_SECONDARY_EXEC_ENABLE_INVPCID \|
4600	VMX_SECONDARY_EXEC_ENABLE_VMFUNC \| VMX_SECONDARY_EXEC_SHADOW_VMCS \|
4601	VMX_SECONDARY_EXEC_RDSEED_EXITING \| VMX_SECONDARY_EXEC_ENABLE_PML,
4602	.features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
4603	.xlevel = 0x80000008,
4604	.model_id = "Intel Core Processor (Skylake)",
4605	.versions = (X86CPUVersionDefinition[]) {
4606	{ .version = 1 },
4607	{
4608	.version = 2,
4609	.alias = "Skylake-Client-IBRS",
4610	.props = (PropValue[]) {
4611	{ "spec-ctrl", "on" },
4612	{ "model-id",
4613	"Intel Core Processor (Skylake, IBRS)" },
4614	{ /* end of list */ }
4615	}
4616	},
4617	{
4618	.version = 3,
4619	.alias = "Skylake-Client-noTSX-IBRS",
4620	.props = (PropValue[]) {
4621	{ "hle", "off" },
4622	{ "rtm", "off" },
4623	{ "model-id",
4624	"Intel Core Processor (Skylake, IBRS, no TSX)" },
4625	{ /* end of list */ }
4626	}
4627	},
4628	{
4629	.version = 4,
4630	.note = "IBRS, XSAVES, no TSX",
4631	.props = (PropValue[]) {
4632	{ "xsaves", "on" },
4633	{ "vmx-xsaves", "on" },
4634	{ /* end of list */ }
4635	}
4636	},
4637	{ /* end of list */ }
4638	}
4639	},
4640	{
4641	.name = "Skylake-Server",
4642	.level = 0xd,
4643	.vendor = CPUID_VENDOR_INTEL,
4644	.family = 6,
4645	.model = 85,
4646	.stepping = 4,
4647	.features[FEAT_1_EDX] =
4648	CPUID_VME \| CPUID_SSE2 \| CPUID_SSE \| CPUID_FXSR \| CPUID_MMX \|
4649	CPUID_CLFLUSH \| CPUID_PSE36 \| CPUID_PAT \| CPUID_CMOV \| CPUID_MCA \|
4650	CPUID_PGE \| CPUID_MTRR \| CPUID_SEP \| CPUID_APIC \| CPUID_CX8 \|
4651	CPUID_MCE \| CPUID_PAE \| CPUID_MSR \| CPUID_TSC \| CPUID_PSE \|
4652	CPUID_DE \| CPUID_FP87,
4653	.features[FEAT_1_ECX] =
4654	CPUID_EXT_AVX \| CPUID_EXT_XSAVE \| CPUID_EXT_AES \|
4655	CPUID_EXT_POPCNT \| CPUID_EXT_X2APIC \| CPUID_EXT_SSE42 \|
4656	CPUID_EXT_SSE41 \| CPUID_EXT_CX16 \| CPUID_EXT_SSSE3 \|
4657	CPUID_EXT_PCLMULQDQ \| CPUID_EXT_SSE3 \|
4658	CPUID_EXT_TSC_DEADLINE_TIMER \| CPUID_EXT_FMA \| CPUID_EXT_MOVBE \|
4659	CPUID_EXT_PCID \| CPUID_EXT_F16C \| CPUID_EXT_RDRAND,
4660	.features[FEAT_8000_0001_EDX] =
4661	CPUID_EXT2_LM \| CPUID_EXT2_PDPE1GB \| CPUID_EXT2_RDTSCP \|
4662	CPUID_EXT2_NX \| CPUID_EXT2_SYSCALL,
4663	.features[FEAT_8000_0001_ECX] =
4664	CPUID_EXT3_ABM \| CPUID_EXT3_LAHF_LM \| CPUID_EXT3_3DNOWPREFETCH,
4665	.features[FEAT_7_0_EBX] =
4666	CPUID_7_0_EBX_FSGSBASE \| CPUID_7_0_EBX_BMI1 \|
4667	CPUID_7_0_EBX_HLE \| CPUID_7_0_EBX_AVX2 \| CPUID_7_0_EBX_SMEP \|
4668	CPUID_7_0_EBX_BMI2 \| CPUID_7_0_EBX_ERMS \| CPUID_7_0_EBX_INVPCID \|
4669	CPUID_7_0_EBX_RTM \| CPUID_7_0_EBX_RDSEED \| CPUID_7_0_EBX_ADX \|
4670	CPUID_7_0_EBX_SMAP \| CPUID_7_0_EBX_CLWB \|
4671	CPUID_7_0_EBX_AVX512F \| CPUID_7_0_EBX_AVX512DQ \|
4672	CPUID_7_0_EBX_AVX512BW \| CPUID_7_0_EBX_AVX512CD \|
4673	CPUID_7_0_EBX_AVX512VL \| CPUID_7_0_EBX_CLFLUSHOPT,
4674	.features[FEAT_7_0_ECX] =
4675	CPUID_7_0_ECX_PKU,
4676	/* XSAVES is added in version 5 */
4677	.features[FEAT_XSAVE] =
4678	CPUID_XSAVE_XSAVEOPT \| CPUID_XSAVE_XSAVEC \|
4679	CPUID_XSAVE_XGETBV1,
4680	.features[FEAT_6_EAX] =
4681	CPUID_6_EAX_ARAT,
4682	/* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
4683	.features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS \|
4684	MSR_VMX_BASIC_TRUE_CTLS,
4685	.features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE \|
4686	VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL \| VMX_VM_ENTRY_LOAD_IA32_PAT \|
4687	VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS \| VMX_VM_ENTRY_LOAD_IA32_EFER,
4688	.features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY \|
4689	MSR_VMX_EPT_PAGE_WALK_LENGTH_4 \| MSR_VMX_EPT_WB \| MSR_VMX_EPT_2MB \|
4690	MSR_VMX_EPT_1GB \| MSR_VMX_EPT_INVEPT \|
4691	MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT \| MSR_VMX_EPT_INVEPT_ALL_CONTEXT \|
4692	MSR_VMX_EPT_INVVPID \| MSR_VMX_EPT_INVVPID_SINGLE_ADDR \|
4693	MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT \| MSR_VMX_EPT_INVVPID_ALL_CONTEXT \|
4694	MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS \| MSR_VMX_EPT_AD_BITS,
4695	.features[FEAT_VMX_EXIT_CTLS] =
4696	VMX_VM_EXIT_ACK_INTR_ON_EXIT \| VMX_VM_EXIT_SAVE_DEBUG_CONTROLS \|
4697	VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL \|
4698	VMX_VM_EXIT_LOAD_IA32_PAT \| VMX_VM_EXIT_LOAD_IA32_EFER \|
4699	VMX_VM_EXIT_SAVE_IA32_PAT \| VMX_VM_EXIT_SAVE_IA32_EFER \|
4700	VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
4701	.features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT \|
4702	MSR_VMX_MISC_STORE_LMA \| MSR_VMX_MISC_VMWRITE_VMEXIT,
4703	.features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK \|
4704	VMX_PIN_BASED_NMI_EXITING \| VMX_PIN_BASED_VIRTUAL_NMIS \|
4705	VMX_PIN_BASED_VMX_PREEMPTION_TIMER \| VMX_PIN_BASED_POSTED_INTR,
4706	.features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING \|
4707	VMX_CPU_BASED_USE_TSC_OFFSETING \| VMX_CPU_BASED_HLT_EXITING \|
4708	VMX_CPU_BASED_INVLPG_EXITING \| VMX_CPU_BASED_MWAIT_EXITING \|
4709	VMX_CPU_BASED_RDPMC_EXITING \| VMX_CPU_BASED_RDTSC_EXITING \|
4710	VMX_CPU_BASED_CR8_LOAD_EXITING \| VMX_CPU_BASED_CR8_STORE_EXITING \|
4711	VMX_CPU_BASED_TPR_SHADOW \| VMX_CPU_BASED_MOV_DR_EXITING \|
4712	VMX_CPU_BASED_UNCOND_IO_EXITING \| VMX_CPU_BASED_USE_IO_BITMAPS \|
4713	VMX_CPU_BASED_MONITOR_EXITING \| VMX_CPU_BASED_PAUSE_EXITING \|
4714	VMX_CPU_BASED_VIRTUAL_NMI_PENDING \| VMX_CPU_BASED_USE_MSR_BITMAPS \|
4715	VMX_CPU_BASED_CR3_LOAD_EXITING \| VMX_CPU_BASED_CR3_STORE_EXITING \|
4716	VMX_CPU_BASED_MONITOR_TRAP_FLAG \|
4717	VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
4718	.features[FEAT_VMX_SECONDARY_CTLS] =
4719	VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES \|
4720	VMX_SECONDARY_EXEC_WBINVD_EXITING \| VMX_SECONDARY_EXEC_ENABLE_EPT \|
4721	VMX_SECONDARY_EXEC_DESC \| VMX_SECONDARY_EXEC_RDTSCP \|
4722	VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE \|
4723	VMX_SECONDARY_EXEC_ENABLE_VPID \| VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST \|
4724	VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT \|
4725	VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY \|
4726	VMX_SECONDARY_EXEC_RDRAND_EXITING \| VMX_SECONDARY_EXEC_ENABLE_INVPCID \|
4727	VMX_SECONDARY_EXEC_ENABLE_VMFUNC \| VMX_SECONDARY_EXEC_SHADOW_VMCS \|
4728	VMX_SECONDARY_EXEC_RDSEED_EXITING \| VMX_SECONDARY_EXEC_ENABLE_PML,
4729	.xlevel = 0x80000008,
4730	.model_id = "Intel Xeon Processor (Skylake)",
4731	.versions = (X86CPUVersionDefinition[]) {
4732	{ .version = 1 },
4733	{
4734	.version = 2,
4735	.alias = "Skylake-Server-IBRS",
4736	.props = (PropValue[]) {
4737	/* clflushopt was not added to Skylake-Server-IBRS */
4738	/* TODO: add -v3 including clflushopt */
4739	{ "clflushopt", "off" },
4740	{ "spec-ctrl", "on" },
4741	{ "model-id",
4742	"Intel Xeon Processor (Skylake, IBRS)" },
4743	{ /* end of list */ }
4744	}
4745	},
4746	{
4747	.version = 3,
4748	.alias = "Skylake-Server-noTSX-IBRS",
4749	.props = (PropValue[]) {
4750	{ "hle", "off" },
4751	{ "rtm", "off" },
4752	{ "model-id",
4753	"Intel Xeon Processor (Skylake, IBRS, no TSX)" },
4754	{ /* end of list */ }
4755	}
4756	},
4757	{
4758	.version = 4,
4759	.note = "IBRS, EPT switching, no TSX",
4760	.props = (PropValue[]) {
4761	{ "vmx-eptp-switching", "on" },
4762	{ /* end of list */ }
4763	}
4764	},
4765	{
4766	.version = 5,
4767	.note = "IBRS, XSAVES, EPT switching, no TSX",
4768	.props = (PropValue[]) {
4769	{ "xsaves", "on" },
4770	{ "vmx-xsaves", "on" },
4771	{ /* end of list */ }
4772	}
4773	},
4774	{
4775	.version = 6,
4776	.note = "with MBEC enabled",
4777	.props = (PropValue[]) {
4778	{ "vmx-mbec", "on" },
4779	{ /* end of list */ }
4780	}
4781	},
4782	{ /* end of list */ }
4783	}
4784	},
4785	{
4786	.name = "Cascadelake-Server",
4787	.level = 0xd,
4788	.vendor = CPUID_VENDOR_INTEL,
4789	.family = 6,
4790	.model = 85,
4791	.stepping = 6,
4792	.features[FEAT_1_EDX] =
4793	CPUID_VME \| CPUID_SSE2 \| CPUID_SSE \| CPUID_FXSR \| CPUID_MMX \|
4794	CPUID_CLFLUSH \| CPUID_PSE36 \| CPUID_PAT \| CPUID_CMOV \| CPUID_MCA \|
4795	CPUID_PGE \| CPUID_MTRR \| CPUID_SEP \| CPUID_APIC \| CPUID_CX8 \|
4796	CPUID_MCE \| CPUID_PAE \| CPUID_MSR \| CPUID_TSC \| CPUID_PSE \|
4797	CPUID_DE \| CPUID_FP87,
4798	.features[FEAT_1_ECX] =
4799	CPUID_EXT_AVX \| CPUID_EXT_XSAVE \| CPUID_EXT_AES \|
4800	CPUID_EXT_POPCNT \| CPUID_EXT_X2APIC \| CPUID_EXT_SSE42 \|
4801	CPUID_EXT_SSE41 \| CPUID_EXT_CX16 \| CPUID_EXT_SSSE3 \|
4802	CPUID_EXT_PCLMULQDQ \| CPUID_EXT_SSE3 \|
4803	CPUID_EXT_TSC_DEADLINE_TIMER \| CPUID_EXT_FMA \| CPUID_EXT_MOVBE \|
4804	CPUID_EXT_PCID \| CPUID_EXT_F16C \| CPUID_EXT_RDRAND,
4805	.features[FEAT_8000_0001_EDX] =
4806	CPUID_EXT2_LM \| CPUID_EXT2_PDPE1GB \| CPUID_EXT2_RDTSCP \|
4807	CPUID_EXT2_NX \| CPUID_EXT2_SYSCALL,
4808	.features[FEAT_8000_0001_ECX] =
4809	CPUID_EXT3_ABM \| CPUID_EXT3_LAHF_LM \| CPUID_EXT3_3DNOWPREFETCH,
4810	.features[FEAT_7_0_EBX] =
4811	CPUID_7_0_EBX_FSGSBASE \| CPUID_7_0_EBX_BMI1 \|
4812	CPUID_7_0_EBX_HLE \| CPUID_7_0_EBX_AVX2 \| CPUID_7_0_EBX_SMEP \|
4813	CPUID_7_0_EBX_BMI2 \| CPUID_7_0_EBX_ERMS \| CPUID_7_0_EBX_INVPCID \|
4814	CPUID_7_0_EBX_RTM \| CPUID_7_0_EBX_RDSEED \| CPUID_7_0_EBX_ADX \|
4815	CPUID_7_0_EBX_SMAP \| CPUID_7_0_EBX_CLWB \|
4816	CPUID_7_0_EBX_AVX512F \| CPUID_7_0_EBX_AVX512DQ \|
4817	CPUID_7_0_EBX_AVX512BW \| CPUID_7_0_EBX_AVX512CD \|
4818	CPUID_7_0_EBX_AVX512VL \| CPUID_7_0_EBX_CLFLUSHOPT,
4819	.features[FEAT_7_0_ECX] =
4820	CPUID_7_0_ECX_PKU \|
4821	CPUID_7_0_ECX_AVX512VNNI,
4822	.features[FEAT_7_0_EDX] =
4823	CPUID_7_0_EDX_SPEC_CTRL \| CPUID_7_0_EDX_SPEC_CTRL_SSBD,
4824	/* XSAVES is added in version 5 */
4825	.features[FEAT_XSAVE] =
4826	CPUID_XSAVE_XSAVEOPT \| CPUID_XSAVE_XSAVEC \|
4827	CPUID_XSAVE_XGETBV1,
4828	.features[FEAT_6_EAX] =
4829	CPUID_6_EAX_ARAT,
4830	/* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
4831	.features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS \|
4832	MSR_VMX_BASIC_TRUE_CTLS,
4833	.features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE \|
4834	VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL \| VMX_VM_ENTRY_LOAD_IA32_PAT \|
4835	VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS \| VMX_VM_ENTRY_LOAD_IA32_EFER,
4836	.features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY \|
4837	MSR_VMX_EPT_PAGE_WALK_LENGTH_4 \| MSR_VMX_EPT_WB \| MSR_VMX_EPT_2MB \|
4838	MSR_VMX_EPT_1GB \| MSR_VMX_EPT_INVEPT \|
4839	MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT \| MSR_VMX_EPT_INVEPT_ALL_CONTEXT \|
4840	MSR_VMX_EPT_INVVPID \| MSR_VMX_EPT_INVVPID_SINGLE_ADDR \|
4841	MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT \| MSR_VMX_EPT_INVVPID_ALL_CONTEXT \|
4842	MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS \| MSR_VMX_EPT_AD_BITS,
4843	.features[FEAT_VMX_EXIT_CTLS] =
4844	VMX_VM_EXIT_ACK_INTR_ON_EXIT \| VMX_VM_EXIT_SAVE_DEBUG_CONTROLS \|
4845	VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL \|
4846	VMX_VM_EXIT_LOAD_IA32_PAT \| VMX_VM_EXIT_LOAD_IA32_EFER \|
4847	VMX_VM_EXIT_SAVE_IA32_PAT \| VMX_VM_EXIT_SAVE_IA32_EFER \|
4848	VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
4849	.features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT \|
4850	MSR_VMX_MISC_STORE_LMA \| MSR_VMX_MISC_VMWRITE_VMEXIT,
4851	.features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK \|
4852	VMX_PIN_BASED_NMI_EXITING \| VMX_PIN_BASED_VIRTUAL_NMIS \|
4853	VMX_PIN_BASED_VMX_PREEMPTION_TIMER \| VMX_PIN_BASED_POSTED_INTR,
4854	.features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING \|
4855	VMX_CPU_BASED_USE_TSC_OFFSETING \| VMX_CPU_BASED_HLT_EXITING \|
4856	VMX_CPU_BASED_INVLPG_EXITING \| VMX_CPU_BASED_MWAIT_EXITING \|
4857	VMX_CPU_BASED_RDPMC_EXITING \| VMX_CPU_BASED_RDTSC_EXITING \|
4858	VMX_CPU_BASED_CR8_LOAD_EXITING \| VMX_CPU_BASED_CR8_STORE_EXITING \|
4859	VMX_CPU_BASED_TPR_SHADOW \| VMX_CPU_BASED_MOV_DR_EXITING \|
4860	VMX_CPU_BASED_UNCOND_IO_EXITING \| VMX_CPU_BASED_USE_IO_BITMAPS \|
4861	VMX_CPU_BASED_MONITOR_EXITING \| VMX_CPU_BASED_PAUSE_EXITING \|
4862	VMX_CPU_BASED_VIRTUAL_NMI_PENDING \| VMX_CPU_BASED_USE_MSR_BITMAPS \|
4863	VMX_CPU_BASED_CR3_LOAD_EXITING \| VMX_CPU_BASED_CR3_STORE_EXITING \|
4864	VMX_CPU_BASED_MONITOR_TRAP_FLAG \|
4865	VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
4866	.features[FEAT_VMX_SECONDARY_CTLS] =
4867	VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES \|
4868	VMX_SECONDARY_EXEC_WBINVD_EXITING \| VMX_SECONDARY_EXEC_ENABLE_EPT \|
4869	VMX_SECONDARY_EXEC_DESC \| VMX_SECONDARY_EXEC_RDTSCP \|
4870	VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE \|
4871	VMX_SECONDARY_EXEC_ENABLE_VPID \| VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST \|
4872	VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT \|
4873	VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY \|
4874	VMX_SECONDARY_EXEC_RDRAND_EXITING \| VMX_SECONDARY_EXEC_ENABLE_INVPCID \|
4875	VMX_SECONDARY_EXEC_ENABLE_VMFUNC \| VMX_SECONDARY_EXEC_SHADOW_VMCS \|
4876	VMX_SECONDARY_EXEC_RDSEED_EXITING \| VMX_SECONDARY_EXEC_ENABLE_PML,
4877	.xlevel = 0x80000008,
4878	.model_id = "Intel Xeon Processor (Cascadelake)",
4879	.versions = (X86CPUVersionDefinition[]) {
4880	{ .version = 1 },
4881	{ .version = 2,
4882	.note = "ARCH_CAPABILITIES",
4883	.props = (PropValue[]) {
4884	{ "arch-capabilities", "on" },
4885	{ "rdctl-no", "on" },
4886	{ "ibrs-all", "on" },
4887	{ "skip-l1dfl-vmentry", "on" },
4888	{ "mds-no", "on" },
4889	{ /* end of list */ }
4890	},
4891	},
4892	{ .version = 3,
4893	.alias = "Cascadelake-Server-noTSX",
4894	.note = "ARCH_CAPABILITIES, no TSX",
4895	.props = (PropValue[]) {
4896	{ "hle", "off" },
4897	{ "rtm", "off" },
4898	{ /* end of list */ }
4899	},
4900	},
4901	{ .version = 4,
4902	.note = "ARCH_CAPABILITIES, EPT switching, no TSX",
4903	.props = (PropValue[]) {
4904	{ "vmx-eptp-switching", "on" },
4905	{ /* end of list */ }
4906	},
4907	},
4908	{ .version = 5,
4909	.note = "ARCH_CAPABILITIES, EPT switching, XSAVES, no TSX",
4910	.props = (PropValue[]) {
4911	{ "xsaves", "on" },
4912	{ "vmx-xsaves", "on" },
4913	{ /* end of list */ }
4914	},
4915	},
4916	{ .version = 6,
4917	.note = "with MMIO/GDS/RFDS mitigation status",
4918	.props = (PropValue[]) {
4919	{ "fb-clear", "on" },
4920	{ "gds-no", "on" },
4921	{ "psdp-no", "on" },
4922	{ "rfds-no", "on" },
4923	{ "sbdr-ssdp-no", "on" },
4924	{ /* end of list */ }
4925	},
4926	},
4927	{ .version = 7,
4928	.note = "with MBEC enabled",
4929	.props = (PropValue[]) {
4930	{ "vmx-mbec", "on" },
4931	{ /* end of list */ }
4932	},
4933	},
4934	{ /* end of list */ }
4935	}
4936	},
4937	{
4938	.name = "Cooperlake",
4939	.level = 0xd,
4940	.vendor = CPUID_VENDOR_INTEL,
4941	.family = 6,
4942	.model = 85,
4943	.stepping = 10,
4944	.features[FEAT_1_EDX] =
4945	CPUID_VME \| CPUID_SSE2 \| CPUID_SSE \| CPUID_FXSR \| CPUID_MMX \|
4946	CPUID_CLFLUSH \| CPUID_PSE36 \| CPUID_PAT \| CPUID_CMOV \| CPUID_MCA \|
4947	CPUID_PGE \| CPUID_MTRR \| CPUID_SEP \| CPUID_APIC \| CPUID_CX8 \|
4948	CPUID_MCE \| CPUID_PAE \| CPUID_MSR \| CPUID_TSC \| CPUID_PSE \|
4949	CPUID_DE \| CPUID_FP87,
4950	.features[FEAT_1_ECX] =
4951	CPUID_EXT_AVX \| CPUID_EXT_XSAVE \| CPUID_EXT_AES \|
4952	CPUID_EXT_POPCNT \| CPUID_EXT_X2APIC \| CPUID_EXT_SSE42 \|
4953	CPUID_EXT_SSE41 \| CPUID_EXT_CX16 \| CPUID_EXT_SSSE3 \|
4954	CPUID_EXT_PCLMULQDQ \| CPUID_EXT_SSE3 \|
4955	CPUID_EXT_TSC_DEADLINE_TIMER \| CPUID_EXT_FMA \| CPUID_EXT_MOVBE \|
4956	CPUID_EXT_PCID \| CPUID_EXT_F16C \| CPUID_EXT_RDRAND,
4957	.features[FEAT_8000_0001_EDX] =
4958	CPUID_EXT2_LM \| CPUID_EXT2_PDPE1GB \| CPUID_EXT2_RDTSCP \|
4959	CPUID_EXT2_NX \| CPUID_EXT2_SYSCALL,
4960	.features[FEAT_8000_0001_ECX] =
4961	CPUID_EXT3_ABM \| CPUID_EXT3_LAHF_LM \| CPUID_EXT3_3DNOWPREFETCH,
4962	.features[FEAT_7_0_EBX] =
4963	CPUID_7_0_EBX_FSGSBASE \| CPUID_7_0_EBX_BMI1 \|
4964	CPUID_7_0_EBX_HLE \| CPUID_7_0_EBX_AVX2 \| CPUID_7_0_EBX_SMEP \|
4965	CPUID_7_0_EBX_BMI2 \| CPUID_7_0_EBX_ERMS \| CPUID_7_0_EBX_INVPCID \|
4966	CPUID_7_0_EBX_RTM \| CPUID_7_0_EBX_RDSEED \| CPUID_7_0_EBX_ADX \|
4967	CPUID_7_0_EBX_SMAP \| CPUID_7_0_EBX_CLWB \|
4968	CPUID_7_0_EBX_AVX512F \| CPUID_7_0_EBX_AVX512DQ \|
4969	CPUID_7_0_EBX_AVX512BW \| CPUID_7_0_EBX_AVX512CD \|
4970	CPUID_7_0_EBX_AVX512VL \| CPUID_7_0_EBX_CLFLUSHOPT,
4971	.features[FEAT_7_0_ECX] =
4972	CPUID_7_0_ECX_PKU \|
4973	CPUID_7_0_ECX_AVX512VNNI,
4974	.features[FEAT_7_0_EDX] =
4975	CPUID_7_0_EDX_SPEC_CTRL \| CPUID_7_0_EDX_STIBP \|
4976	CPUID_7_0_EDX_SPEC_CTRL_SSBD \| CPUID_7_0_EDX_ARCH_CAPABILITIES,
4977	.features[FEAT_ARCH_CAPABILITIES] =
4978	MSR_ARCH_CAP_RDCL_NO \| MSR_ARCH_CAP_IBRS_ALL \|
4979	MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY \| MSR_ARCH_CAP_MDS_NO \|
4980	MSR_ARCH_CAP_PSCHANGE_MC_NO \| MSR_ARCH_CAP_TAA_NO,
4981	.features[FEAT_7_1_EAX] =
4982	CPUID_7_1_EAX_AVX512_BF16,
4983	/* XSAVES is added in version 2 */
4984	.features[FEAT_XSAVE] =
4985	CPUID_XSAVE_XSAVEOPT \| CPUID_XSAVE_XSAVEC \|
4986	CPUID_XSAVE_XGETBV1,
4987	.features[FEAT_6_EAX] =
4988	CPUID_6_EAX_ARAT,
4989	/* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
4990	.features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS \|
4991	MSR_VMX_BASIC_TRUE_CTLS,
4992	.features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE \|
4993	VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL \| VMX_VM_ENTRY_LOAD_IA32_PAT \|
4994	VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS \| VMX_VM_ENTRY_LOAD_IA32_EFER,
4995	.features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY \|
4996	MSR_VMX_EPT_PAGE_WALK_LENGTH_4 \| MSR_VMX_EPT_WB \| MSR_VMX_EPT_2MB \|
4997	MSR_VMX_EPT_1GB \| MSR_VMX_EPT_INVEPT \|
4998	MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT \| MSR_VMX_EPT_INVEPT_ALL_CONTEXT \|
4999	MSR_VMX_EPT_INVVPID \| MSR_VMX_EPT_INVVPID_SINGLE_ADDR \|
5000	MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT \| MSR_VMX_EPT_INVVPID_ALL_CONTEXT \|

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