| 1 | /* |
| 2 | * i386 virtual CPU header |
| 3 | * |
| 4 | * Copyright (c) 2003 Fabrice Bellard |
| 5 | * |
| 6 | * This library is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU Lesser General Public |
| 8 | * License as published by the Free Software Foundation; either |
| 9 | * version 2.1 of the License, or (at your option) any later version. |
| 10 | * |
| 11 | * This library is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 14 | * Lesser General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU Lesser General Public |
| 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
| 18 | */ |
| 19 | |
| 20 | #ifndef I386_CPU_H |
| 21 | #define I386_CPU_H |
| 22 | |
| 23 | #include "system/tcg.h" |
| 24 | #include "cpu-qom.h" |
| 25 | #include "kvm/hyperv-proto.h" |
| 26 | #include "exec/cpu-common.h" |
| 27 | #include "exec/cpu-interrupt.h" |
| 28 | #include "exec/target_long.h" |
| 29 | #include "exec/memop.h" |
| 30 | #include "hw/i386/apic.h" |
| 31 | #include "hw/i386/topology.h" |
| 32 | #include "qapi/qapi-types-common.h" |
| 33 | #include "qemu/cpu-float.h" |
| 34 | #include "qemu/timer.h" |
| 35 | #include "standard-headers/asm-x86/kvm_para.h" |
| 36 | #include "hw/hyperv/hvgdk_mini.h" |
| 37 | |
| 38 | #define XEN_NR_VIRQS 24 |
| 39 | |
| 40 | #ifdef TARGET_X86_64 |
| 41 | #define I386_ELF_MACHINE EM_X86_64 |
| 42 | #define ELF_MACHINE_UNAME "x86_64" |
| 43 | #else |
| 44 | #define I386_ELF_MACHINE EM_386 |
| 45 | #define ELF_MACHINE_UNAME "i686" |
| 46 | #endif |
| 47 | |
| 48 | #ifdef CONFIG_MSHV |
| 49 | #define MSHV_STIMERS_STATE_SIZE 200 |
| 50 | #endif |
| 51 | |
| 52 | enum { |
| 53 | R_EAX = 0, |
| 54 | R_ECX = 1, |
| 55 | R_EDX = 2, |
| 56 | R_EBX = 3, |
| 57 | R_ESP = 4, |
| 58 | R_EBP = 5, |
| 59 | R_ESI = 6, |
| 60 | R_EDI = 7, |
| 61 | R_R8 = 8, |
| 62 | R_R9 = 9, |
| 63 | R_R10 = 10, |
| 64 | R_R11 = 11, |
| 65 | R_R12 = 12, |
| 66 | R_R13 = 13, |
| 67 | R_R14 = 14, |
| 68 | R_R15 = 15, |
| 69 | R_R16 = 16, |
| 70 | R_R17 = 17, |
| 71 | R_R18 = 18, |
| 72 | R_R19 = 19, |
| 73 | R_R20 = 20, |
| 74 | R_R21 = 21, |
| 75 | R_R22 = 22, |
| 76 | R_R23 = 23, |
| 77 | R_R24 = 24, |
| 78 | R_R25 = 25, |
| 79 | R_R26 = 26, |
| 80 | R_R27 = 27, |
| 81 | R_R28 = 28, |
| 82 | R_R29 = 29, |
| 83 | R_R30 = 30, |
| 84 | R_R31 = 31, |
| 85 | |
| 86 | R_AL = 0, |
| 87 | R_CL = 1, |
| 88 | R_DL = 2, |
| 89 | R_BL = 3, |
| 90 | R_AH = 4, |
| 91 | R_CH = 5, |
| 92 | R_DH = 6, |
| 93 | R_BH = 7, |
| 94 | }; |
| 95 | |
| 96 | typedef enum X86Seg { |
| 97 | R_ES = 0, |
| 98 | R_CS = 1, |
| 99 | R_SS = 2, |
| 100 | R_DS = 3, |
| 101 | R_FS = 4, |
| 102 | R_GS = 5, |
| 103 | R_LDTR = 6, |
| 104 | R_TR = 7, |
| 105 | } X86Seg; |
| 106 | |
| 107 | /* segment descriptor fields */ |
| 108 | #define DESC_G_SHIFT 23 |
| 109 | #define DESC_G_MASK (1 << DESC_G_SHIFT) |
| 110 | #define DESC_B_SHIFT 22 |
| 111 | #define DESC_B_MASK (1 << DESC_B_SHIFT) |
| 112 | #define DESC_L_SHIFT 21 /* x86_64 only : 64 bit code segment */ |
| 113 | #define DESC_L_MASK (1 << DESC_L_SHIFT) |
| 114 | #define DESC_AVL_SHIFT 20 |
| 115 | #define DESC_AVL_MASK (1 << DESC_AVL_SHIFT) |
| 116 | #define DESC_P_SHIFT 15 |
| 117 | #define DESC_P_MASK (1 << DESC_P_SHIFT) |
| 118 | #define DESC_DPL_SHIFT 13 |
| 119 | #define DESC_DPL_MASK (3 << DESC_DPL_SHIFT) |
| 120 | #define DESC_S_SHIFT 12 |
| 121 | #define DESC_S_MASK (1 << DESC_S_SHIFT) |
| 122 | #define DESC_TYPE_SHIFT 8 |
| 123 | #define DESC_TYPE_MASK (15 << DESC_TYPE_SHIFT) |
| 124 | #define DESC_A_MASK (1 << 8) |
| 125 | |
| 126 | #define DESC_CS_MASK (1 << 11) /* 1=code segment 0=data segment */ |
| 127 | #define DESC_C_MASK (1 << 10) /* code: conforming */ |
| 128 | #define DESC_R_MASK (1 << 9) /* code: readable */ |
| 129 | |
| 130 | #define DESC_E_MASK (1 << 10) /* data: expansion direction */ |
| 131 | #define DESC_W_MASK (1 << 9) /* data: writable */ |
| 132 | |
| 133 | #define DESC_TSS_BUSY_MASK (1 << 9) |
| 134 | |
| 135 | /* eflags masks */ |
| 136 | #define CC_C 0x0001 |
| 137 | #define CC_P 0x0004 |
| 138 | #define CC_A 0x0010 |
| 139 | #define CC_Z 0x0040 |
| 140 | #define CC_S 0x0080 |
| 141 | #define CC_O 0x0800 |
| 142 | |
| 143 | #define TF_SHIFT 8 |
| 144 | #define IOPL_SHIFT 12 |
| 145 | #define VM_SHIFT 17 |
| 146 | |
| 147 | #define TF_MASK 0x00000100 |
| 148 | #define IF_MASK 0x00000200 |
| 149 | #define DF_MASK 0x00000400 |
| 150 | #define IOPL_MASK 0x00003000 |
| 151 | #define NT_MASK 0x00004000 |
| 152 | #define RF_MASK 0x00010000 |
| 153 | #define VM_MASK 0x00020000 |
| 154 | #define AC_MASK 0x00040000 |
| 155 | #define VIF_MASK 0x00080000 |
| 156 | #define VIP_MASK 0x00100000 |
| 157 | #define ID_MASK 0x00200000 |
| 158 | |
| 159 | /* hidden flags - used internally by qemu to represent additional cpu |
| 160 | states. Only the INHIBIT_IRQ, SMM and SVMI are not redundant. We |
| 161 | avoid using the IOPL_MASK, TF_MASK, VM_MASK and AC_MASK bit |
| 162 | positions to ease oring with eflags. */ |
| 163 | /* current cpl */ |
| 164 | #define HF_CPL_SHIFT 0 |
| 165 | /* true if hardware interrupts must be disabled for next instruction */ |
| 166 | #define HF_INHIBIT_IRQ_SHIFT 3 |
| 167 | /* 16 or 32 segments */ |
| 168 | #define HF_CS32_SHIFT 4 |
| 169 | #define HF_SS32_SHIFT 5 |
| 170 | /* zero base for DS, ES and SS : can be '0' only in 32 bit CS segment */ |
| 171 | #define HF_ADDSEG_SHIFT 6 |
| 172 | /* copy of CR0.PE (protected mode) */ |
| 173 | #define HF_PE_SHIFT 7 |
| 174 | #define HF_TF_SHIFT 8 /* must be same as eflags */ |
| 175 | #define HF_MP_SHIFT 9 /* the order must be MP, EM, TS */ |
| 176 | #define HF_EM_SHIFT 10 |
| 177 | #define HF_TS_SHIFT 11 |
| 178 | #define HF_IOPL_SHIFT 12 /* must be same as eflags */ |
| 179 | #define HF_LMA_SHIFT 14 /* only used on x86_64: long mode active */ |
| 180 | #define HF_CS64_SHIFT 15 /* only used on x86_64: 64 bit code segment */ |
| 181 | #define HF_RF_SHIFT 16 /* must be same as eflags */ |
| 182 | #define HF_VM_SHIFT 17 /* must be same as eflags */ |
| 183 | #define HF_AC_SHIFT 18 /* must be same as eflags */ |
| 184 | #define HF_SMM_SHIFT 19 /* CPU in SMM mode */ |
| 185 | #define HF_SVME_SHIFT 20 /* SVME enabled (copy of EFER.SVME) */ |
| 186 | #define HF_GUEST_SHIFT 21 /* SVM intercepts are active */ |
| 187 | #define HF_OSFXSR_SHIFT 22 /* CR4.OSFXSR */ |
| 188 | #define HF_SMAP_SHIFT 23 /* CR4.SMAP */ |
| 189 | #define HF_IOBPT_SHIFT 24 /* an io breakpoint enabled */ |
| 190 | #define HF_MPX_EN_SHIFT 25 /* MPX Enabled (CR4+XCR0+BNDCFGx) */ |
| 191 | #define HF_MPX_IU_SHIFT 26 /* BND registers in-use */ |
| 192 | #define HF_UMIP_SHIFT 27 /* CR4.UMIP */ |
| 193 | #define HF_AVX_EN_SHIFT 28 /* AVX Enabled (CR4+XCR0) */ |
| 194 | |
| 195 | #define HF_CPL_MASK (3 << HF_CPL_SHIFT) |
| 196 | #define HF_INHIBIT_IRQ_MASK (1 << HF_INHIBIT_IRQ_SHIFT) |
| 197 | #define HF_CS32_MASK (1 << HF_CS32_SHIFT) |
| 198 | #define HF_SS32_MASK (1 << HF_SS32_SHIFT) |
| 199 | #define HF_ADDSEG_MASK (1 << HF_ADDSEG_SHIFT) |
| 200 | #define HF_PE_MASK (1 << HF_PE_SHIFT) |
| 201 | #define HF_TF_MASK (1 << HF_TF_SHIFT) |
| 202 | #define HF_MP_MASK (1 << HF_MP_SHIFT) |
| 203 | #define HF_EM_MASK (1 << HF_EM_SHIFT) |
| 204 | #define HF_TS_MASK (1 << HF_TS_SHIFT) |
| 205 | #define HF_IOPL_MASK (3 << HF_IOPL_SHIFT) |
| 206 | #define HF_LMA_MASK (1 << HF_LMA_SHIFT) |
| 207 | #define HF_CS64_MASK (1 << HF_CS64_SHIFT) |
| 208 | #define HF_RF_MASK (1 << HF_RF_SHIFT) |
| 209 | #define HF_VM_MASK (1 << HF_VM_SHIFT) |
| 210 | #define HF_AC_MASK (1 << HF_AC_SHIFT) |
| 211 | #define HF_SMM_MASK (1 << HF_SMM_SHIFT) |
| 212 | #define HF_SVME_MASK (1 << HF_SVME_SHIFT) |
| 213 | #define HF_GUEST_MASK (1 << HF_GUEST_SHIFT) |
| 214 | #define HF_OSFXSR_MASK (1 << HF_OSFXSR_SHIFT) |
| 215 | #define HF_SMAP_MASK (1 << HF_SMAP_SHIFT) |
| 216 | #define HF_IOBPT_MASK (1 << HF_IOBPT_SHIFT) |
| 217 | #define HF_MPX_EN_MASK (1 << HF_MPX_EN_SHIFT) |
| 218 | #define HF_MPX_IU_MASK (1 << HF_MPX_IU_SHIFT) |
| 219 | #define HF_UMIP_MASK (1 << HF_UMIP_SHIFT) |
| 220 | #define HF_AVX_EN_MASK (1 << HF_AVX_EN_SHIFT) |
| 221 | |
| 222 | /* hflags2 */ |
| 223 | |
| 224 | #define HF2_GIF_SHIFT 0 /* if set CPU takes interrupts */ |
| 225 | #define HF2_HIF_SHIFT 1 /* value of IF_MASK when entering SVM */ |
| 226 | #define HF2_NMI_SHIFT 2 /* CPU serving NMI */ |
| 227 | #define HF2_VINTR_SHIFT 3 /* value of V_INTR_MASKING bit */ |
| 228 | #define HF2_SMM_INSIDE_NMI_SHIFT 4 /* CPU serving SMI nested inside NMI */ |
| 229 | #define HF2_MPX_PR_SHIFT 5 /* BNDCFGx.BNDPRESERVE */ |
| 230 | #define HF2_NPT_SHIFT 6 /* Nested Paging enabled */ |
| 231 | #define HF2_IGNNE_SHIFT 7 /* Ignore CR0.NE=0 */ |
| 232 | #define HF2_VGIF_SHIFT 8 /* Can take VIRQ*/ |
| 233 | #define HF2_HYPERV_HLT_SHIFT 9 /* Hyper-V HV_X64_MSR_GUEST_IDLE */ |
| 234 | |
| 235 | #define HF2_GIF_MASK (1 << HF2_GIF_SHIFT) |
| 236 | #define HF2_HIF_MASK (1 << HF2_HIF_SHIFT) |
| 237 | #define HF2_NMI_MASK (1 << HF2_NMI_SHIFT) |
| 238 | #define HF2_VINTR_MASK (1 << HF2_VINTR_SHIFT) |
| 239 | #define HF2_SMM_INSIDE_NMI_MASK (1 << HF2_SMM_INSIDE_NMI_SHIFT) |
| 240 | #define HF2_MPX_PR_MASK (1 << HF2_MPX_PR_SHIFT) |
| 241 | #define HF2_NPT_MASK (1 << HF2_NPT_SHIFT) |
| 242 | #define HF2_IGNNE_MASK (1 << HF2_IGNNE_SHIFT) |
| 243 | #define HF2_VGIF_MASK (1 << HF2_VGIF_SHIFT) |
| 244 | #define HF2_HYPERV_HLT_MASK (1 << HF2_HYPERV_HLT_SHIFT) |
| 245 | |
| 246 | #define CR0_PE_SHIFT 0 |
| 247 | #define CR0_MP_SHIFT 1 |
| 248 | |
| 249 | #define CR0_PE_MASK (1U << 0) |
| 250 | #define CR0_MP_MASK (1U << 1) |
| 251 | #define CR0_EM_MASK (1U << 2) |
| 252 | #define CR0_TS_MASK (1U << 3) |
| 253 | #define CR0_ET_MASK (1U << 4) |
| 254 | #define CR0_NE_MASK (1U << 5) |
| 255 | #define CR0_WP_MASK (1U << 16) |
| 256 | #define CR0_AM_MASK (1U << 18) |
| 257 | #define CR0_NW_MASK (1U << 29) |
| 258 | #define CR0_CD_MASK (1U << 30) |
| 259 | #define CR0_PG_MASK (1U << 31) |
| 260 | |
| 261 | #define CR4_VME_MASK (1U << 0) |
| 262 | #define CR4_PVI_MASK (1U << 1) |
| 263 | #define CR4_TSD_MASK (1U << 2) |
| 264 | #define CR4_DE_MASK (1U << 3) |
| 265 | #define CR4_PSE_MASK (1U << 4) |
| 266 | #define CR4_PAE_MASK (1U << 5) |
| 267 | #define CR4_MCE_MASK (1U << 6) |
| 268 | #define CR4_PGE_MASK (1U << 7) |
| 269 | #define CR4_PCE_MASK (1U << 8) |
| 270 | #define CR4_OSFXSR_SHIFT 9 |
| 271 | #define CR4_OSFXSR_MASK (1U << CR4_OSFXSR_SHIFT) |
| 272 | #define CR4_OSXMMEXCPT_MASK (1U << 10) |
| 273 | #define CR4_UMIP_MASK (1U << 11) |
| 274 | #define CR4_LA57_MASK (1U << 12) |
| 275 | #define CR4_VMXE_MASK (1U << 13) |
| 276 | #define CR4_SMXE_MASK (1U << 14) |
| 277 | #define CR4_FSGSBASE_MASK (1U << 16) |
| 278 | #define CR4_PCIDE_MASK (1U << 17) |
| 279 | #define CR4_OSXSAVE_MASK (1U << 18) |
| 280 | #define CR4_SMEP_MASK (1U << 20) |
| 281 | #define CR4_SMAP_MASK (1U << 21) |
| 282 | #define CR4_PKE_MASK (1U << 22) |
| 283 | #define CR4_CET_MASK (1U << 23) |
| 284 | #define CR4_PKS_MASK (1U << 24) |
| 285 | #define CR4_LAM_SUP_MASK (1U << 28) |
| 286 | |
| 287 | #ifdef TARGET_X86_64 |
| 288 | #define CR4_FRED_MASK (1ULL << 32) |
| 289 | #else |
| 290 | #define CR4_FRED_MASK 0 |
| 291 | #endif |
| 292 | |
| 293 | #define CR4_RESERVED_MASK \ |
| 294 | (~(target_ulong)(CR4_VME_MASK | CR4_PVI_MASK | CR4_TSD_MASK \ |
| 295 | | CR4_DE_MASK | CR4_PSE_MASK | CR4_PAE_MASK \ |
| 296 | | CR4_MCE_MASK | CR4_PGE_MASK | CR4_PCE_MASK \ |
| 297 | | CR4_OSFXSR_MASK | CR4_OSXMMEXCPT_MASK | CR4_UMIP_MASK \ |
| 298 | | CR4_LA57_MASK \ |
| 299 | | CR4_FSGSBASE_MASK | CR4_PCIDE_MASK | CR4_OSXSAVE_MASK \ |
| 300 | | CR4_SMEP_MASK | CR4_SMAP_MASK | CR4_PKE_MASK | CR4_CET_MASK \ |
| 301 | | CR4_PKS_MASK | CR4_LAM_SUP_MASK | CR4_FRED_MASK)) |
| 302 | |
| 303 | #define DR6_BD (1 << 13) |
| 304 | #define DR6_BS (1 << 14) |
| 305 | #define DR6_BT (1 << 15) |
| 306 | #define DR6_FIXED_1 0xffff0ff0 |
| 307 | |
| 308 | #define DR7_GD (1 << 13) |
| 309 | #define DR7_TYPE_SHIFT 16 |
| 310 | #define DR7_LEN_SHIFT 18 |
| 311 | #define DR7_FIXED_1 0x00000400 |
| 312 | #define DR7_GLOBAL_BP_MASK 0xaa |
| 313 | #define DR7_LOCAL_BP_MASK 0x55 |
| 314 | #define DR7_MAX_BP 4 |
| 315 | #define DR7_TYPE_BP_INST 0x0 |
| 316 | #define DR7_TYPE_DATA_WR 0x1 |
| 317 | #define DR7_TYPE_IO_RW 0x2 |
| 318 | #define DR7_TYPE_DATA_RW 0x3 |
| 319 | |
| 320 | #define DR_RESERVED_MASK 0xffffffff00000000ULL |
| 321 | |
| 322 | #define PG_PRESENT_BIT 0 |
| 323 | #define PG_RW_BIT 1 |
| 324 | #define PG_USER_BIT 2 |
| 325 | #define PG_PWT_BIT 3 |
| 326 | #define PG_PCD_BIT 4 |
| 327 | #define PG_ACCESSED_BIT 5 |
| 328 | #define PG_DIRTY_BIT 6 |
| 329 | #define PG_PSE_BIT 7 |
| 330 | #define PG_GLOBAL_BIT 8 |
| 331 | #define PG_PSE_PAT_BIT 12 |
| 332 | #define PG_PKRU_BIT 59 |
| 333 | #define PG_NX_BIT 63 |
| 334 | |
| 335 | #define PG_PRESENT_MASK (1 << PG_PRESENT_BIT) |
| 336 | #define PG_RW_MASK (1 << PG_RW_BIT) |
| 337 | #define PG_USER_MASK (1 << PG_USER_BIT) |
| 338 | #define PG_PWT_MASK (1 << PG_PWT_BIT) |
| 339 | #define PG_PCD_MASK (1 << PG_PCD_BIT) |
| 340 | #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT) |
| 341 | #define PG_DIRTY_MASK (1 << PG_DIRTY_BIT) |
| 342 | #define PG_PSE_MASK (1 << PG_PSE_BIT) |
| 343 | #define PG_GLOBAL_MASK (1 << PG_GLOBAL_BIT) |
| 344 | #define PG_PSE_PAT_MASK (1 << PG_PSE_PAT_BIT) |
| 345 | #define PG_ADDRESS_MASK 0x000ffffffffff000LL |
| 346 | #define PG_HI_USER_MASK 0x7ff0000000000000LL |
| 347 | #define PG_PKRU_MASK (15ULL << PG_PKRU_BIT) |
| 348 | #define PG_NX_MASK (1ULL << PG_NX_BIT) |
| 349 | |
| 350 | #define PG_ERROR_W_BIT 1 |
| 351 | |
| 352 | #define PG_ERROR_P_MASK 0x01 |
| 353 | #define PG_ERROR_W_MASK (1 << PG_ERROR_W_BIT) |
| 354 | #define PG_ERROR_U_MASK 0x04 |
| 355 | #define PG_ERROR_RSVD_MASK 0x08 |
| 356 | #define PG_ERROR_I_D_MASK 0x10 |
| 357 | #define PG_ERROR_PK_MASK 0x20 |
| 358 | |
| 359 | #define PG_MODE_PAE (1 << 0) |
| 360 | #define PG_MODE_LMA (1 << 1) |
| 361 | #define PG_MODE_NXE (1 << 2) |
| 362 | #define PG_MODE_PSE (1 << 3) |
| 363 | #define PG_MODE_LA57 (1 << 4) |
| 364 | #define PG_MODE_SVM_MASK MAKE_64BIT_MASK(0, 15) |
| 365 | |
| 366 | /* Bits of CR4 that do not affect the NPT page format. */ |
| 367 | #define PG_MODE_WP (1 << 16) |
| 368 | #define PG_MODE_PKE (1 << 17) |
| 369 | #define PG_MODE_PKS (1 << 18) |
| 370 | #define PG_MODE_SMEP (1 << 19) |
| 371 | #define PG_MODE_PG (1 << 20) |
| 372 | |
| 373 | #define MCG_CTL_P (1ULL<<8) /* MCG_CAP register available */ |
| 374 | #define MCG_SER_P (1ULL<<24) /* MCA recovery/new status bits */ |
| 375 | #define MCG_LMCE_P (1ULL<<27) /* Local Machine Check Supported */ |
| 376 | |
| 377 | #define MCE_CAP_DEF (MCG_CTL_P|MCG_SER_P) |
| 378 | #define MCE_BANKS_DEF 10 |
| 379 | |
| 380 | #define MCG_CAP_BANKS_MASK 0xff |
| 381 | |
| 382 | #define MCG_STATUS_RIPV (1ULL<<0) /* restart ip valid */ |
| 383 | #define MCG_STATUS_EIPV (1ULL<<1) /* ip points to correct instruction */ |
| 384 | #define MCG_STATUS_MCIP (1ULL<<2) /* machine check in progress */ |
| 385 | #define MCG_STATUS_LMCE (1ULL<<3) /* Local MCE signaled */ |
| 386 | |
| 387 | #define MCG_EXT_CTL_LMCE_EN (1ULL<<0) /* Local MCE enabled */ |
| 388 | |
| 389 | #define MCI_STATUS_VAL (1ULL<<63) /* valid error */ |
| 390 | #define MCI_STATUS_OVER (1ULL<<62) /* previous errors lost */ |
| 391 | #define MCI_STATUS_UC (1ULL<<61) /* uncorrected error */ |
| 392 | #define MCI_STATUS_EN (1ULL<<60) /* error enabled */ |
| 393 | #define MCI_STATUS_MISCV (1ULL<<59) /* misc error reg. valid */ |
| 394 | #define MCI_STATUS_ADDRV (1ULL<<58) /* addr reg. valid */ |
| 395 | #define MCI_STATUS_PCC (1ULL<<57) /* processor context corrupt */ |
| 396 | #define MCI_STATUS_S (1ULL<<56) /* Signaled machine check */ |
| 397 | #define MCI_STATUS_AR (1ULL<<55) /* Action required */ |
| 398 | #define MCI_STATUS_DEFERRED (1ULL<<44) /* Deferred error */ |
| 399 | #define MCI_STATUS_POISON (1ULL<<43) /* Poisoned data consumed */ |
| 400 | |
| 401 | /* MISC register defines */ |
| 402 | #define MCM_ADDR_SEGOFF 0 /* segment offset */ |
| 403 | #define MCM_ADDR_LINEAR 1 /* linear address */ |
| 404 | #define MCM_ADDR_PHYS 2 /* physical address */ |
| 405 | #define MCM_ADDR_MEM 3 /* memory address */ |
| 406 | #define MCM_ADDR_GENERIC 7 /* generic */ |
| 407 | |
| 408 | #define MSR_IA32_TSC 0x10 |
| 409 | #define MSR_IA32_APICBASE 0x1b |
| 410 | #define MSR_IA32_APICBASE_BSP (1<<8) |
| 411 | #define MSR_IA32_APICBASE_ENABLE (1<<11) |
| 412 | #define MSR_IA32_APICBASE_EXTD (1 << 10) |
| 413 | #define MSR_IA32_APICBASE_BASE (0xfffffU<<12) |
| 414 | #define MSR_IA32_APICBASE_RESERVED \ |
| 415 | (~(uint64_t)(MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE \ |
| 416 | | MSR_IA32_APICBASE_EXTD | MSR_IA32_APICBASE_BASE)) |
| 417 | |
| 418 | #define MSR_IA32_FEATURE_CONTROL 0x0000003a |
| 419 | #define MSR_TSC_ADJUST 0x0000003b |
| 420 | #define MSR_IA32_SPEC_CTRL 0x48 |
| 421 | #define MSR_VIRT_SSBD 0xc001011f |
| 422 | #define MSR_IA32_PRED_CMD 0x49 |
| 423 | #define MSR_IA32_UCODE_REV 0x8b |
| 424 | #define MSR_IA32_CORE_CAPABILITY 0xcf |
| 425 | |
| 426 | #define MSR_IA32_ARCH_CAPABILITIES 0x10a |
| 427 | #define ARCH_CAP_TSX_CTRL_MSR (1 << 7) |
| 428 | |
| 429 | #define MSR_IA32_PERF_CAPABILITIES 0x345 |
| 430 | #define PERF_CAP_LBR_FMT 0x3f |
| 431 | |
| 432 | #define MSR_IA32_TSX_CTRL 0x122 |
| 433 | #define MSR_IA32_TSCDEADLINE 0x6e0 |
| 434 | #define MSR_IA32_PKRS 0x6e1 |
| 435 | #define MSR_RAPL_POWER_UNIT 0x00000606 |
| 436 | #define MSR_PKG_POWER_LIMIT 0x00000610 |
| 437 | #define MSR_PKG_ENERGY_STATUS 0x00000611 |
| 438 | #define MSR_PKG_POWER_INFO 0x00000614 |
| 439 | #define MSR_ARCH_LBR_CTL 0x000014ce |
| 440 | #define MSR_ARCH_LBR_DEPTH 0x000014cf |
| 441 | #define MSR_ARCH_LBR_FROM_0 0x00001500 |
| 442 | #define MSR_ARCH_LBR_TO_0 0x00001600 |
| 443 | #define MSR_ARCH_LBR_INFO_0 0x00001200 |
| 444 | |
| 445 | #define FEATURE_CONTROL_LOCKED (1<<0) |
| 446 | #define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX (1ULL << 1) |
| 447 | #define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2) |
| 448 | #define FEATURE_CONTROL_SGX_LC (1ULL << 17) |
| 449 | #define FEATURE_CONTROL_SGX (1ULL << 18) |
| 450 | #define FEATURE_CONTROL_LMCE (1<<20) |
| 451 | |
| 452 | #define MSR_IA32_SGXLEPUBKEYHASH0 0x8c |
| 453 | #define MSR_IA32_SGXLEPUBKEYHASH1 0x8d |
| 454 | #define MSR_IA32_SGXLEPUBKEYHASH2 0x8e |
| 455 | #define MSR_IA32_SGXLEPUBKEYHASH3 0x8f |
| 456 | |
| 457 | #define MSR_P6_PERFCTR0 0xc1 |
| 458 | |
| 459 | #define MSR_IA32_SMBASE 0x9e |
| 460 | #define MSR_SMI_COUNT 0x34 |
| 461 | #define MSR_CORE_THREAD_COUNT 0x35 |
| 462 | #define MSR_MTRRcap 0xfe |
| 463 | #define MSR_MTRR_MEM_TYPE_WB 0x06 |
| 464 | #define MSR_MTRRcap_VCNT 8 |
| 465 | #define MSR_MTRRcap_FIXRANGE_SUPPORT (1 << 8) |
| 466 | #define MSR_MTRRcap_WC_SUPPORTED (1 << 10) |
| 467 | #define MSR_MTRR_ENABLE (1 << 11) |
| 468 | |
| 469 | #define MSR_IA32_SYSENTER_CS 0x174 |
| 470 | #define MSR_IA32_SYSENTER_ESP 0x175 |
| 471 | #define MSR_IA32_SYSENTER_EIP 0x176 |
| 472 | |
| 473 | #define MSR_MCG_CAP 0x179 |
| 474 | #define MSR_MCG_STATUS 0x17a |
| 475 | #define MSR_MCG_CTL 0x17b |
| 476 | #define MSR_MCG_EXT_CTL 0x4d0 |
| 477 | |
| 478 | #define MSR_P6_EVNTSEL0 0x186 |
| 479 | |
| 480 | #define MSR_IA32_PERF_STATUS 0x198 |
| 481 | |
| 482 | #define MSR_IA32_MISC_ENABLE 0x1a0 |
| 483 | /* Indicates good rep/movs microcode on some processors: */ |
| 484 | #define MSR_IA32_MISC_ENABLE_DEFAULT 1 |
| 485 | #define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << 18) |
| 486 | |
| 487 | #define MSR_MTRRphysBase(reg) (0x200 + 2 * (reg)) |
| 488 | #define MSR_MTRRphysMask(reg) (0x200 + 2 * (reg) + 1) |
| 489 | |
| 490 | #define MSR_MTRRphysIndex(addr) ((((addr) & ~1u) - 0x200) / 2) |
| 491 | |
| 492 | #define MSR_MTRRfix64K_00000 0x250 |
| 493 | #define MSR_MTRRfix16K_80000 0x258 |
| 494 | #define MSR_MTRRfix16K_A0000 0x259 |
| 495 | #define MSR_MTRRfix4K_C0000 0x268 |
| 496 | #define MSR_MTRRfix4K_C8000 0x269 |
| 497 | #define MSR_MTRRfix4K_D0000 0x26a |
| 498 | #define MSR_MTRRfix4K_D8000 0x26b |
| 499 | #define MSR_MTRRfix4K_E0000 0x26c |
| 500 | #define MSR_MTRRfix4K_E8000 0x26d |
| 501 | #define MSR_MTRRfix4K_F0000 0x26e |
| 502 | #define MSR_MTRRfix4K_F8000 0x26f |
| 503 | |
| 504 | #define MSR_PAT 0x277 |
| 505 | |
| 506 | #define MSR_MTRRdefType 0x2ff |
| 507 | |
| 508 | #define MSR_CORE_PERF_FIXED_CTR0 0x309 |
| 509 | #define MSR_CORE_PERF_FIXED_CTR1 0x30a |
| 510 | #define MSR_CORE_PERF_FIXED_CTR2 0x30b |
| 511 | #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x38d |
| 512 | #define MSR_CORE_PERF_GLOBAL_STATUS 0x38e |
| 513 | #define MSR_CORE_PERF_GLOBAL_CTRL 0x38f |
| 514 | #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x390 |
| 515 | |
| 516 | #define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS 0xc0000300 |
| 517 | #define MSR_AMD64_PERF_CNTR_GLOBAL_CTL 0xc0000301 |
| 518 | #define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR 0xc0000302 |
| 519 | |
| 520 | #define MSR_K7_EVNTSEL0 0xc0010000 |
| 521 | #define MSR_K7_PERFCTR0 0xc0010004 |
| 522 | #define MSR_F15H_PERF_CTL0 0xc0010200 |
| 523 | #define MSR_F15H_PERF_CTR0 0xc0010201 |
| 524 | |
| 525 | #define AMD64_NUM_COUNTERS 4 |
| 526 | #define AMD64_NUM_COUNTERS_CORE 6 |
| 527 | |
| 528 | #define MSR_MC0_CTL 0x400 |
| 529 | #define MSR_MC0_STATUS 0x401 |
| 530 | #define MSR_MC0_ADDR 0x402 |
| 531 | #define MSR_MC0_MISC 0x403 |
| 532 | |
| 533 | #define MSR_IA32_RTIT_OUTPUT_BASE 0x560 |
| 534 | #define MSR_IA32_RTIT_OUTPUT_MASK 0x561 |
| 535 | #define MSR_IA32_RTIT_CTL 0x570 |
| 536 | #define MSR_IA32_RTIT_STATUS 0x571 |
| 537 | #define MSR_IA32_RTIT_CR3_MATCH 0x572 |
| 538 | #define MSR_IA32_RTIT_ADDR0_A 0x580 |
| 539 | #define MSR_IA32_RTIT_ADDR0_B 0x581 |
| 540 | #define MSR_IA32_RTIT_ADDR1_A 0x582 |
| 541 | #define MSR_IA32_RTIT_ADDR1_B 0x583 |
| 542 | #define MSR_IA32_RTIT_ADDR2_A 0x584 |
| 543 | #define MSR_IA32_RTIT_ADDR2_B 0x585 |
| 544 | #define MSR_IA32_RTIT_ADDR3_A 0x586 |
| 545 | #define MSR_IA32_RTIT_ADDR3_B 0x587 |
| 546 | #define MAX_RTIT_ADDRS 8 |
| 547 | |
| 548 | #define MSR_EFER 0xc0000080 |
| 549 | |
| 550 | #define MSR_EFER_SCE (1 << 0) |
| 551 | #define MSR_EFER_LME (1 << 8) |
| 552 | #define MSR_EFER_LMA (1 << 10) |
| 553 | #define MSR_EFER_NXE (1 << 11) |
| 554 | #define MSR_EFER_SVME (1 << 12) |
| 555 | #define MSR_EFER_FFXSR (1 << 14) |
| 556 | |
| 557 | #define MSR_EFER_RESERVED\ |
| 558 | (~(target_ulong)(MSR_EFER_SCE | MSR_EFER_LME\ |
| 559 | | MSR_EFER_LMA | MSR_EFER_NXE | MSR_EFER_SVME\ |
| 560 | | MSR_EFER_FFXSR)) |
| 561 | |
| 562 | #define MSR_STAR 0xc0000081 |
| 563 | #define MSR_LSTAR 0xc0000082 |
| 564 | #define MSR_CSTAR 0xc0000083 |
| 565 | #define MSR_FMASK 0xc0000084 |
| 566 | #define MSR_FSBASE 0xc0000100 |
| 567 | #define MSR_GSBASE 0xc0000101 |
| 568 | #define MSR_KERNELGSBASE 0xc0000102 |
| 569 | #define MSR_TSC_AUX 0xc0000103 |
| 570 | #define MSR_AMD64_TSC_RATIO 0xc0000104 |
| 571 | |
| 572 | #define MSR_AMD64_TSC_RATIO_DEFAULT 0x100000000ULL |
| 573 | |
| 574 | #define MSR_K7_HWCR 0xc0010015 |
| 575 | |
| 576 | #define MSR_VM_HSAVE_PA 0xc0010117 |
| 577 | |
| 578 | #define MSR_IA32_XFD 0x000001c4 |
| 579 | #define MSR_IA32_XFD_ERR 0x000001c5 |
| 580 | |
| 581 | /* FRED MSRs (MSR_IA32_FRED_SSP0 is defined as MSR_IA32_PL0_SSP in CET MSRs) */ |
| 582 | #define MSR_IA32_FRED_RSP0 0x000001cc /* Stack level 0 regular stack pointer */ |
| 583 | #define MSR_IA32_FRED_RSP1 0x000001cd /* Stack level 1 regular stack pointer */ |
| 584 | #define MSR_IA32_FRED_RSP2 0x000001ce /* Stack level 2 regular stack pointer */ |
| 585 | #define MSR_IA32_FRED_RSP3 0x000001cf /* Stack level 3 regular stack pointer */ |
| 586 | #define MSR_IA32_FRED_STKLVLS 0x000001d0 /* FRED exception stack levels */ |
| 587 | #define MSR_IA32_FRED_SSP1 0x000001d1 /* Stack level 1 shadow stack pointer in ring 0 */ |
| 588 | #define MSR_IA32_FRED_SSP2 0x000001d2 /* Stack level 2 shadow stack pointer in ring 0 */ |
| 589 | #define MSR_IA32_FRED_SSP3 0x000001d3 /* Stack level 3 shadow stack pointer in ring 0 */ |
| 590 | #define MSR_IA32_FRED_CONFIG 0x000001d4 /* FRED Entrypoint and interrupt stack level */ |
| 591 | |
| 592 | #define MSR_IA32_BNDCFGS 0x00000d90 |
| 593 | #define MSR_IA32_XSS 0x00000da0 |
| 594 | #define MSR_IA32_UMWAIT_CONTROL 0xe1 |
| 595 | |
| 596 | #define MSR_IA32_VMX_BASIC 0x00000480 |
| 597 | #define MSR_IA32_VMX_PINBASED_CTLS 0x00000481 |
| 598 | #define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482 |
| 599 | #define MSR_IA32_VMX_EXIT_CTLS 0x00000483 |
| 600 | #define MSR_IA32_VMX_ENTRY_CTLS 0x00000484 |
| 601 | #define MSR_IA32_VMX_MISC 0x00000485 |
| 602 | #define MSR_IA32_VMX_CR0_FIXED0 0x00000486 |
| 603 | #define MSR_IA32_VMX_CR0_FIXED1 0x00000487 |
| 604 | #define MSR_IA32_VMX_CR4_FIXED0 0x00000488 |
| 605 | #define MSR_IA32_VMX_CR4_FIXED1 0x00000489 |
| 606 | #define MSR_IA32_VMX_VMCS_ENUM 0x0000048a |
| 607 | #define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b |
| 608 | #define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c |
| 609 | #define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d |
| 610 | #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e |
| 611 | #define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f |
| 612 | #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490 |
| 613 | #define MSR_IA32_VMX_VMFUNC 0x00000491 |
| 614 | |
| 615 | #define MSR_APIC_START 0x00000800 |
| 616 | #define MSR_APIC_END 0x000008ff |
| 617 | |
| 618 | /* CET MSRs */ |
| 619 | #define MSR_IA32_U_CET 0x000006a0 /* user mode cet */ |
| 620 | #define MSR_IA32_S_CET 0x000006a2 /* kernel mode cet */ |
| 621 | #define MSR_IA32_PL0_SSP 0x000006a4 /* ring-0 shadow stack pointer */ |
| 622 | #define MSR_IA32_PL1_SSP 0x000006a5 /* ring-1 shadow stack pointer */ |
| 623 | #define MSR_IA32_PL2_SSP 0x000006a6 /* ring-2 shadow stack pointer */ |
| 624 | #define MSR_IA32_PL3_SSP 0x000006a7 /* ring-3 shadow stack pointer */ |
| 625 | #define MSR_IA32_INT_SSP_TAB 0x000006a8 /* exception shadow stack table */ |
| 626 | |
| 627 | #define XSTATE_FP_BIT 0 |
| 628 | #define XSTATE_SSE_BIT 1 |
| 629 | #define XSTATE_YMM_BIT 2 |
| 630 | #define XSTATE_BNDREGS_BIT 3 |
| 631 | #define XSTATE_BNDCSR_BIT 4 |
| 632 | #define XSTATE_OPMASK_BIT 5 |
| 633 | #define XSTATE_ZMM_Hi256_BIT 6 |
| 634 | #define XSTATE_Hi16_ZMM_BIT 7 |
| 635 | #define XSTATE_PT_BIT 8 |
| 636 | #define XSTATE_PKRU_BIT 9 |
| 637 | #define XSTATE_CET_U_BIT 11 |
| 638 | #define XSTATE_CET_S_BIT 12 |
| 639 | #define XSTATE_ARCH_LBR_BIT 15 |
| 640 | #define XSTATE_XTILE_CFG_BIT 17 |
| 641 | #define XSTATE_XTILE_DATA_BIT 18 |
| 642 | #define XSTATE_APX_BIT 19 |
| 643 | |
| 644 | #define XSTATE_FP_MASK (1ULL << XSTATE_FP_BIT) |
| 645 | #define XSTATE_SSE_MASK (1ULL << XSTATE_SSE_BIT) |
| 646 | #define XSTATE_YMM_MASK (1ULL << XSTATE_YMM_BIT) |
| 647 | #define XSTATE_BNDREGS_MASK (1ULL << XSTATE_BNDREGS_BIT) |
| 648 | #define XSTATE_BNDCSR_MASK (1ULL << XSTATE_BNDCSR_BIT) |
| 649 | #define XSTATE_OPMASK_MASK (1ULL << XSTATE_OPMASK_BIT) |
| 650 | #define XSTATE_ZMM_Hi256_MASK (1ULL << XSTATE_ZMM_Hi256_BIT) |
| 651 | #define XSTATE_Hi16_ZMM_MASK (1ULL << XSTATE_Hi16_ZMM_BIT) |
| 652 | #define XSTATE_PT_MASK (1ULL << XSTATE_PT_BIT) |
| 653 | #define XSTATE_PKRU_MASK (1ULL << XSTATE_PKRU_BIT) |
| 654 | #define XSTATE_CET_U_MASK (1ULL << XSTATE_CET_U_BIT) |
| 655 | #define XSTATE_CET_S_MASK (1ULL << XSTATE_CET_S_BIT) |
| 656 | #define XSTATE_ARCH_LBR_MASK (1ULL << XSTATE_ARCH_LBR_BIT) |
| 657 | #define XSTATE_XTILE_CFG_MASK (1ULL << XSTATE_XTILE_CFG_BIT) |
| 658 | #define XSTATE_XTILE_DATA_MASK (1ULL << XSTATE_XTILE_DATA_BIT) |
| 659 | #define XSTATE_APX_MASK (1ULL << XSTATE_APX_BIT) |
| 660 | |
| 661 | #define XSTATE_DYNAMIC_MASK (XSTATE_XTILE_DATA_MASK) |
| 662 | |
| 663 | #define ESA_FEATURE_XSS_BIT 0 |
| 664 | #define ESA_FEATURE_ALIGN64_BIT 1 |
| 665 | #define ESA_FEATURE_XFD_BIT 2 |
| 666 | |
| 667 | #define ESA_FEATURE_XSS_MASK (1U << ESA_FEATURE_XSS_BIT) |
| 668 | #define ESA_FEATURE_ALIGN64_MASK (1U << ESA_FEATURE_ALIGN64_BIT) |
| 669 | #define ESA_FEATURE_XFD_MASK (1U << ESA_FEATURE_XFD_BIT) |
| 670 | |
| 671 | |
| 672 | /* CPUID feature bits available in XCR0 */ |
| 673 | #define CPUID_XSTATE_XCR0_MASK (XSTATE_FP_MASK | XSTATE_SSE_MASK | \ |
| 674 | XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | \ |
| 675 | XSTATE_BNDCSR_MASK | XSTATE_OPMASK_MASK | \ |
| 676 | XSTATE_ZMM_Hi256_MASK | \ |
| 677 | XSTATE_Hi16_ZMM_MASK | XSTATE_PKRU_MASK | \ |
| 678 | XSTATE_XTILE_CFG_MASK | \ |
| 679 | XSTATE_XTILE_DATA_MASK | XSTATE_APX_MASK) |
| 680 | |
| 681 | /* CPUID feature bits available in XSS */ |
| 682 | #define CPUID_XSTATE_XSS_MASK (XSTATE_ARCH_LBR_MASK | XSTATE_CET_U_MASK | \ |
| 683 | XSTATE_CET_S_MASK) |
| 684 | |
| 685 | #define CPUID_XSTATE_MASK (CPUID_XSTATE_XCR0_MASK | CPUID_XSTATE_XSS_MASK) |
| 686 | |
| 687 | /* CPUID feature words */ |
| 688 | typedef enum FeatureWord { |
| 689 | FEAT_1_EDX, /* CPUID[1].EDX */ |
| 690 | FEAT_1_ECX, /* CPUID[1].ECX */ |
| 691 | FEAT_7_0_EBX, /* CPUID[EAX=7,ECX=0].EBX */ |
| 692 | FEAT_7_0_ECX, /* CPUID[EAX=7,ECX=0].ECX */ |
| 693 | FEAT_7_0_EDX, /* CPUID[EAX=7,ECX=0].EDX */ |
| 694 | FEAT_7_1_EAX, /* CPUID[EAX=7,ECX=1].EAX */ |
| 695 | FEAT_8000_0001_EDX, /* CPUID[8000_0001].EDX */ |
| 696 | FEAT_8000_0001_ECX, /* CPUID[8000_0001].ECX */ |
| 697 | FEAT_8000_0007_EBX, /* CPUID[8000_0007].EBX */ |
| 698 | FEAT_8000_0007_EDX, /* CPUID[8000_0007].EDX */ |
| 699 | FEAT_8000_0008_EBX, /* CPUID[8000_0008].EBX */ |
| 700 | FEAT_8000_0021_EAX, /* CPUID[8000_0021].EAX */ |
| 701 | FEAT_8000_0021_EBX, /* CPUID[8000_0021].EBX */ |
| 702 | FEAT_8000_0021_ECX, /* CPUID[8000_0021].ECX */ |
| 703 | FEAT_8000_0022_EAX, /* CPUID[8000_0022].EAX */ |
| 704 | FEAT_C000_0001_EDX, /* CPUID[C000_0001].EDX */ |
| 705 | FEAT_KVM, /* CPUID[4000_0001].EAX (KVM_CPUID_FEATURES) */ |
| 706 | FEAT_KVM_HINTS, /* CPUID[4000_0001].EDX */ |
| 707 | FEAT_SVM, /* CPUID[8000_000A].EDX */ |
| 708 | FEAT_XSAVE, /* CPUID[EAX=0xd,ECX=1].EAX */ |
| 709 | FEAT_6_EAX, /* CPUID[6].EAX */ |
| 710 | FEAT_XSAVE_XCR0_LO, /* CPUID[EAX=0xd,ECX=0].EAX */ |
| 711 | FEAT_XSAVE_XCR0_HI, /* CPUID[EAX=0xd,ECX=0].EDX */ |
| 712 | FEAT_ARCH_CAPABILITIES, |
| 713 | FEAT_CORE_CAPABILITY, |
| 714 | FEAT_PERF_CAPABILITIES, |
| 715 | FEAT_VMX_PROCBASED_CTLS, |
| 716 | FEAT_VMX_SECONDARY_CTLS, |
| 717 | FEAT_VMX_PINBASED_CTLS, |
| 718 | FEAT_VMX_EXIT_CTLS, |
| 719 | FEAT_VMX_ENTRY_CTLS, |
| 720 | FEAT_VMX_MISC, |
| 721 | FEAT_VMX_EPT_VPID_CAPS, |
| 722 | FEAT_VMX_BASIC, |
| 723 | FEAT_VMX_VMFUNC, |
| 724 | FEAT_14_0_ECX, |
| 725 | FEAT_SGX_12_0_EAX, /* CPUID[EAX=0x12,ECX=0].EAX (SGX) */ |
| 726 | FEAT_SGX_12_0_EBX, /* CPUID[EAX=0x12,ECX=0].EBX (SGX MISCSELECT[31:0]) */ |
| 727 | FEAT_SGX_12_1_EAX, /* CPUID[EAX=0x12,ECX=1].EAX (SGX ATTRIBUTES[31:0]) */ |
| 728 | FEAT_XSAVE_XSS_LO, /* CPUID[EAX=0xd,ECX=1].ECX */ |
| 729 | FEAT_XSAVE_XSS_HI, /* CPUID[EAX=0xd,ECX=1].EDX */ |
| 730 | FEAT_7_1_ECX, /* CPUID[EAX=7,ECX=1].ECX */ |
| 731 | FEAT_7_1_EDX, /* CPUID[EAX=7,ECX=1].EDX */ |
| 732 | FEAT_7_2_EDX, /* CPUID[EAX=7,ECX=2].EDX */ |
| 733 | FEAT_24_0_EBX, /* CPUID[EAX=0x24,ECX=0].EBX */ |
| 734 | FEAT_29_0_EBX, /* CPUID[EAX=0x29,ECX=0].EBX */ |
| 735 | FEAT_1E_1_EAX, /* CPUID[EAX=0x1E,ECX=1].EAX */ |
| 736 | FEAT_24_1_ECX, /* CPUID[EAX=0x24,ECX=0].ECX */ |
| 737 | FEATURE_WORDS, |
| 738 | } FeatureWord; |
| 739 | |
| 740 | typedef struct FeatureMask { |
| 741 | FeatureWord index; |
| 742 | uint64_t mask; |
| 743 | } FeatureMask; |
| 744 | |
| 745 | typedef struct FeatureDep { |
| 746 | FeatureMask from, to; |
| 747 | } FeatureDep; |
| 748 | |
| 749 | typedef uint64_t FeatureWordArray[FEATURE_WORDS]; |
| 750 | uint64_t x86_cpu_get_supported_feature_word(X86CPU *cpu, FeatureWord w); |
| 751 | |
| 752 | /* cpuid_features bits */ |
| 753 | #define CPUID_FP87 (1U << 0) |
| 754 | #define CPUID_VME (1U << 1) |
| 755 | #define CPUID_DE (1U << 2) |
| 756 | #define CPUID_PSE (1U << 3) |
| 757 | #define CPUID_TSC (1U << 4) |
| 758 | #define CPUID_MSR (1U << 5) |
| 759 | #define CPUID_PAE (1U << 6) |
| 760 | #define CPUID_MCE (1U << 7) |
| 761 | #define CPUID_CX8 (1U << 8) |
| 762 | #define CPUID_APIC (1U << 9) |
| 763 | #define CPUID_SEP (1U << 11) /* sysenter/sysexit */ |
| 764 | #define CPUID_MTRR (1U << 12) |
| 765 | #define CPUID_PGE (1U << 13) |
| 766 | #define CPUID_MCA (1U << 14) |
| 767 | #define CPUID_CMOV (1U << 15) |
| 768 | #define CPUID_PAT (1U << 16) |
| 769 | #define CPUID_PSE36 (1U << 17) |
| 770 | #define CPUID_PN (1U << 18) |
| 771 | #define CPUID_CLFLUSH (1U << 19) |
| 772 | #define CPUID_DTS (1U << 21) |
| 773 | #define CPUID_ACPI (1U << 22) |
| 774 | #define CPUID_MMX (1U << 23) |
| 775 | #define CPUID_FXSR (1U << 24) |
| 776 | #define CPUID_SSE (1U << 25) |
| 777 | #define CPUID_SSE2 (1U << 26) |
| 778 | #define CPUID_SS (1U << 27) |
| 779 | #define CPUID_HT (1U << 28) |
| 780 | #define CPUID_TM (1U << 29) |
| 781 | #define CPUID_IA64 (1U << 30) |
| 782 | #define CPUID_PBE (1U << 31) |
| 783 | |
| 784 | #define CPUID_EXT_SSE3 (1U << 0) |
| 785 | #define CPUID_EXT_PCLMULQDQ (1U << 1) |
| 786 | #define CPUID_EXT_DTES64 (1U << 2) |
| 787 | #define CPUID_EXT_MONITOR (1U << 3) |
| 788 | #define CPUID_EXT_DSCPL (1U << 4) |
| 789 | #define CPUID_EXT_VMX (1U << 5) |
| 790 | #define CPUID_EXT_SMX (1U << 6) |
| 791 | #define CPUID_EXT_EST (1U << 7) |
| 792 | #define CPUID_EXT_TM2 (1U << 8) |
| 793 | #define CPUID_EXT_SSSE3 (1U << 9) |
| 794 | #define CPUID_EXT_CID (1U << 10) |
| 795 | #define CPUID_EXT_FMA (1U << 12) |
| 796 | #define CPUID_EXT_CX16 (1U << 13) |
| 797 | #define CPUID_EXT_XTPR (1U << 14) |
| 798 | #define CPUID_EXT_PDCM (1U << 15) |
| 799 | #define CPUID_EXT_PCID (1U << 17) |
| 800 | #define CPUID_EXT_DCA (1U << 18) |
| 801 | #define CPUID_EXT_SSE41 (1U << 19) |
| 802 | #define CPUID_EXT_SSE42 (1U << 20) |
| 803 | #define CPUID_EXT_X2APIC (1U << 21) |
| 804 | #define CPUID_EXT_MOVBE (1U << 22) |
| 805 | #define CPUID_EXT_POPCNT (1U << 23) |
| 806 | #define CPUID_EXT_TSC_DEADLINE_TIMER (1U << 24) |
| 807 | #define CPUID_EXT_AES (1U << 25) |
| 808 | #define CPUID_EXT_XSAVE (1U << 26) |
| 809 | #define CPUID_EXT_OSXSAVE (1U << 27) |
| 810 | #define CPUID_EXT_AVX (1U << 28) |
| 811 | #define CPUID_EXT_F16C (1U << 29) |
| 812 | #define CPUID_EXT_RDRAND (1U << 30) |
| 813 | #define CPUID_EXT_HYPERVISOR (1U << 31) |
| 814 | |
| 815 | #define CPUID_EXT2_FPU (1U << 0) |
| 816 | #define CPUID_EXT2_VME (1U << 1) |
| 817 | #define CPUID_EXT2_DE (1U << 2) |
| 818 | #define CPUID_EXT2_PSE (1U << 3) |
| 819 | #define CPUID_EXT2_TSC (1U << 4) |
| 820 | #define CPUID_EXT2_MSR (1U << 5) |
| 821 | #define CPUID_EXT2_PAE (1U << 6) |
| 822 | #define CPUID_EXT2_MCE (1U << 7) |
| 823 | #define CPUID_EXT2_CX8 (1U << 8) |
| 824 | #define CPUID_EXT2_APIC (1U << 9) |
| 825 | #define CPUID_EXT2_SYSCALL (1U << 11) |
| 826 | #define CPUID_EXT2_MTRR (1U << 12) |
| 827 | #define CPUID_EXT2_PGE (1U << 13) |
| 828 | #define CPUID_EXT2_MCA (1U << 14) |
| 829 | #define CPUID_EXT2_CMOV (1U << 15) |
| 830 | #define CPUID_EXT2_PAT (1U << 16) |
| 831 | #define CPUID_EXT2_PSE36 (1U << 17) |
| 832 | #define CPUID_EXT2_MP (1U << 19) |
| 833 | #define CPUID_EXT2_NX (1U << 20) |
| 834 | #define CPUID_EXT2_MMXEXT (1U << 22) |
| 835 | #define CPUID_EXT2_MMX (1U << 23) |
| 836 | #define CPUID_EXT2_FXSR (1U << 24) |
| 837 | #define CPUID_EXT2_FFXSR (1U << 25) |
| 838 | #define CPUID_EXT2_PDPE1GB (1U << 26) |
| 839 | #define CPUID_EXT2_RDTSCP (1U << 27) |
| 840 | #define CPUID_EXT2_LM (1U << 29) |
| 841 | #define CPUID_EXT2_3DNOWEXT (1U << 30) |
| 842 | #define CPUID_EXT2_3DNOW (1U << 31) |
| 843 | |
| 844 | /* CPUID[8000_0001].EDX bits that are aliases of CPUID[1].EDX bits on AMD CPUs */ |
| 845 | #define CPUID_EXT2_AMD_ALIASES (CPUID_EXT2_FPU | CPUID_EXT2_VME | \ |
| 846 | CPUID_EXT2_DE | CPUID_EXT2_PSE | \ |
| 847 | CPUID_EXT2_TSC | CPUID_EXT2_MSR | \ |
| 848 | CPUID_EXT2_PAE | CPUID_EXT2_MCE | \ |
| 849 | CPUID_EXT2_CX8 | CPUID_EXT2_APIC | \ |
| 850 | CPUID_EXT2_MTRR | CPUID_EXT2_PGE | \ |
| 851 | CPUID_EXT2_MCA | CPUID_EXT2_CMOV | \ |
| 852 | CPUID_EXT2_PAT | CPUID_EXT2_PSE36 | \ |
| 853 | CPUID_EXT2_MMX | CPUID_EXT2_FXSR) |
| 854 | |
| 855 | #define CPUID_EXT3_LAHF_LM (1U << 0) |
| 856 | #define CPUID_EXT3_CMP_LEG (1U << 1) |
| 857 | #define CPUID_EXT3_SVM (1U << 2) |
| 858 | #define CPUID_EXT3_EXTAPIC (1U << 3) |
| 859 | #define CPUID_EXT3_CR8LEG (1U << 4) |
| 860 | #define CPUID_EXT3_ABM (1U << 5) |
| 861 | #define CPUID_EXT3_SSE4A (1U << 6) |
| 862 | #define CPUID_EXT3_MISALIGNSSE (1U << 7) |
| 863 | #define CPUID_EXT3_3DNOWPREFETCH (1U << 8) |
| 864 | #define CPUID_EXT3_OSVW (1U << 9) |
| 865 | #define CPUID_EXT3_IBS (1U << 10) |
| 866 | #define CPUID_EXT3_XOP (1U << 11) |
| 867 | #define CPUID_EXT3_SKINIT (1U << 12) |
| 868 | #define CPUID_EXT3_WDT (1U << 13) |
| 869 | #define CPUID_EXT3_LWP (1U << 15) |
| 870 | #define CPUID_EXT3_FMA4 (1U << 16) |
| 871 | #define CPUID_EXT3_TCE (1U << 17) |
| 872 | #define CPUID_EXT3_NODEID (1U << 19) |
| 873 | #define CPUID_EXT3_TBM (1U << 21) |
| 874 | #define CPUID_EXT3_TOPOEXT (1U << 22) |
| 875 | #define CPUID_EXT3_PERFCORE (1U << 23) |
| 876 | #define CPUID_EXT3_PERFNB (1U << 24) |
| 877 | |
| 878 | #define CPUID_SVM_NPT (1U << 0) |
| 879 | #define CPUID_SVM_LBRV (1U << 1) |
| 880 | #define CPUID_SVM_SVMLOCK (1U << 2) |
| 881 | #define CPUID_SVM_NRIPSAVE (1U << 3) |
| 882 | #define CPUID_SVM_TSCSCALE (1U << 4) |
| 883 | #define CPUID_SVM_VMCBCLEAN (1U << 5) |
| 884 | #define CPUID_SVM_FLUSHASID (1U << 6) |
| 885 | #define CPUID_SVM_DECODEASSIST (1U << 7) |
| 886 | #define CPUID_SVM_PAUSEFILTER (1U << 10) |
| 887 | #define CPUID_SVM_PFTHRESHOLD (1U << 12) |
| 888 | #define CPUID_SVM_AVIC (1U << 13) |
| 889 | #define CPUID_SVM_V_VMSAVE_VMLOAD (1U << 15) |
| 890 | #define CPUID_SVM_VGIF (1U << 16) |
| 891 | #define CPUID_SVM_GMET (1U << 17) |
| 892 | #define CPUID_SVM_VNMI (1U << 25) |
| 893 | #define CPUID_SVM_SVME_ADDR_CHK (1U << 28) |
| 894 | |
| 895 | /* Support RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE */ |
| 896 | #define CPUID_7_0_EBX_FSGSBASE (1U << 0) |
| 897 | /* Support TSC adjust MSR */ |
| 898 | #define CPUID_7_0_EBX_TSC_ADJUST (1U << 1) |
| 899 | /* Support SGX */ |
| 900 | #define CPUID_7_0_EBX_SGX (1U << 2) |
| 901 | /* 1st Group of Advanced Bit Manipulation Extensions */ |
| 902 | #define CPUID_7_0_EBX_BMI1 (1U << 3) |
| 903 | /* Hardware Lock Elision */ |
| 904 | #define CPUID_7_0_EBX_HLE (1U << 4) |
| 905 | /* Intel Advanced Vector Extensions 2 */ |
| 906 | #define CPUID_7_0_EBX_AVX2 (1U << 5) |
| 907 | /* FPU data pointer updated only on x87 exceptions */ |
| 908 | #define CPUID_7_0_EBX_FDP_EXCPTN_ONLY (1u << 6) |
| 909 | /* Supervisor-mode Execution Prevention */ |
| 910 | #define CPUID_7_0_EBX_SMEP (1U << 7) |
| 911 | /* 2nd Group of Advanced Bit Manipulation Extensions */ |
| 912 | #define CPUID_7_0_EBX_BMI2 (1U << 8) |
| 913 | /* Enhanced REP MOVSB/STOSB */ |
| 914 | #define CPUID_7_0_EBX_ERMS (1U << 9) |
| 915 | /* Invalidate Process-Context Identifier */ |
| 916 | #define CPUID_7_0_EBX_INVPCID (1U << 10) |
| 917 | /* Restricted Transactional Memory */ |
| 918 | #define CPUID_7_0_EBX_RTM (1U << 11) |
| 919 | /* Zero out FPU CS and FPU DS */ |
| 920 | #define CPUID_7_0_EBX_ZERO_FCS_FDS (1U << 13) |
| 921 | /* Memory Protection Extension */ |
| 922 | #define CPUID_7_0_EBX_MPX (1U << 14) |
| 923 | /* AVX-512 Foundation */ |
| 924 | #define CPUID_7_0_EBX_AVX512F (1U << 16) |
| 925 | /* AVX-512 Doubleword & Quadword Instruction */ |
| 926 | #define CPUID_7_0_EBX_AVX512DQ (1U << 17) |
| 927 | /* Read Random SEED */ |
| 928 | #define CPUID_7_0_EBX_RDSEED (1U << 18) |
| 929 | /* ADCX and ADOX instructions */ |
| 930 | #define CPUID_7_0_EBX_ADX (1U << 19) |
| 931 | /* Supervisor Mode Access Prevention */ |
| 932 | #define CPUID_7_0_EBX_SMAP (1U << 20) |
| 933 | /* AVX-512 Integer Fused Multiply Add */ |
| 934 | #define CPUID_7_0_EBX_AVX512IFMA (1U << 21) |
| 935 | /* Flush a Cache Line Optimized */ |
| 936 | #define CPUID_7_0_EBX_CLFLUSHOPT (1U << 23) |
| 937 | /* Cache Line Write Back */ |
| 938 | #define CPUID_7_0_EBX_CLWB (1U << 24) |
| 939 | /* Intel Processor Trace */ |
| 940 | #define CPUID_7_0_EBX_INTEL_PT (1U << 25) |
| 941 | /* AVX-512 Prefetch */ |
| 942 | #define CPUID_7_0_EBX_AVX512PF (1U << 26) |
| 943 | /* AVX-512 Exponential and Reciprocal */ |
| 944 | #define CPUID_7_0_EBX_AVX512ER (1U << 27) |
| 945 | /* AVX-512 Conflict Detection */ |
| 946 | #define CPUID_7_0_EBX_AVX512CD (1U << 28) |
| 947 | /* SHA1/SHA256 Instruction Extensions */ |
| 948 | #define CPUID_7_0_EBX_SHA_NI (1U << 29) |
| 949 | /* AVX-512 Byte and Word Instructions */ |
| 950 | #define CPUID_7_0_EBX_AVX512BW (1U << 30) |
| 951 | /* AVX-512 Vector Length Extensions */ |
| 952 | #define CPUID_7_0_EBX_AVX512VL (1U << 31) |
| 953 | |
| 954 | /* AVX-512 Vector Byte Manipulation Instruction */ |
| 955 | #define CPUID_7_0_ECX_AVX512_VBMI (1U << 1) |
| 956 | /* User-Mode Instruction Prevention */ |
| 957 | #define CPUID_7_0_ECX_UMIP (1U << 2) |
| 958 | /* Protection Keys for User-mode Pages */ |
| 959 | #define CPUID_7_0_ECX_PKU (1U << 3) |
| 960 | /* OS Enable Protection Keys */ |
| 961 | #define CPUID_7_0_ECX_OSPKE (1U << 4) |
| 962 | /* UMONITOR/UMWAIT/TPAUSE Instructions */ |
| 963 | #define CPUID_7_0_ECX_WAITPKG (1U << 5) |
| 964 | /* Additional AVX-512 Vector Byte Manipulation Instruction */ |
| 965 | #define CPUID_7_0_ECX_AVX512_VBMI2 (1U << 6) |
| 966 | /* Control-flow enforcement technology: shadow stack */ |
| 967 | #define CPUID_7_0_ECX_CET_SHSTK (1U << 7) |
| 968 | /* Galois Field New Instructions */ |
| 969 | #define CPUID_7_0_ECX_GFNI (1U << 8) |
| 970 | /* Vector AES Instructions */ |
| 971 | #define CPUID_7_0_ECX_VAES (1U << 9) |
| 972 | /* Carry-Less Multiplication Quadword */ |
| 973 | #define CPUID_7_0_ECX_VPCLMULQDQ (1U << 10) |
| 974 | /* Vector Neural Network Instructions */ |
| 975 | #define CPUID_7_0_ECX_AVX512VNNI (1U << 11) |
| 976 | /* Support for VPOPCNT[B,W] and VPSHUFBITQMB */ |
| 977 | #define CPUID_7_0_ECX_AVX512BITALG (1U << 12) |
| 978 | /* POPCNT for vectors of DW/QW */ |
| 979 | #define CPUID_7_0_ECX_AVX512_VPOPCNTDQ (1U << 14) |
| 980 | /* 5-level Page Tables */ |
| 981 | #define CPUID_7_0_ECX_LA57 (1U << 16) |
| 982 | /* Read Processor ID */ |
| 983 | #define CPUID_7_0_ECX_RDPID (1U << 22) |
| 984 | /* KeyLocker */ |
| 985 | #define CPUID_7_0_ECX_KeyLocker (1U << 23) |
| 986 | /* Bus Lock Debug Exception */ |
| 987 | #define CPUID_7_0_ECX_BUS_LOCK_DETECT (1U << 24) |
| 988 | /* Cache Line Demote Instruction */ |
| 989 | #define CPUID_7_0_ECX_CLDEMOTE (1U << 25) |
| 990 | /* Move Doubleword as Direct Store Instruction */ |
| 991 | #define CPUID_7_0_ECX_MOVDIRI (1U << 27) |
| 992 | /* Move 64 Bytes as Direct Store Instruction */ |
| 993 | #define CPUID_7_0_ECX_MOVDIR64B (1U << 28) |
| 994 | /* Support SGX Launch Control */ |
| 995 | #define CPUID_7_0_ECX_SGX_LC (1U << 30) |
| 996 | /* Protection Keys for Supervisor-mode Pages */ |
| 997 | #define CPUID_7_0_ECX_PKS (1U << 31) |
| 998 | |
| 999 | /* AVX512 Neural Network Instructions */ |
| 1000 | #define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2) |
| 1001 | /* AVX512 Multiply Accumulation Single Precision */ |
| 1002 | #define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) |
| 1003 | /* Fast Short Rep Mov */ |
| 1004 | #define CPUID_7_0_EDX_FSRM (1U << 4) |
| 1005 | /* AVX512 Vector Pair Intersection to a Pair of Mask Registers */ |
| 1006 | #define CPUID_7_0_EDX_AVX512_VP2INTERSECT (1U << 8) |
| 1007 | /* "md_clear" VERW clears CPU buffers */ |
| 1008 | #define CPUID_7_0_EDX_MD_CLEAR (1U << 10) |
| 1009 | /* SERIALIZE instruction */ |
| 1010 | #define CPUID_7_0_EDX_SERIALIZE (1U << 14) |
| 1011 | /* TSX Suspend Load Address Tracking instruction */ |
| 1012 | #define CPUID_7_0_EDX_TSX_LDTRK (1U << 16) |
| 1013 | /* Architectural LBRs */ |
| 1014 | #define CPUID_7_0_EDX_ARCH_LBR (1U << 19) |
| 1015 | /* Control-flow enforcement technology: indirect branch tracking */ |
| 1016 | #define CPUID_7_0_EDX_CET_IBT (1U << 20) |
| 1017 | /* AMX_BF16 instruction */ |
| 1018 | #define CPUID_7_0_EDX_AMX_BF16 (1U << 22) |
| 1019 | /* AVX512_FP16 instruction */ |
| 1020 | #define CPUID_7_0_EDX_AVX512_FP16 (1U << 23) |
| 1021 | /* AMX tile (two-dimensional register) */ |
| 1022 | #define CPUID_7_0_EDX_AMX_TILE (1U << 24) |
| 1023 | /* AMX_INT8 instruction */ |
| 1024 | #define CPUID_7_0_EDX_AMX_INT8 (1U << 25) |
| 1025 | /* Speculation Control */ |
| 1026 | #define CPUID_7_0_EDX_SPEC_CTRL (1U << 26) |
| 1027 | /* Single Thread Indirect Branch Predictors */ |
| 1028 | #define CPUID_7_0_EDX_STIBP (1U << 27) |
| 1029 | /* Flush L1D cache */ |
| 1030 | #define CPUID_7_0_EDX_FLUSH_L1D (1U << 28) |
| 1031 | /* Arch Capabilities */ |
| 1032 | #define CPUID_7_0_EDX_ARCH_CAPABILITIES (1U << 29) |
| 1033 | /* Core Capability */ |
| 1034 | #define CPUID_7_0_EDX_CORE_CAPABILITY (1U << 30) |
| 1035 | /* Speculative Store Bypass Disable */ |
| 1036 | #define CPUID_7_0_EDX_SPEC_CTRL_SSBD (1U << 31) |
| 1037 | |
| 1038 | /* SHA512 Instruction */ |
| 1039 | #define CPUID_7_1_EAX_SHA512 (1U << 0) |
| 1040 | /* SM3 Instruction */ |
| 1041 | #define CPUID_7_1_EAX_SM3 (1U << 1) |
| 1042 | /* SM4 Instruction */ |
| 1043 | #define CPUID_7_1_EAX_SM4 (1U << 2) |
| 1044 | /* AVX VNNI Instruction */ |
| 1045 | #define CPUID_7_1_EAX_AVX_VNNI (1U << 4) |
| 1046 | /* AVX512 BFloat16 Instruction */ |
| 1047 | #define CPUID_7_1_EAX_AVX512_BF16 (1U << 5) |
| 1048 | /* Linear address space separation */ |
| 1049 | #define CPUID_7_1_EAX_LASS (1U << 6) |
| 1050 | /* CMPCCXADD Instructions */ |
| 1051 | #define CPUID_7_1_EAX_CMPCCXADD (1U << 7) |
| 1052 | /* Fast Zero REP MOVS */ |
| 1053 | #define CPUID_7_1_EAX_FZRM (1U << 10) |
| 1054 | /* Fast Short REP STOS */ |
| 1055 | #define CPUID_7_1_EAX_FSRS (1U << 11) |
| 1056 | /* Fast Short REP CMPS/SCAS */ |
| 1057 | #define CPUID_7_1_EAX_FSRC (1U << 12) |
| 1058 | /* Flexible return and event delivery (FRED) */ |
| 1059 | #define CPUID_7_1_EAX_FRED (1U << 17) |
| 1060 | /* Load into IA32_KERNEL_GS_BASE (LKGS) */ |
| 1061 | #define CPUID_7_1_EAX_LKGS (1U << 18) |
| 1062 | /* Non-Serializing Write to Model Specific Register (WRMSRNS) */ |
| 1063 | #define CPUID_7_1_EAX_WRMSRNS (1U << 19) |
| 1064 | /* Support Tile Computational Operations on FP16 Numbers */ |
| 1065 | #define CPUID_7_1_EAX_AMX_FP16 (1U << 21) |
| 1066 | /* Support for VPMADD52[H,L]UQ */ |
| 1067 | #define CPUID_7_1_EAX_AVX_IFMA (1U << 23) |
| 1068 | /* Linear Address Masking */ |
| 1069 | #define CPUID_7_1_EAX_LAM (1U << 26) |
| 1070 | /* MOVRS Instructions */ |
| 1071 | #define CPUID_7_1_EAX_MOVRS (1U << 31) |
| 1072 | |
| 1073 | /* The immediate form of MSR access instructions */ |
| 1074 | #define CPUID_7_1_ECX_MSR_IMM (1U << 5) |
| 1075 | |
| 1076 | /* Support for VPDPB[SU,UU,SS]D[,S] */ |
| 1077 | #define CPUID_7_1_EDX_AVX_VNNI_INT8 (1U << 4) |
| 1078 | /* AVX NE CONVERT Instructions */ |
| 1079 | #define CPUID_7_1_EDX_AVX_NE_CONVERT (1U << 5) |
| 1080 | /* AMX COMPLEX Instructions */ |
| 1081 | #define CPUID_7_1_EDX_AMX_COMPLEX (1U << 8) |
| 1082 | /* AVX-VNNI-INT16 Instructions */ |
| 1083 | #define CPUID_7_1_EDX_AVX_VNNI_INT16 (1U << 10) |
| 1084 | /* PREFETCHIT0/1 Instructions */ |
| 1085 | #define CPUID_7_1_EDX_PREFETCHITI (1U << 14) |
| 1086 | /* Support for Advanced Vector Extensions 10 */ |
| 1087 | #define CPUID_7_1_EDX_AVX10 (1U << 19) |
| 1088 | /* Support for Advanced Performance Extensions */ |
| 1089 | #define CPUID_7_1_EDX_APXF (1U << 21) |
| 1090 | |
| 1091 | /* Indicate bit 7 of the IA32_SPEC_CTRL MSR is supported */ |
| 1092 | #define CPUID_7_2_EDX_PSFD (1U << 0) |
| 1093 | /* Indicate bits 3 and 4 of the IA32_SPEC_CTRL MSR are supported */ |
| 1094 | #define CPUID_7_2_EDX_IPRED_CTRL (1U << 1) |
| 1095 | /* Indicate bits 5 and 6 of the IA32_SPEC_CTRL MSR are supported */ |
| 1096 | #define CPUID_7_2_EDX_RRSBA_CTRL (1U << 2) |
| 1097 | /* Indicate bit 8 of the IA32_SPEC_CTRL MSR is supported */ |
| 1098 | #define CPUID_7_2_EDX_DDPD_U (1U << 3) |
| 1099 | /* Indicate bit 10 of the IA32_SPEC_CTRL MSR is supported */ |
| 1100 | #define CPUID_7_2_EDX_BHI_CTRL (1U << 4) |
| 1101 | |
| 1102 | /* Do not exhibit MXCSR Configuration Dependent Timing (MCDT) behavior */ |
| 1103 | #define CPUID_7_2_EDX_MCDT_NO (1U << 5) |
| 1104 | |
| 1105 | /* XFD Extend Feature Disabled */ |
| 1106 | #define CPUID_D_1_EAX_XFD (1U << 4) |
| 1107 | |
| 1108 | /* Packets which contain IP payload have LIP values */ |
| 1109 | #define CPUID_14_0_ECX_LIP (1U << 31) |
| 1110 | |
| 1111 | /* AMX_INT8 instruction (alias of CPUID_7_0_EDX_AMX_INT8) */ |
| 1112 | #define CPUID_1E_1_EAX_AMX_INT8_ALIAS (1U << 0) |
| 1113 | /* AMX_BF16 instruction (alias of CPUID_7_0_EDX_AMX_BF16) */ |
| 1114 | #define CPUID_1E_1_EAX_AMX_BF16_ALIAS (1U << 1) |
| 1115 | /* AMX_COMPLEX instruction (alias of CPUID_7_1_EDX_AMX_COMPLEX) */ |
| 1116 | #define CPUID_1E_1_EAX_AMX_COMPLEX_ALIAS (1U << 2) |
| 1117 | /* AMX_FP16 instruction (alias of CPUID_7_1_EAX_AMX_FP16) */ |
| 1118 | #define CPUID_1E_1_EAX_AMX_FP16_ALIAS (1U << 3) |
| 1119 | /* AMX_FP8 instruction */ |
| 1120 | #define CPUID_1E_1_EAX_AMX_FP8 (1U << 4) |
| 1121 | /* AMX_TF32 instruction */ |
| 1122 | #define CPUID_1E_1_EAX_AMX_TF32 (1U << 6) |
| 1123 | /* AMX_AVX512 instruction */ |
| 1124 | #define CPUID_1E_1_EAX_AMX_AVX512 (1U << 7) |
| 1125 | /* AMX_MOVRS instruction */ |
| 1126 | #define CPUID_1E_1_EAX_AMX_MOVRS (1U << 8) |
| 1127 | |
| 1128 | /* AVX10 128-bit vector support is present */ |
| 1129 | #define CPUID_24_0_EBX_AVX10_128 (1U << 16) |
| 1130 | /* AVX10 256-bit vector support is present */ |
| 1131 | #define CPUID_24_0_EBX_AVX10_256 (1U << 17) |
| 1132 | /* AVX10 512-bit vector support is present */ |
| 1133 | #define CPUID_24_0_EBX_AVX10_512 (1U << 18) |
| 1134 | /* AVX10 vector length support mask */ |
| 1135 | #define CPUID_24_0_EBX_AVX10_VL_MASK (CPUID_24_0_EBX_AVX10_128 | \ |
| 1136 | CPUID_24_0_EBX_AVX10_256 | \ |
| 1137 | CPUID_24_0_EBX_AVX10_512) |
| 1138 | |
| 1139 | /* AVX10_VNNI_INT instruction */ |
| 1140 | #define CPUID_24_1_ECX_AVX10_VNNI_INT (1U << 2) |
| 1141 | |
| 1142 | /* |
| 1143 | * New Conditional Instructions (NCIs), explicit New Data Destination (NDD) |
| 1144 | * controls, and explicit Flags Suppression (NF) controls for select sets of |
| 1145 | * EVEX-encoded Intel APX instructions |
| 1146 | */ |
| 1147 | #define CPUID_29_0_EBX_APX_NCI_NDD_NF (1U << 0) |
| 1148 | |
| 1149 | /* RAS Features */ |
| 1150 | #define CPUID_8000_0007_EBX_OVERFLOW_RECOV (1U << 0) |
| 1151 | #define CPUID_8000_0007_EBX_SUCCOR (1U << 1) |
| 1152 | |
| 1153 | /* (Old) KVM paravirtualized clocksource */ |
| 1154 | #define CPUID_KVM_CLOCK (1U << KVM_FEATURE_CLOCKSOURCE) |
| 1155 | /* (New) KVM specific paravirtualized clocksource */ |
| 1156 | #define CPUID_KVM_CLOCK2 (1U << KVM_FEATURE_CLOCKSOURCE2) |
| 1157 | /* KVM asynchronous page fault */ |
| 1158 | #define CPUID_KVM_ASYNCPF (1U << KVM_FEATURE_ASYNC_PF) |
| 1159 | /* KVM stolen (when guest vCPU is not running) time accounting */ |
| 1160 | #define CPUID_KVM_STEAL_TIME (1U << KVM_FEATURE_STEAL_TIME) |
| 1161 | /* KVM paravirtualized end-of-interrupt signaling */ |
| 1162 | #define CPUID_KVM_PV_EOI (1U << KVM_FEATURE_PV_EOI) |
| 1163 | /* KVM paravirtualized spinlocks support */ |
| 1164 | #define CPUID_KVM_PV_UNHALT (1U << KVM_FEATURE_PV_UNHALT) |
| 1165 | /* KVM host-side polling on HLT control from the guest */ |
| 1166 | #define CPUID_KVM_POLL_CONTROL (1U << KVM_FEATURE_POLL_CONTROL) |
| 1167 | /* KVM interrupt based asynchronous page fault*/ |
| 1168 | #define CPUID_KVM_ASYNCPF_INT (1U << KVM_FEATURE_ASYNC_PF_INT) |
| 1169 | /* KVM 'Extended Destination ID' support for external interrupts */ |
| 1170 | #define CPUID_KVM_MSI_EXT_DEST_ID (1U << KVM_FEATURE_MSI_EXT_DEST_ID) |
| 1171 | |
| 1172 | /* Hint to KVM that vCPUs expect never preempted for an unlimited time */ |
| 1173 | #define CPUID_KVM_HINTS_REALTIME (1U << KVM_HINTS_REALTIME) |
| 1174 | |
| 1175 | /* CLZERO instruction */ |
| 1176 | #define CPUID_8000_0008_EBX_CLZERO (1U << 0) |
| 1177 | /* Always save/restore FP error pointers */ |
| 1178 | #define CPUID_8000_0008_EBX_XSAVEERPTR (1U << 2) |
| 1179 | /* Write back and do not invalidate cache */ |
| 1180 | #define CPUID_8000_0008_EBX_WBNOINVD (1U << 9) |
| 1181 | /* Indirect Branch Prediction Barrier */ |
| 1182 | #define CPUID_8000_0008_EBX_IBPB (1U << 12) |
| 1183 | /* Indirect Branch Restricted Speculation */ |
| 1184 | #define CPUID_8000_0008_EBX_IBRS (1U << 14) |
| 1185 | /* Single Thread Indirect Branch Predictors */ |
| 1186 | #define CPUID_8000_0008_EBX_STIBP (1U << 15) |
| 1187 | /* STIBP mode has enhanced performance and may be left always on */ |
| 1188 | #define CPUID_8000_0008_EBX_STIBP_ALWAYS_ON (1U << 17) |
| 1189 | /* Speculative Store Bypass Disable */ |
| 1190 | #define CPUID_8000_0008_EBX_AMD_SSBD (1U << 24) |
| 1191 | /* Paravirtualized Speculative Store Bypass Disable MSR */ |
| 1192 | #define CPUID_8000_0008_EBX_VIRT_SSBD (1U << 25) |
| 1193 | /* Predictive Store Forwarding Disable */ |
| 1194 | #define CPUID_8000_0008_EBX_AMD_PSFD (1U << 28) |
| 1195 | |
| 1196 | /* Processor ignores nested data breakpoints */ |
| 1197 | #define CPUID_8000_0021_EAX_NO_NESTED_DATA_BP (1U << 0) |
| 1198 | /* WRMSR to FS_BASE, GS_BASE, or KERNEL_GS_BASE is non-serializing */ |
| 1199 | #define CPUID_8000_0021_EAX_FS_GS_BASE_NS (1U << 1) |
| 1200 | /* LFENCE is always serializing */ |
| 1201 | #define CPUID_8000_0021_EAX_LFENCE_ALWAYS_SERIALIZING (1U << 2) |
| 1202 | /* Memory form of VERW mitigates TSA */ |
| 1203 | #define CPUID_8000_0021_EAX_VERW_CLEAR (1U << 5) |
| 1204 | /* Null Selector Clears Base */ |
| 1205 | #define CPUID_8000_0021_EAX_NULL_SEL_CLR_BASE (1U << 6) |
| 1206 | /* Automatic IBRS */ |
| 1207 | #define CPUID_8000_0021_EAX_AUTO_IBRS (1U << 8) |
| 1208 | /* Indicates support for IC prefetch */ |
| 1209 | #define CPUID_8000_0021_EAX_PREFETCHI (1U << 20) |
| 1210 | /* Enhanced Return Address Predictor Scurity */ |
| 1211 | #define CPUID_8000_0021_EAX_ERAPS (1U << 24) |
| 1212 | /* Selective Branch Predictor Barrier */ |
| 1213 | #define CPUID_8000_0021_EAX_SBPB (1U << 27) |
| 1214 | /* IBPB includes branch type prediction flushing */ |
| 1215 | #define CPUID_8000_0021_EAX_IBPB_BRTYPE (1U << 28) |
| 1216 | /* Not vulnerable to Speculative Return Stack Overflow */ |
| 1217 | #define CPUID_8000_0021_EAX_SRSO_NO (1U << 29) |
| 1218 | /* Not vulnerable to SRSO at the user-kernel boundary */ |
| 1219 | #define CPUID_8000_0021_EAX_SRSO_USER_KERNEL_NO (1U << 30) |
| 1220 | |
| 1221 | /* |
| 1222 | * Return Address Predictor size. RapSize x 8 is the minimum number of |
| 1223 | * CALL instructions software needs to execute to flush the RAP. |
| 1224 | */ |
| 1225 | #define CPUID_8000_0021_EBX_RAPSIZE (8U << 16) |
| 1226 | |
| 1227 | /* CPU is not vulnerable TSA SA-SQ attack */ |
| 1228 | #define CPUID_8000_0021_ECX_TSA_SQ_NO (1U << 1) |
| 1229 | /* CPU is not vulnerable TSA SA-L1 attack */ |
| 1230 | #define CPUID_8000_0021_ECX_TSA_L1_NO (1U << 2) |
| 1231 | |
| 1232 | /* Performance Monitoring Version 2 */ |
| 1233 | #define CPUID_8000_0022_EAX_PERFMON_V2 (1U << 0) |
| 1234 | |
| 1235 | #define CPUID_XSAVE_XSAVEOPT (1U << 0) |
| 1236 | #define CPUID_XSAVE_XSAVEC (1U << 1) |
| 1237 | #define CPUID_XSAVE_XGETBV1 (1U << 2) |
| 1238 | #define CPUID_XSAVE_XSAVES (1U << 3) |
| 1239 | #define CPUID_XSAVE_XFD (1U << 4) |
| 1240 | |
| 1241 | #define CPUID_6_EAX_ARAT (1U << 2) |
| 1242 | |
| 1243 | /* CPUID[0x80000007].EDX flags: */ |
| 1244 | #define CPUID_APM_INVTSC (1U << 8) |
| 1245 | |
| 1246 | /* "rng" RNG present (xstore) */ |
| 1247 | #define CPUID_C000_0001_EDX_XSTORE (1U << 2) |
| 1248 | /* "rng_en" RNG enabled */ |
| 1249 | #define CPUID_C000_0001_EDX_XSTORE_EN (1U << 3) |
| 1250 | /* "ace" on-CPU crypto (xcrypt) */ |
| 1251 | #define CPUID_C000_0001_EDX_XCRYPT (1U << 6) |
| 1252 | /* "ace_en" on-CPU crypto enabled */ |
| 1253 | #define CPUID_C000_0001_EDX_XCRYPT_EN (1U << 7) |
| 1254 | /* Advanced Cryptography Engine v2 */ |
| 1255 | #define CPUID_C000_0001_EDX_ACE2 (1U << 8) |
| 1256 | /* ACE v2 enabled */ |
| 1257 | #define CPUID_C000_0001_EDX_ACE2_EN (1U << 9) |
| 1258 | /* PadLock Hash Engine */ |
| 1259 | #define CPUID_C000_0001_EDX_PHE (1U << 10) |
| 1260 | /* PHE enabled */ |
| 1261 | #define CPUID_C000_0001_EDX_PHE_EN (1U << 11) |
| 1262 | /* PadLock Montgomery Multiplier */ |
| 1263 | #define CPUID_C000_0001_EDX_PMM (1U << 12) |
| 1264 | /* PMM enabled */ |
| 1265 | #define CPUID_C000_0001_EDX_PMM_EN (1U << 13) |
| 1266 | |
| 1267 | #define CPUID_VENDOR_SZ 12 |
| 1268 | #define CPUID_MODEL_ID_SZ 48 |
| 1269 | |
| 1270 | #define CPUID_VENDOR_INTEL_1 0x756e6547 /* "Genu" */ |
| 1271 | #define CPUID_VENDOR_INTEL_2 0x49656e69 /* "ineI" */ |
| 1272 | #define CPUID_VENDOR_INTEL_3 0x6c65746e /* "ntel" */ |
| 1273 | #define CPUID_VENDOR_INTEL "GenuineIntel" |
| 1274 | |
| 1275 | #define CPUID_VENDOR_AMD_1 0x68747541 /* "Auth" */ |
| 1276 | #define CPUID_VENDOR_AMD_2 0x69746e65 /* "enti" */ |
| 1277 | #define CPUID_VENDOR_AMD_3 0x444d4163 /* "cAMD" */ |
| 1278 | #define CPUID_VENDOR_AMD "AuthenticAMD" |
| 1279 | |
| 1280 | #define CPUID_VENDOR_ZHAOXIN1_1 0x746E6543 /* "Cent" */ |
| 1281 | #define CPUID_VENDOR_ZHAOXIN1_2 0x48727561 /* "aurH" */ |
| 1282 | #define CPUID_VENDOR_ZHAOXIN1_3 0x736C7561 /* "auls" */ |
| 1283 | |
| 1284 | #define CPUID_VENDOR_ZHAOXIN2_1 0x68532020 /* " Sh" */ |
| 1285 | #define CPUID_VENDOR_ZHAOXIN2_2 0x68676E61 /* "angh" */ |
| 1286 | #define CPUID_VENDOR_ZHAOXIN2_3 0x20206961 /* "ai " */ |
| 1287 | |
| 1288 | #define CPUID_VENDOR_ZHAOXIN1 "CentaurHauls" |
| 1289 | #define CPUID_VENDOR_ZHAOXIN2 " Shanghai " |
| 1290 | |
| 1291 | #define CPUID_VENDOR_HYGON "HygonGenuine" |
| 1292 | |
| 1293 | #define IS_INTEL_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && \ |
| 1294 | (env)->cpuid_vendor2 == CPUID_VENDOR_INTEL_2 && \ |
| 1295 | (env)->cpuid_vendor3 == CPUID_VENDOR_INTEL_3) |
| 1296 | #define IS_AMD_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_AMD_1 && \ |
| 1297 | (env)->cpuid_vendor2 == CPUID_VENDOR_AMD_2 && \ |
| 1298 | (env)->cpuid_vendor3 == CPUID_VENDOR_AMD_3) |
| 1299 | #define IS_ZHAOXIN1_CPU(env) \ |
| 1300 | ((env)->cpuid_vendor1 == CPUID_VENDOR_ZHAOXIN1_1 && \ |
| 1301 | (env)->cpuid_vendor2 == CPUID_VENDOR_ZHAOXIN1_2 && \ |
| 1302 | (env)->cpuid_vendor3 == CPUID_VENDOR_ZHAOXIN1_3) |
| 1303 | #define IS_ZHAOXIN2_CPU(env) \ |
| 1304 | ((env)->cpuid_vendor1 == CPUID_VENDOR_ZHAOXIN2_1 && \ |
| 1305 | (env)->cpuid_vendor2 == CPUID_VENDOR_ZHAOXIN2_2 && \ |
| 1306 | (env)->cpuid_vendor3 == CPUID_VENDOR_ZHAOXIN2_3) |
| 1307 | #define IS_ZHAOXIN_CPU(env) (IS_ZHAOXIN1_CPU(env) || IS_ZHAOXIN2_CPU(env)) |
| 1308 | |
| 1309 | #define CPUID_MWAIT_IBE (1U << 1) /* Interrupts can exit capability */ |
| 1310 | #define CPUID_MWAIT_EMX (1U << 0) /* enumeration supported */ |
| 1311 | |
| 1312 | /* CPUID[0xB].ECX level types */ |
| 1313 | #define CPUID_B_ECX_TOPO_LEVEL_INVALID 0 |
| 1314 | #define CPUID_B_ECX_TOPO_LEVEL_SMT 1 |
| 1315 | #define CPUID_B_ECX_TOPO_LEVEL_CORE 2 |
| 1316 | |
| 1317 | /* COUID[0x1F].ECX level types */ |
| 1318 | #define CPUID_1F_ECX_TOPO_LEVEL_INVALID CPUID_B_ECX_TOPO_LEVEL_INVALID |
| 1319 | #define CPUID_1F_ECX_TOPO_LEVEL_SMT CPUID_B_ECX_TOPO_LEVEL_SMT |
| 1320 | #define CPUID_1F_ECX_TOPO_LEVEL_CORE CPUID_B_ECX_TOPO_LEVEL_CORE |
| 1321 | #define CPUID_1F_ECX_TOPO_LEVEL_MODULE 3 |
| 1322 | #define CPUID_1F_ECX_TOPO_LEVEL_DIE 5 |
| 1323 | |
| 1324 | /* MSR Feature Bits */ |
| 1325 | #define MSR_ARCH_CAP_RDCL_NO (1U << 0) |
| 1326 | #define MSR_ARCH_CAP_IBRS_ALL (1U << 1) |
| 1327 | #define MSR_ARCH_CAP_RSBA (1U << 2) |
| 1328 | #define MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY (1U << 3) |
| 1329 | #define MSR_ARCH_CAP_SSB_NO (1U << 4) |
| 1330 | #define MSR_ARCH_CAP_MDS_NO (1U << 5) |
| 1331 | #define MSR_ARCH_CAP_PSCHANGE_MC_NO (1U << 6) |
| 1332 | #define MSR_ARCH_CAP_TSX_CTRL_MSR (1U << 7) |
| 1333 | #define MSR_ARCH_CAP_TAA_NO (1U << 8) |
| 1334 | #define MSR_ARCH_CAP_SBDR_SSDP_NO (1U << 13) |
| 1335 | #define MSR_ARCH_CAP_FBSDP_NO (1U << 14) |
| 1336 | #define MSR_ARCH_CAP_PSDP_NO (1U << 15) |
| 1337 | #define MSR_ARCH_CAP_FB_CLEAR (1U << 17) |
| 1338 | #define MSR_ARCH_CAP_BHI_NO (1U << 20) |
| 1339 | #define MSR_ARCH_CAP_PBRSB_NO (1U << 24) |
| 1340 | #define MSR_ARCH_CAP_GDS_NO (1U << 26) |
| 1341 | #define MSR_ARCH_CAP_RFDS_NO (1U << 27) |
| 1342 | #define MSR_ARCH_CAP_ITS_NO (1U << 62) |
| 1343 | |
| 1344 | #define MSR_CORE_CAP_SPLIT_LOCK_DETECT (1U << 5) |
| 1345 | |
| 1346 | /* VMX MSR features */ |
| 1347 | #define MSR_VMX_BASIC_VMCS_REVISION_MASK 0x7FFFFFFFull |
| 1348 | #define MSR_VMX_BASIC_VMXON_REGION_SIZE_MASK (0x00001FFFull << 32) |
| 1349 | #define MSR_VMX_BASIC_VMCS_MEM_TYPE_MASK (0x003C0000ull << 32) |
| 1350 | #define MSR_VMX_BASIC_DUAL_MONITOR (1ULL << 49) |
| 1351 | #define MSR_VMX_BASIC_INS_OUTS (1ULL << 54) |
| 1352 | #define MSR_VMX_BASIC_TRUE_CTLS (1ULL << 55) |
| 1353 | #define MSR_VMX_BASIC_ANY_ERRCODE (1ULL << 56) |
| 1354 | #define MSR_VMX_BASIC_NESTED_EXCEPTION (1ULL << 58) |
| 1355 | |
| 1356 | #define MSR_VMX_MISC_PREEMPTION_TIMER_SHIFT_MASK 0x1Full |
| 1357 | #define MSR_VMX_MISC_STORE_LMA (1ULL << 5) |
| 1358 | #define MSR_VMX_MISC_ACTIVITY_HLT (1ULL << 6) |
| 1359 | #define MSR_VMX_MISC_ACTIVITY_SHUTDOWN (1ULL << 7) |
| 1360 | #define MSR_VMX_MISC_ACTIVITY_WAIT_SIPI (1ULL << 8) |
| 1361 | #define MSR_VMX_MISC_MAX_MSR_LIST_SIZE_MASK 0x0E000000ull |
| 1362 | #define MSR_VMX_MISC_VMWRITE_VMEXIT (1ULL << 29) |
| 1363 | #define MSR_VMX_MISC_ZERO_LEN_INJECT (1ULL << 30) |
| 1364 | |
| 1365 | #define MSR_VMX_EPT_EXECONLY (1ULL << 0) |
| 1366 | #define MSR_VMX_EPT_PAGE_WALK_LENGTH_4 (1ULL << 6) |
| 1367 | #define MSR_VMX_EPT_PAGE_WALK_LENGTH_5 (1ULL << 7) |
| 1368 | #define MSR_VMX_EPT_UC (1ULL << 8) |
| 1369 | #define MSR_VMX_EPT_WB (1ULL << 14) |
| 1370 | #define MSR_VMX_EPT_2MB (1ULL << 16) |
| 1371 | #define MSR_VMX_EPT_1GB (1ULL << 17) |
| 1372 | #define MSR_VMX_EPT_INVEPT (1ULL << 20) |
| 1373 | #define MSR_VMX_EPT_AD_BITS (1ULL << 21) |
| 1374 | #define MSR_VMX_EPT_ADVANCED_VMEXIT_INFO (1ULL << 22) |
| 1375 | #define MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT (1ULL << 25) |
| 1376 | #define MSR_VMX_EPT_INVEPT_ALL_CONTEXT (1ULL << 26) |
| 1377 | #define MSR_VMX_EPT_INVVPID (1ULL << 32) |
| 1378 | #define MSR_VMX_EPT_INVVPID_SINGLE_ADDR (1ULL << 40) |
| 1379 | #define MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT (1ULL << 41) |
| 1380 | #define MSR_VMX_EPT_INVVPID_ALL_CONTEXT (1ULL << 42) |
| 1381 | #define MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS (1ULL << 43) |
| 1382 | |
| 1383 | #define MSR_VMX_VMFUNC_EPT_SWITCHING (1ULL << 0) |
| 1384 | |
| 1385 | |
| 1386 | /* VMX controls */ |
| 1387 | #define VMX_CPU_BASED_VIRTUAL_INTR_PENDING 0x00000004 |
| 1388 | #define VMX_CPU_BASED_USE_TSC_OFFSETING 0x00000008 |
| 1389 | #define VMX_CPU_BASED_HLT_EXITING 0x00000080 |
| 1390 | #define VMX_CPU_BASED_INVLPG_EXITING 0x00000200 |
| 1391 | #define VMX_CPU_BASED_MWAIT_EXITING 0x00000400 |
| 1392 | #define VMX_CPU_BASED_RDPMC_EXITING 0x00000800 |
| 1393 | #define VMX_CPU_BASED_RDTSC_EXITING 0x00001000 |
| 1394 | #define VMX_CPU_BASED_CR3_LOAD_EXITING 0x00008000 |
| 1395 | #define VMX_CPU_BASED_CR3_STORE_EXITING 0x00010000 |
| 1396 | #define VMX_CPU_BASED_CR8_LOAD_EXITING 0x00080000 |
| 1397 | #define VMX_CPU_BASED_CR8_STORE_EXITING 0x00100000 |
| 1398 | #define VMX_CPU_BASED_TPR_SHADOW 0x00200000 |
| 1399 | #define VMX_CPU_BASED_VIRTUAL_NMI_PENDING 0x00400000 |
| 1400 | #define VMX_CPU_BASED_MOV_DR_EXITING 0x00800000 |
| 1401 | #define VMX_CPU_BASED_UNCOND_IO_EXITING 0x01000000 |
| 1402 | #define VMX_CPU_BASED_USE_IO_BITMAPS 0x02000000 |
| 1403 | #define VMX_CPU_BASED_MONITOR_TRAP_FLAG 0x08000000 |
| 1404 | #define VMX_CPU_BASED_USE_MSR_BITMAPS 0x10000000 |
| 1405 | #define VMX_CPU_BASED_MONITOR_EXITING 0x20000000 |
| 1406 | #define VMX_CPU_BASED_PAUSE_EXITING 0x40000000 |
| 1407 | #define VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS 0x80000000 |
| 1408 | |
| 1409 | #define VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES 0x00000001 |
| 1410 | #define VMX_SECONDARY_EXEC_ENABLE_EPT 0x00000002 |
| 1411 | #define VMX_SECONDARY_EXEC_DESC 0x00000004 |
| 1412 | #define VMX_SECONDARY_EXEC_RDTSCP 0x00000008 |
| 1413 | #define VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE 0x00000010 |
| 1414 | #define VMX_SECONDARY_EXEC_ENABLE_VPID 0x00000020 |
| 1415 | #define VMX_SECONDARY_EXEC_WBINVD_EXITING 0x00000040 |
| 1416 | #define VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST 0x00000080 |
| 1417 | #define VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT 0x00000100 |
| 1418 | #define VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY 0x00000200 |
| 1419 | #define VMX_SECONDARY_EXEC_PAUSE_LOOP_EXITING 0x00000400 |
| 1420 | #define VMX_SECONDARY_EXEC_RDRAND_EXITING 0x00000800 |
| 1421 | #define VMX_SECONDARY_EXEC_ENABLE_INVPCID 0x00001000 |
| 1422 | #define VMX_SECONDARY_EXEC_ENABLE_VMFUNC 0x00002000 |
| 1423 | #define VMX_SECONDARY_EXEC_SHADOW_VMCS 0x00004000 |
| 1424 | #define VMX_SECONDARY_EXEC_ENCLS_EXITING 0x00008000 |
| 1425 | #define VMX_SECONDARY_EXEC_RDSEED_EXITING 0x00010000 |
| 1426 | #define VMX_SECONDARY_EXEC_ENABLE_PML 0x00020000 |
| 1427 | #define VMX_SECONDARY_EXEC_XSAVES 0x00100000 |
| 1428 | #define VMX_SECONDARY_EXEC_MODE_BASED_EPT_EXEC 0x00400000 |
| 1429 | #define VMX_SECONDARY_EXEC_TSC_SCALING 0x02000000 |
| 1430 | #define VMX_SECONDARY_EXEC_ENABLE_USER_WAIT_PAUSE 0x04000000 |
| 1431 | |
| 1432 | #define VMX_PIN_BASED_EXT_INTR_MASK 0x00000001 |
| 1433 | #define VMX_PIN_BASED_NMI_EXITING 0x00000008 |
| 1434 | #define VMX_PIN_BASED_VIRTUAL_NMIS 0x00000020 |
| 1435 | #define VMX_PIN_BASED_VMX_PREEMPTION_TIMER 0x00000040 |
| 1436 | #define VMX_PIN_BASED_POSTED_INTR 0x00000080 |
| 1437 | |
| 1438 | #define VMX_VM_EXIT_SAVE_DEBUG_CONTROLS 0x00000004 |
| 1439 | #define VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE 0x00000200 |
| 1440 | #define VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL 0x00001000 |
| 1441 | #define VMX_VM_EXIT_ACK_INTR_ON_EXIT 0x00008000 |
| 1442 | #define VMX_VM_EXIT_SAVE_IA32_PAT 0x00040000 |
| 1443 | #define VMX_VM_EXIT_LOAD_IA32_PAT 0x00080000 |
| 1444 | #define VMX_VM_EXIT_SAVE_IA32_EFER 0x00100000 |
| 1445 | #define VMX_VM_EXIT_LOAD_IA32_EFER 0x00200000 |
| 1446 | #define VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER 0x00400000 |
| 1447 | #define VMX_VM_EXIT_CLEAR_BNDCFGS 0x00800000 |
| 1448 | #define VMX_VM_EXIT_PT_CONCEAL_PIP 0x01000000 |
| 1449 | #define VMX_VM_EXIT_CLEAR_IA32_RTIT_CTL 0x02000000 |
| 1450 | #define VMX_VM_EXIT_SAVE_CET 0x10000000 |
| 1451 | #define VMX_VM_EXIT_LOAD_IA32_PKRS 0x20000000 |
| 1452 | #define VMX_VM_EXIT_ACTIVATE_SECONDARY_CONTROLS 0x80000000 |
| 1453 | |
| 1454 | #define VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS 0x00000004 |
| 1455 | #define VMX_VM_ENTRY_IA32E_MODE 0x00000200 |
| 1456 | #define VMX_VM_ENTRY_SMM 0x00000400 |
| 1457 | #define VMX_VM_ENTRY_DEACT_DUAL_MONITOR 0x00000800 |
| 1458 | #define VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL 0x00002000 |
| 1459 | #define VMX_VM_ENTRY_LOAD_IA32_PAT 0x00004000 |
| 1460 | #define VMX_VM_ENTRY_LOAD_IA32_EFER 0x00008000 |
| 1461 | #define VMX_VM_ENTRY_LOAD_BNDCFGS 0x00010000 |
| 1462 | #define VMX_VM_ENTRY_PT_CONCEAL_PIP 0x00020000 |
| 1463 | #define VMX_VM_ENTRY_LOAD_IA32_RTIT_CTL 0x00040000 |
| 1464 | #define VMX_VM_ENTRY_LOAD_CET 0x00100000 |
| 1465 | #define VMX_VM_ENTRY_LOAD_IA32_PKRS 0x00400000 |
| 1466 | #define VMX_VM_ENTRY_LOAD_IA32_FRED 0x00800000 |
| 1467 | |
| 1468 | /* Supported Hyper-V Enlightenments */ |
| 1469 | #define HYPERV_FEAT_RELAXED 0 |
| 1470 | #define HYPERV_FEAT_VAPIC 1 |
| 1471 | #define HYPERV_FEAT_TIME 2 |
| 1472 | #define HYPERV_FEAT_CRASH 3 |
| 1473 | #define HYPERV_FEAT_RESET 4 |
| 1474 | #define HYPERV_FEAT_VPINDEX 5 |
| 1475 | #define HYPERV_FEAT_RUNTIME 6 |
| 1476 | #define HYPERV_FEAT_SYNIC 7 |
| 1477 | #define HYPERV_FEAT_STIMER 8 |
| 1478 | #define HYPERV_FEAT_FREQUENCIES 9 |
| 1479 | #define HYPERV_FEAT_REENLIGHTENMENT 10 |
| 1480 | #define HYPERV_FEAT_TLBFLUSH 11 |
| 1481 | #define HYPERV_FEAT_EVMCS 12 |
| 1482 | #define HYPERV_FEAT_IPI 13 |
| 1483 | #define HYPERV_FEAT_STIMER_DIRECT 14 |
| 1484 | #define HYPERV_FEAT_AVIC 15 |
| 1485 | #define HYPERV_FEAT_SYNDBG 16 |
| 1486 | #define HYPERV_FEAT_MSR_BITMAP 17 |
| 1487 | #define HYPERV_FEAT_XMM_INPUT 18 |
| 1488 | #define HYPERV_FEAT_TLBFLUSH_EXT 19 |
| 1489 | #define HYPERV_FEAT_TLBFLUSH_DIRECT 20 |
| 1490 | |
| 1491 | #ifndef HYPERV_SPINLOCK_NEVER_NOTIFY |
| 1492 | #define HYPERV_SPINLOCK_NEVER_NOTIFY 0xFFFFFFFF |
| 1493 | #endif |
| 1494 | |
| 1495 | #define EXCP00_DIVZ 0 |
| 1496 | #define EXCP01_DB 1 |
| 1497 | #define EXCP02_NMI 2 |
| 1498 | #define EXCP03_INT3 3 |
| 1499 | #define EXCP04_INTO 4 |
| 1500 | #define EXCP05_BOUND 5 |
| 1501 | #define EXCP06_ILLOP 6 |
| 1502 | #define EXCP07_PREX 7 |
| 1503 | #define EXCP08_DBLE 8 |
| 1504 | #define EXCP09_XERR 9 |
| 1505 | #define EXCP0A_TSS 10 |
| 1506 | #define EXCP0B_NOSEG 11 |
| 1507 | #define EXCP0C_STACK 12 |
| 1508 | #define EXCP0D_GPF 13 |
| 1509 | #define EXCP0E_PAGE 14 |
| 1510 | #define EXCP10_COPR 16 |
| 1511 | #define EXCP11_ALGN 17 |
| 1512 | #define EXCP12_MCHK 18 |
| 1513 | |
| 1514 | #define EXCP_VMEXIT 0x100 /* only for system emulation */ |
| 1515 | #define EXCP_SYSCALL 0x101 /* only for user emulation */ |
| 1516 | #define EXCP_VSYSCALL 0x102 /* only for user emulation */ |
| 1517 | |
| 1518 | /* i386-specific interrupt pending bits. */ |
| 1519 | #define CPU_INTERRUPT_POLL CPU_INTERRUPT_TGT_EXT_1 |
| 1520 | #define CPU_INTERRUPT_SMI CPU_INTERRUPT_TGT_EXT_2 |
| 1521 | #define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3 |
| 1522 | #define CPU_INTERRUPT_MCE CPU_INTERRUPT_TGT_EXT_4 |
| 1523 | #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_INT_0 |
| 1524 | #define CPU_INTERRUPT_SIPI CPU_INTERRUPT_TGT_INT_1 |
| 1525 | #define CPU_INTERRUPT_TPR CPU_INTERRUPT_TGT_INT_2 |
| 1526 | |
| 1527 | /* Use a clearer name for this. */ |
| 1528 | #define CPU_INTERRUPT_INIT CPU_INTERRUPT_RESET |
| 1529 | |
| 1530 | #define CC_OP_HAS_EFLAGS(op) ((op) >= CC_OP_EFLAGS && (op) <= CC_OP_ADCOX) |
| 1531 | |
| 1532 | /* Instead of computing the condition codes after each x86 instruction, |
| 1533 | * QEMU just stores one operand (called CC_SRC), the result |
| 1534 | * (called CC_DST) and the type of operation (called CC_OP). When the |
| 1535 | * condition codes are needed, the condition codes can be calculated |
| 1536 | * using this information. Condition codes are not generated if they |
| 1537 | * are only needed for conditional branches. |
| 1538 | */ |
| 1539 | typedef enum { |
| 1540 | CC_OP_EFLAGS = 0, /* all cc are explicitly computed, CC_SRC = flags */ |
| 1541 | CC_OP_ADCX = 1, /* CC_DST = C, CC_SRC = rest. */ |
| 1542 | CC_OP_ADOX = 2, /* CC_SRC2 = O, CC_SRC = rest. */ |
| 1543 | CC_OP_ADCOX = 3, /* CC_DST = C, CC_SRC2 = O, CC_SRC = rest. */ |
| 1544 | |
| 1545 | /* Low 2 bits = MemOp constant for the size */ |
| 1546 | #define CC_OP_FIRST_BWLQ CC_OP_MULB |
| 1547 | CC_OP_MULB = 4, /* modify all flags, C, O = (CC_SRC != 0) */ |
| 1548 | CC_OP_MULW, |
| 1549 | CC_OP_MULL, |
| 1550 | CC_OP_MULQ, |
| 1551 | |
| 1552 | CC_OP_ADDB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ |
| 1553 | CC_OP_ADDW, |
| 1554 | CC_OP_ADDL, |
| 1555 | CC_OP_ADDQ, |
| 1556 | |
| 1557 | CC_OP_ADCB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ |
| 1558 | CC_OP_ADCW, |
| 1559 | CC_OP_ADCL, |
| 1560 | CC_OP_ADCQ, |
| 1561 | |
| 1562 | CC_OP_SUBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ |
| 1563 | CC_OP_SUBW, |
| 1564 | CC_OP_SUBL, |
| 1565 | CC_OP_SUBQ, |
| 1566 | |
| 1567 | CC_OP_SBBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ |
| 1568 | CC_OP_SBBW, |
| 1569 | CC_OP_SBBL, |
| 1570 | CC_OP_SBBQ, |
| 1571 | |
| 1572 | CC_OP_LOGICB, /* modify all flags, CC_DST = res */ |
| 1573 | CC_OP_LOGICW, |
| 1574 | CC_OP_LOGICL, |
| 1575 | CC_OP_LOGICQ, |
| 1576 | |
| 1577 | CC_OP_INCB, /* modify all flags except, CC_DST = res, CC_SRC = C */ |
| 1578 | CC_OP_INCW, |
| 1579 | CC_OP_INCL, |
| 1580 | CC_OP_INCQ, |
| 1581 | |
| 1582 | CC_OP_DECB, /* modify all flags except, CC_DST = res, CC_SRC = C */ |
| 1583 | CC_OP_DECW, |
| 1584 | CC_OP_DECL, |
| 1585 | CC_OP_DECQ, |
| 1586 | |
| 1587 | CC_OP_SHLB, /* modify all flags, CC_DST = res, CC_SRC.msb = C */ |
| 1588 | CC_OP_SHLW, |
| 1589 | CC_OP_SHLL, |
| 1590 | CC_OP_SHLQ, |
| 1591 | |
| 1592 | CC_OP_SARB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */ |
| 1593 | CC_OP_SARW, |
| 1594 | CC_OP_SARL, |
| 1595 | CC_OP_SARQ, |
| 1596 | |
| 1597 | CC_OP_BMILGB, /* P,Z,S via CC_DST, C = SRC==0; A=O=0 */ |
| 1598 | CC_OP_BMILGW, |
| 1599 | CC_OP_BMILGL, |
| 1600 | CC_OP_BMILGQ, |
| 1601 | |
| 1602 | CC_OP_BLSIB, /* P,Z,S via CC_DST, C = SRC!=0; A=O=0 */ |
| 1603 | CC_OP_BLSIW, |
| 1604 | CC_OP_BLSIL, |
| 1605 | CC_OP_BLSIQ, |
| 1606 | |
| 1607 | /* |
| 1608 | * Note that only CC_OP_POPCNT (i.e. the one with MO_TL size) |
| 1609 | * is used or implemented, because the translation needs |
| 1610 | * to zero-extend CC_DST anyway. |
| 1611 | */ |
| 1612 | CC_OP_POPCNTB__, /* Z via CC_DST, all other flags clear. */ |
| 1613 | CC_OP_POPCNTW__, |
| 1614 | CC_OP_POPCNTL__, |
| 1615 | CC_OP_POPCNTQ__, |
| 1616 | CC_OP_POPCNT = sizeof(target_ulong) == 8 ? CC_OP_POPCNTQ__ : CC_OP_POPCNTL__, |
| 1617 | |
| 1618 | /* |
| 1619 | * Note that only CC_OP_SBB_SELF (i.e. the one with MO_TL size) |
| 1620 | * is used or implemented, because the translator sign-extends |
| 1621 | * the -1 or 0 value that is written in CC_DST. |
| 1622 | */ |
| 1623 | CC_OP_SBB_SELFB__, /* S/Z/C/A via CC_DST, O clear, P set. */ |
| 1624 | CC_OP_SBB_SELFW__, |
| 1625 | CC_OP_SBB_SELFL__, |
| 1626 | CC_OP_SBB_SELFQ__, |
| 1627 | CC_OP_SBB_SELF = sizeof(target_ulong) == 8 ? CC_OP_SBB_SELFQ__ : CC_OP_SBB_SELFL__, |
| 1628 | #define CC_OP_LAST_BWLQ CC_OP_SBB_SELFQ__ |
| 1629 | |
| 1630 | CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */ |
| 1631 | } CCOp; |
| 1632 | |
| 1633 | /* See X86DecodedInsn.cc_op, using int8_t. */ |
| 1634 | QEMU_BUILD_BUG_ON(CC_OP_DYNAMIC > INT8_MAX); |
| 1635 | |
| 1636 | static inline MemOp cc_op_size(CCOp op) |
| 1637 | { |
| 1638 | MemOp size = op & 3; |
| 1639 | |
| 1640 | QEMU_BUILD_BUG_ON(CC_OP_FIRST_BWLQ & 3); |
| 1641 | assert(op >= CC_OP_FIRST_BWLQ && op <= CC_OP_LAST_BWLQ); |
| 1642 | assert(size <= MO_TL); |
| 1643 | |
| 1644 | return size; |
| 1645 | } |
| 1646 | |
| 1647 | typedef struct SegmentCache { |
| 1648 | uint32_t selector; |
| 1649 | target_ulong base; |
| 1650 | uint32_t limit; |
| 1651 | uint32_t flags; |
| 1652 | } SegmentCache; |
| 1653 | |
| 1654 | typedef union MMXReg { |
| 1655 | uint8_t _b_MMXReg[64 / 8]; |
| 1656 | uint16_t _w_MMXReg[64 / 16]; |
| 1657 | uint32_t _l_MMXReg[64 / 32]; |
| 1658 | uint64_t _q_MMXReg[64 / 64]; |
| 1659 | float32 _s_MMXReg[64 / 32]; |
| 1660 | float64 _d_MMXReg[64 / 64]; |
| 1661 | } MMXReg; |
| 1662 | |
| 1663 | typedef union XMMReg { |
| 1664 | uint64_t _q_XMMReg[128 / 64]; |
| 1665 | } XMMReg; |
| 1666 | |
| 1667 | typedef union YMMReg { |
| 1668 | uint64_t _q_YMMReg[256 / 64]; |
| 1669 | XMMReg _x_YMMReg[256 / 128]; |
| 1670 | } YMMReg; |
| 1671 | |
| 1672 | typedef union ZMMReg { |
| 1673 | uint8_t _b_ZMMReg[512 / 8]; |
| 1674 | uint16_t _w_ZMMReg[512 / 16]; |
| 1675 | uint32_t _l_ZMMReg[512 / 32]; |
| 1676 | uint64_t _q_ZMMReg[512 / 64]; |
| 1677 | float16 _h_ZMMReg[512 / 16]; |
| 1678 | float32 _s_ZMMReg[512 / 32]; |
| 1679 | float64 _d_ZMMReg[512 / 64]; |
| 1680 | XMMReg _x_ZMMReg[512 / 128]; |
| 1681 | YMMReg _y_ZMMReg[512 / 256]; |
| 1682 | } ZMMReg; |
| 1683 | |
| 1684 | typedef struct BNDReg { |
| 1685 | uint64_t lb; |
| 1686 | uint64_t ub; |
| 1687 | } BNDReg; |
| 1688 | |
| 1689 | typedef struct BNDCSReg { |
| 1690 | uint64_t cfgu; |
| 1691 | uint64_t sts; |
| 1692 | } BNDCSReg; |
| 1693 | |
| 1694 | #define BNDCFG_ENABLE 1ULL |
| 1695 | #define BNDCFG_BNDPRESERVE 2ULL |
| 1696 | #define BNDCFG_BDIR_MASK TARGET_PAGE_MASK |
| 1697 | |
| 1698 | #if HOST_BIG_ENDIAN |
| 1699 | #define ZMM_B(n) _b_ZMMReg[63 - (n)] |
| 1700 | #define ZMM_W(n) _w_ZMMReg[31 - (n)] |
| 1701 | #define ZMM_L(n) _l_ZMMReg[15 - (n)] |
| 1702 | #define ZMM_H(n) _h_ZMMReg[31 - (n)] |
| 1703 | #define ZMM_S(n) _s_ZMMReg[15 - (n)] |
| 1704 | #define ZMM_Q(n) _q_ZMMReg[7 - (n)] |
| 1705 | #define ZMM_D(n) _d_ZMMReg[7 - (n)] |
| 1706 | #define ZMM_X(n) _x_ZMMReg[3 - (n)] |
| 1707 | #define ZMM_Y(n) _y_ZMMReg[1 - (n)] |
| 1708 | |
| 1709 | #define XMM_Q(n) _q_XMMReg[1 - (n)] |
| 1710 | |
| 1711 | #define YMM_Q(n) _q_YMMReg[3 - (n)] |
| 1712 | #define YMM_X(n) _x_YMMReg[1 - (n)] |
| 1713 | |
| 1714 | #define MMX_B(n) _b_MMXReg[7 - (n)] |
| 1715 | #define MMX_W(n) _w_MMXReg[3 - (n)] |
| 1716 | #define MMX_L(n) _l_MMXReg[1 - (n)] |
| 1717 | #define MMX_S(n) _s_MMXReg[1 - (n)] |
| 1718 | #else |
| 1719 | #define ZMM_B(n) _b_ZMMReg[n] |
| 1720 | #define ZMM_W(n) _w_ZMMReg[n] |
| 1721 | #define ZMM_L(n) _l_ZMMReg[n] |
| 1722 | #define ZMM_H(n) _h_ZMMReg[n] |
| 1723 | #define ZMM_S(n) _s_ZMMReg[n] |
| 1724 | #define ZMM_Q(n) _q_ZMMReg[n] |
| 1725 | #define ZMM_D(n) _d_ZMMReg[n] |
| 1726 | #define ZMM_X(n) _x_ZMMReg[n] |
| 1727 | #define ZMM_Y(n) _y_ZMMReg[n] |
| 1728 | |
| 1729 | #define XMM_Q(n) _q_XMMReg[n] |
| 1730 | |
| 1731 | #define YMM_Q(n) _q_YMMReg[n] |
| 1732 | #define YMM_X(n) _x_YMMReg[n] |
| 1733 | |
| 1734 | #define MMX_B(n) _b_MMXReg[n] |
| 1735 | #define MMX_W(n) _w_MMXReg[n] |
| 1736 | #define MMX_L(n) _l_MMXReg[n] |
| 1737 | #define MMX_S(n) _s_MMXReg[n] |
| 1738 | #endif |
| 1739 | #define MMX_Q(n) _q_MMXReg[n] |
| 1740 | |
| 1741 | typedef union { |
| 1742 | floatx80 d __attribute__((aligned(16))); |
| 1743 | MMXReg mmx; |
| 1744 | } FPReg; |
| 1745 | |
| 1746 | typedef struct { |
| 1747 | uint64_t base; |
| 1748 | uint64_t mask; |
| 1749 | } MTRRVar; |
| 1750 | |
| 1751 | #define CPU_NB_EREGS64 32 |
| 1752 | #define CPU_NB_REGS64 16 |
| 1753 | #define CPU_NB_REGS32 8 |
| 1754 | |
| 1755 | #ifdef TARGET_X86_64 |
| 1756 | #define CPU_NB_EREGS CPU_NB_EREGS64 |
| 1757 | #define CPU_NB_REGS CPU_NB_REGS64 |
| 1758 | #else |
| 1759 | #define CPU_NB_EREGS CPU_NB_REGS32 |
| 1760 | #define CPU_NB_REGS CPU_NB_REGS32 |
| 1761 | #endif |
| 1762 | |
| 1763 | #define MAX_FIXED_COUNTERS 3 |
| 1764 | /* |
| 1765 | * This formula is based on Intel's MSR. The current size also meets AMD's |
| 1766 | * needs. |
| 1767 | */ |
| 1768 | #define MAX_GP_COUNTERS (MSR_IA32_PERF_STATUS - MSR_P6_EVNTSEL0) |
| 1769 | |
| 1770 | #define NB_OPMASK_REGS 8 |
| 1771 | |
| 1772 | typedef struct { |
| 1773 | uint64_t from; |
| 1774 | uint64_t to; |
| 1775 | uint64_t info; |
| 1776 | } LBREntry; |
| 1777 | |
| 1778 | #define ARCH_LBR_NR_ENTRIES 32 |
| 1779 | |
| 1780 | #define EGPR_NUM 16 |
| 1781 | |
| 1782 | /* CPU can't have 0xFFFFFFFF APIC ID, use that value to distinguish |
| 1783 | * that APIC ID hasn't been set yet |
| 1784 | */ |
| 1785 | #define UNASSIGNED_APIC_ID 0xFFFFFFFF |
| 1786 | |
| 1787 | typedef struct X86LegacyXSaveArea { |
| 1788 | uint16_t fcw; |
| 1789 | uint16_t fsw; |
| 1790 | uint8_t ftw; |
| 1791 | uint8_t reserved; |
| 1792 | uint16_t fpop; |
| 1793 | union { |
| 1794 | struct { |
| 1795 | uint64_t fpip; |
| 1796 | uint64_t fpdp; |
| 1797 | }; |
| 1798 | struct { |
| 1799 | uint32_t fip; |
| 1800 | uint32_t fcs; |
| 1801 | uint32_t foo; |
| 1802 | uint32_t fos; |
| 1803 | }; |
| 1804 | }; |
| 1805 | uint32_t mxcsr; |
| 1806 | uint32_t mxcsr_mask; |
| 1807 | FPReg fpregs[8]; |
| 1808 | uint8_t xmm_regs[16][16]; |
| 1809 | uint32_t hw_reserved[12]; |
| 1810 | uint32_t sw_reserved[12]; |
| 1811 | } X86LegacyXSaveArea; |
| 1812 | |
| 1813 | QEMU_BUILD_BUG_ON(sizeof(X86LegacyXSaveArea) != 512); |
| 1814 | |
| 1815 | typedef struct X86XSaveHeader { |
| 1816 | uint64_t xstate_bv; |
| 1817 | uint64_t xcomp_bv; |
| 1818 | uint64_t reserve0; |
| 1819 | uint8_t reserved[40]; |
| 1820 | } X86XSaveHeader; |
| 1821 | |
| 1822 | /* Ext. save area 2: AVX State */ |
| 1823 | typedef struct XSaveAVX { |
| 1824 | uint8_t ymmh[16][16]; |
| 1825 | } XSaveAVX; |
| 1826 | |
| 1827 | /* Ext. save area 3: BNDREG */ |
| 1828 | typedef struct XSaveBNDREG { |
| 1829 | BNDReg bnd_regs[4]; |
| 1830 | } XSaveBNDREG; |
| 1831 | |
| 1832 | /* Ext. save area 4: BNDCSR */ |
| 1833 | typedef union XSaveBNDCSR { |
| 1834 | BNDCSReg bndcsr; |
| 1835 | uint8_t data[64]; |
| 1836 | } XSaveBNDCSR; |
| 1837 | |
| 1838 | /* Ext. save area 5: Opmask */ |
| 1839 | typedef struct XSaveOpmask { |
| 1840 | uint64_t opmask_regs[NB_OPMASK_REGS]; |
| 1841 | } XSaveOpmask; |
| 1842 | |
| 1843 | /* Ext. save area 6: ZMM_Hi256 */ |
| 1844 | typedef struct XSaveZMM_Hi256 { |
| 1845 | uint8_t zmm_hi256[16][32]; |
| 1846 | } XSaveZMM_Hi256; |
| 1847 | |
| 1848 | /* Ext. save area 7: Hi16_ZMM */ |
| 1849 | typedef struct XSaveHi16_ZMM { |
| 1850 | uint8_t hi16_zmm[16][64]; |
| 1851 | } XSaveHi16_ZMM; |
| 1852 | |
| 1853 | /* Ext. save area 9: PKRU state */ |
| 1854 | typedef struct XSavePKRU { |
| 1855 | uint32_t pkru; |
| 1856 | uint32_t padding; |
| 1857 | } XSavePKRU; |
| 1858 | |
| 1859 | /* Ext. save area 11: CET_U state */ |
| 1860 | typedef struct XSaveCETU { |
| 1861 | uint64_t u_cet; |
| 1862 | uint64_t pl3_ssp; |
| 1863 | } XSaveCETU; |
| 1864 | |
| 1865 | /* Ext. save area 12: CET_S state */ |
| 1866 | typedef struct XSaveCETS { |
| 1867 | uint64_t pl0_ssp; |
| 1868 | uint64_t pl1_ssp; |
| 1869 | uint64_t pl2_ssp; |
| 1870 | } XSaveCETS; |
| 1871 | |
| 1872 | /* Ext. save area 15: Arch LBR state */ |
| 1873 | typedef struct XSaveArchLBR { |
| 1874 | uint64_t lbr_ctl; |
| 1875 | uint64_t lbr_depth; |
| 1876 | uint64_t ler_from; |
| 1877 | uint64_t ler_to; |
| 1878 | uint64_t ler_info; |
| 1879 | LBREntry lbr_records[ARCH_LBR_NR_ENTRIES]; |
| 1880 | } XSaveArchLBR; |
| 1881 | |
| 1882 | /* Ext. save area 17: AMX XTILECFG state */ |
| 1883 | typedef struct XSaveXTILECFG { |
| 1884 | uint8_t xtilecfg[64]; |
| 1885 | } XSaveXTILECFG; |
| 1886 | |
| 1887 | /* Ext. save area 18: AMX XTILEDATA state */ |
| 1888 | typedef struct XSaveXTILEDATA { |
| 1889 | uint8_t xtiledata[8][1024]; |
| 1890 | } XSaveXTILEDATA; |
| 1891 | |
| 1892 | /* Ext. save area 19: APX state */ |
| 1893 | typedef struct XSaveAPX { |
| 1894 | uint64_t egprs[EGPR_NUM]; |
| 1895 | } XSaveAPX; |
| 1896 | |
| 1897 | QEMU_BUILD_BUG_ON(sizeof(XSaveAVX) != 0x100); |
| 1898 | QEMU_BUILD_BUG_ON(sizeof(XSaveBNDREG) != 0x40); |
| 1899 | QEMU_BUILD_BUG_ON(sizeof(XSaveBNDCSR) != 0x40); |
| 1900 | QEMU_BUILD_BUG_ON(sizeof(XSaveOpmask) != 0x40); |
| 1901 | QEMU_BUILD_BUG_ON(sizeof(XSaveZMM_Hi256) != 0x200); |
| 1902 | QEMU_BUILD_BUG_ON(sizeof(XSaveHi16_ZMM) != 0x400); |
| 1903 | QEMU_BUILD_BUG_ON(sizeof(XSavePKRU) != 0x8); |
| 1904 | QEMU_BUILD_BUG_ON(sizeof(XSaveCETU) != 0x10); |
| 1905 | QEMU_BUILD_BUG_ON(sizeof(XSaveCETS) != 0x18); |
| 1906 | QEMU_BUILD_BUG_ON(sizeof(XSaveArchLBR) != 0x328); |
| 1907 | QEMU_BUILD_BUG_ON(sizeof(XSaveXTILECFG) != 0x40); |
| 1908 | QEMU_BUILD_BUG_ON(sizeof(XSaveXTILEDATA) != 0x2000); |
| 1909 | QEMU_BUILD_BUG_ON(sizeof(XSaveAPX) != 0x80); |
| 1910 | |
| 1911 | typedef struct ExtSaveArea { |
| 1912 | uint32_t offset, size; |
| 1913 | uint32_t ecx; |
| 1914 | /* |
| 1915 | * The dependencies in the array work as OR relationships, which |
| 1916 | * means having just one of those features is enough. |
| 1917 | * |
| 1918 | * At most two features are sharing the same xsave area. |
| 1919 | * Number of features can be adjusted if necessary. |
| 1920 | */ |
| 1921 | const FeatureMask features[2]; |
| 1922 | } ExtSaveArea; |
| 1923 | |
| 1924 | #define XSAVE_STATE_AREA_COUNT (XSTATE_APX_BIT + 1) |
| 1925 | |
| 1926 | extern ExtSaveArea x86_ext_save_areas[XSAVE_STATE_AREA_COUNT]; |
| 1927 | |
| 1928 | typedef enum TPRAccess { |
| 1929 | TPR_ACCESS_READ, |
| 1930 | TPR_ACCESS_WRITE, |
| 1931 | } TPRAccess; |
| 1932 | |
| 1933 | /* Cache information data structures: */ |
| 1934 | |
| 1935 | typedef struct CPUCacheInfo { |
| 1936 | enum CacheType type; |
| 1937 | uint8_t level; |
| 1938 | /* Size in bytes */ |
| 1939 | uint32_t size; |
| 1940 | /* Line size, in bytes */ |
| 1941 | uint16_t line_size; |
| 1942 | /* |
| 1943 | * Associativity. |
| 1944 | * Note: representation of fully-associative caches is not implemented |
| 1945 | */ |
| 1946 | uint8_t associativity; |
| 1947 | /* Physical line partitions. CPUID[0x8000001D].EBX, CPUID[4].EBX */ |
| 1948 | uint8_t partitions; |
| 1949 | /* Number of sets. CPUID[0x8000001D].ECX, CPUID[4].ECX */ |
| 1950 | uint32_t sets; |
| 1951 | /* |
| 1952 | * Lines per tag. |
| 1953 | * AMD-specific: CPUID[0x80000005], CPUID[0x80000006]. |
| 1954 | * (Is this synonym to @partitions?) |
| 1955 | */ |
| 1956 | uint8_t lines_per_tag; |
| 1957 | |
| 1958 | /* Self-initializing cache */ |
| 1959 | bool self_init; |
| 1960 | /* |
| 1961 | * WBINVD/INVD is not guaranteed to act upon lower level caches of |
| 1962 | * non-originating threads sharing this cache. |
| 1963 | * CPUID[4].EDX[bit 0], CPUID[0x8000001D].EDX[bit 0] |
| 1964 | */ |
| 1965 | bool no_invd_sharing; |
| 1966 | /* |
| 1967 | * Cache is inclusive of lower cache levels. |
| 1968 | * CPUID[4].EDX[bit 1], CPUID[0x8000001D].EDX[bit 1]. |
| 1969 | */ |
| 1970 | bool inclusive; |
| 1971 | /* |
| 1972 | * A complex function is used to index the cache, potentially using all |
| 1973 | * address bits. CPUID[4].EDX[bit 2]. |
| 1974 | */ |
| 1975 | bool complex_indexing; |
| 1976 | |
| 1977 | /* |
| 1978 | * Cache Topology. The level that cache is shared in. |
| 1979 | * Used to encode CPUID[4].EAX[bits 25:14] or |
| 1980 | * CPUID[0x8000001D].EAX[bits 25:14]. |
| 1981 | */ |
| 1982 | CpuTopologyLevel share_level; |
| 1983 | } CPUCacheInfo; |
| 1984 | |
| 1985 | |
| 1986 | typedef struct CPUCaches { |
| 1987 | CPUCacheInfo *l1d_cache; |
| 1988 | CPUCacheInfo *l1i_cache; |
| 1989 | CPUCacheInfo *l2_cache; |
| 1990 | CPUCacheInfo *l3_cache; |
| 1991 | } CPUCaches; |
| 1992 | |
| 1993 | struct kvm_msrs; |
| 1994 | struct hv_vp_register_page; |
| 1995 | |
| 1996 | typedef struct CPUArchState { |
| 1997 | /* standard registers */ |
| 1998 | target_ulong regs[CPU_NB_EREGS]; |
| 1999 | target_ulong eip; |
| 2000 | target_ulong eflags; /* eflags register. During CPU emulation, CC |
| 2001 | flags and DF are set to zero because they are |
| 2002 | stored elsewhere */ |
| 2003 | |
| 2004 | /* emulator internal eflags handling */ |
| 2005 | target_ulong cc_dst; |
| 2006 | target_ulong cc_src; |
| 2007 | target_ulong cc_src2; |
| 2008 | uint32_t cc_op; |
| 2009 | int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */ |
| 2010 | uint32_t hflags; /* TB flags, see HF_xxx constants. These flags |
| 2011 | are known at translation time. */ |
| 2012 | uint32_t hflags2; /* various other flags, see HF2_xxx constants. */ |
| 2013 | |
| 2014 | /* segments */ |
| 2015 | SegmentCache segs[6]; /* selector values */ |
| 2016 | SegmentCache ldt; |
| 2017 | SegmentCache tr; |
| 2018 | SegmentCache gdt; /* only base and limit are used */ |
| 2019 | SegmentCache idt; /* only base and limit are used */ |
| 2020 | |
| 2021 | target_ulong cr[5]; /* NOTE: cr1 is unused */ |
| 2022 | |
| 2023 | bool pdptrs_valid; |
| 2024 | uint64_t pdptrs[4]; |
| 2025 | int32_t a20_mask; |
| 2026 | |
| 2027 | BNDReg bnd_regs[4]; |
| 2028 | BNDCSReg bndcs_regs; |
| 2029 | uint64_t msr_bndcfgs; |
| 2030 | uint64_t efer; |
| 2031 | |
| 2032 | /* Beginning of state preserved by INIT (dummy marker). */ |
| 2033 | struct {} start_init_save; |
| 2034 | |
| 2035 | /* FPU state */ |
| 2036 | unsigned int fpstt; /* top of stack index */ |
| 2037 | uint16_t fpus; |
| 2038 | uint16_t fpuc; |
| 2039 | uint8_t fptags[8]; /* 0 = valid, 1 = empty */ |
| 2040 | FPReg fpregs[8]; |
| 2041 | /* KVM-only so far */ |
| 2042 | uint16_t fpop; |
| 2043 | uint16_t fpcs; |
| 2044 | uint16_t fpds; |
| 2045 | uint64_t fpip; |
| 2046 | uint64_t fpdp; |
| 2047 | |
| 2048 | /* emulator internal variables */ |
| 2049 | float_status fp_status; |
| 2050 | floatx80 ft0; |
| 2051 | |
| 2052 | float_status mmx_status; /* for 3DNow! float ops */ |
| 2053 | float_status sse_status; |
| 2054 | uint32_t mxcsr; |
| 2055 | ZMMReg xmm_regs[CPU_NB_EREGS] QEMU_ALIGNED(16); |
| 2056 | ZMMReg xmm_t0 QEMU_ALIGNED(16); |
| 2057 | MMXReg mmx_t0; |
| 2058 | |
| 2059 | uint64_t opmask_regs[NB_OPMASK_REGS]; |
| 2060 | #ifdef TARGET_X86_64 |
| 2061 | uint8_t xtilecfg[64]; |
| 2062 | uint8_t xtiledata[8192]; |
| 2063 | #endif |
| 2064 | |
| 2065 | /* sysenter registers */ |
| 2066 | uint32_t sysenter_cs; |
| 2067 | target_ulong sysenter_esp; |
| 2068 | target_ulong sysenter_eip; |
| 2069 | uint64_t star; |
| 2070 | |
| 2071 | uint64_t vm_hsave; |
| 2072 | |
| 2073 | #ifdef TARGET_X86_64 |
| 2074 | uint64_t lstar; |
| 2075 | uint64_t cstar; |
| 2076 | uint64_t fmask; |
| 2077 | uint64_t kernelgsbase; |
| 2078 | |
| 2079 | /* FRED MSRs */ |
| 2080 | uint64_t fred_rsp0; |
| 2081 | uint64_t fred_rsp1; |
| 2082 | uint64_t fred_rsp2; |
| 2083 | uint64_t fred_rsp3; |
| 2084 | uint64_t fred_stklvls; |
| 2085 | uint64_t fred_ssp1; |
| 2086 | uint64_t fred_ssp2; |
| 2087 | uint64_t fred_ssp3; |
| 2088 | uint64_t fred_config; |
| 2089 | #endif |
| 2090 | |
| 2091 | /* CET MSRs and register */ |
| 2092 | uint64_t u_cet; |
| 2093 | uint64_t s_cet; |
| 2094 | uint64_t pl0_ssp; /* also used for FRED */ |
| 2095 | uint64_t pl1_ssp; |
| 2096 | uint64_t pl2_ssp; |
| 2097 | uint64_t pl3_ssp; |
| 2098 | #ifdef TARGET_X86_64 |
| 2099 | uint64_t int_ssp_table; |
| 2100 | #endif |
| 2101 | uint64_t guest_ssp; |
| 2102 | |
| 2103 | uint64_t tsc_adjust; |
| 2104 | uint64_t tsc_deadline; |
| 2105 | uint64_t tsc_aux; |
| 2106 | |
| 2107 | uint64_t xcr0; |
| 2108 | |
| 2109 | uint64_t mcg_status; |
| 2110 | uint64_t msr_ia32_misc_enable; |
| 2111 | uint64_t msr_ia32_feature_control; |
| 2112 | uint64_t msr_ia32_sgxlepubkeyhash[4]; |
| 2113 | |
| 2114 | uint64_t msr_fixed_ctr_ctrl; |
| 2115 | uint64_t msr_global_ctrl; |
| 2116 | uint64_t msr_global_status; |
| 2117 | uint64_t msr_global_ovf_ctrl; |
| 2118 | uint64_t msr_fixed_counters[MAX_FIXED_COUNTERS]; |
| 2119 | uint64_t msr_gp_counters[MAX_GP_COUNTERS]; |
| 2120 | uint64_t msr_gp_evtsel[MAX_GP_COUNTERS]; |
| 2121 | |
| 2122 | uint64_t pat; |
| 2123 | uint32_t smbase; |
| 2124 | uint64_t msr_smi_count; |
| 2125 | |
| 2126 | uint32_t pkru; |
| 2127 | uint32_t pkrs; |
| 2128 | uint32_t tsx_ctrl; |
| 2129 | |
| 2130 | uint64_t spec_ctrl; |
| 2131 | uint64_t amd_tsc_scale_msr; |
| 2132 | uint64_t virt_ssbd; |
| 2133 | |
| 2134 | /* End of state preserved by INIT (dummy marker). */ |
| 2135 | struct {} end_init_save; |
| 2136 | |
| 2137 | uint64_t system_time_msr; |
| 2138 | uint64_t wall_clock_msr; |
| 2139 | uint64_t steal_time_msr; |
| 2140 | uint64_t async_pf_en_msr; |
| 2141 | uint64_t async_pf_int_msr; |
| 2142 | uint64_t pv_eoi_en_msr; |
| 2143 | uint64_t poll_control_msr; |
| 2144 | |
| 2145 | /* Partition-wide HV MSRs, will be updated only on the first vcpu */ |
| 2146 | uint64_t msr_hv_hypercall; |
| 2147 | uint64_t msr_hv_guest_os_id; |
| 2148 | uint64_t msr_hv_tsc; |
| 2149 | uint64_t msr_hv_syndbg_control; |
| 2150 | uint64_t msr_hv_syndbg_status; |
| 2151 | uint64_t msr_hv_syndbg_send_page; |
| 2152 | uint64_t msr_hv_syndbg_recv_page; |
| 2153 | uint64_t msr_hv_syndbg_pending_page; |
| 2154 | uint64_t msr_hv_syndbg_options; |
| 2155 | |
| 2156 | /* Per-VCPU HV MSRs */ |
| 2157 | uint64_t msr_hv_vapic; |
| 2158 | uint64_t msr_hv_crash_params[HV_CRASH_PARAMS]; |
| 2159 | uint64_t msr_hv_runtime; |
| 2160 | uint64_t msr_hv_synic_control; |
| 2161 | uint64_t msr_hv_synic_evt_page; |
| 2162 | uint64_t msr_hv_synic_msg_page; |
| 2163 | uint64_t msr_hv_synic_sint[HV_SINT_COUNT]; |
| 2164 | uint64_t msr_hv_stimer_config[HV_STIMER_COUNT]; |
| 2165 | uint64_t msr_hv_stimer_count[HV_STIMER_COUNT]; |
| 2166 | uint64_t msr_hv_reenlightenment_control; |
| 2167 | uint64_t msr_hv_tsc_emulation_control; |
| 2168 | uint64_t msr_hv_tsc_emulation_status; |
| 2169 | |
| 2170 | uint64_t msr_rtit_ctrl; |
| 2171 | uint64_t msr_rtit_status; |
| 2172 | uint64_t msr_rtit_output_base; |
| 2173 | uint64_t msr_rtit_output_mask; |
| 2174 | uint64_t msr_rtit_cr3_match; |
| 2175 | uint64_t msr_rtit_addrs[MAX_RTIT_ADDRS]; |
| 2176 | |
| 2177 | /* Per-VCPU XFD MSRs */ |
| 2178 | uint64_t msr_xfd; |
| 2179 | uint64_t msr_xfd_err; |
| 2180 | |
| 2181 | /* Per-VCPU Arch LBR MSRs */ |
| 2182 | uint64_t msr_lbr_ctl; |
| 2183 | uint64_t msr_lbr_depth; |
| 2184 | LBREntry lbr_records[ARCH_LBR_NR_ENTRIES]; |
| 2185 | |
| 2186 | /* AMD MSRC001_0015 Hardware Configuration */ |
| 2187 | uint64_t msr_hwcr; |
| 2188 | |
| 2189 | /* exception/interrupt handling */ |
| 2190 | int error_code; |
| 2191 | int exception_is_int; |
| 2192 | target_ulong exception_next_eip; |
| 2193 | target_ulong dr[8]; /* debug registers; note dr4 and dr5 are unused */ |
| 2194 | union { |
| 2195 | struct CPUBreakpoint *cpu_breakpoint[4]; |
| 2196 | struct CPUWatchpoint *cpu_watchpoint[4]; |
| 2197 | }; /* break/watchpoints for dr[0..3] */ |
| 2198 | int old_exception; /* exception in flight */ |
| 2199 | |
| 2200 | uint64_t vm_vmcb; |
| 2201 | uint64_t tsc_offset; |
| 2202 | uint64_t intercept; |
| 2203 | uint16_t intercept_cr_read; |
| 2204 | uint16_t intercept_cr_write; |
| 2205 | uint16_t intercept_dr_read; |
| 2206 | uint16_t intercept_dr_write; |
| 2207 | uint32_t intercept_exceptions; |
| 2208 | uint64_t nested_cr3; |
| 2209 | uint32_t nested_pg_mode; |
| 2210 | uint8_t v_tpr; |
| 2211 | uint32_t int_ctl; |
| 2212 | |
| 2213 | /* KVM states, automatically cleared on reset */ |
| 2214 | uint8_t nmi_injected; |
| 2215 | uint8_t nmi_pending; |
| 2216 | |
| 2217 | uintptr_t retaddr; |
| 2218 | |
| 2219 | /* RAPL MSR */ |
| 2220 | uint64_t msr_rapl_power_unit; |
| 2221 | uint64_t msr_pkg_energy_status; |
| 2222 | |
| 2223 | /* Fields up to this point are cleared by a CPU reset */ |
| 2224 | struct {} end_reset_fields; |
| 2225 | |
| 2226 | /* Fields after this point are preserved across CPU reset. */ |
| 2227 | |
| 2228 | /* processor features (e.g. for CPUID insn) */ |
| 2229 | /* Minimum cpuid leaf 7 value */ |
| 2230 | uint32_t cpuid_level_func7; |
| 2231 | /* Actual cpuid leaf 7 value */ |
| 2232 | uint32_t cpuid_min_level_func7; |
| 2233 | /* Minimum level/xlevel/xlevel2, based on CPU model + features */ |
| 2234 | uint32_t cpuid_min_level, cpuid_min_xlevel, cpuid_min_xlevel2; |
| 2235 | /* Maximum level/xlevel/xlevel2 value for auto-assignment: */ |
| 2236 | uint32_t cpuid_max_level, cpuid_max_xlevel, cpuid_max_xlevel2; |
| 2237 | /* Actual level/xlevel/xlevel2 value: */ |
| 2238 | uint32_t cpuid_level, cpuid_xlevel, cpuid_xlevel2; |
| 2239 | uint32_t cpuid_vendor1; |
| 2240 | uint32_t cpuid_vendor2; |
| 2241 | uint32_t cpuid_vendor3; |
| 2242 | uint32_t cpuid_version; |
| 2243 | FeatureWordArray features; |
| 2244 | /* AVX10 version */ |
| 2245 | uint8_t avx10_version; |
| 2246 | /* AVX10 (CPUID 0x24) maximum supported sub-leaf. */ |
| 2247 | uint8_t avx10_max_subleaf; |
| 2248 | /* Features that were explicitly enabled/disabled */ |
| 2249 | FeatureWordArray user_features; |
| 2250 | uint32_t cpuid_model[12]; |
| 2251 | /* |
| 2252 | * Cache information for CPUID. When legacy-cache=on, the cache data |
| 2253 | * on each CPUID leaf will be different, because we keep compatibility |
| 2254 | * with old QEMU versions. |
| 2255 | */ |
| 2256 | CPUCaches cache_info; |
| 2257 | bool enable_legacy_cpuid2_cache; |
| 2258 | bool enable_legacy_vendor_cache; |
| 2259 | |
| 2260 | /* MTRRs */ |
| 2261 | uint64_t mtrr_fixed[11]; |
| 2262 | uint64_t mtrr_deftype; |
| 2263 | MTRRVar mtrr_var[MSR_MTRRcap_VCNT]; |
| 2264 | |
| 2265 | /* For KVM */ |
| 2266 | uint32_t mp_state; |
| 2267 | int32_t exception_nr; |
| 2268 | int32_t interrupt_injected; |
| 2269 | uint8_t soft_interrupt; |
| 2270 | uint8_t exception_pending; |
| 2271 | uint8_t exception_injected; |
| 2272 | uint8_t has_error_code; |
| 2273 | uint8_t exception_has_payload; |
| 2274 | uint64_t exception_payload; |
| 2275 | uint8_t triple_fault_pending; |
| 2276 | uint32_t ins_len; |
| 2277 | uint32_t sipi_vector; |
| 2278 | bool tsc_valid; |
| 2279 | int64_t tsc_khz; |
| 2280 | int64_t user_tsc_khz; /* for sanity check only */ |
| 2281 | uint64_t apic_bus_freq; |
| 2282 | uint64_t tsc; |
| 2283 | void *xsave_buf; |
| 2284 | uint32_t xsave_buf_len; |
| 2285 | #if defined(CONFIG_KVM) |
| 2286 | struct kvm_nested_state *nested_state; |
| 2287 | MemoryRegion *xen_vcpu_info_mr; |
| 2288 | void *xen_vcpu_info_hva; |
| 2289 | uint64_t xen_vcpu_info_gpa; |
| 2290 | uint64_t xen_vcpu_info_default_gpa; |
| 2291 | uint64_t xen_vcpu_time_info_gpa; |
| 2292 | uint64_t xen_vcpu_runstate_gpa; |
| 2293 | uint8_t xen_vcpu_callback_vector; |
| 2294 | bool xen_callback_asserted; |
| 2295 | uint16_t xen_virq[XEN_NR_VIRQS]; |
| 2296 | uint64_t xen_singleshot_timer_ns; |
| 2297 | QEMUTimer *xen_singleshot_timer; |
| 2298 | uint64_t xen_periodic_timer_period; |
| 2299 | QEMUTimer *xen_periodic_timer; |
| 2300 | QemuMutex xen_timers_lock; |
| 2301 | #endif |
| 2302 | #if defined(CONFIG_MSHV) |
| 2303 | /* Shared register page */ |
| 2304 | struct hv_vp_register_page *regs_page; |
| 2305 | #endif |
| 2306 | #if defined(CONFIG_HVF) || defined(CONFIG_MSHV) || defined(CONFIG_WHPX) |
| 2307 | void *emu_mmio_buf; |
| 2308 | #endif |
| 2309 | #if defined(CONFIG_MSHV) |
| 2310 | uint8_t hv_simp_page[HV_HYP_PAGE_SIZE]; |
| 2311 | uint8_t hv_siefp_page[HV_HYP_PAGE_SIZE]; |
| 2312 | uint8_t hv_synthetic_timers_state[MSHV_STIMERS_STATE_SIZE]; |
| 2313 | #endif |
| 2314 | |
| 2315 | uint64_t mcg_cap; |
| 2316 | uint64_t mcg_ctl; |
| 2317 | uint64_t mcg_ext_ctl; |
| 2318 | uint64_t mce_banks[MCE_BANKS_DEF*4]; |
| 2319 | uint64_t xstate_bv; |
| 2320 | |
| 2321 | /* vmstate */ |
| 2322 | uint16_t fpus_vmstate; |
| 2323 | uint16_t fptag_vmstate; |
| 2324 | uint16_t fpregs_format_vmstate; |
| 2325 | |
| 2326 | uint64_t xss; |
| 2327 | uint32_t umwait; |
| 2328 | |
| 2329 | TPRAccess tpr_access_type; |
| 2330 | |
| 2331 | X86CPUTopoInfo topo_info; |
| 2332 | |
| 2333 | /* Bitmap of available CPU topology levels for this CPU. */ |
| 2334 | DECLARE_BITMAP(avail_cpu_topo, CPU_TOPOLOGY_LEVEL__MAX); |
| 2335 | } CPUX86State; |
| 2336 | |
| 2337 | /** |
| 2338 | * X86CPU: |
| 2339 | * @env: #CPUX86State |
| 2340 | * @migratable: If set, only migratable flags will be accepted when "enforce" |
| 2341 | * mode is used, and only migratable flags will be included in the "host" |
| 2342 | * CPU model. |
| 2343 | * |
| 2344 | * An x86 CPU. |
| 2345 | */ |
| 2346 | struct ArchCPU { |
| 2347 | CPUState parent_obj; |
| 2348 | |
| 2349 | CPUX86State env; |
| 2350 | VMChangeStateEntry *vmsentry; |
| 2351 | |
| 2352 | uint64_t ucode_rev; |
| 2353 | |
| 2354 | uint32_t hyperv_spinlock_attempts; |
| 2355 | char *hyperv_vendor; |
| 2356 | uint64_t hyperv_features; |
| 2357 | bool hyperv_passthrough; |
| 2358 | OnOffAuto hyperv_no_nonarch_cs; |
| 2359 | uint32_t hyperv_vendor_id[3]; |
| 2360 | uint32_t hyperv_interface_id[4]; |
| 2361 | uint32_t hyperv_limits[3]; |
| 2362 | bool hyperv_enforce_cpuid; |
| 2363 | uint32_t hyperv_ver_id_build; |
| 2364 | uint16_t hyperv_ver_id_major; |
| 2365 | uint16_t hyperv_ver_id_minor; |
| 2366 | uint32_t hyperv_ver_id_sp; |
| 2367 | uint8_t hyperv_ver_id_sb; |
| 2368 | uint32_t hyperv_ver_id_sn; |
| 2369 | |
| 2370 | bool check_cpuid; |
| 2371 | bool enforce_cpuid; |
| 2372 | /* |
| 2373 | * Force features to be enabled even if the host doesn't support them. |
| 2374 | * This is dangerous and should be done only for testing CPUID |
| 2375 | * compatibility. |
| 2376 | */ |
| 2377 | bool force_features; |
| 2378 | bool expose_kvm; |
| 2379 | bool expose_tcg; |
| 2380 | bool migratable; |
| 2381 | bool migrate_smi_count; |
| 2382 | bool migrate_error_code; |
| 2383 | uint32_t apic_id; |
| 2384 | |
| 2385 | /* Enables publishing of TSC increment and Local APIC bus frequencies to |
| 2386 | * the guest OS in CPUID page 0x40000010, the same way that VMWare does. */ |
| 2387 | bool vmware_cpuid_freq; |
| 2388 | |
| 2389 | /* if true the CPUID code directly forward host cache leaves to the guest */ |
| 2390 | bool cache_info_passthrough; |
| 2391 | |
| 2392 | /* if true the CPUID code directly forwards |
| 2393 | * host monitor/mwait leaves to the guest */ |
| 2394 | struct { |
| 2395 | uint32_t eax; |
| 2396 | uint32_t ebx; |
| 2397 | uint32_t ecx; |
| 2398 | uint32_t edx; |
| 2399 | } mwait; |
| 2400 | |
| 2401 | /* Features that were filtered out because of missing host capabilities */ |
| 2402 | FeatureWordArray filtered_features; |
| 2403 | |
| 2404 | /* Features that are forced enabled by underlying hypervisor, e.g., TDX */ |
| 2405 | FeatureWordArray forced_on_features; |
| 2406 | |
| 2407 | /* Enable PMU CPUID bits. This can't be enabled by default yet because |
| 2408 | * it doesn't have ABI stability guarantees, as it passes all PMU CPUID |
| 2409 | * bits returned by GET_SUPPORTED_CPUID (that depend on host CPU and kernel |
| 2410 | * capabilities) directly to the guest. |
| 2411 | */ |
| 2412 | bool enable_pmu; |
| 2413 | |
| 2414 | /* |
| 2415 | * Enable LBR_FMT bits of IA32_PERF_CAPABILITIES MSR. |
| 2416 | * This can't be initialized with a default because it doesn't have |
| 2417 | * stable ABI support yet. It is only allowed to pass all LBR_FMT bits |
| 2418 | * returned by kvm_arch_get_supported_msr_feature()(which depends on both |
| 2419 | * host CPU and kernel capabilities) to the guest. |
| 2420 | */ |
| 2421 | uint64_t lbr_fmt; |
| 2422 | |
| 2423 | /* LMCE support can be enabled/disabled via cpu option 'lmce=on/off'. It is |
| 2424 | * disabled by default to avoid breaking migration between QEMU with |
| 2425 | * different LMCE configurations. |
| 2426 | */ |
| 2427 | bool enable_lmce; |
| 2428 | |
| 2429 | /* Compatibility bits for old machine types. |
| 2430 | * If true present virtual l3 cache for VM, the vcpus in the same virtual |
| 2431 | * socket share an virtual l3 cache. |
| 2432 | */ |
| 2433 | bool enable_l3_cache; |
| 2434 | |
| 2435 | /* Compatibility bits for old machine types. |
| 2436 | * If true present L1 cache as per-thread, not per-core. |
| 2437 | */ |
| 2438 | bool l1_cache_per_core; |
| 2439 | |
| 2440 | /* Compatibility bits for old machine types. |
| 2441 | * If true present the old cache topology information |
| 2442 | */ |
| 2443 | bool legacy_cache; |
| 2444 | |
| 2445 | /* |
| 2446 | * Compatibility bits for old machine types. |
| 2447 | * If true, use the same cache model in CPUID leaf 0x2 |
| 2448 | * and 0x4. |
| 2449 | */ |
| 2450 | bool consistent_cache; |
| 2451 | |
| 2452 | /* Compatibility bits for old machine types. |
| 2453 | * If true decode the CPUID Function 0x8000001E_ECX to support multiple |
| 2454 | * nodes per processor |
| 2455 | */ |
| 2456 | bool legacy_multi_node; |
| 2457 | |
| 2458 | /* Compatibility bits for old machine types: */ |
| 2459 | bool enable_cpuid_0xb; |
| 2460 | |
| 2461 | /* Force to enable cpuid 0x1f */ |
| 2462 | bool force_cpuid_0x1f; |
| 2463 | |
| 2464 | /* |
| 2465 | * Compatibility bits for old machine types (PC machine v6.0 and older). |
| 2466 | * Only advertise CPUID leaves defined by the vendor. |
| 2467 | */ |
| 2468 | bool vendor_cpuid_only; |
| 2469 | |
| 2470 | /* |
| 2471 | * Compatibility bits for old machine types (PC machine v10.0 and older). |
| 2472 | * Only advertise CPUID leaves defined by the vendor. |
| 2473 | */ |
| 2474 | bool vendor_cpuid_only_v2; |
| 2475 | |
| 2476 | /* Only advertise TOPOEXT features that AMD defines */ |
| 2477 | bool amd_topoext_features_only; |
| 2478 | |
| 2479 | /* if true fill the top bits of the MTRR_PHYSMASKn variable range */ |
| 2480 | bool fill_mtrr_mask; |
| 2481 | |
| 2482 | /* if true override the phys_bits value with a value read from the host */ |
| 2483 | bool host_phys_bits; |
| 2484 | |
| 2485 | /* if set, limit maximum value for phys_bits when host_phys_bits is true */ |
| 2486 | uint8_t host_phys_bits_limit; |
| 2487 | |
| 2488 | /* Forcefully disable KVM PV features not exposed in guest CPUIDs */ |
| 2489 | bool kvm_pv_enforce_cpuid; |
| 2490 | |
| 2491 | /* |
| 2492 | * Expose arch-capabilities unconditionally even on AMD models, for backwards |
| 2493 | * compatibility with QEMU <10.1. |
| 2494 | */ |
| 2495 | bool arch_cap_always_on; |
| 2496 | |
| 2497 | /* |
| 2498 | * Backwards compatibility with QEMU <10.1. The PDCM feature is now disabled when |
| 2499 | * PMU is not available, but prior to 10.1 it was enabled even if PMU is off. |
| 2500 | */ |
| 2501 | bool pdcm_on_even_without_pmu; |
| 2502 | |
| 2503 | /* Number of physical address bits supported */ |
| 2504 | uint32_t phys_bits; |
| 2505 | |
| 2506 | /* |
| 2507 | * Number of guest physical address bits available. Usually this is |
| 2508 | * identical to host physical address bits. With NPT or EPT 4-level |
| 2509 | * paging, guest physical address space might be restricted to 48 bits |
| 2510 | * even if the host cpu supports more physical address bits. |
| 2511 | */ |
| 2512 | uint32_t guest_phys_bits; |
| 2513 | |
| 2514 | /* in order to simplify APIC support, we leave this pointer to the |
| 2515 | user */ |
| 2516 | APICCommonState *apic_state; |
| 2517 | struct MemoryRegion *cpu_as_root, *cpu_as_mem, *smram; |
| 2518 | Notifier machine_done; |
| 2519 | |
| 2520 | struct kvm_msrs *kvm_msr_buf; |
| 2521 | |
| 2522 | int32_t node_id; /* NUMA node this CPU belongs to */ |
| 2523 | int32_t socket_id; |
| 2524 | int32_t die_id; |
| 2525 | int32_t module_id; |
| 2526 | int32_t core_id; |
| 2527 | int32_t thread_id; |
| 2528 | |
| 2529 | int32_t hv_max_vps; |
| 2530 | |
| 2531 | bool xen_vapic; |
| 2532 | }; |
| 2533 | |
| 2534 | typedef struct X86CPUModel X86CPUModel; |
| 2535 | |
| 2536 | /** |
| 2537 | * X86CPUClass: |
| 2538 | * @cpu_def: CPU model definition |
| 2539 | * @host_cpuid_required: Whether CPU model requires cpuid from host. |
| 2540 | * @ordering: Ordering on the "-cpu help" CPU model list. |
| 2541 | * @migration_safe: See CpuDefinitionInfo::migration_safe |
| 2542 | * @static_model: See CpuDefinitionInfo::static |
| 2543 | * @parent_realize: The parent class' realize handler. |
| 2544 | * @parent_phases: The parent class' reset phase handlers. |
| 2545 | * |
| 2546 | * An x86 CPU model or family. |
| 2547 | */ |
| 2548 | struct X86CPUClass { |
| 2549 | CPUClass parent_class; |
| 2550 | |
| 2551 | /* |
| 2552 | * CPU definition, automatically loaded by instance_init if not NULL. |
| 2553 | * Should be eventually replaced by subclass-specific property defaults. |
| 2554 | */ |
| 2555 | const X86CPUModel *model; |
| 2556 | |
| 2557 | bool max_features; /* Enable all supported features automatically */ |
| 2558 | bool host_cpuid_required; |
| 2559 | int ordering; |
| 2560 | bool migration_safe; |
| 2561 | bool static_model; |
| 2562 | |
| 2563 | /* |
| 2564 | * Optional description of CPU model. |
| 2565 | * If unavailable, cpu_def->model_id is used. |
| 2566 | */ |
| 2567 | const char *model_description; |
| 2568 | |
| 2569 | DeviceRealize parent_realize; |
| 2570 | DeviceUnrealize parent_unrealize; |
| 2571 | ResettablePhases parent_phases; |
| 2572 | }; |
| 2573 | |
| 2574 | #ifndef CONFIG_USER_ONLY |
| 2575 | extern const VMStateDescription vmstate_x86_cpu; |
| 2576 | #endif |
| 2577 | |
| 2578 | int x86_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu, |
| 2579 | int cpuid, DumpState *s); |
| 2580 | int x86_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu, |
| 2581 | int cpuid, DumpState *s); |
| 2582 | int x86_cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu, |
| 2583 | DumpState *s); |
| 2584 | int x86_cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu, |
| 2585 | DumpState *s); |
| 2586 | |
| 2587 | bool x86_cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list, |
| 2588 | Error **errp); |
| 2589 | |
| 2590 | void x86_cpu_dump_state(CPUState *cs, FILE *f, int flags); |
| 2591 | |
| 2592 | int x86_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); |
| 2593 | int x86_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); |
| 2594 | void x86_cpu_gdb_init(CPUState *cs); |
| 2595 | |
| 2596 | int cpu_x86_support_mca_broadcast(CPUX86State *env); |
| 2597 | |
| 2598 | #ifndef CONFIG_USER_ONLY |
| 2599 | int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request); |
| 2600 | |
| 2601 | bool x86_cpu_translate_for_debug(CPUState *cpu, vaddr addr, |
| 2602 | TranslateForDebugResult *result); |
| 2603 | int cpu_get_pic_interrupt(CPUX86State *s); |
| 2604 | |
| 2605 | /* MS-DOS compatibility mode FPU exception support */ |
| 2606 | void x86_register_ferr_irq(qemu_irq irq); |
| 2607 | void fpu_check_raise_ferr_irq(CPUX86State *s); |
| 2608 | void cpu_set_ignne(void); |
| 2609 | void cpu_clear_ignne(void); |
| 2610 | #endif |
| 2611 | |
| 2612 | /* mpx_helper.c */ |
| 2613 | void cpu_sync_bndcs_hflags(CPUX86State *env); |
| 2614 | |
| 2615 | /* this function must always be used to load data in the segment |
| 2616 | cache: it synchronizes the hflags with the segment cache values */ |
| 2617 | static inline void cpu_x86_load_seg_cache(CPUX86State *env, |
| 2618 | X86Seg seg_reg, unsigned int selector, |
| 2619 | target_ulong base, |
| 2620 | unsigned int limit, |
| 2621 | unsigned int flags) |
| 2622 | { |
| 2623 | SegmentCache *sc; |
| 2624 | unsigned int new_hflags; |
| 2625 | |
| 2626 | if (seg_reg == R_LDTR) { |
| 2627 | sc = &env->ldt; |
| 2628 | } else if (seg_reg == R_TR) { |
| 2629 | sc = &env->tr; |
| 2630 | } else { |
| 2631 | sc = &env->segs[seg_reg]; |
| 2632 | } |
| 2633 | |
| 2634 | sc->selector = selector; |
| 2635 | sc->base = base; |
| 2636 | sc->limit = limit; |
| 2637 | sc->flags = flags; |
| 2638 | |
| 2639 | /* update the hidden flags */ |
| 2640 | { |
| 2641 | if (seg_reg == R_CS) { |
| 2642 | #ifdef TARGET_X86_64 |
| 2643 | if ((env->hflags & HF_LMA_MASK) && (flags & DESC_L_MASK)) { |
| 2644 | /* long mode */ |
| 2645 | env->hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK; |
| 2646 | env->hflags &= ~(HF_ADDSEG_MASK); |
| 2647 | } else |
| 2648 | #endif |
| 2649 | { |
| 2650 | /* legacy / compatibility case */ |
| 2651 | new_hflags = (env->segs[R_CS].flags & DESC_B_MASK) |
| 2652 | >> (DESC_B_SHIFT - HF_CS32_SHIFT); |
| 2653 | env->hflags = (env->hflags & ~(HF_CS32_MASK | HF_CS64_MASK)) | |
| 2654 | new_hflags; |
| 2655 | } |
| 2656 | } |
| 2657 | if (seg_reg == R_SS) { |
| 2658 | int cpl = (flags >> DESC_DPL_SHIFT) & 3; |
| 2659 | #if HF_CPL_MASK != 3 |
| 2660 | #error HF_CPL_MASK is hardcoded |
| 2661 | #endif |
| 2662 | env->hflags = (env->hflags & ~HF_CPL_MASK) | cpl; |
| 2663 | /* Possibly switch between BNDCFGS and BNDCFGU */ |
| 2664 | cpu_sync_bndcs_hflags(env); |
| 2665 | } |
| 2666 | new_hflags = (env->segs[R_SS].flags & DESC_B_MASK) |
| 2667 | >> (DESC_B_SHIFT - HF_SS32_SHIFT); |
| 2668 | if (env->hflags & HF_CS64_MASK) { |
| 2669 | /* zero base assumed for DS, ES and SS in long mode */ |
| 2670 | } else if (!(env->cr[0] & CR0_PE_MASK) || |
| 2671 | (env->eflags & VM_MASK) || |
| 2672 | !(env->hflags & HF_CS32_MASK)) { |
| 2673 | /* XXX: try to avoid this test. The problem comes from the |
| 2674 | fact that is real mode or vm86 mode we only modify the |
| 2675 | 'base' and 'selector' fields of the segment cache to go |
| 2676 | faster. A solution may be to force addseg to one in |
| 2677 | translate-i386.c. */ |
| 2678 | new_hflags |= HF_ADDSEG_MASK; |
| 2679 | } else { |
| 2680 | new_hflags |= ((env->segs[R_DS].base | |
| 2681 | env->segs[R_ES].base | |
| 2682 | env->segs[R_SS].base) != 0) << |
| 2683 | HF_ADDSEG_SHIFT; |
| 2684 | } |
| 2685 | env->hflags = (env->hflags & |
| 2686 | ~(HF_SS32_MASK | HF_ADDSEG_MASK)) | new_hflags; |
| 2687 | } |
| 2688 | } |
| 2689 | |
| 2690 | static inline void cpu_x86_load_seg_cache_sipi(X86CPU *cpu, |
| 2691 | uint8_t sipi_vector) |
| 2692 | { |
| 2693 | CPUState *cs = CPU(cpu); |
| 2694 | CPUX86State *env = &cpu->env; |
| 2695 | |
| 2696 | env->eip = 0; |
| 2697 | cpu_x86_load_seg_cache(env, R_CS, sipi_vector << 8, |
| 2698 | sipi_vector << 12, |
| 2699 | env->segs[R_CS].limit, |
| 2700 | env->segs[R_CS].flags); |
| 2701 | cs->halted = 0; |
| 2702 | } |
| 2703 | |
| 2704 | uint64_t cpu_x86_get_msr_core_thread_count(X86CPU *cpu); |
| 2705 | |
| 2706 | int cpu_x86_get_descr_debug(CPUX86State *env, unsigned int selector, |
| 2707 | target_ulong *base, unsigned int *limit, |
| 2708 | unsigned int *flags); |
| 2709 | |
| 2710 | /* op_helper.c */ |
| 2711 | /* used for debug or cpu save/restore */ |
| 2712 | |
| 2713 | /* cpu-exec.c */ |
| 2714 | /* |
| 2715 | * The following helpers are only usable in user mode simulation. |
| 2716 | * The host pointers should come from lock_user(). |
| 2717 | */ |
| 2718 | void cpu_x86_load_seg(CPUX86State *s, X86Seg seg_reg, int selector); |
| 2719 | void cpu_x86_fsave(CPUX86State *s, void *host, size_t len); |
| 2720 | void cpu_x86_frstor(CPUX86State *s, void *host, size_t len); |
| 2721 | void cpu_x86_fxsave(CPUX86State *s, void *host, size_t len); |
| 2722 | void cpu_x86_fxrstor(CPUX86State *s, void *host, size_t len); |
| 2723 | void cpu_x86_xsave(CPUX86State *s, void *host, size_t len, uint64_t rbfm); |
| 2724 | bool cpu_x86_xrstor(CPUX86State *s, void *host, size_t len, uint64_t rbfm); |
| 2725 | |
| 2726 | /* cpu.c */ |
| 2727 | void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1, |
| 2728 | uint32_t vendor2, uint32_t vendor3); |
| 2729 | typedef struct PropValue { |
| 2730 | const char *prop, *value; |
| 2731 | } PropValue; |
| 2732 | void x86_cpu_apply_props(X86CPU *cpu, PropValue *props); |
| 2733 | |
| 2734 | void x86_cpu_after_reset(X86CPU *cpu); |
| 2735 | |
| 2736 | uint32_t cpu_x86_virtual_addr_width(CPUX86State *env); |
| 2737 | |
| 2738 | /* cpu.c other functions (cpuid) */ |
| 2739 | void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, |
| 2740 | uint32_t *eax, uint32_t *ebx, |
| 2741 | uint32_t *ecx, uint32_t *edx); |
| 2742 | void cpu_clear_apic_feature(CPUX86State *env); |
| 2743 | void cpu_set_apic_feature(CPUX86State *env); |
| 2744 | void host_cpuid(uint32_t function, uint32_t count, |
| 2745 | uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx); |
| 2746 | bool cpu_has_x2apic_feature(CPUX86State *env); |
| 2747 | bool is_feature_word_cpuid(uint32_t feature, uint32_t index, int reg); |
| 2748 | void mark_unavailable_features(X86CPU *cpu, FeatureWord w, uint64_t mask, |
| 2749 | const char *verbose_prefix); |
| 2750 | void mark_forced_on_features(X86CPU *cpu, FeatureWord w, uint64_t mask, |
| 2751 | const char *verbose_prefix); |
| 2752 | |
| 2753 | static inline bool x86_has_cpuid_0x1f(X86CPU *cpu) |
| 2754 | { |
| 2755 | return cpu->force_cpuid_0x1f || |
| 2756 | x86_has_extended_topo(cpu->env.avail_cpu_topo); |
| 2757 | } |
| 2758 | |
| 2759 | /* helper.c */ |
| 2760 | void x86_cpu_set_a20(X86CPU *cpu, int a20_state); |
| 2761 | void cpu_sync_avx_hflag(CPUX86State *env); |
| 2762 | |
| 2763 | typedef enum X86ASIdx { |
| 2764 | X86ASIdx_MEM = 0, |
| 2765 | X86ASIdx_SMM = 1, |
| 2766 | X86ASIdx_MAX = X86ASIdx_SMM |
| 2767 | } X86ASIdx; |
| 2768 | |
| 2769 | #ifndef CONFIG_USER_ONLY |
| 2770 | static inline int x86_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs) |
| 2771 | { |
| 2772 | return !!attrs.secure; |
| 2773 | } |
| 2774 | |
| 2775 | static inline AddressSpace *cpu_addressspace(CPUState *cs, MemTxAttrs attrs) |
| 2776 | { |
| 2777 | return cpu_get_address_space(cs, cpu_asidx_from_attrs(cs, attrs)); |
| 2778 | } |
| 2779 | |
| 2780 | /* |
| 2781 | * load efer and update the corresponding hflags. XXX: do consistency |
| 2782 | * checks with cpuid bits? |
| 2783 | */ |
| 2784 | void cpu_load_efer(CPUX86State *env, uint64_t val); |
| 2785 | uint8_t x86_ldub_phys(CPUState *cs, hwaddr addr); |
| 2786 | uint32_t x86_lduw_phys(CPUState *cs, hwaddr addr); |
| 2787 | uint32_t x86_ldl_phys(CPUState *cs, hwaddr addr); |
| 2788 | uint64_t x86_ldq_phys(CPUState *cs, hwaddr addr); |
| 2789 | void x86_stb_phys(CPUState *cs, hwaddr addr, uint8_t val); |
| 2790 | void x86_stw_phys(CPUState *cs, hwaddr addr, uint32_t val); |
| 2791 | void x86_stl_phys(CPUState *cs, hwaddr addr, uint32_t val); |
| 2792 | void x86_stq_phys(CPUState *cs, hwaddr addr, uint64_t val); |
| 2793 | #endif |
| 2794 | |
| 2795 | /* will be suppressed */ |
| 2796 | void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0); |
| 2797 | void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3); |
| 2798 | void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4); |
| 2799 | void cpu_x86_update_dr7(CPUX86State *env, uint32_t new_dr7); |
| 2800 | |
| 2801 | /* hw/pc.c */ |
| 2802 | uint64_t cpu_get_tsc(CPUX86State *env); |
| 2803 | |
| 2804 | #define CPU_RESOLVING_TYPE TYPE_X86_CPU |
| 2805 | |
| 2806 | #ifdef TARGET_X86_64 |
| 2807 | #define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu64") |
| 2808 | #else |
| 2809 | #define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu32") |
| 2810 | #endif |
| 2811 | |
| 2812 | /* MMU modes definitions */ |
| 2813 | #define MMU_KSMAP64_IDX 0 |
| 2814 | #define MMU_KSMAP32_IDX 1 |
| 2815 | #define MMU_USER64_IDX 2 |
| 2816 | #define MMU_USER32_IDX 3 |
| 2817 | #define MMU_KNOSMAP64_IDX 4 |
| 2818 | #define MMU_KNOSMAP32_IDX 5 |
| 2819 | #define MMU_PHYS_IDX 6 |
| 2820 | #define MMU_NESTED_IDX 7 |
| 2821 | |
| 2822 | #ifdef CONFIG_USER_ONLY |
| 2823 | #ifdef TARGET_X86_64 |
| 2824 | #define MMU_USER_IDX MMU_USER64_IDX |
| 2825 | #else |
| 2826 | #define MMU_USER_IDX MMU_USER32_IDX |
| 2827 | #endif |
| 2828 | #endif |
| 2829 | |
| 2830 | static inline bool is_mmu_index_smap(int mmu_index) |
| 2831 | { |
| 2832 | return (mmu_index & ~1) == MMU_KSMAP64_IDX; |
| 2833 | } |
| 2834 | |
| 2835 | static inline bool is_mmu_index_user(int mmu_index) |
| 2836 | { |
| 2837 | return (mmu_index & ~1) == MMU_USER64_IDX; |
| 2838 | } |
| 2839 | |
| 2840 | static inline bool is_mmu_index_32(int mmu_index) |
| 2841 | { |
| 2842 | assert(mmu_index < MMU_PHYS_IDX); |
| 2843 | return mmu_index & 1; |
| 2844 | } |
| 2845 | |
| 2846 | #define CC_DST (env->cc_dst) |
| 2847 | #define CC_SRC (env->cc_src) |
| 2848 | #define CC_SRC2 (env->cc_src2) |
| 2849 | #define CC_OP (env->cc_op) |
| 2850 | |
| 2851 | #include "svm.h" |
| 2852 | |
| 2853 | #if !defined(CONFIG_USER_ONLY) |
| 2854 | #include "hw/i386/apic.h" |
| 2855 | #endif |
| 2856 | |
| 2857 | void do_cpu_init(X86CPU *cpu); |
| 2858 | |
| 2859 | #define MCE_INJECT_BROADCAST 1 |
| 2860 | #define MCE_INJECT_UNCOND_AO 2 |
| 2861 | |
| 2862 | bool cpu_x86_inject_mce(X86CPU *cpu, int bank, |
| 2863 | uint64_t status, uint64_t mcg_status, uint64_t addr, |
| 2864 | uint64_t misc, int flags, Error **errp); |
| 2865 | |
| 2866 | uint32_t cpu_cc_compute_all(CPUX86State *env1); |
| 2867 | |
| 2868 | static inline uint32_t cpu_compute_eflags(CPUX86State *env) |
| 2869 | { |
| 2870 | uint32_t eflags = env->eflags; |
| 2871 | if (tcg_enabled()) { |
| 2872 | eflags |= cpu_cc_compute_all(env) | (env->df & DF_MASK); |
| 2873 | } |
| 2874 | return eflags; |
| 2875 | } |
| 2876 | |
| 2877 | static inline MemTxAttrs cpu_get_mem_attrs(CPUX86State *env) |
| 2878 | { |
| 2879 | return ((MemTxAttrs) { .secure = (env->hflags & HF_SMM_MASK) != 0 }); |
| 2880 | } |
| 2881 | |
| 2882 | static inline int32_t x86_get_a20_mask(CPUX86State *env) |
| 2883 | { |
| 2884 | if (env->hflags & HF_SMM_MASK) { |
| 2885 | return -1; |
| 2886 | } else { |
| 2887 | return env->a20_mask; |
| 2888 | } |
| 2889 | } |
| 2890 | |
| 2891 | static inline uint32_t x86_cpu_family(uint32_t eax) |
| 2892 | { |
| 2893 | uint32_t family = (eax >> 8) & 0xf; |
| 2894 | |
| 2895 | if (family == 0xf) { |
| 2896 | family += (eax >> 20) & 0xff; |
| 2897 | } |
| 2898 | |
| 2899 | return family; |
| 2900 | } |
| 2901 | |
| 2902 | static inline uint32_t x86_cpu_model(uint32_t eax) |
| 2903 | { |
| 2904 | uint32_t family, model; |
| 2905 | |
| 2906 | family = x86_cpu_family(eax); |
| 2907 | model = (eax >> 4) & 0xf; |
| 2908 | |
| 2909 | if (family >= 0x6) { |
| 2910 | model += ((eax >> 16) & 0xf) << 4; |
| 2911 | } |
| 2912 | |
| 2913 | return model; |
| 2914 | } |
| 2915 | |
| 2916 | static inline uint32_t x86_cpu_stepping(uint32_t eax) |
| 2917 | { |
| 2918 | return eax & 0xf; |
| 2919 | } |
| 2920 | |
| 2921 | static inline bool cpu_has_vmx(CPUX86State *env) |
| 2922 | { |
| 2923 | return env->features[FEAT_1_ECX] & CPUID_EXT_VMX; |
| 2924 | } |
| 2925 | |
| 2926 | static inline bool cpu_has_svm(CPUX86State *env) |
| 2927 | { |
| 2928 | return env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM; |
| 2929 | } |
| 2930 | |
| 2931 | /* |
| 2932 | * In order for a vCPU to enter VMX operation it must have CR4.VMXE set. |
| 2933 | * Since it was set, CR4.VMXE must remain set as long as vCPU is in |
| 2934 | * VMX operation. This is because CR4.VMXE is one of the bits set |
| 2935 | * in MSR_IA32_VMX_CR4_FIXED1. |
| 2936 | * |
| 2937 | * There is one exception to above statement when vCPU enters SMM mode. |
| 2938 | * When a vCPU enters SMM mode, it temporarily exit VMX operation and |
| 2939 | * may also reset CR4.VMXE during execution in SMM mode. |
| 2940 | * When vCPU exits SMM mode, vCPU state is restored to be in VMX operation |
| 2941 | * and CR4.VMXE is restored to it's original value of being set. |
| 2942 | * |
| 2943 | * Therefore, when vCPU is not in SMM mode, we can infer whether |
| 2944 | * VMX is being used by examining CR4.VMXE. Otherwise, we cannot |
| 2945 | * know for certain. |
| 2946 | */ |
| 2947 | static inline bool cpu_vmx_maybe_enabled(CPUX86State *env) |
| 2948 | { |
| 2949 | return cpu_has_vmx(env) && |
| 2950 | ((env->cr[4] & CR4_VMXE_MASK) || (env->hflags & HF_SMM_MASK)); |
| 2951 | } |
| 2952 | |
| 2953 | /* excp_helper.c */ |
| 2954 | int get_pg_mode(CPUX86State *env); |
| 2955 | |
| 2956 | /* fpu_helper.c */ |
| 2957 | |
| 2958 | /* Set all non-runtime-variable float_status fields to x86 handling */ |
| 2959 | void cpu_init_fp_statuses(CPUX86State *env); |
| 2960 | void update_fp_status(CPUX86State *env); |
| 2961 | void update_mxcsr_status(CPUX86State *env); |
| 2962 | void update_mxcsr_from_sse_status(CPUX86State *env); |
| 2963 | |
| 2964 | static inline void cpu_set_mxcsr(CPUX86State *env, uint32_t mxcsr) |
| 2965 | { |
| 2966 | env->mxcsr = mxcsr; |
| 2967 | if (tcg_enabled()) { |
| 2968 | update_mxcsr_status(env); |
| 2969 | } |
| 2970 | } |
| 2971 | |
| 2972 | static inline void cpu_set_fpuc(CPUX86State *env, uint16_t fpuc) |
| 2973 | { |
| 2974 | env->fpuc = fpuc; |
| 2975 | if (tcg_enabled()) { |
| 2976 | update_fp_status(env); |
| 2977 | } |
| 2978 | } |
| 2979 | |
| 2980 | /* svm_helper.c */ |
| 2981 | #ifdef CONFIG_USER_ONLY |
| 2982 | static inline void |
| 2983 | cpu_svm_check_intercept_param(CPUX86State *env1, uint32_t type, |
| 2984 | uint64_t param, uintptr_t retaddr) |
| 2985 | { /* no-op */ } |
| 2986 | static inline bool |
| 2987 | cpu_svm_has_intercept(CPUX86State *env, uint32_t type) |
| 2988 | { return false; } |
| 2989 | #else |
| 2990 | void cpu_svm_check_intercept_param(CPUX86State *env1, uint32_t type, |
| 2991 | uint64_t param, uintptr_t retaddr); |
| 2992 | bool cpu_svm_has_intercept(CPUX86State *env, uint32_t type); |
| 2993 | #endif |
| 2994 | |
| 2995 | /* apic.c */ |
| 2996 | void cpu_report_tpr_access(CPUX86State *env, TPRAccess access); |
| 2997 | void apic_handle_tpr_access_report(APICCommonState *s, target_ulong ip, |
| 2998 | TPRAccess access); |
| 2999 | |
| 3000 | /* Special values for X86CPUVersion: */ |
| 3001 | |
| 3002 | /* Resolve to latest CPU version */ |
| 3003 | #define CPU_VERSION_LATEST -1 |
| 3004 | |
| 3005 | /* |
| 3006 | * Resolve to version defined by current machine type. |
| 3007 | * See x86_cpu_set_default_version() |
| 3008 | */ |
| 3009 | #define CPU_VERSION_AUTO -2 |
| 3010 | |
| 3011 | /* Don't resolve to any versioned CPU models, like old QEMU versions */ |
| 3012 | #define CPU_VERSION_LEGACY 0 |
| 3013 | |
| 3014 | typedef int X86CPUVersion; |
| 3015 | |
| 3016 | /* |
| 3017 | * Set default CPU model version for CPU models having |
| 3018 | * version == CPU_VERSION_AUTO. |
| 3019 | */ |
| 3020 | void x86_cpu_set_default_version(X86CPUVersion version); |
| 3021 | |
| 3022 | #ifndef CONFIG_USER_ONLY |
| 3023 | |
| 3024 | void do_cpu_sipi(X86CPU *cpu); |
| 3025 | |
| 3026 | #define APIC_DEFAULT_ADDRESS 0xfee00000 |
| 3027 | #define APIC_SPACE_SIZE 0x100000 |
| 3028 | |
| 3029 | /* cpu-dump.c */ |
| 3030 | void x86_cpu_dump_local_apic_state(CPUState *cs, int flags); |
| 3031 | |
| 3032 | #endif |
| 3033 | |
| 3034 | /* igvm.c */ |
| 3035 | void qigvm_x86_bsp_reset(CPUX86State *env); |
| 3036 | |
| 3037 | /* cpu.c */ |
| 3038 | bool cpu_is_bsp(X86CPU *cpu); |
| 3039 | |
| 3040 | void x86_cpu_xrstor_all_areas(X86CPU *cpu, const void *buf, uint32_t buflen); |
| 3041 | void x86_cpu_xsave_all_areas(X86CPU *cpu, void *buf, uint32_t buflen); |
| 3042 | uint32_t xsave_area_size(uint64_t mask, bool compacted); |
| 3043 | void x86_update_hflags(CPUX86State* env); |
| 3044 | int decompact_xsave_area(const void *buf, size_t buflen, CPUX86State *env); |
| 3045 | int compact_xsave_area(CPUX86State *env, void *buf, size_t buflen); |
| 3046 | |
| 3047 | static inline bool hyperv_feat_enabled(X86CPU *cpu, int feat) |
| 3048 | { |
| 3049 | return !!(cpu->hyperv_features & BIT(feat)); |
| 3050 | } |
| 3051 | |
| 3052 | static inline uint64_t cr4_reserved_bits(CPUX86State *env) |
| 3053 | { |
| 3054 | uint64_t reserved_bits = CR4_RESERVED_MASK; |
| 3055 | if (!env->features[FEAT_XSAVE]) { |
| 3056 | reserved_bits |= CR4_OSXSAVE_MASK; |
| 3057 | } |
| 3058 | if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SMEP)) { |
| 3059 | reserved_bits |= CR4_SMEP_MASK; |
| 3060 | } |
| 3061 | if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SMAP)) { |
| 3062 | reserved_bits |= CR4_SMAP_MASK; |
| 3063 | } |
| 3064 | if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE)) { |
| 3065 | reserved_bits |= CR4_FSGSBASE_MASK; |
| 3066 | } |
| 3067 | if (!(env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_PKU)) { |
| 3068 | reserved_bits |= CR4_PKE_MASK; |
| 3069 | } |
| 3070 | if (!(env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_LA57)) { |
| 3071 | reserved_bits |= CR4_LA57_MASK; |
| 3072 | } |
| 3073 | if (!(env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_UMIP)) { |
| 3074 | reserved_bits |= CR4_UMIP_MASK; |
| 3075 | } |
| 3076 | if (!(env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_PKS)) { |
| 3077 | reserved_bits |= CR4_PKS_MASK; |
| 3078 | } |
| 3079 | if (!(env->features[FEAT_7_1_EAX] & CPUID_7_1_EAX_LAM)) { |
| 3080 | reserved_bits |= CR4_LAM_SUP_MASK; |
| 3081 | } |
| 3082 | if (!(env->features[FEAT_7_1_EAX] & CPUID_7_1_EAX_FRED)) { |
| 3083 | reserved_bits |= CR4_FRED_MASK; |
| 3084 | } |
| 3085 | if (!(env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_CET_SHSTK) && |
| 3086 | !(env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_CET_IBT)) { |
| 3087 | reserved_bits |= CR4_CET_MASK; |
| 3088 | } |
| 3089 | return reserved_bits; |
| 3090 | } |
| 3091 | |
| 3092 | static inline bool ctl_has_irq(CPUX86State *env) |
| 3093 | { |
| 3094 | uint32_t int_prio; |
| 3095 | uint32_t tpr; |
| 3096 | |
| 3097 | int_prio = (env->int_ctl & V_INTR_PRIO_MASK) >> V_INTR_PRIO_SHIFT; |
| 3098 | tpr = env->int_ctl & V_TPR_MASK; |
| 3099 | |
| 3100 | if (env->int_ctl & V_IGN_TPR_MASK) { |
| 3101 | return (env->int_ctl & V_IRQ_MASK); |
| 3102 | } |
| 3103 | |
| 3104 | return (env->int_ctl & V_IRQ_MASK) && (int_prio >= tpr); |
| 3105 | } |
| 3106 | |
| 3107 | static inline bool x86_cpu_interrupts_enabled(CPUX86State *env) |
| 3108 | { |
| 3109 | return ((env->eflags & IF_MASK) && |
| 3110 | !(env->hflags & HF_INHIBIT_IRQ_MASK)) || |
| 3111 | (env->hflags2 & HF2_HYPERV_HLT_MASK); |
| 3112 | } |
| 3113 | |
| 3114 | #if defined(TARGET_X86_64) && \ |
| 3115 | defined(CONFIG_USER_ONLY) && \ |
| 3116 | defined(CONFIG_LINUX) |
| 3117 | # define TARGET_VSYSCALL_PAGE (UINT64_C(-10) << 20) |
| 3118 | #endif |
| 3119 | |
| 3120 | /* majority(NOT a, b, c) = (a ^ b) ? b : c */ |
| 3121 | #define MAJ_INV1(a, b, c) ((((a) ^ (b)) & ((b) ^ (c))) ^ (c)) |
| 3122 | |
| 3123 | /* |
| 3124 | * ADD_COUT_VEC(x, y) = majority((x + y) ^ x ^ y, x, y) |
| 3125 | * |
| 3126 | * If two corresponding bits in x and y are the same, that's the carry |
| 3127 | * independent of the value (x+y)^x^y. Hence x^y can be replaced with |
| 3128 | * 1 in (x+y)^x^y, resulting in majority(NOT (x+y), x, y) |
| 3129 | */ |
| 3130 | #define ADD_COUT_VEC(op1, op2, result) \ |
| 3131 | MAJ_INV1(result, op1, op2) |
| 3132 | |
| 3133 | /* |
| 3134 | * SUB_COUT_VEC(x, y) = NOT majority(x, NOT y, (x - y) ^ x ^ NOT y) |
| 3135 | * = majority(NOT x, y, (x - y) ^ x ^ y) |
| 3136 | * |
| 3137 | * Note that the carry out is actually a borrow, i.e. it is inverted. |
| 3138 | * If two corresponding bits in x and y are different, the value of the |
| 3139 | * bit in (x-y)^x^y likewise does not matter. Hence, x^y can be replaced |
| 3140 | * with 0 in (x-y)^x^y, resulting in majority(NOT x, y, x-y) |
| 3141 | */ |
| 3142 | #define SUB_COUT_VEC(op1, op2, result) \ |
| 3143 | MAJ_INV1(op1, op2, result) |
| 3144 | |
| 3145 | #endif /* I386_CPU_H */ |