| 1 | /* |
| 2 | * x86 gdb server stub |
| 3 | * |
| 4 | * Copyright (c) 2003-2005 Fabrice Bellard |
| 5 | * Copyright (c) 2013 SUSE LINUX Products GmbH |
| 6 | * |
| 7 | * This library is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU Lesser General Public |
| 9 | * License as published by the Free Software Foundation; either |
| 10 | * version 2.1 of the License, or (at your option) any later version. |
| 11 | * |
| 12 | * This library is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 15 | * Lesser General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU Lesser General Public |
| 18 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
| 19 | */ |
| 20 | #include "qemu/osdep.h" |
| 21 | #include "accel/tcg/vcpu-state.h" |
| 22 | #include "cpu.h" |
| 23 | #include "exec/gdbstub.h" |
| 24 | #include "gdbstub/helpers.h" |
| 25 | #ifdef CONFIG_LINUX_USER |
| 26 | #include "linux-user/qemu.h" |
| 27 | #endif |
| 28 | |
| 29 | #ifdef TARGET_X86_64 |
| 30 | static const int gpr_map[CPU_NB_EREGS] = { |
| 31 | R_EAX, R_EBX, R_ECX, R_EDX, R_ESI, R_EDI, R_EBP, R_ESP, |
| 32 | R_R8, R_R9, R_R10, R_R11, R_R12, R_R13, R_R14, R_R15, |
| 33 | R_R16, R_R17, R_R18, R_R19, R_R20, R_R21, R_R22, R_R23, |
| 34 | R_R24, R_R25, R_R26, R_R27, R_R28, R_R29, R_R30, R_R31, |
| 35 | }; |
| 36 | #else |
| 37 | #define gpr_map gpr_map32 |
| 38 | #endif |
| 39 | static const int gpr_map32[8] = { 0, 1, 2, 3, 4, 5, 6, 7 }; |
| 40 | |
| 41 | /* |
| 42 | * Keep these in sync with the machine description |
| 43 | */ |
| 44 | |
| 45 | /* |
| 46 | * SEG: 6 segments, plus fs_base, gs_base, kernel_gs_base |
| 47 | */ |
| 48 | |
| 49 | /* |
| 50 | * general regs -----> 8 or 16 |
| 51 | */ |
| 52 | #define IDX_NB_IP 1 |
| 53 | #define IDX_NB_FLAGS 1 |
| 54 | #define IDX_NB_SEG (6 + 3) |
| 55 | #define IDX_NB_CTL 6 |
| 56 | #define IDX_NB_FP 16 |
| 57 | /* |
| 58 | * fpu regs ----------> 8 or 16 |
| 59 | */ |
| 60 | #define IDX_NB_MXCSR 1 |
| 61 | /* |
| 62 | * total ----> 8+1+1+9+6+16+8+1=50 or 16+1+1+9+6+16+16+1=66 |
| 63 | */ |
| 64 | |
| 65 | #define IDX_IP_REG CPU_NB_REGS |
| 66 | #define IDX_FLAGS_REG (IDX_IP_REG + IDX_NB_IP) |
| 67 | #define IDX_SEG_REGS (IDX_FLAGS_REG + IDX_NB_FLAGS) |
| 68 | #define IDX_CTL_REGS (IDX_SEG_REGS + IDX_NB_SEG) |
| 69 | #define IDX_FP_REGS (IDX_CTL_REGS + IDX_NB_CTL) |
| 70 | #define IDX_XMM_REGS (IDX_FP_REGS + IDX_NB_FP) |
| 71 | #define IDX_MXCSR_REG (IDX_XMM_REGS + CPU_NB_REGS) |
| 72 | |
| 73 | #define IDX_CTL_CR0_REG (IDX_CTL_REGS + 0) |
| 74 | #define IDX_CTL_CR2_REG (IDX_CTL_REGS + 1) |
| 75 | #define IDX_CTL_CR3_REG (IDX_CTL_REGS + 2) |
| 76 | #define IDX_CTL_CR4_REG (IDX_CTL_REGS + 3) |
| 77 | #define IDX_CTL_CR8_REG (IDX_CTL_REGS + 4) |
| 78 | #define IDX_CTL_EFER_REG (IDX_CTL_REGS + 5) |
| 79 | |
| 80 | static int gdb_read_reg_cs64(uint32_t hflags, GByteArray *buf, target_ulong val) |
| 81 | { |
| 82 | if ((hflags & HF_CS64_MASK) || TARGET_LONG_BITS == 64) { |
| 83 | return gdb_get_reg64(buf, val); |
| 84 | } |
| 85 | return gdb_get_reg32(buf, val); |
| 86 | } |
| 87 | |
| 88 | static int gdb_write_reg_cs64(uint32_t hflags, uint8_t *buf, target_ulong *val) |
| 89 | { |
| 90 | if (hflags & HF_CS64_MASK) { |
| 91 | *val = ldq_p(buf); |
| 92 | return 8; |
| 93 | } |
| 94 | *val = ldl_p(buf); |
| 95 | return 4; |
| 96 | } |
| 97 | |
| 98 | static int gdb_get_reg(CPUX86State *env, GByteArray *mem_buf, target_ulong val) |
| 99 | { |
| 100 | if (TARGET_LONG_BITS == 64) { |
| 101 | if (env->hflags & HF_CS64_MASK) { |
| 102 | return gdb_get_reg64(mem_buf, val); |
| 103 | } else { |
| 104 | return gdb_get_reg64(mem_buf, val & 0xffffffffUL); |
| 105 | } |
| 106 | } else { |
| 107 | return gdb_get_reg32(mem_buf, val); |
| 108 | } |
| 109 | } |
| 110 | |
| 111 | int x86_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) |
| 112 | { |
| 113 | X86CPU *cpu = X86_CPU(cs); |
| 114 | CPUX86State *env = &cpu->env; |
| 115 | |
| 116 | uint64_t tpr; |
| 117 | |
| 118 | /* N.B. GDB can't deal with changes in registers or sizes in the middle |
| 119 | of a session. So if we're in 32-bit mode on a 64-bit cpu, still act |
| 120 | as if we're on a 64-bit cpu. */ |
| 121 | |
| 122 | if (n < CPU_NB_REGS) { |
| 123 | if (TARGET_LONG_BITS == 64) { |
| 124 | if (env->hflags & HF_CS64_MASK) { |
| 125 | return gdb_get_reg64(mem_buf, env->regs[gpr_map[n]]); |
| 126 | } else if (n < CPU_NB_REGS32) { |
| 127 | return gdb_get_reg64(mem_buf, |
| 128 | env->regs[gpr_map[n]] & 0xffffffffUL); |
| 129 | } else { |
| 130 | return gdb_get_reg64(mem_buf, 0); |
| 131 | } |
| 132 | } else { |
| 133 | return gdb_get_reg32(mem_buf, env->regs[gpr_map32[n]]); |
| 134 | } |
| 135 | } else if (n >= IDX_FP_REGS && n < IDX_FP_REGS + 8) { |
| 136 | int st_index = n - IDX_FP_REGS; |
| 137 | int r_index = (st_index + env->fpstt) % 8; |
| 138 | floatx80 *fp = &env->fpregs[r_index].d; |
| 139 | int len = gdb_get_reg64(mem_buf, cpu_to_le64(fp->low)); |
| 140 | len += gdb_get_reg16(mem_buf, cpu_to_le16(fp->high)); |
| 141 | return len; |
| 142 | } else if (n >= IDX_XMM_REGS && n < IDX_XMM_REGS + CPU_NB_REGS) { |
| 143 | n -= IDX_XMM_REGS; |
| 144 | if (n < CPU_NB_REGS32 || TARGET_LONG_BITS == 64) { |
| 145 | return gdb_get_reg128(mem_buf, |
| 146 | env->xmm_regs[n].ZMM_Q(1), |
| 147 | env->xmm_regs[n].ZMM_Q(0)); |
| 148 | } |
| 149 | } else { |
| 150 | switch (n) { |
| 151 | case IDX_IP_REG: |
| 152 | return gdb_get_reg(env, mem_buf, env->eip); |
| 153 | case IDX_FLAGS_REG: |
| 154 | return gdb_get_reg32(mem_buf, env->eflags); |
| 155 | |
| 156 | case IDX_SEG_REGS: |
| 157 | return gdb_get_reg32(mem_buf, env->segs[R_CS].selector); |
| 158 | case IDX_SEG_REGS + 1: |
| 159 | return gdb_get_reg32(mem_buf, env->segs[R_SS].selector); |
| 160 | case IDX_SEG_REGS + 2: |
| 161 | return gdb_get_reg32(mem_buf, env->segs[R_DS].selector); |
| 162 | case IDX_SEG_REGS + 3: |
| 163 | return gdb_get_reg32(mem_buf, env->segs[R_ES].selector); |
| 164 | case IDX_SEG_REGS + 4: |
| 165 | return gdb_get_reg32(mem_buf, env->segs[R_FS].selector); |
| 166 | case IDX_SEG_REGS + 5: |
| 167 | return gdb_get_reg32(mem_buf, env->segs[R_GS].selector); |
| 168 | case IDX_SEG_REGS + 6: |
| 169 | return gdb_read_reg_cs64(env->hflags, mem_buf, env->segs[R_FS].base); |
| 170 | case IDX_SEG_REGS + 7: |
| 171 | return gdb_read_reg_cs64(env->hflags, mem_buf, env->segs[R_GS].base); |
| 172 | |
| 173 | case IDX_SEG_REGS + 8: |
| 174 | #ifdef TARGET_X86_64 |
| 175 | return gdb_read_reg_cs64(env->hflags, mem_buf, env->kernelgsbase); |
| 176 | #else |
| 177 | return gdb_get_reg32(mem_buf, 0); |
| 178 | #endif |
| 179 | |
| 180 | case IDX_FP_REGS + 8: |
| 181 | return gdb_get_reg32(mem_buf, env->fpuc); |
| 182 | case IDX_FP_REGS + 9: |
| 183 | return gdb_get_reg32(mem_buf, (env->fpus & ~0x3800) | |
| 184 | (env->fpstt & 0x7) << 11); |
| 185 | case IDX_FP_REGS + 10: |
| 186 | return gdb_get_reg32(mem_buf, 0); /* ftag */ |
| 187 | case IDX_FP_REGS + 11: |
| 188 | return gdb_get_reg32(mem_buf, 0); /* fiseg */ |
| 189 | case IDX_FP_REGS + 12: |
| 190 | return gdb_get_reg32(mem_buf, 0); /* fioff */ |
| 191 | case IDX_FP_REGS + 13: |
| 192 | return gdb_get_reg32(mem_buf, 0); /* foseg */ |
| 193 | case IDX_FP_REGS + 14: |
| 194 | return gdb_get_reg32(mem_buf, 0); /* fooff */ |
| 195 | case IDX_FP_REGS + 15: |
| 196 | return gdb_get_reg32(mem_buf, 0); /* fop */ |
| 197 | |
| 198 | case IDX_MXCSR_REG: |
| 199 | update_mxcsr_from_sse_status(env); |
| 200 | return gdb_get_reg32(mem_buf, env->mxcsr); |
| 201 | |
| 202 | case IDX_CTL_CR0_REG: |
| 203 | return gdb_read_reg_cs64(env->hflags, mem_buf, env->cr[0]); |
| 204 | case IDX_CTL_CR2_REG: |
| 205 | return gdb_read_reg_cs64(env->hflags, mem_buf, env->cr[2]); |
| 206 | case IDX_CTL_CR3_REG: |
| 207 | return gdb_read_reg_cs64(env->hflags, mem_buf, env->cr[3]); |
| 208 | case IDX_CTL_CR4_REG: |
| 209 | return gdb_read_reg_cs64(env->hflags, mem_buf, env->cr[4]); |
| 210 | case IDX_CTL_CR8_REG: |
| 211 | #ifndef CONFIG_USER_ONLY |
| 212 | tpr = cpu_get_apic_tpr(cpu->apic_state); |
| 213 | #else |
| 214 | tpr = 0; |
| 215 | #endif |
| 216 | return gdb_read_reg_cs64(env->hflags, mem_buf, tpr); |
| 217 | |
| 218 | case IDX_CTL_EFER_REG: |
| 219 | return gdb_read_reg_cs64(env->hflags, mem_buf, env->efer); |
| 220 | } |
| 221 | } |
| 222 | return 0; |
| 223 | } |
| 224 | |
| 225 | static int x86_cpu_gdb_load_seg(X86CPU *cpu, X86Seg sreg, uint8_t *mem_buf) |
| 226 | { |
| 227 | CPUX86State *env = &cpu->env; |
| 228 | uint16_t selector = ldl_p(mem_buf); |
| 229 | |
| 230 | if (selector != env->segs[sreg].selector) { |
| 231 | #if defined(CONFIG_USER_ONLY) |
| 232 | cpu_x86_load_seg(env, sreg, selector); |
| 233 | #else |
| 234 | unsigned int limit, flags; |
| 235 | target_ulong base; |
| 236 | |
| 237 | if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) { |
| 238 | int dpl = (env->eflags & VM_MASK) ? 3 : 0; |
| 239 | base = selector << 4; |
| 240 | limit = 0xffff; |
| 241 | flags = DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | |
| 242 | DESC_A_MASK | (dpl << DESC_DPL_SHIFT); |
| 243 | } else { |
| 244 | if (!cpu_x86_get_descr_debug(env, selector, &base, &limit, |
| 245 | &flags)) { |
| 246 | return 4; |
| 247 | } |
| 248 | } |
| 249 | cpu_x86_load_seg_cache(env, sreg, selector, base, limit, flags); |
| 250 | #endif |
| 251 | } |
| 252 | return 4; |
| 253 | } |
| 254 | |
| 255 | static int gdb_write_reg(CPUX86State *env, uint8_t *mem_buf, target_ulong *val) |
| 256 | { |
| 257 | if (TARGET_LONG_BITS == 64) { |
| 258 | if (env->hflags & HF_CS64_MASK) { |
| 259 | *val = ldq_p(mem_buf); |
| 260 | } else { |
| 261 | *val = ldq_p(mem_buf) & 0xffffffffUL; |
| 262 | } |
| 263 | return 8; |
| 264 | } else { |
| 265 | *val = (uint32_t)ldl_p(mem_buf); |
| 266 | return 4; |
| 267 | } |
| 268 | } |
| 269 | |
| 270 | int x86_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) |
| 271 | { |
| 272 | X86CPU *cpu = X86_CPU(cs); |
| 273 | CPUX86State *env = &cpu->env; |
| 274 | target_ulong tmp; |
| 275 | int len; |
| 276 | |
| 277 | /* N.B. GDB can't deal with changes in registers or sizes in the middle |
| 278 | of a session. So if we're in 32-bit mode on a 64-bit cpu, still act |
| 279 | as if we're on a 64-bit cpu. */ |
| 280 | |
| 281 | if (n < CPU_NB_REGS) { |
| 282 | if (TARGET_LONG_BITS == 64) { |
| 283 | if (env->hflags & HF_CS64_MASK) { |
| 284 | env->regs[gpr_map[n]] = ldq_p(mem_buf); |
| 285 | } else if (n < CPU_NB_REGS32) { |
| 286 | env->regs[gpr_map[n]] = ldq_p(mem_buf) & 0xffffffffUL; |
| 287 | } |
| 288 | return sizeof(target_ulong); |
| 289 | } else if (n < CPU_NB_REGS32) { |
| 290 | n = gpr_map32[n]; |
| 291 | env->regs[n] &= ~0xffffffffUL; |
| 292 | env->regs[n] |= (uint32_t)ldl_p(mem_buf); |
| 293 | return 4; |
| 294 | } |
| 295 | } else if (n >= IDX_FP_REGS && n < IDX_FP_REGS + 8) { |
| 296 | floatx80 *fp = (floatx80 *) &env->fpregs[n - IDX_FP_REGS]; |
| 297 | fp->low = le64_to_cpu(* (uint64_t *) mem_buf); |
| 298 | fp->high = le16_to_cpu(* (uint16_t *) (mem_buf + 8)); |
| 299 | return 10; |
| 300 | } else if (n >= IDX_XMM_REGS && n < IDX_XMM_REGS + CPU_NB_REGS) { |
| 301 | n -= IDX_XMM_REGS; |
| 302 | if (n < CPU_NB_REGS32 || TARGET_LONG_BITS == 64) { |
| 303 | env->xmm_regs[n].ZMM_Q(0) = ldq_p(mem_buf); |
| 304 | env->xmm_regs[n].ZMM_Q(1) = ldq_p(mem_buf + 8); |
| 305 | return 16; |
| 306 | } |
| 307 | } else { |
| 308 | switch (n) { |
| 309 | case IDX_IP_REG: |
| 310 | return gdb_write_reg(env, mem_buf, &env->eip); |
| 311 | case IDX_FLAGS_REG: |
| 312 | env->eflags = ldl_p(mem_buf); |
| 313 | return 4; |
| 314 | |
| 315 | case IDX_SEG_REGS: |
| 316 | return x86_cpu_gdb_load_seg(cpu, R_CS, mem_buf); |
| 317 | case IDX_SEG_REGS + 1: |
| 318 | return x86_cpu_gdb_load_seg(cpu, R_SS, mem_buf); |
| 319 | case IDX_SEG_REGS + 2: |
| 320 | return x86_cpu_gdb_load_seg(cpu, R_DS, mem_buf); |
| 321 | case IDX_SEG_REGS + 3: |
| 322 | return x86_cpu_gdb_load_seg(cpu, R_ES, mem_buf); |
| 323 | case IDX_SEG_REGS + 4: |
| 324 | return x86_cpu_gdb_load_seg(cpu, R_FS, mem_buf); |
| 325 | case IDX_SEG_REGS + 5: |
| 326 | return x86_cpu_gdb_load_seg(cpu, R_GS, mem_buf); |
| 327 | case IDX_SEG_REGS + 6: |
| 328 | return gdb_write_reg_cs64(env->hflags, mem_buf, &env->segs[R_FS].base); |
| 329 | case IDX_SEG_REGS + 7: |
| 330 | return gdb_write_reg_cs64(env->hflags, mem_buf, &env->segs[R_GS].base); |
| 331 | case IDX_SEG_REGS + 8: |
| 332 | #ifdef TARGET_X86_64 |
| 333 | return gdb_write_reg_cs64(env->hflags, mem_buf, &env->kernelgsbase); |
| 334 | #endif |
| 335 | return 4; |
| 336 | |
| 337 | case IDX_FP_REGS + 8: |
| 338 | cpu_set_fpuc(env, ldl_p(mem_buf)); |
| 339 | return 4; |
| 340 | case IDX_FP_REGS + 9: |
| 341 | tmp = ldl_p(mem_buf); |
| 342 | env->fpstt = (tmp >> 11) & 7; |
| 343 | env->fpus = tmp & ~0x3800; |
| 344 | return 4; |
| 345 | case IDX_FP_REGS + 10: /* ftag */ |
| 346 | return 4; |
| 347 | case IDX_FP_REGS + 11: /* fiseg */ |
| 348 | return 4; |
| 349 | case IDX_FP_REGS + 12: /* fioff */ |
| 350 | return 4; |
| 351 | case IDX_FP_REGS + 13: /* foseg */ |
| 352 | return 4; |
| 353 | case IDX_FP_REGS + 14: /* fooff */ |
| 354 | return 4; |
| 355 | case IDX_FP_REGS + 15: /* fop */ |
| 356 | return 4; |
| 357 | |
| 358 | case IDX_MXCSR_REG: |
| 359 | cpu_set_mxcsr(env, ldl_p(mem_buf)); |
| 360 | return 4; |
| 361 | |
| 362 | case IDX_CTL_CR0_REG: |
| 363 | len = gdb_write_reg_cs64(env->hflags, mem_buf, &tmp); |
| 364 | #ifndef CONFIG_USER_ONLY |
| 365 | cpu_x86_update_cr0(env, tmp); |
| 366 | #endif |
| 367 | return len; |
| 368 | |
| 369 | case IDX_CTL_CR2_REG: |
| 370 | len = gdb_write_reg_cs64(env->hflags, mem_buf, &tmp); |
| 371 | #ifndef CONFIG_USER_ONLY |
| 372 | env->cr[2] = tmp; |
| 373 | #endif |
| 374 | return len; |
| 375 | |
| 376 | case IDX_CTL_CR3_REG: |
| 377 | len = gdb_write_reg_cs64(env->hflags, mem_buf, &tmp); |
| 378 | #ifndef CONFIG_USER_ONLY |
| 379 | cpu_x86_update_cr3(env, tmp); |
| 380 | #endif |
| 381 | return len; |
| 382 | |
| 383 | case IDX_CTL_CR4_REG: |
| 384 | len = gdb_write_reg_cs64(env->hflags, mem_buf, &tmp); |
| 385 | #ifndef CONFIG_USER_ONLY |
| 386 | cpu_x86_update_cr4(env, tmp); |
| 387 | #endif |
| 388 | return len; |
| 389 | |
| 390 | case IDX_CTL_CR8_REG: |
| 391 | len = gdb_write_reg_cs64(env->hflags, mem_buf, &tmp); |
| 392 | #ifndef CONFIG_USER_ONLY |
| 393 | cpu_set_apic_tpr(cpu->apic_state, tmp); |
| 394 | #endif |
| 395 | return len; |
| 396 | |
| 397 | case IDX_CTL_EFER_REG: |
| 398 | len = gdb_write_reg_cs64(env->hflags, mem_buf, &tmp); |
| 399 | #ifndef CONFIG_USER_ONLY |
| 400 | cpu_load_efer(env, tmp); |
| 401 | #endif |
| 402 | return len; |
| 403 | } |
| 404 | } |
| 405 | /* Unrecognised register. */ |
| 406 | return 0; |
| 407 | } |
| 408 | |
| 409 | #ifdef CONFIG_LINUX_USER |
| 410 | |
| 411 | #define IDX_ORIG_AX 0 |
| 412 | |
| 413 | static int x86_cpu_gdb_read_linux_register(CPUState *cs, GByteArray *mem_buf, |
| 414 | int n) |
| 415 | { |
| 416 | X86CPU *cpu = X86_CPU(cs); |
| 417 | CPUX86State *env = &cpu->env; |
| 418 | |
| 419 | switch (n) { |
| 420 | case IDX_ORIG_AX: |
| 421 | return gdb_get_reg(env, mem_buf, get_task_state(cs)->orig_ax); |
| 422 | } |
| 423 | return 0; |
| 424 | } |
| 425 | |
| 426 | static int x86_cpu_gdb_write_linux_register(CPUState *cs, uint8_t *mem_buf, |
| 427 | int n) |
| 428 | { |
| 429 | X86CPU *cpu = X86_CPU(cs); |
| 430 | CPUX86State *env = &cpu->env; |
| 431 | |
| 432 | switch (n) { |
| 433 | case IDX_ORIG_AX: |
| 434 | return gdb_write_reg(env, mem_buf, &get_task_state(cs)->orig_ax); |
| 435 | } |
| 436 | return 0; |
| 437 | } |
| 438 | |
| 439 | #endif |
| 440 | |
| 441 | #ifdef TARGET_X86_64 |
| 442 | static int i386_cpu_gdb_get_egprs(CPUState *cs, GByteArray *mem_buf, int n) |
| 443 | { |
| 444 | CPUX86State *env = &X86_CPU(cs)->env; |
| 445 | |
| 446 | if (n >= 0 && n < EGPR_NUM) { |
| 447 | /* EGPRs can be only directly accessible in 64-bit mode. */ |
| 448 | if (env->hflags & HF_CS64_MASK) { |
| 449 | return gdb_get_reg64(mem_buf, env->regs[gpr_map[n + CPU_NB_REGS]]); |
| 450 | } else if (TARGET_LONG_BITS == 64) { |
| 451 | return gdb_get_reg64(mem_buf, 0); |
| 452 | } else { |
| 453 | return gdb_get_reg32(mem_buf, 0); |
| 454 | } |
| 455 | } |
| 456 | |
| 457 | return 0; |
| 458 | } |
| 459 | |
| 460 | static int i386_cpu_gdb_set_egprs(CPUState *cs, uint8_t *mem_buf, int n) |
| 461 | { |
| 462 | const unsigned regsz = target_long_bits() / 8; |
| 463 | CPUX86State *env = &X86_CPU(cs)->env; |
| 464 | |
| 465 | if (n >= 0 && n < EGPR_NUM) { |
| 466 | /* |
| 467 | * EGPRs can be only directly accessible in 64-bit mode, and require |
| 468 | * XCR0[APX_F] (at least for modification in gdbstub) to be enabled. |
| 469 | */ |
| 470 | if (env->hflags & HF_CS64_MASK && env->xcr0 & XSTATE_APX_MASK) { |
| 471 | env->regs[gpr_map[n + CPU_NB_REGS]] = ldn_p(mem_buf, regsz); |
| 472 | |
| 473 | /* |
| 474 | * Per SDM Vol 1, "Processor Tracking of XSAVE-Managed State", |
| 475 | * XSTATE_BV[i] *may* be either 0 or 1 if the state component is |
| 476 | * in its initial configuration. |
| 477 | * |
| 478 | * However, it is observed on Diamond Rapids (DMR) that |
| 479 | * XSTATE_BV[APX_F] is set whenever EGPRs are modified, regardless |
| 480 | * of the value written (even if zero). |
| 481 | * |
| 482 | * Since GDB modifies the software register cache directly, |
| 483 | * manually force the bit set to emulate this behavior observed |
| 484 | * on hardware. |
| 485 | */ |
| 486 | if (!(env->xstate_bv & XSTATE_APX_MASK)) { |
| 487 | env->xstate_bv |= XSTATE_APX_MASK; |
| 488 | } |
| 489 | } |
| 490 | return regsz; |
| 491 | } |
| 492 | return 0; |
| 493 | } |
| 494 | #endif |
| 495 | |
| 496 | void x86_cpu_gdb_init(CPUState *cs) |
| 497 | { |
| 498 | #ifdef TARGET_X86_64 |
| 499 | CPUX86State *env = &X86_CPU(cs)->env; |
| 500 | |
| 501 | if (env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_APXF) { |
| 502 | gdb_register_coprocessor(cs, i386_cpu_gdb_get_egprs, |
| 503 | i386_cpu_gdb_set_egprs, |
| 504 | gdb_find_static_feature("i386-64bit-apx.xml")); |
| 505 | } |
| 506 | #endif |
| 507 | |
| 508 | #ifdef CONFIG_LINUX_USER |
| 509 | gdb_register_coprocessor(cs, x86_cpu_gdb_read_linux_register, |
| 510 | x86_cpu_gdb_write_linux_register, |
| 511 | #ifdef TARGET_X86_64 |
| 512 | gdb_find_static_feature("i386-64bit-linux.xml")); |
| 513 | #else |
| 514 | gdb_find_static_feature("i386-32bit-linux.xml")); |
| 515 | #endif |
| 516 | #endif |
| 517 | } |