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1 /*
2 * i386 helpers (without register variable usage)
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "qapi/error.h"
22 #include "qapi/qapi-events-run-state.h"
23 #include "cpu.h"
24 #include "exec/cputlb.h"
25 #include "exec/translation-block.h"
26 #include "exec/target_page.h"
27 #include "system/runstate.h"
28 #ifndef CONFIG_USER_ONLY
29 #include "system/hw_accel.h"
30 #include "system/memory.h"
31 #include "kvm/kvm_i386.h"
32 #endif
33 #include "qemu/log.h"
34 #ifdef CONFIG_TCG
35 #include "accel/tcg/cpu-loop.h"
36 #include "tcg/insn-start-words.h"
37 #endif
38
39 void cpu_sync_avx_hflag(CPUX86State *env)
40 {
41 if ((env->cr[4] & CR4_OSXSAVE_MASK)
42 && (env->xcr0 & (XSTATE_SSE_MASK | XSTATE_YMM_MASK))
43 == (XSTATE_SSE_MASK | XSTATE_YMM_MASK)) {
44 env->hflags |= HF_AVX_EN_MASK;
45 } else{
46 env->hflags &= ~HF_AVX_EN_MASK;
47 }
48 }
49
50 void cpu_sync_bndcs_hflags(CPUX86State *env)
51 {
52 uint32_t hflags = env->hflags;
53 uint32_t hflags2 = env->hflags2;
54 uint32_t bndcsr;
55
56 if ((hflags & HF_CPL_MASK) == 3) {
57 bndcsr = env->bndcs_regs.cfgu;
58 } else {
59 bndcsr = env->msr_bndcfgs;
60 }
61
62 if ((env->cr[4] & CR4_OSXSAVE_MASK)
63 && (env->xcr0 & XSTATE_BNDCSR_MASK)
64 && (bndcsr & BNDCFG_ENABLE)) {
65 hflags |= HF_MPX_EN_MASK;
66 } else {
67 hflags &= ~HF_MPX_EN_MASK;
68 }
69
70 if (bndcsr & BNDCFG_BNDPRESERVE) {
71 hflags2 |= HF2_MPX_PR_MASK;
72 } else {
73 hflags2 &= ~HF2_MPX_PR_MASK;
74 }
75
76 env->hflags = hflags;
77 env->hflags2 = hflags2;
78 }
79
80 static void cpu_x86_version(CPUX86State *env, int *family, int *model)
81 {
82 int cpuver = env->cpuid_version;
83
84 if (family == NULL || model == NULL) {
85 return;
86 }
87
88 *family = (cpuver >> 8) & 0x0f;
89 *model = ((cpuver >> 12) & 0xf0) + ((cpuver >> 4) & 0x0f);
90 }
91
92 /* Broadcast MCA signal for processor version 06H_EH and above */
93 int cpu_x86_support_mca_broadcast(CPUX86State *env)
94 {
95 int family = 0;
96 int model = 0;
97
98 if (IS_AMD_CPU(env)) {
99 return 0;
100 }
101
102 cpu_x86_version(env, &family, &model);
103 if ((family == 6 && model >= 14) || family > 6) {
104 return 1;
105 }
106
107 return 0;
108 }
109
110 /***********************************************************/
111 /* x86 mmu */
112 /* XXX: add PGE support */
113
114 #ifndef CONFIG_USER_ONLY
115 void x86_cpu_set_a20(X86CPU *cpu, int a20_state)
116 {
117 CPUX86State *env = &cpu->env;
118
119 a20_state = (a20_state != 0);
120 if (a20_state != ((env->a20_mask >> 20) & 1)) {
121 CPUState *cs = CPU(cpu);
122
123 qemu_log_mask(CPU_LOG_MMU, "A20 update: a20=%d\n", a20_state);
124 /* if the cpu is currently executing code, we must unlink it and
125 all the potentially executing TB */
126 cpu_interrupt(cs, CPU_INTERRUPT_EXITTB);
127
128 /* when a20 is changed, all the MMU mappings are invalid, so
129 we must flush everything */
130 tlb_flush(cs);
131 env->a20_mask = ~(1 << 20) | (a20_state << 20);
132 }
133 }
134 #endif
135
136 void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0)
137 {
138 X86CPU *cpu = env_archcpu(env);
139 int pe_state;
140
141 qemu_log_mask(CPU_LOG_MMU, "CR0 update: CR0=0x%08x\n", new_cr0);
142 if ((new_cr0 & (CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK)) !=
143 (env->cr[0] & (CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK))) {
144 tlb_flush(CPU(cpu));
145 }
146
147 #ifdef TARGET_X86_64
148 if (!(env->cr[0] & CR0_PG_MASK) && (new_cr0 & CR0_PG_MASK) &&
149 (env->efer & MSR_EFER_LME)) {
150 /* enter in long mode */
151 /* XXX: generate an exception */
152 if (!(env->cr[4] & CR4_PAE_MASK))
153 return;
154 env->efer |= MSR_EFER_LMA;
155 env->hflags |= HF_LMA_MASK;
156 } else if ((env->cr[0] & CR0_PG_MASK) && !(new_cr0 & CR0_PG_MASK) &&
157 (env->efer & MSR_EFER_LMA)) {
158 /* exit long mode */
159 env->efer &= ~MSR_EFER_LMA;
160 env->hflags &= ~(HF_LMA_MASK | HF_CS64_MASK);
161 env->eip &= 0xffffffff;
162 }
163 #endif
164 env->cr[0] = new_cr0 | CR0_ET_MASK;
165
166 /* update PE flag in hidden flags */
167 pe_state = (env->cr[0] & CR0_PE_MASK);
168 env->hflags = (env->hflags & ~HF_PE_MASK) | (pe_state << HF_PE_SHIFT);
169 /* ensure that ADDSEG is always set in real mode */
170 env->hflags |= ((pe_state ^ 1) << HF_ADDSEG_SHIFT);
171 /* update FPU flags */
172 env->hflags = (env->hflags & ~(HF_MP_MASK | HF_EM_MASK | HF_TS_MASK)) |
173 ((new_cr0 << (HF_MP_SHIFT - 1)) & (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK));
174 }
175
176 /* XXX: in legacy PAE mode, generate a GPF if reserved bits are set in
177 the PDPT */
178 void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3)
179 {
180 env->cr[3] = new_cr3;
181 if (env->cr[0] & CR0_PG_MASK) {
182 qemu_log_mask(CPU_LOG_MMU,
183 "CR3 update: CR3=" TARGET_FMT_lx "\n", new_cr3);
184 tlb_flush(env_cpu(env));
185 }
186 }
187
188 void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4)
189 {
190 uint32_t hflags;
191
192 #if defined(DEBUG_MMU)
193 printf("CR4 update: %08x -> %08x\n", (uint32_t)env->cr[4], new_cr4);
194 #endif
195 if ((new_cr4 ^ env->cr[4]) &
196 (CR4_PGE_MASK | CR4_PAE_MASK | CR4_PSE_MASK |
197 CR4_SMEP_MASK | CR4_SMAP_MASK | CR4_LA57_MASK)) {
198 tlb_flush(env_cpu(env));
199 }
200
201 /* Clear bits we're going to recompute. */
202 hflags = env->hflags & ~(HF_OSFXSR_MASK | HF_SMAP_MASK | HF_UMIP_MASK);
203
204 /* SSE handling */
205 if (!(env->features[FEAT_1_EDX] & CPUID_SSE)) {
206 new_cr4 &= ~CR4_OSFXSR_MASK;
207 }
208 if (new_cr4 & CR4_OSFXSR_MASK) {
209 hflags |= HF_OSFXSR_MASK;
210 }
211
212 if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SMAP)) {
213 new_cr4 &= ~CR4_SMAP_MASK;
214 }
215 if (new_cr4 & CR4_SMAP_MASK) {
216 hflags |= HF_SMAP_MASK;
217 }
218 if (!(env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_UMIP)) {
219 new_cr4 &= ~CR4_UMIP_MASK;
220 }
221 if (new_cr4 & CR4_UMIP_MASK) {
222 hflags |= HF_UMIP_MASK;
223 }
224
225 if (!(env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_PKU)) {
226 new_cr4 &= ~CR4_PKE_MASK;
227 }
228 if (!(env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_PKS)) {
229 new_cr4 &= ~CR4_PKS_MASK;
230 }
231
232 if (!(env->features[FEAT_7_1_EAX] & CPUID_7_1_EAX_LAM)) {
233 new_cr4 &= ~CR4_LAM_SUP_MASK;
234 }
235
236 /*
237 * In fact, "CR4.CET can be set only if CR0.WP is set, and it must be
238 * clear before CR0.WP can be cleared". However, here we only check
239 * CR4.CET based on the supported CPUID CET bit, without checking the
240 * dependency on CR4.WP - the latter need to be determined by the
241 * underlying accelerators.
242 */
243 if (!(env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_CET_SHSTK) &&
244 !(env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_CET_IBT)) {
245 new_cr4 &= ~CR4_CET_MASK;
246 }
247
248 env->cr[4] = new_cr4;
249 env->hflags = hflags;
250
251 cpu_sync_bndcs_hflags(env);
252 cpu_sync_avx_hflag(env);
253 }
254
255 #if !defined(CONFIG_USER_ONLY)
256 bool x86_cpu_translate_for_debug(CPUState *cs, vaddr addr,
257 TranslateForDebugResult *result)
258 {
259 X86CPU *cpu = X86_CPU(cs);
260 CPUX86State *env = &cpu->env;
261 target_ulong pde_addr, pte_addr;
262 uint64_t pte;
263 int32_t a20_mask;
264 uint32_t page_offset;
265 int page_size;
266
267 a20_mask = x86_get_a20_mask(env);
268 if (!(env->cr[0] & CR0_PG_MASK)) {
269 pte = addr & a20_mask;
270 page_size = 4096;
271 } else if (env->cr[4] & CR4_PAE_MASK) {
272 target_ulong pdpe_addr;
273 uint64_t pde, pdpe;
274
275 #ifdef TARGET_X86_64
276 if (env->hflags & HF_LMA_MASK) {
277 bool la57 = env->cr[4] & CR4_LA57_MASK;
278 uint64_t pml5e_addr, pml5e;
279 uint64_t pml4e_addr, pml4e;
280 int32_t sext;
281
282 /* test virtual address sign extension */
283 sext = la57 ? (int64_t)addr >> 56 : (int64_t)addr >> 47;
284 if (sext != 0 && sext != -1) {
285 return false;
286 }
287
288 if (la57) {
289 pml5e_addr = ((env->cr[3] & ~0xfff) +
290 (((addr >> 48) & 0x1ff) << 3)) & a20_mask;
291 pml5e = x86_ldq_phys(cs, pml5e_addr);
292 if (!(pml5e & PG_PRESENT_MASK)) {
293 return false;
294 }
295 } else {
296 pml5e = env->cr[3];
297 }
298
299 pml4e_addr = ((pml5e & PG_ADDRESS_MASK) +
300 (((addr >> 39) & 0x1ff) << 3)) & a20_mask;
301 pml4e = x86_ldq_phys(cs, pml4e_addr);
302 if (!(pml4e & PG_PRESENT_MASK)) {
303 return false;
304 }
305 pdpe_addr = ((pml4e & PG_ADDRESS_MASK) +
306 (((addr >> 30) & 0x1ff) << 3)) & a20_mask;
307 pdpe = x86_ldq_phys(cs, pdpe_addr);
308 if (!(pdpe & PG_PRESENT_MASK)) {
309 return false;
310 }
311 if (pdpe & PG_PSE_MASK) {
312 page_size = 1024 * 1024 * 1024;
313 pte = pdpe;
314 goto out;
315 }
316
317 } else
318 #endif
319 {
320 pdpe_addr = ((env->cr[3] & ~0x1f) + ((addr >> 27) & 0x18)) &
321 a20_mask;
322 pdpe = x86_ldq_phys(cs, pdpe_addr);
323 if (!(pdpe & PG_PRESENT_MASK))
324 return false;
325 }
326
327 pde_addr = ((pdpe & PG_ADDRESS_MASK) +
328 (((addr >> 21) & 0x1ff) << 3)) & a20_mask;
329 pde = x86_ldq_phys(cs, pde_addr);
330 if (!(pde & PG_PRESENT_MASK)) {
331 return false;
332 }
333 if (pde & PG_PSE_MASK) {
334 /* 2 MB page */
335 page_size = 2048 * 1024;
336 pte = pde;
337 } else {
338 /* 4 KB page */
339 pte_addr = ((pde & PG_ADDRESS_MASK) +
340 (((addr >> 12) & 0x1ff) << 3)) & a20_mask;
341 page_size = 4096;
342 pte = x86_ldq_phys(cs, pte_addr);
343 }
344 if (!(pte & PG_PRESENT_MASK)) {
345 return false;
346 }
347 } else {
348 uint32_t pde;
349
350 /* page directory entry */
351 pde_addr = ((env->cr[3] & ~0xfff) + ((addr >> 20) & 0xffc)) & a20_mask;
352 pde = x86_ldl_phys(cs, pde_addr);
353 if (!(pde & PG_PRESENT_MASK))
354 return false;
355 if ((pde & PG_PSE_MASK) && (env->cr[4] & CR4_PSE_MASK)) {
356 pte = pde | ((pde & 0x1fe000LL) << (32 - 13));
357 page_size = 4096 * 1024;
358 } else {
359 /* page directory entry */
360 pte_addr = ((pde & ~0xfff) + ((addr >> 10) & 0xffc)) & a20_mask;
361 pte = x86_ldl_phys(cs, pte_addr);
362 if (!(pte & PG_PRESENT_MASK)) {
363 return false;
364 }
365 page_size = 4096;
366 }
367 pte = pte & a20_mask;
368 }
369
370 #ifdef TARGET_X86_64
371 out:
372 #endif
373 pte &= PG_ADDRESS_MASK & ~(page_size - 1);
374 page_offset = addr & (page_size - 1);
375
376 result->attrs = cpu_get_mem_attrs(env);
377 result->attrs.debug = 1;
378 result->physaddr = pte | page_offset;
379 result->lg_page_size = ctz64(page_size);
380 return true;
381 }
382
383 typedef struct MCEInjectionParams {
384 Error **errp;
385 int bank;
386 uint64_t status;
387 uint64_t mcg_status;
388 uint64_t addr;
389 uint64_t misc;
390 int flags;
391 } MCEInjectionParams;
392
393 static void emit_guest_memory_failure(MemoryFailureAction action, bool ar,
394 bool recursive)
395 {
396 MemoryFailureFlags mff = {.action_required = ar, .recursive = recursive};
397
398 qapi_event_send_memory_failure(MEMORY_FAILURE_RECIPIENT_GUEST, action,
399 &mff);
400 }
401
402 static void do_inject_x86_mce(CPUState *cs, run_on_cpu_data data)
403 {
404 MCEInjectionParams *params = data.host_ptr;
405 X86CPU *cpu = X86_CPU(cs);
406 CPUX86State *cenv = &cpu->env;
407 uint64_t *banks = cenv->mce_banks + 4 * params->bank;
408 g_autofree char *msg = NULL;
409 bool need_reset = false;
410 bool recursive;
411 bool ar = !!(params->status & MCI_STATUS_AR);
412
413 cpu_synchronize_state(cs);
414 recursive = !!(cenv->mcg_status & MCG_STATUS_MCIP);
415
416 /*
417 * If there is an MCE exception being processed, ignore this SRAO MCE
418 * unless unconditional injection was requested.
419 */
420 if (!(params->flags & MCE_INJECT_UNCOND_AO) && !ar && recursive) {
421 emit_guest_memory_failure(MEMORY_FAILURE_ACTION_IGNORE, ar, recursive);
422 return;
423 }
424
425 if (params->status & MCI_STATUS_UC) {
426 /*
427 * if MSR_MCG_CTL is not all 1s, the uncorrected error
428 * reporting is disabled
429 */
430 if ((cenv->mcg_cap & MCG_CTL_P) && cenv->mcg_ctl != ~(uint64_t)0) {
431 error_setg(params->errp,
432 "CPU %d: Uncorrected error reporting disabled",
433 cs->cpu_index);
434 return;
435 }
436
437 /*
438 * if MSR_MCi_CTL is not all 1s, the uncorrected error
439 * reporting is disabled for the bank
440 */
441 if (banks[0] != ~(uint64_t)0) {
442 error_setg(params->errp,
443 "CPU %d: Uncorrected error reporting disabled for bank %d",
444 cs->cpu_index, params->bank);
445 return;
446 }
447
448 if (!(cenv->cr[4] & CR4_MCE_MASK)) {
449 need_reset = true;
450 msg = g_strdup_printf("CPU %d: MCE capability is not enabled, "
451 "raising triple fault", cs->cpu_index);
452 } else if (recursive) {
453 need_reset = true;
454 msg = g_strdup_printf("CPU %d: Previous MCE still in progress, "
455 "raising triple fault", cs->cpu_index);
456 }
457
458 if (need_reset) {
459 emit_guest_memory_failure(MEMORY_FAILURE_ACTION_RESET, ar,
460 recursive);
461 error_setg(params->errp, "%s", msg);
462 qemu_log_mask(CPU_LOG_RESET, "%s\n", msg);
463 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
464 return;
465 }
466
467 if (banks[1] & MCI_STATUS_VAL) {
468 params->status |= MCI_STATUS_OVER;
469 }
470 banks[2] = params->addr;
471 banks[3] = params->misc;
472 cenv->mcg_status = params->mcg_status;
473 banks[1] = params->status;
474 cpu_interrupt(cs, CPU_INTERRUPT_MCE);
475 } else if (!(banks[1] & MCI_STATUS_VAL)
476 || !(banks[1] & MCI_STATUS_UC)) {
477 if (banks[1] & MCI_STATUS_VAL) {
478 params->status |= MCI_STATUS_OVER;
479 }
480 banks[2] = params->addr;
481 banks[3] = params->misc;
482 banks[1] = params->status;
483 } else {
484 banks[1] |= MCI_STATUS_OVER;
485 }
486
487 emit_guest_memory_failure(MEMORY_FAILURE_ACTION_INJECT, ar, recursive);
488 }
489
490 bool cpu_x86_inject_mce(X86CPU *cpu, int bank,
491 uint64_t status, uint64_t mcg_status, uint64_t addr,
492 uint64_t misc, int flags, Error **errp)
493 {
494 ERRP_GUARD();
495 CPUState *cs = CPU(cpu);
496 CPUX86State *cenv = &cpu->env;
497 MCEInjectionParams params = {
498 .errp = errp,
499 .bank = bank,
500 .status = status,
501 .mcg_status = mcg_status,
502 .addr = addr,
503 .misc = misc,
504 .flags = flags,
505 };
506 unsigned bank_num = cenv->mcg_cap & 0xff;
507
508 if (!cenv->mcg_cap) {
509 error_setg(errp, "MCE injection not supported");
510 return false;
511 }
512 if (bank >= bank_num) {
513 error_setg(errp, "Invalid MCE bank number");
514 return false;
515 }
516 if (!(status & MCI_STATUS_VAL)) {
517 error_setg(errp, "Invalid MCE status code");
518 return false;
519 }
520 if ((flags & MCE_INJECT_BROADCAST)
521 && !cpu_x86_support_mca_broadcast(cenv)) {
522 error_setg(errp, "Guest CPU does not support MCA broadcast");
523 return false;
524 }
525
526 run_on_cpu(cs, do_inject_x86_mce, RUN_ON_CPU_HOST_PTR(&params));
527 if (*errp) {
528 return false;
529 }
530 if (flags & MCE_INJECT_BROADCAST) {
531 CPUState *other_cs;
532
533 params.bank = 1;
534 params.status = MCI_STATUS_VAL | MCI_STATUS_UC;
535 params.mcg_status = MCG_STATUS_MCIP | MCG_STATUS_RIPV;
536 params.addr = 0;
537 params.misc = 0;
538 CPU_FOREACH(other_cs) {
539 if (other_cs == cs) {
540 continue;
541 }
542 run_on_cpu(other_cs, do_inject_x86_mce, RUN_ON_CPU_HOST_PTR(&params));
543 if (*errp) {
544 return false;
545 }
546 }
547 }
548 return true;
549 }
550
551 static inline target_ulong get_memio_eip(CPUX86State *env)
552 {
553 #ifdef CONFIG_TCG
554 uint64_t data[INSN_START_WORDS];
555 CPUState *cs = env_cpu(env);
556
557 if (!cpu_unwind_state_data(cs, cs->mem_io_pc, data)) {
558 return env->eip;
559 }
560
561 /* Per x86_restore_state_to_opc. */
562 if (tcg_cflags_has(cs, CF_PCREL)) {
563 return (env->eip & TARGET_PAGE_MASK) | data[0];
564 } else {
565 return data[0] - env->segs[R_CS].base;
566 }
567 #else
568 qemu_build_not_reached();
569 #endif
570 }
571
572 void cpu_report_tpr_access(CPUX86State *env, TPRAccess access)
573 {
574 X86CPU *cpu = env_archcpu(env);
575 CPUState *cs = env_cpu(env);
576
577 if (kvm_enabled() || whpx_enabled() || nvmm_enabled() || hvf_enabled()) {
578 env->tpr_access_type = access;
579
580 cpu_interrupt(cs, CPU_INTERRUPT_TPR);
581 } else if (tcg_enabled()) {
582 target_ulong eip = get_memio_eip(env);
583
584 apic_handle_tpr_access_report(cpu->apic_state, eip, access);
585 }
586 }
587 #endif /* !CONFIG_USER_ONLY */
588
589 int cpu_x86_get_descr_debug(CPUX86State *env, unsigned int selector,
590 target_ulong *base, unsigned int *limit,
591 unsigned int *flags)
592 {
593 CPUState *cs = env_cpu(env);
594 SegmentCache *dt;
595 target_ulong ptr;
596 uint32_t e1, e2;
597 int index;
598
599 if (selector & 0x4)
600 dt = &env->ldt;
601 else
602 dt = &env->gdt;
603 index = selector & ~7;
604 ptr = dt->base + index;
605 if ((index + 7) > dt->limit
606 || cpu_memory_rw_debug(cs, ptr, (uint8_t *)&e1, sizeof(e1), 0) != 0
607 || cpu_memory_rw_debug(cs, ptr+4, (uint8_t *)&e2, sizeof(e2), 0) != 0)
608 return 0;
609
610 *base = ((e1 >> 16) | ((e2 & 0xff) << 16) | (e2 & 0xff000000));
611 *limit = (e1 & 0xffff) | (e2 & 0x000f0000);
612 if (e2 & DESC_G_MASK)
613 *limit = (*limit << 12) | 0xfff;
614 *flags = e2;
615
616 return 1;
617 }
618
619 void do_cpu_init(X86CPU *cpu)
620 {
621 #if !defined(CONFIG_USER_ONLY)
622 CPUState *cs = CPU(cpu);
623 CPUX86State *env = &cpu->env;
624 CPUX86State *save = g_new(CPUX86State, 1);
625 int sipi = cs->interrupt_request & CPU_INTERRUPT_SIPI;
626
627 *save = *env;
628
629 cpu_reset(cs);
630 cs->interrupt_request = sipi;
631 memcpy(&env->start_init_save, &save->start_init_save,
632 offsetof(CPUX86State, end_init_save) -
633 offsetof(CPUX86State, start_init_save));
634 g_free(save);
635
636 if (kvm_enabled()) {
637 kvm_arch_do_init_vcpu(cpu);
638 }
639 apic_init_reset(cpu->apic_state);
640 #endif /* CONFIG_USER_ONLY */
641 }
642
643 #ifndef CONFIG_USER_ONLY
644
645 void do_cpu_sipi(X86CPU *cpu)
646 {
647 CPUX86State *env = &cpu->env;
648 if (env->hflags & HF_SMM_MASK) {
649 return;
650 }
651 apic_sipi(cpu->apic_state);
652 }
653
654 void cpu_load_efer(CPUX86State *env, uint64_t val)
655 {
656 env->efer = val;
657 env->hflags &= ~(HF_LMA_MASK | HF_SVME_MASK);
658 if (env->efer & MSR_EFER_LMA) {
659 env->hflags |= HF_LMA_MASK;
660 }
661 if (env->efer & MSR_EFER_SVME) {
662 env->hflags |= HF_SVME_MASK;
663 }
664 }
665
666 uint8_t x86_ldub_phys(CPUState *cs, hwaddr addr)
667 {
668 X86CPU *cpu = X86_CPU(cs);
669 CPUX86State *env = &cpu->env;
670 MemTxAttrs attrs = cpu_get_mem_attrs(env);
671 AddressSpace *as = cpu_addressspace(cs, attrs);
672
673 return address_space_ldub(as, addr, attrs, NULL);
674 }
675
676 uint32_t x86_lduw_phys(CPUState *cs, hwaddr addr)
677 {
678 X86CPU *cpu = X86_CPU(cs);
679 CPUX86State *env = &cpu->env;
680 MemTxAttrs attrs = cpu_get_mem_attrs(env);
681 AddressSpace *as = cpu_addressspace(cs, attrs);
682
683 return address_space_lduw_le(as, addr, attrs, NULL);
684 }
685
686 uint32_t x86_ldl_phys(CPUState *cs, hwaddr addr)
687 {
688 X86CPU *cpu = X86_CPU(cs);
689 CPUX86State *env = &cpu->env;
690 MemTxAttrs attrs = cpu_get_mem_attrs(env);
691 AddressSpace *as = cpu_addressspace(cs, attrs);
692
693 return address_space_ldl_le(as, addr, attrs, NULL);
694 }
695
696 uint64_t x86_ldq_phys(CPUState *cs, hwaddr addr)
697 {
698 X86CPU *cpu = X86_CPU(cs);
699 CPUX86State *env = &cpu->env;
700 MemTxAttrs attrs = cpu_get_mem_attrs(env);
701 AddressSpace *as = cpu_addressspace(cs, attrs);
702
703 return address_space_ldq_le(as, addr, attrs, NULL);
704 }
705
706 void x86_stb_phys(CPUState *cs, hwaddr addr, uint8_t val)
707 {
708 X86CPU *cpu = X86_CPU(cs);
709 CPUX86State *env = &cpu->env;
710 MemTxAttrs attrs = cpu_get_mem_attrs(env);
711 AddressSpace *as = cpu_addressspace(cs, attrs);
712
713 address_space_stb(as, addr, val, attrs, NULL);
714 }
715
716 void x86_stw_phys(CPUState *cs, hwaddr addr, uint32_t val)
717 {
718 X86CPU *cpu = X86_CPU(cs);
719 CPUX86State *env = &cpu->env;
720 MemTxAttrs attrs = cpu_get_mem_attrs(env);
721 AddressSpace *as = cpu_addressspace(cs, attrs);
722
723 address_space_stw_le(as, addr, val, attrs, NULL);
724 }
725
726 void x86_stl_phys(CPUState *cs, hwaddr addr, uint32_t val)
727 {
728 X86CPU *cpu = X86_CPU(cs);
729 CPUX86State *env = &cpu->env;
730 MemTxAttrs attrs = cpu_get_mem_attrs(env);
731 AddressSpace *as = cpu_addressspace(cs, attrs);
732
733 address_space_stl_le(as, addr, val, attrs, NULL);
734 }
735
736 void x86_stq_phys(CPUState *cs, hwaddr addr, uint64_t val)
737 {
738 X86CPU *cpu = X86_CPU(cs);
739 CPUX86State *env = &cpu->env;
740 MemTxAttrs attrs = cpu_get_mem_attrs(env);
741 AddressSpace *as = cpu_addressspace(cs, attrs);
742
743 address_space_stq_le(as, addr, val, attrs, NULL);
744 }
745 #endif