| 1 | /* Copyright 2008 IBM Corporation |
| 2 | * 2008 Red Hat, Inc. |
| 3 | * Copyright 2011 Intel Corporation |
| 4 | * Copyright 2016 Veertu, Inc. |
| 5 | * Copyright 2017 The Android Open Source Project |
| 6 | * |
| 7 | * QEMU Hypervisor.framework support |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or |
| 10 | * modify it under the terms of version 2 of the GNU General Public |
| 11 | * License as published by the Free Software Foundation. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 16 | * General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, see <http://www.gnu.org/licenses/>. |
| 20 | * |
| 21 | * This file contain code under public domain from the hvdos project: |
| 22 | * https://github.com/mist64/hvdos |
| 23 | * |
| 24 | * Parts Copyright (c) 2011 NetApp, Inc. |
| 25 | * All rights reserved. |
| 26 | * |
| 27 | * Redistribution and use in source and binary forms, with or without |
| 28 | * modification, are permitted provided that the following conditions |
| 29 | * are met: |
| 30 | * 1. Redistributions of source code must retain the above copyright |
| 31 | * notice, this list of conditions and the following disclaimer. |
| 32 | * 2. Redistributions in binary form must reproduce the above copyright |
| 33 | * notice, this list of conditions and the following disclaimer in the |
| 34 | * documentation and/or other materials provided with the distribution. |
| 35 | * |
| 36 | * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND |
| 37 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 38 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 39 | * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE |
| 40 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| 41 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
| 42 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
| 43 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
| 44 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
| 45 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
| 46 | * SUCH DAMAGE. |
| 47 | */ |
| 48 | |
| 49 | #include "qemu/osdep.h" |
| 50 | #include "qemu/error-report.h" |
| 51 | #include "qemu/memalign.h" |
| 52 | #include "qapi/error.h" |
| 53 | #include "migration/blocker.h" |
| 54 | |
| 55 | #include "system/hvf.h" |
| 56 | #include "system/hvf_int.h" |
| 57 | #include "system/runstate.h" |
| 58 | #include "system/cpus.h" |
| 59 | #include "hvf-i386.h" |
| 60 | #include "vmcs.h" |
| 61 | #include "vmx.h" |
| 62 | #include "emulate/x86.h" |
| 63 | #include "x86_descr.h" |
| 64 | #include "emulate/x86_flags.h" |
| 65 | #include "emulate/x86_mmu.h" |
| 66 | #include "emulate/x86_decode.h" |
| 67 | #include "emulate/x86_emu.h" |
| 68 | #include "x86_task.h" |
| 69 | #include "x86hvf.h" |
| 70 | |
| 71 | #include <Hypervisor/hv.h> |
| 72 | #include <Hypervisor/hv_vmx.h> |
| 73 | #include <sys/sysctl.h> |
| 74 | |
| 75 | #include "hw/i386/apic_internal.h" |
| 76 | #include "qemu/main-loop.h" |
| 77 | #include "qemu/accel.h" |
| 78 | #include "target/i386/cpu.h" |
| 79 | #include "exec/cpu-common.h" |
| 80 | |
| 81 | static Error *invtsc_mig_blocker; |
| 82 | |
| 83 | void vmx_update_tpr(CPUState *cpu) |
| 84 | { |
| 85 | /* TODO: need integrate APIC handling */ |
| 86 | X86CPU *x86_cpu = X86_CPU(cpu); |
| 87 | int tpr = cpu_get_apic_tpr(x86_cpu->apic_state) << 4; |
| 88 | int irr = apic_get_highest_priority_irr(x86_cpu->apic_state); |
| 89 | |
| 90 | wreg(cpu->accel->fd, HV_X86_TPR, tpr); |
| 91 | if (irr == -1) { |
| 92 | wvmcs(cpu->accel->fd, VMCS_TPR_THRESHOLD, 0); |
| 93 | } else { |
| 94 | wvmcs(cpu->accel->fd, VMCS_TPR_THRESHOLD, (irr > tpr) ? tpr >> 4 : |
| 95 | irr >> 4); |
| 96 | } |
| 97 | } |
| 98 | |
| 99 | static void update_apic_tpr(CPUState *cpu) |
| 100 | { |
| 101 | X86CPU *x86_cpu = X86_CPU(cpu); |
| 102 | int tpr = rreg(cpu->accel->fd, HV_X86_TPR) >> 4; |
| 103 | cpu_set_apic_tpr(x86_cpu->apic_state, tpr); |
| 104 | } |
| 105 | |
| 106 | #define VECTORING_INFO_VECTOR_MASK 0xff |
| 107 | |
| 108 | void hvf_handle_io(CPUState *env, uint16_t port, void *buffer, |
| 109 | int direction, int size, int count) |
| 110 | { |
| 111 | int i; |
| 112 | uint8_t *ptr = buffer; |
| 113 | |
| 114 | for (i = 0; i < count; i++) { |
| 115 | address_space_rw(&address_space_io, port, MEMTXATTRS_UNSPECIFIED, |
| 116 | ptr, size, |
| 117 | direction); |
| 118 | ptr += size; |
| 119 | } |
| 120 | } |
| 121 | |
| 122 | static bool ept_emulation_fault(CPUState *cs, uint64_t gpa, uint64_t ept_qual) |
| 123 | { |
| 124 | bool read, write; |
| 125 | MemoryRegion *mr; |
| 126 | hwaddr gpa_page = gpa & qemu_real_host_page_mask(); |
| 127 | hwaddr xlat; |
| 128 | |
| 129 | /* EPT fault on an instruction fetch doesn't make sense here */ |
| 130 | if (ept_qual & EPT_VIOLATION_INST_FETCH) { |
| 131 | return false; |
| 132 | } |
| 133 | |
| 134 | /* EPT fault must be a read fault or a write fault */ |
| 135 | read = ept_qual & EPT_VIOLATION_DATA_READ; |
| 136 | write = ept_qual & EPT_VIOLATION_DATA_WRITE; |
| 137 | if (!read && !write) { |
| 138 | return false; |
| 139 | } |
| 140 | |
| 141 | mr = address_space_translate(cpu_get_address_space(cs, X86ASIdx_MEM), |
| 142 | gpa_page, &xlat, NULL, write, |
| 143 | MEMTXATTRS_UNSPECIFIED); |
| 144 | |
| 145 | /* Handle dirty page logging for ram. */ |
| 146 | if (write && memory_region_get_dirty_log_mask(mr)) { |
| 147 | uintptr_t page_size = qemu_real_host_page_size(); |
| 148 | |
| 149 | memory_region_set_dirty(mr, xlat, page_size); |
| 150 | hvf_unprotect_dirty_range(gpa_page, page_size); |
| 151 | } |
| 152 | |
| 153 | /* |
| 154 | * The EPT violation must have been caused by accessing a |
| 155 | * guest-physical address that is a translation of a guest-linear |
| 156 | * address. |
| 157 | */ |
| 158 | if ((ept_qual & EPT_VIOLATION_GLA_VALID) == 0 || |
| 159 | (ept_qual & EPT_VIOLATION_XLAT_VALID) == 0) { |
| 160 | return false; |
| 161 | } |
| 162 | |
| 163 | if (!memory_region_is_ram(mr) && |
| 164 | !(read && memory_region_is_romd(mr))) { |
| 165 | return true; |
| 166 | } |
| 167 | return false; |
| 168 | } |
| 169 | |
| 170 | void hvf_arch_vcpu_destroy(CPUState *cpu) |
| 171 | { |
| 172 | X86CPU *x86_cpu = X86_CPU(cpu); |
| 173 | CPUX86State *env = &x86_cpu->env; |
| 174 | |
| 175 | g_free(env->emu_mmio_buf); |
| 176 | } |
| 177 | |
| 178 | static void init_tsc_freq(CPUX86State *env) |
| 179 | { |
| 180 | size_t length; |
| 181 | uint64_t tsc_freq; |
| 182 | |
| 183 | if (env->tsc_khz != 0) { |
| 184 | return; |
| 185 | } |
| 186 | |
| 187 | length = sizeof(uint64_t); |
| 188 | if (sysctlbyname("machdep.tsc.frequency", &tsc_freq, &length, NULL, 0)) { |
| 189 | return; |
| 190 | } |
| 191 | env->tsc_khz = tsc_freq / 1000; /* Hz to KHz */ |
| 192 | } |
| 193 | |
| 194 | static void init_apic_bus_freq(CPUX86State *env) |
| 195 | { |
| 196 | size_t length; |
| 197 | uint64_t bus_freq; |
| 198 | |
| 199 | if (env->apic_bus_freq != 0) { |
| 200 | return; |
| 201 | } |
| 202 | |
| 203 | length = sizeof(uint64_t); |
| 204 | if (sysctlbyname("hw.busfrequency", &bus_freq, &length, NULL, 0)) { |
| 205 | return; |
| 206 | } |
| 207 | env->apic_bus_freq = bus_freq; |
| 208 | } |
| 209 | |
| 210 | static inline bool tsc_is_known(CPUX86State *env) |
| 211 | { |
| 212 | return env->tsc_khz != 0; |
| 213 | } |
| 214 | |
| 215 | static inline bool apic_bus_freq_is_known(CPUX86State *env) |
| 216 | { |
| 217 | return env->apic_bus_freq != 0; |
| 218 | } |
| 219 | |
| 220 | void hvf_kick_vcpu_thread(CPUState *cpu) |
| 221 | { |
| 222 | cpus_kick_thread(cpu); |
| 223 | hv_vcpu_interrupt(&cpu->accel->fd, 1); |
| 224 | } |
| 225 | |
| 226 | int hvf_arch_init(void) |
| 227 | { |
| 228 | return 0; |
| 229 | } |
| 230 | |
| 231 | /* 48-bit on all Intel Macs. Function currently unused. */ |
| 232 | uint32_t hvf_arch_get_default_ipa_bit_size(void) |
| 233 | { |
| 234 | g_assert_not_reached(); |
| 235 | } |
| 236 | |
| 237 | uint32_t hvf_arch_get_max_ipa_bit_size(void) |
| 238 | { |
| 239 | g_assert_not_reached(); |
| 240 | } |
| 241 | |
| 242 | hv_return_t hvf_arch_vm_create(MachineState *ms, uint32_t pa_range) |
| 243 | { |
| 244 | return hv_vm_create(HV_VM_DEFAULT); |
| 245 | } |
| 246 | |
| 247 | static void hvf_read_segment_descriptor(CPUState *s, struct x86_segment_descriptor *desc, |
| 248 | X86Seg seg) |
| 249 | { |
| 250 | struct vmx_segment vmx_segment; |
| 251 | vmx_read_segment_descriptor(s, &vmx_segment, seg); |
| 252 | vmx_segment_to_x86_descriptor(s, &vmx_segment, desc); |
| 253 | } |
| 254 | |
| 255 | static const struct x86_emul_ops hvf_x86_emul_ops = { |
| 256 | .read_segment_descriptor = hvf_read_segment_descriptor, |
| 257 | .handle_io = hvf_handle_io, |
| 258 | .simulate_rdmsr = hvf_simulate_rdmsr, |
| 259 | .simulate_wrmsr = hvf_simulate_wrmsr, |
| 260 | }; |
| 261 | |
| 262 | int hvf_arch_init_vcpu(CPUState *cpu) |
| 263 | { |
| 264 | X86CPU *x86cpu = X86_CPU(cpu); |
| 265 | CPUX86State *env = &x86cpu->env; |
| 266 | Error *local_err = NULL; |
| 267 | int r; |
| 268 | uint64_t reqCap; |
| 269 | |
| 270 | init_emu(&hvf_x86_emul_ops); |
| 271 | init_decoder(); |
| 272 | |
| 273 | if (hvf_state->hvf_caps == NULL) { |
| 274 | hvf_state->hvf_caps = g_new0(struct hvf_vcpu_caps, 1); |
| 275 | } |
| 276 | env->emu_mmio_buf = g_new(char, 4096); |
| 277 | |
| 278 | if (x86cpu->vmware_cpuid_freq) { |
| 279 | init_tsc_freq(env); |
| 280 | init_apic_bus_freq(env); |
| 281 | |
| 282 | if (!tsc_is_known(env) || !apic_bus_freq_is_known(env)) { |
| 283 | error_report("vmware-cpuid-freq: feature couldn't be enabled"); |
| 284 | } |
| 285 | } |
| 286 | |
| 287 | if ((env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC) && |
| 288 | invtsc_mig_blocker == NULL) { |
| 289 | error_setg(&invtsc_mig_blocker, |
| 290 | "State blocked by non-migratable CPU device (invtsc flag)"); |
| 291 | r = migrate_add_blocker(&invtsc_mig_blocker, &local_err); |
| 292 | if (r < 0) { |
| 293 | error_report_err(local_err); |
| 294 | return r; |
| 295 | } |
| 296 | } |
| 297 | |
| 298 | |
| 299 | if (hv_vmx_read_capability(HV_VMX_CAP_PINBASED, |
| 300 | &hvf_state->hvf_caps->vmx_cap_pinbased)) { |
| 301 | abort(); |
| 302 | } |
| 303 | if (hv_vmx_read_capability(HV_VMX_CAP_PROCBASED, |
| 304 | &hvf_state->hvf_caps->vmx_cap_procbased)) { |
| 305 | abort(); |
| 306 | } |
| 307 | if (hv_vmx_read_capability(HV_VMX_CAP_PROCBASED2, |
| 308 | &hvf_state->hvf_caps->vmx_cap_procbased2)) { |
| 309 | abort(); |
| 310 | } |
| 311 | if (hv_vmx_read_capability(HV_VMX_CAP_ENTRY, |
| 312 | &hvf_state->hvf_caps->vmx_cap_entry)) { |
| 313 | abort(); |
| 314 | } |
| 315 | |
| 316 | /* set VMCS control fields */ |
| 317 | wvmcs(cpu->accel->fd, VMCS_PIN_BASED_CTLS, |
| 318 | cap2ctrl(hvf_state->hvf_caps->vmx_cap_pinbased, |
| 319 | VMCS_PIN_BASED_CTLS_EXTINT | |
| 320 | VMCS_PIN_BASED_CTLS_NMI | |
| 321 | VMCS_PIN_BASED_CTLS_VNMI)); |
| 322 | wvmcs(cpu->accel->fd, VMCS_PRI_PROC_BASED_CTLS, |
| 323 | cap2ctrl(hvf_state->hvf_caps->vmx_cap_procbased, |
| 324 | VMCS_PRI_PROC_BASED_CTLS_HLT | |
| 325 | VMCS_PRI_PROC_BASED_CTLS_MWAIT | |
| 326 | VMCS_PRI_PROC_BASED_CTLS_TSC_OFFSET | |
| 327 | VMCS_PRI_PROC_BASED_CTLS_TPR_SHADOW) | |
| 328 | VMCS_PRI_PROC_BASED_CTLS_SEC_CONTROL); |
| 329 | |
| 330 | reqCap = VMCS_PRI_PROC_BASED2_CTLS_APIC_ACCESSES; |
| 331 | |
| 332 | /* Is RDTSCP support in CPUID? If so, enable it in the VMCS. */ |
| 333 | if (hvf_get_supported_cpuid(0x80000001, 0, R_EDX) & CPUID_EXT2_RDTSCP) { |
| 334 | reqCap |= VMCS_PRI_PROC_BASED2_CTLS_RDTSCP; |
| 335 | } |
| 336 | |
| 337 | wvmcs(cpu->accel->fd, VMCS_SEC_PROC_BASED_CTLS, |
| 338 | cap2ctrl(hvf_state->hvf_caps->vmx_cap_procbased2, reqCap)); |
| 339 | |
| 340 | wvmcs(cpu->accel->fd, VMCS_ENTRY_CTLS, |
| 341 | cap2ctrl(hvf_state->hvf_caps->vmx_cap_entry, 0)); |
| 342 | wvmcs(cpu->accel->fd, VMCS_EXCEPTION_BITMAP, 0); /* Double fault */ |
| 343 | |
| 344 | wvmcs(cpu->accel->fd, VMCS_TPR_THRESHOLD, 0); |
| 345 | |
| 346 | x86cpu = X86_CPU(cpu); |
| 347 | x86cpu->env.xsave_buf_len = 4096; |
| 348 | x86cpu->env.xsave_buf = qemu_memalign(4096, x86cpu->env.xsave_buf_len); |
| 349 | |
| 350 | /* |
| 351 | * The allocated storage must be large enough for all of the |
| 352 | * possible XSAVE state components. |
| 353 | */ |
| 354 | assert(hvf_get_supported_cpuid(0xd, 0, R_ECX) <= x86cpu->env.xsave_buf_len); |
| 355 | |
| 356 | hv_vcpu_enable_native_msr(cpu->accel->fd, MSR_STAR, 1); |
| 357 | hv_vcpu_enable_native_msr(cpu->accel->fd, MSR_LSTAR, 1); |
| 358 | hv_vcpu_enable_native_msr(cpu->accel->fd, MSR_CSTAR, 1); |
| 359 | hv_vcpu_enable_native_msr(cpu->accel->fd, MSR_FMASK, 1); |
| 360 | hv_vcpu_enable_native_msr(cpu->accel->fd, MSR_FSBASE, 1); |
| 361 | hv_vcpu_enable_native_msr(cpu->accel->fd, MSR_GSBASE, 1); |
| 362 | hv_vcpu_enable_native_msr(cpu->accel->fd, MSR_KERNELGSBASE, 1); |
| 363 | hv_vcpu_enable_native_msr(cpu->accel->fd, MSR_TSC_AUX, 1); |
| 364 | hv_vcpu_enable_native_msr(cpu->accel->fd, MSR_IA32_TSC, 1); |
| 365 | hv_vcpu_enable_native_msr(cpu->accel->fd, MSR_IA32_SYSENTER_CS, 1); |
| 366 | hv_vcpu_enable_native_msr(cpu->accel->fd, MSR_IA32_SYSENTER_EIP, 1); |
| 367 | hv_vcpu_enable_native_msr(cpu->accel->fd, MSR_IA32_SYSENTER_ESP, 1); |
| 368 | |
| 369 | return 0; |
| 370 | } |
| 371 | |
| 372 | bool hvf_arch_cpu_realize(CPUState *cs, Error **errp) |
| 373 | { |
| 374 | return true; |
| 375 | } |
| 376 | |
| 377 | static void hvf_store_events(CPUState *cpu, uint32_t ins_len, uint64_t idtvec_info) |
| 378 | { |
| 379 | X86CPU *x86_cpu = X86_CPU(cpu); |
| 380 | CPUX86State *env = &x86_cpu->env; |
| 381 | |
| 382 | env->exception_nr = -1; |
| 383 | env->exception_pending = 0; |
| 384 | env->exception_injected = 0; |
| 385 | env->interrupt_injected = -1; |
| 386 | env->nmi_injected = false; |
| 387 | env->ins_len = 0; |
| 388 | env->has_error_code = false; |
| 389 | if (idtvec_info & VMCS_IDT_VEC_VALID) { |
| 390 | switch (idtvec_info & VMCS_IDT_VEC_TYPE) { |
| 391 | case VMCS_IDT_VEC_HWINTR: |
| 392 | case VMCS_IDT_VEC_SWINTR: |
| 393 | env->interrupt_injected = idtvec_info & VMCS_IDT_VEC_VECNUM; |
| 394 | break; |
| 395 | case VMCS_IDT_VEC_NMI: |
| 396 | env->nmi_injected = true; |
| 397 | break; |
| 398 | case VMCS_IDT_VEC_HWEXCEPTION: |
| 399 | case VMCS_IDT_VEC_SWEXCEPTION: |
| 400 | env->exception_nr = idtvec_info & VMCS_IDT_VEC_VECNUM; |
| 401 | env->exception_injected = 1; |
| 402 | break; |
| 403 | case VMCS_IDT_VEC_PRIV_SWEXCEPTION: |
| 404 | default: |
| 405 | abort(); |
| 406 | } |
| 407 | if ((idtvec_info & VMCS_IDT_VEC_TYPE) == VMCS_IDT_VEC_SWEXCEPTION || |
| 408 | (idtvec_info & VMCS_IDT_VEC_TYPE) == VMCS_IDT_VEC_SWINTR) { |
| 409 | env->ins_len = ins_len; |
| 410 | } |
| 411 | if (idtvec_info & VMCS_IDT_VEC_ERRCODE_VALID) { |
| 412 | env->has_error_code = true; |
| 413 | env->error_code = rvmcs(cpu->accel->fd, VMCS_IDT_VECTORING_ERROR); |
| 414 | } |
| 415 | } |
| 416 | if ((rvmcs(cpu->accel->fd, VMCS_GUEST_INTERRUPTIBILITY) & |
| 417 | VMCS_INTERRUPTIBILITY_NMI_BLOCKING)) { |
| 418 | env->hflags2 |= HF2_NMI_MASK; |
| 419 | } else { |
| 420 | env->hflags2 &= ~HF2_NMI_MASK; |
| 421 | } |
| 422 | if (rvmcs(cpu->accel->fd, VMCS_GUEST_INTERRUPTIBILITY) & |
| 423 | (VMCS_INTERRUPTIBILITY_STI_BLOCKING | |
| 424 | VMCS_INTERRUPTIBILITY_MOVSS_BLOCKING)) { |
| 425 | env->hflags |= HF_INHIBIT_IRQ_MASK; |
| 426 | } else { |
| 427 | env->hflags &= ~HF_INHIBIT_IRQ_MASK; |
| 428 | } |
| 429 | } |
| 430 | |
| 431 | static void hvf_cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, |
| 432 | uint32_t *eax, uint32_t *ebx, |
| 433 | uint32_t *ecx, uint32_t *edx) |
| 434 | { |
| 435 | /* |
| 436 | * A wrapper extends cpu_x86_cpuid with 0x40000000 and 0x40000010 leafs, |
| 437 | * leafs 0x40000001-0x4000000F are filled with zeros |
| 438 | * Provides vmware-cpuid-freq support to hvf |
| 439 | * |
| 440 | * Note: leaf 0x40000000 not exposes HVF, |
| 441 | * leaving hypervisor signature empty |
| 442 | */ |
| 443 | |
| 444 | if (index < 0x40000000 || index > 0x40000010 || |
| 445 | !tsc_is_known(env) || !apic_bus_freq_is_known(env)) { |
| 446 | |
| 447 | cpu_x86_cpuid(env, index, count, eax, ebx, ecx, edx); |
| 448 | return; |
| 449 | } |
| 450 | |
| 451 | switch (index) { |
| 452 | case 0x40000000: |
| 453 | *eax = 0x40000010; /* Max available cpuid leaf */ |
| 454 | *ebx = 0; /* Leave signature empty */ |
| 455 | *ecx = 0; |
| 456 | *edx = 0; |
| 457 | break; |
| 458 | case 0x40000010: |
| 459 | *eax = env->tsc_khz; |
| 460 | *ebx = env->apic_bus_freq / 1000; /* Hz to KHz */ |
| 461 | *ecx = 0; |
| 462 | *edx = 0; |
| 463 | break; |
| 464 | default: |
| 465 | *eax = 0; |
| 466 | *ebx = 0; |
| 467 | *ecx = 0; |
| 468 | *edx = 0; |
| 469 | break; |
| 470 | } |
| 471 | } |
| 472 | |
| 473 | static void hvf_load_crs(CPUState *cs) |
| 474 | { |
| 475 | X86CPU *x86_cpu = X86_CPU(cs); |
| 476 | CPUX86State *env = &x86_cpu->env; |
| 477 | |
| 478 | env->cr[0] = rvmcs(cs->accel->fd, VMCS_GUEST_CR0); |
| 479 | env->cr[3] = rvmcs(cs->accel->fd, VMCS_GUEST_CR3); |
| 480 | env->cr[2] = rreg(cs->accel->fd, HV_X86_CR2); |
| 481 | } |
| 482 | |
| 483 | static void hvf_save_crs(CPUState *cs) |
| 484 | { |
| 485 | X86CPU *x86_cpu = X86_CPU(cs); |
| 486 | CPUX86State *env = &x86_cpu->env; |
| 487 | |
| 488 | wvmcs(cs->accel->fd, VMCS_GUEST_CR0, env->cr[0]); |
| 489 | wvmcs(cs->accel->fd, VMCS_GUEST_CR3, env->cr[3]); |
| 490 | wreg(cs->accel->fd, HV_X86_CR2, env->cr[2]); |
| 491 | } |
| 492 | |
| 493 | void hvf_load_regs(CPUState *cs) |
| 494 | { |
| 495 | X86CPU *cpu = X86_CPU(cs); |
| 496 | CPUX86State *env = &cpu->env; |
| 497 | |
| 498 | int i = 0; |
| 499 | RRX(env, R_EAX) = rreg(cs->accel->fd, HV_X86_RAX); |
| 500 | RRX(env, R_EBX) = rreg(cs->accel->fd, HV_X86_RBX); |
| 501 | RRX(env, R_ECX) = rreg(cs->accel->fd, HV_X86_RCX); |
| 502 | RRX(env, R_EDX) = rreg(cs->accel->fd, HV_X86_RDX); |
| 503 | RRX(env, R_ESI) = rreg(cs->accel->fd, HV_X86_RSI); |
| 504 | RRX(env, R_EDI) = rreg(cs->accel->fd, HV_X86_RDI); |
| 505 | RRX(env, R_ESP) = rreg(cs->accel->fd, HV_X86_RSP); |
| 506 | RRX(env, R_EBP) = rreg(cs->accel->fd, HV_X86_RBP); |
| 507 | for (i = 8; i < 16; i++) { |
| 508 | RRX(env, i) = rreg(cs->accel->fd, HV_X86_RAX + i); |
| 509 | } |
| 510 | |
| 511 | env->eflags = rreg(cs->accel->fd, HV_X86_RFLAGS); |
| 512 | rflags_to_lflags(env); |
| 513 | env->eip = rreg(cs->accel->fd, HV_X86_RIP); |
| 514 | } |
| 515 | |
| 516 | void hvf_store_regs(CPUState *cs) |
| 517 | { |
| 518 | X86CPU *cpu = X86_CPU(cs); |
| 519 | CPUX86State *env = &cpu->env; |
| 520 | |
| 521 | int i = 0; |
| 522 | wreg(cs->accel->fd, HV_X86_RAX, RAX(env)); |
| 523 | wreg(cs->accel->fd, HV_X86_RBX, RBX(env)); |
| 524 | wreg(cs->accel->fd, HV_X86_RCX, RCX(env)); |
| 525 | wreg(cs->accel->fd, HV_X86_RDX, RDX(env)); |
| 526 | wreg(cs->accel->fd, HV_X86_RSI, RSI(env)); |
| 527 | wreg(cs->accel->fd, HV_X86_RDI, RDI(env)); |
| 528 | wreg(cs->accel->fd, HV_X86_RBP, RBP(env)); |
| 529 | wreg(cs->accel->fd, HV_X86_RSP, RSP(env)); |
| 530 | for (i = 8; i < 16; i++) { |
| 531 | wreg(cs->accel->fd, HV_X86_RAX + i, RRX(env, i)); |
| 532 | } |
| 533 | |
| 534 | lflags_to_rflags(env); |
| 535 | wreg(cs->accel->fd, HV_X86_RFLAGS, env->eflags); |
| 536 | macvm_set_rip(cs, env->eip); |
| 537 | } |
| 538 | |
| 539 | bool hvf_simulate_rdmsr(CPUState *cs) |
| 540 | { |
| 541 | X86CPU *cpu = X86_CPU(cs); |
| 542 | CPUX86State *env = &cpu->env; |
| 543 | uint32_t msr = ECX(env); |
| 544 | uint64_t val = 0; |
| 545 | |
| 546 | switch (msr) { |
| 547 | case MSR_IA32_TSC: |
| 548 | val = rdtscp() + rvmcs(cs->accel->fd, VMCS_TSC_OFFSET); |
| 549 | break; |
| 550 | case MSR_IA32_APICBASE: |
| 551 | val = cpu_get_apic_base(cpu->apic_state); |
| 552 | break; |
| 553 | case MSR_APIC_START ... MSR_APIC_END: { |
| 554 | int ret; |
| 555 | int index = (uint32_t)env->regs[R_ECX] - MSR_APIC_START; |
| 556 | |
| 557 | ret = apic_msr_read(cpu->apic_state, index, &val); |
| 558 | if (ret < 0) { |
| 559 | x86_emul_raise_exception(env, EXCP0D_GPF, 0); |
| 560 | return 1; |
| 561 | } |
| 562 | |
| 563 | break; |
| 564 | } |
| 565 | case MSR_IA32_UCODE_REV: |
| 566 | val = cpu->ucode_rev; |
| 567 | break; |
| 568 | case MSR_EFER: |
| 569 | val = rvmcs(cs->accel->fd, VMCS_GUEST_IA32_EFER); |
| 570 | break; |
| 571 | case MSR_FSBASE: |
| 572 | val = rvmcs(cs->accel->fd, VMCS_GUEST_FS_BASE); |
| 573 | break; |
| 574 | case MSR_GSBASE: |
| 575 | val = rvmcs(cs->accel->fd, VMCS_GUEST_GS_BASE); |
| 576 | break; |
| 577 | case MSR_KERNELGSBASE: |
| 578 | val = rvmcs(cs->accel->fd, VMCS_HOST_FS_BASE); |
| 579 | break; |
| 580 | case MSR_STAR: |
| 581 | abort(); |
| 582 | break; |
| 583 | case MSR_LSTAR: |
| 584 | abort(); |
| 585 | break; |
| 586 | case MSR_CSTAR: |
| 587 | abort(); |
| 588 | break; |
| 589 | case MSR_IA32_MISC_ENABLE: |
| 590 | val = env->msr_ia32_misc_enable; |
| 591 | break; |
| 592 | case MSR_MTRRphysBase(0): |
| 593 | case MSR_MTRRphysBase(1): |
| 594 | case MSR_MTRRphysBase(2): |
| 595 | case MSR_MTRRphysBase(3): |
| 596 | case MSR_MTRRphysBase(4): |
| 597 | case MSR_MTRRphysBase(5): |
| 598 | case MSR_MTRRphysBase(6): |
| 599 | case MSR_MTRRphysBase(7): |
| 600 | val = env->mtrr_var[(ECX(env) - MSR_MTRRphysBase(0)) / 2].base; |
| 601 | break; |
| 602 | case MSR_MTRRphysMask(0): |
| 603 | case MSR_MTRRphysMask(1): |
| 604 | case MSR_MTRRphysMask(2): |
| 605 | case MSR_MTRRphysMask(3): |
| 606 | case MSR_MTRRphysMask(4): |
| 607 | case MSR_MTRRphysMask(5): |
| 608 | case MSR_MTRRphysMask(6): |
| 609 | case MSR_MTRRphysMask(7): |
| 610 | val = env->mtrr_var[(ECX(env) - MSR_MTRRphysMask(0)) / 2].mask; |
| 611 | break; |
| 612 | case MSR_MTRRfix64K_00000: |
| 613 | val = env->mtrr_fixed[0]; |
| 614 | break; |
| 615 | case MSR_MTRRfix16K_80000: |
| 616 | case MSR_MTRRfix16K_A0000: |
| 617 | val = env->mtrr_fixed[ECX(env) - MSR_MTRRfix16K_80000 + 1]; |
| 618 | break; |
| 619 | case MSR_MTRRfix4K_C0000: |
| 620 | case MSR_MTRRfix4K_C8000: |
| 621 | case MSR_MTRRfix4K_D0000: |
| 622 | case MSR_MTRRfix4K_D8000: |
| 623 | case MSR_MTRRfix4K_E0000: |
| 624 | case MSR_MTRRfix4K_E8000: |
| 625 | case MSR_MTRRfix4K_F0000: |
| 626 | case MSR_MTRRfix4K_F8000: |
| 627 | val = env->mtrr_fixed[ECX(env) - MSR_MTRRfix4K_C0000 + 3]; |
| 628 | break; |
| 629 | case MSR_MTRRdefType: |
| 630 | val = env->mtrr_deftype; |
| 631 | break; |
| 632 | case MSR_CORE_THREAD_COUNT: |
| 633 | val = cpu_x86_get_msr_core_thread_count(cpu); |
| 634 | break; |
| 635 | default: |
| 636 | /* fprintf(stderr, "%s: unknown msr 0x%x\n", __func__, msr); */ |
| 637 | val = 0; |
| 638 | break; |
| 639 | } |
| 640 | |
| 641 | RAX(env) = (uint32_t)val; |
| 642 | RDX(env) = (uint32_t)(val >> 32); |
| 643 | return 0; |
| 644 | } |
| 645 | |
| 646 | bool hvf_simulate_wrmsr(CPUState *cs) |
| 647 | { |
| 648 | X86CPU *cpu = X86_CPU(cs); |
| 649 | CPUX86State *env = &cpu->env; |
| 650 | uint32_t msr = ECX(env); |
| 651 | uint64_t data = ((uint64_t)EDX(env) << 32) | EAX(env); |
| 652 | |
| 653 | switch (msr) { |
| 654 | case MSR_IA32_TSC: |
| 655 | break; |
| 656 | case MSR_IA32_APICBASE: { |
| 657 | int r; |
| 658 | |
| 659 | r = cpu_set_apic_base(cpu->apic_state, data); |
| 660 | if (r < 0) { |
| 661 | x86_emul_raise_exception(env, EXCP0D_GPF, 0); |
| 662 | return 1; |
| 663 | } |
| 664 | |
| 665 | break; |
| 666 | } |
| 667 | case MSR_APIC_START ... MSR_APIC_END: { |
| 668 | int ret; |
| 669 | int index = (uint32_t)env->regs[R_ECX] - MSR_APIC_START; |
| 670 | |
| 671 | ret = apic_msr_write(cpu->apic_state, index, data); |
| 672 | if (ret < 0) { |
| 673 | x86_emul_raise_exception(env, EXCP0D_GPF, 0); |
| 674 | return 1; |
| 675 | } |
| 676 | |
| 677 | break; |
| 678 | } |
| 679 | case MSR_FSBASE: |
| 680 | wvmcs(cs->accel->fd, VMCS_GUEST_FS_BASE, data); |
| 681 | break; |
| 682 | case MSR_GSBASE: |
| 683 | wvmcs(cs->accel->fd, VMCS_GUEST_GS_BASE, data); |
| 684 | break; |
| 685 | case MSR_KERNELGSBASE: |
| 686 | wvmcs(cs->accel->fd, VMCS_HOST_FS_BASE, data); |
| 687 | break; |
| 688 | case MSR_STAR: |
| 689 | abort(); |
| 690 | break; |
| 691 | case MSR_LSTAR: |
| 692 | abort(); |
| 693 | break; |
| 694 | case MSR_CSTAR: |
| 695 | abort(); |
| 696 | break; |
| 697 | case MSR_EFER: |
| 698 | /*printf("new efer %llx\n", EFER(cs));*/ |
| 699 | wvmcs(cs->accel->fd, VMCS_GUEST_IA32_EFER, data); |
| 700 | if (data & MSR_EFER_NXE) { |
| 701 | hv_vcpu_invalidate_tlb(cs->accel->fd); |
| 702 | } |
| 703 | break; |
| 704 | case MSR_MTRRphysBase(0): |
| 705 | case MSR_MTRRphysBase(1): |
| 706 | case MSR_MTRRphysBase(2): |
| 707 | case MSR_MTRRphysBase(3): |
| 708 | case MSR_MTRRphysBase(4): |
| 709 | case MSR_MTRRphysBase(5): |
| 710 | case MSR_MTRRphysBase(6): |
| 711 | case MSR_MTRRphysBase(7): |
| 712 | env->mtrr_var[(ECX(env) - MSR_MTRRphysBase(0)) / 2].base = data; |
| 713 | break; |
| 714 | case MSR_MTRRphysMask(0): |
| 715 | case MSR_MTRRphysMask(1): |
| 716 | case MSR_MTRRphysMask(2): |
| 717 | case MSR_MTRRphysMask(3): |
| 718 | case MSR_MTRRphysMask(4): |
| 719 | case MSR_MTRRphysMask(5): |
| 720 | case MSR_MTRRphysMask(6): |
| 721 | case MSR_MTRRphysMask(7): |
| 722 | env->mtrr_var[(ECX(env) - MSR_MTRRphysMask(0)) / 2].mask = data; |
| 723 | break; |
| 724 | case MSR_MTRRfix64K_00000: |
| 725 | env->mtrr_fixed[ECX(env) - MSR_MTRRfix64K_00000] = data; |
| 726 | break; |
| 727 | case MSR_MTRRfix16K_80000: |
| 728 | case MSR_MTRRfix16K_A0000: |
| 729 | env->mtrr_fixed[ECX(env) - MSR_MTRRfix16K_80000 + 1] = data; |
| 730 | break; |
| 731 | case MSR_MTRRfix4K_C0000: |
| 732 | case MSR_MTRRfix4K_C8000: |
| 733 | case MSR_MTRRfix4K_D0000: |
| 734 | case MSR_MTRRfix4K_D8000: |
| 735 | case MSR_MTRRfix4K_E0000: |
| 736 | case MSR_MTRRfix4K_E8000: |
| 737 | case MSR_MTRRfix4K_F0000: |
| 738 | case MSR_MTRRfix4K_F8000: |
| 739 | env->mtrr_fixed[ECX(env) - MSR_MTRRfix4K_C0000 + 3] = data; |
| 740 | break; |
| 741 | case MSR_MTRRdefType: |
| 742 | env->mtrr_deftype = data; |
| 743 | break; |
| 744 | default: |
| 745 | break; |
| 746 | } |
| 747 | |
| 748 | /* Related to support known hypervisor interface */ |
| 749 | /* if (g_hypervisor_iface) |
| 750 | g_hypervisor_iface->wrmsr_handler(cs, msr, data); |
| 751 | |
| 752 | printf("write msr %llx\n", RCX(cs));*/ |
| 753 | return 0; |
| 754 | } |
| 755 | |
| 756 | static int hvf_handle_vmexit(CPUState *cpu) |
| 757 | { |
| 758 | X86CPU *x86_cpu = env_archcpu(cpu_env(cpu)); |
| 759 | uint64_t exit_reason = rvmcs(cpu->accel->fd, VMCS_EXIT_REASON); |
| 760 | uint64_t exit_qual = rvmcs(cpu->accel->fd, VMCS_EXIT_QUALIFICATION); |
| 761 | uint32_t ins_len = (uint32_t)rvmcs(cpu->accel->fd, |
| 762 | VMCS_EXIT_INSTRUCTION_LENGTH); |
| 763 | CPUX86State *env = &x86_cpu->env; |
| 764 | uint64_t rip = 0; |
| 765 | uint64_t idtvec_info = rvmcs(cpu->accel->fd, VMCS_IDT_VECTORING_INFO); |
| 766 | int ret = 0; |
| 767 | |
| 768 | hvf_store_events(cpu, ins_len, idtvec_info); |
| 769 | rip = rreg(cpu->accel->fd, HV_X86_RIP); |
| 770 | env->eflags = rreg(cpu->accel->fd, HV_X86_RFLAGS); |
| 771 | |
| 772 | bql_lock(); |
| 773 | |
| 774 | update_apic_tpr(cpu); |
| 775 | current_cpu = cpu; |
| 776 | |
| 777 | switch (exit_reason) { |
| 778 | case EXIT_REASON_HLT: { |
| 779 | macvm_set_rip(cpu, rip + ins_len); |
| 780 | if (!(cpu_test_interrupt(cpu, CPU_INTERRUPT_HARD) |
| 781 | && (env->eflags & IF_MASK)) |
| 782 | && !cpu_test_interrupt(cpu, CPU_INTERRUPT_NMI) |
| 783 | && !(idtvec_info & VMCS_IDT_VEC_VALID)) { |
| 784 | cpu->halted = 1; |
| 785 | ret = EXCP_HLT; |
| 786 | break; |
| 787 | } |
| 788 | ret = EXCP_INTERRUPT; |
| 789 | break; |
| 790 | } |
| 791 | case EXIT_REASON_MWAIT: { |
| 792 | ret = EXCP_INTERRUPT; |
| 793 | break; |
| 794 | } |
| 795 | /* Need to check if MMIO or unmapped fault */ |
| 796 | case EXIT_REASON_EPT_FAULT: |
| 797 | { |
| 798 | uint64_t gpa = rvmcs(cpu->accel->fd, VMCS_GUEST_PHYSICAL_ADDRESS); |
| 799 | |
| 800 | if (((idtvec_info & VMCS_IDT_VEC_VALID) == 0) && |
| 801 | ((exit_qual & EXIT_QUAL_NMIUDTI) != 0)) { |
| 802 | vmx_set_nmi_blocking(cpu); |
| 803 | } |
| 804 | |
| 805 | /* mmio */ |
| 806 | if (ept_emulation_fault(cpu, gpa, exit_qual)) { |
| 807 | struct x86_decode decode; |
| 808 | |
| 809 | hvf_load_regs(cpu); |
| 810 | hvf_load_crs(cpu); |
| 811 | decode_instruction(env, &decode); |
| 812 | exec_instruction(env, &decode); |
| 813 | hvf_store_regs(cpu); |
| 814 | hvf_save_crs(cpu); |
| 815 | break; |
| 816 | } |
| 817 | break; |
| 818 | } |
| 819 | case EXIT_REASON_INOUT: |
| 820 | { |
| 821 | uint32_t in = (exit_qual & 8) != 0; |
| 822 | uint32_t size = (exit_qual & 7) + 1; |
| 823 | uint32_t string = (exit_qual & 16) != 0; |
| 824 | uint32_t port = exit_qual >> 16; |
| 825 | /*uint32_t rep = (exit_qual & 0x20) != 0;*/ |
| 826 | struct x86_decode decode; |
| 827 | |
| 828 | if (!string && in) { |
| 829 | uint64_t val = 0; |
| 830 | |
| 831 | hvf_load_regs(cpu); |
| 832 | hvf_handle_io(env_cpu(env), port, &val, 0, size, 1); |
| 833 | if (size == 1) { |
| 834 | AL(env) = val; |
| 835 | } else if (size == 2) { |
| 836 | AX(env) = val; |
| 837 | } else if (size == 4) { |
| 838 | RAX(env) = (uint32_t)val; |
| 839 | } else { |
| 840 | RAX(env) = (uint64_t)val; |
| 841 | } |
| 842 | env->eip += ins_len; |
| 843 | hvf_store_regs(cpu); |
| 844 | break; |
| 845 | } else if (!string && !in) { |
| 846 | RAX(env) = rreg(cpu->accel->fd, HV_X86_RAX); |
| 847 | hvf_handle_io(env_cpu(env), port, &RAX(env), 1, size, 1); |
| 848 | macvm_set_rip(cpu, rip + ins_len); |
| 849 | break; |
| 850 | } |
| 851 | |
| 852 | hvf_load_regs(cpu); |
| 853 | hvf_load_crs(cpu); |
| 854 | decode_instruction(env, &decode); |
| 855 | assert(ins_len == decode.len); |
| 856 | exec_instruction(env, &decode); |
| 857 | hvf_store_regs(cpu); |
| 858 | hvf_save_crs(cpu); |
| 859 | |
| 860 | break; |
| 861 | } |
| 862 | case EXIT_REASON_CPUID: { |
| 863 | uint32_t rax = (uint32_t)rreg(cpu->accel->fd, HV_X86_RAX); |
| 864 | uint32_t rbx = (uint32_t)rreg(cpu->accel->fd, HV_X86_RBX); |
| 865 | uint32_t rcx = (uint32_t)rreg(cpu->accel->fd, HV_X86_RCX); |
| 866 | uint32_t rdx = (uint32_t)rreg(cpu->accel->fd, HV_X86_RDX); |
| 867 | |
| 868 | if (rax == 1) { |
| 869 | /* CPUID1.ecx.OSXSAVE needs to know CR4 */ |
| 870 | env->cr[4] = rvmcs(cpu->accel->fd, VMCS_GUEST_CR4); |
| 871 | } |
| 872 | hvf_cpu_x86_cpuid(env, rax, rcx, &rax, &rbx, &rcx, &rdx); |
| 873 | |
| 874 | wreg(cpu->accel->fd, HV_X86_RAX, rax); |
| 875 | wreg(cpu->accel->fd, HV_X86_RBX, rbx); |
| 876 | wreg(cpu->accel->fd, HV_X86_RCX, rcx); |
| 877 | wreg(cpu->accel->fd, HV_X86_RDX, rdx); |
| 878 | |
| 879 | macvm_set_rip(cpu, rip + ins_len); |
| 880 | break; |
| 881 | } |
| 882 | case EXIT_REASON_XSETBV: { |
| 883 | uint32_t eax = (uint32_t)rreg(cpu->accel->fd, HV_X86_RAX); |
| 884 | uint32_t ecx = (uint32_t)rreg(cpu->accel->fd, HV_X86_RCX); |
| 885 | uint32_t edx = (uint32_t)rreg(cpu->accel->fd, HV_X86_RDX); |
| 886 | |
| 887 | if (ecx) { |
| 888 | macvm_set_rip(cpu, rip + ins_len); |
| 889 | break; |
| 890 | } |
| 891 | env->xcr0 = ((uint64_t)edx << 32) | eax; |
| 892 | wreg(cpu->accel->fd, HV_X86_XCR0, env->xcr0 | 1); |
| 893 | macvm_set_rip(cpu, rip + ins_len); |
| 894 | break; |
| 895 | } |
| 896 | case EXIT_REASON_INTR_WINDOW: |
| 897 | vmx_clear_int_window_exiting(cpu); |
| 898 | ret = EXCP_INTERRUPT; |
| 899 | break; |
| 900 | case EXIT_REASON_NMI_WINDOW: |
| 901 | vmx_clear_nmi_window_exiting(cpu); |
| 902 | ret = EXCP_INTERRUPT; |
| 903 | break; |
| 904 | case EXIT_REASON_EXT_INTR: |
| 905 | /* force exit and allow io handling */ |
| 906 | ret = EXCP_INTERRUPT; |
| 907 | break; |
| 908 | case EXIT_REASON_RDMSR: |
| 909 | case EXIT_REASON_WRMSR: |
| 910 | { |
| 911 | hvf_load_regs(cpu); |
| 912 | if (exit_reason == EXIT_REASON_RDMSR) { |
| 913 | hvf_simulate_rdmsr(cpu); |
| 914 | } else { |
| 915 | hvf_simulate_wrmsr(cpu); |
| 916 | } |
| 917 | env->eip += ins_len; |
| 918 | hvf_store_regs(cpu); |
| 919 | break; |
| 920 | } |
| 921 | case EXIT_REASON_CR_ACCESS: { |
| 922 | int cr; |
| 923 | int reg; |
| 924 | |
| 925 | hvf_load_regs(cpu); |
| 926 | cr = exit_qual & 15; |
| 927 | reg = (exit_qual >> 8) & 15; |
| 928 | |
| 929 | switch (cr) { |
| 930 | case 0x0: { |
| 931 | macvm_set_cr0(cpu->accel->fd, RRX(env, reg)); |
| 932 | break; |
| 933 | } |
| 934 | case 4: { |
| 935 | macvm_set_cr4(cpu->accel->fd, RRX(env, reg)); |
| 936 | break; |
| 937 | } |
| 938 | case 8: { |
| 939 | if (exit_qual & 0x10) { |
| 940 | RRX(env, reg) = cpu_get_apic_tpr(x86_cpu->apic_state); |
| 941 | } else { |
| 942 | int tpr = RRX(env, reg); |
| 943 | cpu_set_apic_tpr(x86_cpu->apic_state, tpr); |
| 944 | ret = EXCP_INTERRUPT; |
| 945 | } |
| 946 | break; |
| 947 | } |
| 948 | default: |
| 949 | error_report("Unrecognized CR %d", cr); |
| 950 | abort(); |
| 951 | } |
| 952 | env->eip += ins_len; |
| 953 | hvf_store_regs(cpu); |
| 954 | break; |
| 955 | } |
| 956 | case EXIT_REASON_APIC_ACCESS: { /* TODO */ |
| 957 | struct x86_decode decode; |
| 958 | |
| 959 | hvf_load_regs(cpu); |
| 960 | hvf_load_crs(cpu); |
| 961 | decode_instruction(env, &decode); |
| 962 | exec_instruction(env, &decode); |
| 963 | hvf_store_regs(cpu); |
| 964 | hvf_save_crs(cpu); |
| 965 | break; |
| 966 | } |
| 967 | case EXIT_REASON_TPR: { |
| 968 | ret = 1; |
| 969 | break; |
| 970 | } |
| 971 | case EXIT_REASON_TASK_SWITCH: { |
| 972 | uint64_t vinfo = rvmcs(cpu->accel->fd, VMCS_IDT_VECTORING_INFO); |
| 973 | x86_segment_selector sel = {.sel = exit_qual & 0xffff}; |
| 974 | |
| 975 | vmx_handle_task_switch(cpu, sel, (exit_qual >> 30) & 0x3, |
| 976 | vinfo & VMCS_INTR_VALID, |
| 977 | vinfo & VECTORING_INFO_VECTOR_MASK, |
| 978 | vinfo & VMCS_INTR_T_MASK); |
| 979 | break; |
| 980 | } |
| 981 | case EXIT_REASON_TRIPLE_FAULT: { |
| 982 | qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); |
| 983 | ret = EXCP_INTERRUPT; |
| 984 | break; |
| 985 | } |
| 986 | case EXIT_REASON_RDPMC: |
| 987 | wreg(cpu->accel->fd, HV_X86_RAX, 0); |
| 988 | wreg(cpu->accel->fd, HV_X86_RDX, 0); |
| 989 | macvm_set_rip(cpu, rip + ins_len); |
| 990 | break; |
| 991 | case VMX_REASON_VMCALL: |
| 992 | env->exception_nr = EXCP0D_GPF; |
| 993 | env->exception_injected = 1; |
| 994 | env->has_error_code = true; |
| 995 | env->error_code = 0; |
| 996 | break; |
| 997 | default: |
| 998 | error_report("%llx: unhandled exit %llx", rip, exit_reason); |
| 999 | } |
| 1000 | |
| 1001 | return ret; |
| 1002 | } |
| 1003 | |
| 1004 | int hvf_arch_vcpu_exec(CPUState *cpu) |
| 1005 | { |
| 1006 | int ret = 0; |
| 1007 | |
| 1008 | if (hvf_process_events(cpu)) { |
| 1009 | return EXCP_HLT; |
| 1010 | } |
| 1011 | |
| 1012 | do { |
| 1013 | if (cpu->vcpu_dirty) { |
| 1014 | hvf_arch_put_registers(cpu); |
| 1015 | cpu->vcpu_dirty = false; |
| 1016 | } |
| 1017 | |
| 1018 | if (hvf_inject_interrupts(cpu)) { |
| 1019 | return EXCP_INTERRUPT; |
| 1020 | } |
| 1021 | vmx_update_tpr(cpu); |
| 1022 | |
| 1023 | bql_unlock(); |
| 1024 | if (!cpu_is_bsp(X86_CPU(cpu)) && cpu->halted) { |
| 1025 | bql_lock(); |
| 1026 | return EXCP_HLT; |
| 1027 | } |
| 1028 | |
| 1029 | cpu_exec_start(cpu); |
| 1030 | |
| 1031 | hv_return_t r = hv_vcpu_run_until(cpu->accel->fd, HV_DEADLINE_FOREVER); |
| 1032 | assert_hvf_ok(r); |
| 1033 | |
| 1034 | cpu_exec_end(cpu); |
| 1035 | |
| 1036 | ret = hvf_handle_vmexit(cpu); |
| 1037 | } while (ret == 0); |
| 1038 | |
| 1039 | return ret; |
| 1040 | } |
| 1041 | |
| 1042 | int hvf_arch_insert_sw_breakpoint(CPUState *cpu, struct hvf_sw_breakpoint *bp) |
| 1043 | { |
| 1044 | return -ENOSYS; |
| 1045 | } |
| 1046 | |
| 1047 | int hvf_arch_remove_sw_breakpoint(CPUState *cpu, struct hvf_sw_breakpoint *bp) |
| 1048 | { |
| 1049 | return -ENOSYS; |
| 1050 | } |
| 1051 | |
| 1052 | int hvf_arch_insert_gdbstub_hw_breakpoint(vaddr addr, vaddr len, |
| 1053 | GdbBreakpointType type) |
| 1054 | { |
| 1055 | return -ENOSYS; |
| 1056 | } |
| 1057 | |
| 1058 | int hvf_arch_remove_gdbstub_hw_breakpoint(vaddr addr, vaddr len, |
| 1059 | GdbBreakpointType type) |
| 1060 | { |
| 1061 | return -ENOSYS; |
| 1062 | } |
| 1063 | |
| 1064 | void hvf_arch_remove_all_gdbstub_hw_breakpoints(void) |
| 1065 | { |
| 1066 | } |
| 1067 | |
| 1068 | void hvf_arch_update_guest_debug(CPUState *cpu) |
| 1069 | { |
| 1070 | } |