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1 /*
2 * QEMU TDX support
3 *
4 * Copyright (c) 2025 Intel Corporation
5 *
6 * Author:
7 * Xiaoyao Li <xiaoyao.li@intel.com>
8 *
9 * SPDX-License-Identifier: GPL-2.0-or-later
10 */
11
12 #include "qemu/osdep.h"
13 #include "qemu/error-report.h"
14 #include "qemu/base64.h"
15 #include "qemu/mmap-alloc.h"
16 #include "qapi/error.h"
17 #include "qapi/qapi-visit-sockets.h"
18 #include "qom/object_interfaces.h"
19 #include "crypto/hash.h"
20 #include "system/kvm_int.h"
21 #include "system/runstate.h"
22 #include "system/reset.h"
23 #include "system/system.h"
24 #include "system/ramblock.h"
25 #include "system/address-spaces.h"
26
27 #include <linux/kvm_para.h>
28
29 #include "cpu.h"
30 #include "cpu-internal.h"
31 #include "host-cpu.h"
32 #include "hw/i386/apic_internal.h"
33 #include "hw/i386/apic-msidef.h"
34 #include "hw/i386/e820_memory_layout.h"
35 #include "hw/i386/tdvf.h"
36 #include "hw/i386/x86.h"
37 #include "hw/i386/tdvf-hob.h"
38 #include "hw/pci/msi.h"
39 #include "kvm_i386.h"
40 #include "tdx.h"
41 #include "tdx-quote-generator.h"
42 #include "trace.h"
43
44 #include "standard-headers/asm-x86/kvm_para.h"
45
46 #define TDX_MIN_TSC_FREQUENCY_KHZ (100 * 1000)
47 #define TDX_MAX_TSC_FREQUENCY_KHZ (10 * 1000 * 1000)
48
49 #define TDX_TD_ATTRIBUTES_DEBUG BIT_ULL(0)
50 #define TDX_TD_ATTRIBUTES_SEPT_VE_DISABLE BIT_ULL(28)
51 #define TDX_TD_ATTRIBUTES_PKS BIT_ULL(30)
52 #define TDX_TD_ATTRIBUTES_PERFMON BIT_ULL(63)
53
54 #define TDX_SUPPORTED_TD_ATTRS (TDX_TD_ATTRIBUTES_SEPT_VE_DISABLE |\
55 TDX_TD_ATTRIBUTES_PKS | \
56 TDX_TD_ATTRIBUTES_PERFMON)
57
58 #define TDX_SUPPORTED_KVM_FEATURES ((1U << KVM_FEATURE_NOP_IO_DELAY) | \
59 (1U << KVM_FEATURE_PV_UNHALT) | \
60 (1U << KVM_FEATURE_PV_TLB_FLUSH) | \
61 (1U << KVM_FEATURE_PV_SEND_IPI) | \
62 (1U << KVM_FEATURE_POLL_CONTROL) | \
63 (1U << KVM_FEATURE_PV_SCHED_YIELD) | \
64 (1U << KVM_FEATURE_MSI_EXT_DEST_ID))
65
66 static TdxGuest *tdx_guest;
67
68 static struct kvm_tdx_capabilities *tdx_caps;
69 static struct kvm_cpuid2 *tdx_supported_cpuid;
70
71 /* Valid after kvm_arch_init()->confidential_guest_kvm_init()->tdx_kvm_init() */
72 bool is_tdx_vm(void)
73 {
74 return !!tdx_guest;
75 }
76
77 enum tdx_ioctl_level {
78 TDX_VM_IOCTL,
79 TDX_VCPU_IOCTL,
80 };
81
82 static int tdx_ioctl_internal(enum tdx_ioctl_level level, void *state,
83 int cmd_id, __u32 flags, void *data,
84 Error **errp)
85 {
86 struct kvm_tdx_cmd tdx_cmd = {};
87 int r;
88
89 const char *tdx_ioctl_name[] = {
90 [KVM_TDX_CAPABILITIES] = "KVM_TDX_CAPABILITIES",
91 [KVM_TDX_INIT_VM] = "KVM_TDX_INIT_VM",
92 [KVM_TDX_INIT_VCPU] = "KVM_TDX_INIT_VCPU",
93 [KVM_TDX_INIT_MEM_REGION] = "KVM_TDX_INIT_MEM_REGION",
94 [KVM_TDX_FINALIZE_VM] = "KVM_TDX_FINALIZE_VM",
95 [KVM_TDX_GET_CPUID] = "KVM_TDX_GET_CPUID",
96 };
97
98 tdx_cmd.id = cmd_id;
99 tdx_cmd.flags = flags;
100 tdx_cmd.data = (__u64)(unsigned long)data;
101
102 switch (level) {
103 case TDX_VM_IOCTL:
104 r = kvm_vm_ioctl(kvm_state, KVM_MEMORY_ENCRYPT_OP, &tdx_cmd);
105 break;
106 case TDX_VCPU_IOCTL:
107 r = kvm_vcpu_ioctl(state, KVM_MEMORY_ENCRYPT_OP, &tdx_cmd);
108 break;
109 default:
110 error_setg(errp, "Invalid tdx_ioctl_level %d", level);
111 return -EINVAL;
112 }
113
114 if (r < 0) {
115 error_setg_errno(errp, -r, "TDX ioctl %s failed, hw_errors: 0x%llx",
116 tdx_ioctl_name[cmd_id], tdx_cmd.hw_error);
117 }
118 return r;
119 }
120
121 static inline int tdx_vm_ioctl(int cmd_id, __u32 flags, void *data,
122 Error **errp)
123 {
124 return tdx_ioctl_internal(TDX_VM_IOCTL, NULL, cmd_id, flags, data, errp);
125 }
126
127 static inline int tdx_vcpu_ioctl(CPUState *cpu, int cmd_id, __u32 flags,
128 void *data, Error **errp)
129 {
130 return tdx_ioctl_internal(TDX_VCPU_IOCTL, cpu, cmd_id, flags, data, errp);
131 }
132
133 static int get_tdx_capabilities(Error **errp)
134 {
135 struct kvm_tdx_capabilities *caps;
136 /* 1st generation of TDX reports 6 cpuid configs */
137 int nr_cpuid_configs = 6;
138 size_t size;
139 int r;
140
141 do {
142 Error *local_err = NULL;
143 size = sizeof(struct kvm_tdx_capabilities) +
144 nr_cpuid_configs * sizeof(struct kvm_cpuid_entry2);
145 caps = g_malloc0(size);
146 caps->cpuid.nent = nr_cpuid_configs;
147
148 r = tdx_vm_ioctl(KVM_TDX_CAPABILITIES, 0, caps, &local_err);
149 if (r == -E2BIG) {
150 g_free(caps);
151 nr_cpuid_configs *= 2;
152 if (nr_cpuid_configs > KVM_MAX_CPUID_ENTRIES) {
153 error_report("KVM TDX seems broken that number of CPUID entries"
154 " in kvm_tdx_capabilities exceeds limit: %d",
155 KVM_MAX_CPUID_ENTRIES);
156 error_propagate(errp, local_err);
157 return r;
158 }
159 error_free(local_err);
160 } else if (r < 0) {
161 g_free(caps);
162 error_propagate(errp, local_err);
163 return r;
164 }
165 } while (r == -E2BIG);
166
167 tdx_caps = caps;
168
169 return 0;
170 }
171
172 void tdx_set_tdvf_region(MemoryRegion *tdvf_mr)
173 {
174 assert(!tdx_guest->tdvf_mr);
175 tdx_guest->tdvf_mr = tdvf_mr;
176 }
177
178 static TdxFirmwareEntry *tdx_get_hob_entry(TdxGuest *tdx)
179 {
180 TdxFirmwareEntry *entry;
181
182 for_each_tdx_fw_entry(&tdx->tdvf, entry) {
183 if (entry->type == TDVF_SECTION_TYPE_TD_HOB) {
184 return entry;
185 }
186 }
187 error_report("TDVF metadata doesn't specify TD_HOB location.");
188 exit(1);
189 }
190
191 static void tdx_add_ram_entry(uint64_t address, uint64_t length,
192 enum TdxRamType type)
193 {
194 uint32_t nr_entries = tdx_guest->nr_ram_entries;
195 tdx_guest->ram_entries = g_renew(TdxRamEntry, tdx_guest->ram_entries,
196 nr_entries + 1);
197
198 tdx_guest->ram_entries[nr_entries].address = address;
199 tdx_guest->ram_entries[nr_entries].length = length;
200 tdx_guest->ram_entries[nr_entries].type = type;
201 tdx_guest->nr_ram_entries++;
202 }
203
204 static int tdx_accept_ram_range(uint64_t address, uint64_t length)
205 {
206 uint64_t head_start, tail_start, head_length, tail_length;
207 uint64_t tmp_address, tmp_length;
208 TdxRamEntry *e;
209 int i = 0;
210
211 do {
212 if (i == tdx_guest->nr_ram_entries) {
213 return -1;
214 }
215
216 e = &tdx_guest->ram_entries[i++];
217 } while (address + length <= e->address || address >= e->address + e->length);
218
219 /*
220 * The to-be-accepted ram range must be fully contained by one
221 * RAM entry.
222 */
223 if (e->address > address ||
224 e->address + e->length < address + length) {
225 return -1;
226 }
227
228 if (e->type == TDX_RAM_ADDED) {
229 return 0;
230 }
231
232 tmp_address = e->address;
233 tmp_length = e->length;
234
235 e->address = address;
236 e->length = length;
237 e->type = TDX_RAM_ADDED;
238
239 head_length = address - tmp_address;
240 if (head_length > 0) {
241 head_start = tmp_address;
242 tdx_add_ram_entry(head_start, head_length, TDX_RAM_UNACCEPTED);
243 }
244
245 tail_start = address + length;
246 if (tail_start < tmp_address + tmp_length) {
247 tail_length = tmp_address + tmp_length - tail_start;
248 tdx_add_ram_entry(tail_start, tail_length, TDX_RAM_UNACCEPTED);
249 }
250
251 return 0;
252 }
253
254 static int tdx_ram_entry_compare(const void *lhs_, const void* rhs_)
255 {
256 const TdxRamEntry *lhs = lhs_;
257 const TdxRamEntry *rhs = rhs_;
258
259 if (lhs->address == rhs->address) {
260 return 0;
261 }
262 if (le64_to_cpu(lhs->address) > le64_to_cpu(rhs->address)) {
263 return 1;
264 }
265 return -1;
266 }
267
268 static void tdx_init_ram_entries(void)
269 {
270 unsigned i, j, nr_e820_entries;
271
272 nr_e820_entries = e820_get_table(NULL);
273 tdx_guest->ram_entries = g_new(TdxRamEntry, nr_e820_entries);
274
275 for (i = 0, j = 0; i < nr_e820_entries; i++) {
276 uint64_t addr, len;
277
278 if (e820_get_entry(i, E820_RAM, &addr, &len)) {
279 tdx_guest->ram_entries[j].address = addr;
280 tdx_guest->ram_entries[j].length = len;
281 tdx_guest->ram_entries[j].type = TDX_RAM_UNACCEPTED;
282 j++;
283 }
284 }
285 tdx_guest->nr_ram_entries = j;
286 }
287
288 static void tdx_post_init_vcpus(void)
289 {
290 TdxFirmwareEntry *hob;
291 CPUState *cpu;
292
293 hob = tdx_get_hob_entry(tdx_guest);
294 CPU_FOREACH(cpu) {
295 tdx_vcpu_ioctl(cpu, KVM_TDX_INIT_VCPU, 0, (void *)(uintptr_t)hob->address,
296 &error_fatal);
297 }
298 }
299
300 static void tdx_init_fw_mem_region(void)
301 {
302 TdxFirmware *tdvf = &tdx_guest->tdvf;
303 TdxFirmwareEntry *entry;
304 Error *local_err = NULL;
305 int r;
306
307 for_each_tdx_fw_entry(tdvf, entry) {
308 struct kvm_tdx_init_mem_region region;
309 uint32_t flags;
310
311 region = (struct kvm_tdx_init_mem_region) {
312 .source_addr = (uintptr_t)entry->mem_ptr,
313 .gpa = entry->address,
314 .nr_pages = entry->size >> 12,
315 };
316
317 flags = entry->attributes & TDVF_SECTION_ATTRIBUTES_MR_EXTEND ?
318 KVM_TDX_MEASURE_MEMORY_REGION : 0;
319
320 do {
321 error_free(local_err);
322 local_err = NULL;
323 r = tdx_vcpu_ioctl(first_cpu, KVM_TDX_INIT_MEM_REGION, flags,
324 &region, &local_err);
325 } while (r == -EAGAIN || r == -EINTR);
326 if (r < 0) {
327 error_report_err(local_err);
328 exit(1);
329 }
330
331 if (entry->type == TDVF_SECTION_TYPE_TD_HOB ||
332 entry->type == TDVF_SECTION_TYPE_TEMP_MEM) {
333 qemu_ram_munmap(-1, entry->mem_ptr, entry->size);
334 entry->mem_ptr = NULL;
335 }
336 }
337 }
338
339 static void tdx_finalize_vm(Notifier *notifier, void *unused)
340 {
341 TdxFirmware *tdvf = &tdx_guest->tdvf;
342 TdxFirmwareEntry *entry;
343 RAMBlock *ram_block;
344
345 tdx_init_ram_entries();
346
347 for_each_tdx_fw_entry(tdvf, entry) {
348 switch (entry->type) {
349 case TDVF_SECTION_TYPE_BFV:
350 case TDVF_SECTION_TYPE_CFV:
351 entry->mem_ptr = tdvf->mem_ptr + entry->data_offset;
352 break;
353 case TDVF_SECTION_TYPE_TD_HOB:
354 case TDVF_SECTION_TYPE_TEMP_MEM:
355 entry->mem_ptr = qemu_ram_mmap(-1, entry->size,
356 qemu_real_host_page_size(), 0, 0);
357 if (entry->mem_ptr == MAP_FAILED) {
358 error_report("Failed to mmap memory for TDVF section %d",
359 entry->type);
360 exit(1);
361 }
362 if (tdx_accept_ram_range(entry->address, entry->size)) {
363 error_report("Failed to accept memory for TDVF section %d",
364 entry->type);
365 qemu_ram_munmap(-1, entry->mem_ptr, entry->size);
366 exit(1);
367 }
368 break;
369 default:
370 error_report("Unsupported TDVF section %d", entry->type);
371 exit(1);
372 }
373 }
374
375 qsort(tdx_guest->ram_entries, tdx_guest->nr_ram_entries,
376 sizeof(TdxRamEntry), &tdx_ram_entry_compare);
377
378 tdvf_hob_create(tdx_guest, tdx_get_hob_entry(tdx_guest));
379
380 tdx_post_init_vcpus();
381 tdx_init_fw_mem_region();
382
383 /*
384 * TDVF image has been copied into private region above via
385 * KVM_MEMORY_MAPPING. It becomes useless.
386 */
387 ram_block = tdx_guest->tdvf_mr->ram_block;
388 ram_block_discard_shared_range(ram_block, 0, ram_block->max_length);
389
390 tdx_vm_ioctl(KVM_TDX_FINALIZE_VM, 0, NULL, &error_fatal);
391 CONFIDENTIAL_GUEST_SUPPORT(tdx_guest)->ready = true;
392 }
393
394 static void tdx_handle_reset(Object *obj, ResetType type)
395 {
396 if (!runstate_is_running() && !phase_check(PHASE_MACHINE_READY)) {
397 return;
398 }
399
400 if (!kvm_enable_hypercall(BIT_ULL(KVM_HC_MAP_GPA_RANGE))) {
401 error_setg(&error_fatal, "KVM_HC_MAP_GPA_RANGE not enabled for guest");
402 }
403
404 tdx_finalize_vm(NULL, NULL);
405 trace_tdx_handle_reset();
406 }
407
408 /* TDX guest reset will require us to reinitialize some of tdx guest state. */
409 static int set_tdx_vm_uninitialized(NotifierWithReturn *notifier,
410 void *data, Error** errp)
411 {
412 TdxFirmware *fw = &tdx_guest->tdvf;
413
414 if (!((VmfdChangeNotifier *)data)->pre) {
415 return 0;
416 }
417
418 if (tdx_guest->initialized) {
419 tdx_guest->initialized = false;
420 }
421
422 g_free(tdx_guest->ram_entries);
423
424 /*
425 * the firmware entries will be parsed again, see
426 * x86_firmware_configure() -> tdx_parse_tdvf()
427 */
428 fw->entries = 0;
429 g_free(fw->entries);
430
431 return 0;
432 }
433
434 static NotifierWithReturn tdx_vmfd_change_notifier = {
435 .notify = set_tdx_vm_uninitialized,
436 };
437
438 /*
439 * Some CPUID bits change from fixed1 to configurable bits when TDX module
440 * supports TDX_FEATURES0.VE_REDUCTION. e.g., MCA/MCE/MTRR/CORE_CAPABILITY.
441 *
442 * To make QEMU work with all the versions of TDX module, keep the fixed1 bits
443 * here if they are ever fixed1 bits in any of the version though not fixed1 in
444 * the latest version. Otherwise, with the older version of TDX module, QEMU may
445 * treat the fixed1 bit as unsupported.
446 *
447 * For newer TDX module, it does no harm to keep them in tdx_fixed1_bits even
448 * though they changed to configurable bits. Because tdx_fixed1_bits is used to
449 * setup the supported bits.
450 */
451 KvmCpuidInfo tdx_fixed1_bits = {
452 .cpuid.nent = 8,
453 .entries[0] = {
454 .function = 0x1,
455 .index = 0,
456 .ecx = CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_DTES64 |
457 CPUID_EXT_DSCPL | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 |
458 CPUID_EXT_PDCM | CPUID_EXT_PCID | CPUID_EXT_SSE41 |
459 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE |
460 CPUID_EXT_POPCNT | CPUID_EXT_AES | CPUID_EXT_XSAVE |
461 CPUID_EXT_RDRAND | CPUID_EXT_HYPERVISOR,
462 .edx = CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC |
463 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC |
464 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV |
465 CPUID_PAT | CPUID_CLFLUSH | CPUID_DTS | CPUID_MMX | CPUID_FXSR |
466 CPUID_SSE | CPUID_SSE2,
467 },
468 .entries[1] = {
469 .function = 0x6,
470 .index = 0,
471 .eax = CPUID_6_EAX_ARAT,
472 },
473 .entries[2] = {
474 .function = 0x7,
475 .index = 0,
476 .flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX,
477 .ebx = CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_FDP_EXCPTN_ONLY |
478 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_INVPCID |
479 CPUID_7_0_EBX_ZERO_FCS_FDS | CPUID_7_0_EBX_RDSEED |
480 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
481 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_SHA_NI,
482 .ecx = CPUID_7_0_ECX_BUS_LOCK_DETECT | CPUID_7_0_ECX_MOVDIRI |
483 CPUID_7_0_ECX_MOVDIR64B,
484 .edx = CPUID_7_0_EDX_MD_CLEAR | CPUID_7_0_EDX_SPEC_CTRL |
485 CPUID_7_0_EDX_STIBP | CPUID_7_0_EDX_FLUSH_L1D |
486 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_CORE_CAPABILITY |
487 CPUID_7_0_EDX_SPEC_CTRL_SSBD,
488 },
489 .entries[3] = {
490 .function = 0x7,
491 .index = 2,
492 .flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX,
493 .edx = CPUID_7_2_EDX_PSFD | CPUID_7_2_EDX_IPRED_CTRL |
494 CPUID_7_2_EDX_RRSBA_CTRL | CPUID_7_2_EDX_BHI_CTRL,
495 },
496 .entries[4] = {
497 .function = 0xD,
498 .index = 0,
499 .flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX,
500 .eax = XSTATE_FP_MASK | XSTATE_SSE_MASK,
501 },
502 .entries[5] = {
503 .function = 0xD,
504 .index = 1,
505 .flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX,
506 .eax = CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC|
507 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES,
508 },
509 .entries[6] = {
510 .function = 0x80000001,
511 .index = 0,
512 .ecx = CPUID_EXT3_LAHF_LM | CPUID_EXT3_ABM | CPUID_EXT3_3DNOWPREFETCH,
513 /*
514 * Strictly speaking, SYSCALL is not fixed1 bit since it depends on
515 * the CPU to be in 64-bit mode. But here fixed1 is used to serve the
516 * purpose of supported bits for TDX. In this sense, SYACALL is always
517 * supported.
518 */
519 .edx = CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB |
520 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM,
521 },
522 .entries[7] = {
523 .function = 0x80000007,
524 .index = 0,
525 .edx = CPUID_APM_INVTSC,
526 },
527 };
528
529 typedef struct TdxAttrsMap {
530 uint32_t attr_index;
531 uint32_t cpuid_leaf;
532 uint32_t cpuid_subleaf;
533 int cpuid_reg;
534 uint32_t feat_mask;
535 } TdxAttrsMap;
536
537 static TdxAttrsMap tdx_attrs_maps[] = {
538 {.attr_index = 27,
539 .cpuid_leaf = 7,
540 .cpuid_subleaf = 1,
541 .cpuid_reg = R_EAX,
542 .feat_mask = CPUID_7_1_EAX_LASS,},
543
544 {.attr_index = 30,
545 .cpuid_leaf = 7,
546 .cpuid_subleaf = 0,
547 .cpuid_reg = R_ECX,
548 .feat_mask = CPUID_7_0_ECX_PKS,},
549
550 {.attr_index = 31,
551 .cpuid_leaf = 7,
552 .cpuid_subleaf = 0,
553 .cpuid_reg = R_ECX,
554 .feat_mask = CPUID_7_0_ECX_KeyLocker,},
555 };
556
557 typedef struct TdxXFAMDep {
558 int xfam_bit;
559 FeatureMask feat_mask;
560 } TdxXFAMDep;
561
562 /*
563 * Note, usually the CPUID bits whose virtualization type are "XFAM & Native"
564 * are defined here while "XFAM & Configured & Native" are not. Because the
565 * latter are reported as configurable bits by KVM when they are supported.
566 * And they are not supported when not in the configurable bits list from KVM
567 * even if the corresponding XFAM bit is supported.
568 *
569 * Special cases:
570 *
571 * - AMX alias bits, their type is "CPUID_Enabled & Native" which means their
572 * value is determined by the CPUID bit they are aliased to.
573 *
574 * - AVX10_VL_MASK, their type is "XFAM & CPUID_Enabled & Native" which means
575 * their value is determined by both the corresponding XFAM bit and CPUID bit.
576 *
577 * For simplicity, relax the dependency to related XFAM bit.
578 * tdx_check_features() will eventually catch the unsupported configurations.
579 */
580 TdxXFAMDep tdx_xfam_deps[] = {
581 { XSTATE_YMM_BIT, { FEAT_1_ECX, CPUID_EXT_FMA } },
582 { XSTATE_YMM_BIT, { FEAT_7_0_EBX, CPUID_7_0_EBX_AVX2 } },
583 { XSTATE_OPMASK_BIT, { FEAT_7_0_ECX, CPUID_7_0_ECX_AVX512_VBMI } },
584 { XSTATE_OPMASK_BIT, { FEAT_7_0_EDX, CPUID_7_0_EDX_AVX512_FP16 } },
585 { XSTATE_OPMASK_BIT, { FEAT_24_0_EBX, CPUID_24_0_EBX_AVX10_VL_MASK } },
586 { XSTATE_PT_BIT, { FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT } },
587 { XSTATE_PKRU_BIT, { FEAT_7_0_ECX, CPUID_7_0_ECX_PKU } },
588 { XSTATE_CET_U_BIT, { FEAT_7_0_ECX, CPUID_7_0_ECX_CET_SHSTK } },
589 { XSTATE_CET_U_BIT, { FEAT_7_0_EDX, CPUID_7_0_EDX_CET_IBT } },
590 { XSTATE_XTILE_CFG_BIT, { FEAT_7_0_EDX, CPUID_7_0_EDX_AMX_BF16 } },
591 { XSTATE_XTILE_CFG_BIT, { FEAT_7_0_EDX, CPUID_7_0_EDX_AMX_TILE } },
592 { XSTATE_XTILE_CFG_BIT, { FEAT_7_0_EDX, CPUID_7_0_EDX_AMX_INT8 } },
593 { XSTATE_XTILE_CFG_BIT, { FEAT_1E_1_EAX, CPUID_1E_1_EAX_AMX_INT8_ALIAS } },
594 { XSTATE_XTILE_CFG_BIT, { FEAT_1E_1_EAX, CPUID_1E_1_EAX_AMX_BF16_ALIAS } },
595 { XSTATE_XTILE_CFG_BIT, { FEAT_1E_1_EAX, CPUID_1E_1_EAX_AMX_COMPLEX_ALIAS } },
596 { XSTATE_XTILE_CFG_BIT, { FEAT_1E_1_EAX, CPUID_1E_1_EAX_AMX_FP16_ALIAS } },
597 };
598
599 static struct kvm_cpuid_entry2 *find_in_supported_entry(uint32_t function,
600 uint32_t index)
601 {
602 struct kvm_cpuid_entry2 *e;
603
604 e = cpuid_find_entry(tdx_supported_cpuid, function, index);
605 if (!e) {
606 if (tdx_supported_cpuid->nent >= KVM_MAX_CPUID_ENTRIES) {
607 error_report("tdx_supported_cpuid requries more space than %d entries",
608 KVM_MAX_CPUID_ENTRIES);
609 exit(1);
610 }
611 e = &tdx_supported_cpuid->entries[tdx_supported_cpuid->nent++];
612 e->function = function;
613 e->index = index;
614 }
615
616 return e;
617 }
618
619 static void tdx_add_supported_cpuid_by_fixed1_bits(void)
620 {
621 struct kvm_cpuid_entry2 *e, *e1;
622 int i;
623
624 for (i = 0; i < tdx_fixed1_bits.cpuid.nent; i++) {
625 e = &tdx_fixed1_bits.entries[i];
626
627 e1 = find_in_supported_entry(e->function, e->index);
628 e1->eax |= e->eax;
629 e1->ebx |= e->ebx;
630 e1->ecx |= e->ecx;
631 e1->edx |= e->edx;
632 }
633 }
634
635 static void tdx_add_supported_cpuid_by_attrs(void)
636 {
637 struct kvm_cpuid_entry2 *e;
638 TdxAttrsMap *map;
639 int i;
640
641 for (i = 0; i < ARRAY_SIZE(tdx_attrs_maps); i++) {
642 map = &tdx_attrs_maps[i];
643 if (!((1ULL << map->attr_index) & tdx_caps->supported_attrs)) {
644 continue;
645 }
646
647 e = find_in_supported_entry(map->cpuid_leaf, map->cpuid_subleaf);
648
649 switch(map->cpuid_reg) {
650 case R_EAX:
651 e->eax |= map->feat_mask;
652 break;
653 case R_EBX:
654 e->ebx |= map->feat_mask;
655 break;
656 case R_ECX:
657 e->ecx |= map->feat_mask;
658 break;
659 case R_EDX:
660 e->edx |= map->feat_mask;
661 break;
662 }
663 }
664 }
665
666 static void tdx_add_supported_cpuid_by_xfam(void)
667 {
668 struct kvm_cpuid_entry2 *e;
669 int i;
670
671 const TdxXFAMDep *xfam_dep;
672 const FeatureWordInfo *f;
673 for (i = 0; i < ARRAY_SIZE(tdx_xfam_deps); i++) {
674 xfam_dep = &tdx_xfam_deps[i];
675 if (!((1ULL << xfam_dep->xfam_bit) & tdx_caps->supported_xfam)) {
676 continue;
677 }
678
679 f = &feature_word_info[xfam_dep->feat_mask.index];
680 if (f->type != CPUID_FEATURE_WORD) {
681 continue;
682 }
683
684 e = find_in_supported_entry(f->cpuid.eax, f->cpuid.ecx);
685 switch(f->cpuid.reg) {
686 case R_EAX:
687 e->eax |= xfam_dep->feat_mask.mask;
688 break;
689 case R_EBX:
690 e->ebx |= xfam_dep->feat_mask.mask;
691 break;
692 case R_ECX:
693 e->ecx |= xfam_dep->feat_mask.mask;
694 break;
695 case R_EDX:
696 e->edx |= xfam_dep->feat_mask.mask;
697 break;
698 }
699 }
700
701 e = find_in_supported_entry(0xd, 0);
702 e->eax |= (tdx_caps->supported_xfam & CPUID_XSTATE_XCR0_MASK);
703 e->edx |= (tdx_caps->supported_xfam & CPUID_XSTATE_XCR0_MASK) >> 32;
704
705 e = find_in_supported_entry(0xd, 1);
706 /*
707 * Mark XFD always support for TDX, it will be cleared finally in
708 * tdx_adjust_cpuid_features() if XFD is unavailable on the hardware
709 * because in this case the original data has it as 0.
710 */
711 e->eax |= CPUID_XSAVE_XFD;
712 e->ecx |= (tdx_caps->supported_xfam & CPUID_XSTATE_XSS_MASK);
713 e->edx |= (tdx_caps->supported_xfam & CPUID_XSTATE_XSS_MASK) >> 32;
714 }
715
716 static void tdx_add_supported_kvm_features(void)
717 {
718 struct kvm_cpuid_entry2 *e;
719
720 e = find_in_supported_entry(0x40000001, 0);
721 e->eax = TDX_SUPPORTED_KVM_FEATURES;
722 }
723
724 static void tdx_setup_supported_cpuid(void)
725 {
726 if (tdx_supported_cpuid) {
727 return;
728 }
729
730 tdx_supported_cpuid = g_malloc0(sizeof(*tdx_supported_cpuid) +
731 KVM_MAX_CPUID_ENTRIES * sizeof(struct kvm_cpuid_entry2));
732
733 memcpy(tdx_supported_cpuid->entries, tdx_caps->cpuid.entries,
734 tdx_caps->cpuid.nent * sizeof(struct kvm_cpuid_entry2));
735 tdx_supported_cpuid->nent = tdx_caps->cpuid.nent;
736
737 tdx_add_supported_cpuid_by_fixed1_bits();
738 tdx_add_supported_cpuid_by_attrs();
739 tdx_add_supported_cpuid_by_xfam();
740
741 tdx_add_supported_kvm_features();
742 }
743
744 static int tdx_kvm_init(ConfidentialGuestSupport *cgs, Error **errp)
745 {
746 MachineState *ms = MACHINE(qdev_get_machine());
747 X86MachineState *x86ms = X86_MACHINE(ms);
748 TdxGuest *tdx = TDX_GUEST(cgs);
749 int r = 0;
750
751 kvm_mark_guest_state_protected();
752
753 if (x86ms->smm == ON_OFF_AUTO_AUTO) {
754 x86ms->smm = ON_OFF_AUTO_OFF;
755 } else if (x86ms->smm == ON_OFF_AUTO_ON) {
756 error_setg(errp, "TDX VM doesn't support SMM");
757 return -EINVAL;
758 }
759
760 if (x86ms->pic == ON_OFF_AUTO_AUTO) {
761 x86ms->pic = ON_OFF_AUTO_OFF;
762 } else if (x86ms->pic == ON_OFF_AUTO_ON) {
763 error_setg(errp, "TDX VM doesn't support PIC");
764 return -EINVAL;
765 }
766
767 if (kvm_state->kernel_irqchip_split == ON_OFF_AUTO_AUTO) {
768 kvm_state->kernel_irqchip_split = ON_OFF_AUTO_ON;
769 } else if (kvm_state->kernel_irqchip_split != ON_OFF_AUTO_ON) {
770 error_setg(errp, "TDX VM requires kernel_irqchip to be split");
771 return -EINVAL;
772 }
773
774 if (!tdx_caps) {
775 r = get_tdx_capabilities(errp);
776 if (r) {
777 return r;
778 }
779 }
780
781 tdx_setup_supported_cpuid();
782
783 /* TDX relies on KVM_HC_MAP_GPA_RANGE to handle TDG.VP.VMCALL<MapGPA> */
784 if (!kvm_enable_hypercall(BIT_ULL(KVM_HC_MAP_GPA_RANGE))) {
785 return -EOPNOTSUPP;
786 }
787
788 /*
789 * Set kvm_readonly_mem_allowed to false, because TDX only supports readonly
790 * memory for shared memory but not for private memory. Besides, whether a
791 * memslot is private or shared is not determined by QEMU.
792 *
793 * Thus, just mark readonly memory not supported for simplicity.
794 */
795 kvm_readonly_mem_allowed = false;
796
797 tdx_guest = tdx;
798 return 0;
799 }
800
801 static int tdx_kvm_type(X86ConfidentialGuest *cg)
802 {
803 /* Do the object check */
804 TDX_GUEST(cg);
805
806 return KVM_X86_TDX_VM;
807 }
808
809 static void tdx_cpu_instance_init(X86ConfidentialGuest *cg, CPUState *cpu)
810 {
811 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
812 X86CPU *x86cpu = X86_CPU(cpu);
813
814 if (xcc->model) {
815 error_report("Named cpu model is not supported for TDX yet!");
816 exit(1);
817 }
818
819 object_property_set_bool(OBJECT(cpu), "pmu", false, &error_abort);
820
821 /* invtsc is fixed1 for TD guest */
822 object_property_set_bool(OBJECT(cpu), "invtsc", true, &error_abort);
823
824 x86cpu->force_cpuid_0x1f = true;
825 }
826
827 static uint32_t tdx_adjust_cpuid_features(X86ConfidentialGuest *cg,
828 uint32_t feature, uint32_t index,
829 int reg, uint32_t value)
830 {
831 struct kvm_cpuid_entry2 *e;
832
833 e = cpuid_find_entry(&tdx_fixed1_bits.cpuid, feature, index);
834 if (e) {
835 value |= cpuid_entry_get_reg(e, reg);
836 }
837
838 if (is_feature_word_cpuid(feature, index, reg)) {
839 e = cpuid_find_entry(tdx_supported_cpuid, feature, index);
840 if (e) {
841 value &= cpuid_entry_get_reg(e, reg);
842 }
843 }
844
845 return value;
846 }
847
848 static struct kvm_cpuid2 *tdx_fetch_cpuid(CPUState *cpu, int *ret)
849 {
850 struct kvm_cpuid2 *fetch_cpuid;
851 int size = KVM_MAX_CPUID_ENTRIES;
852 Error *local_err = NULL;
853 int r;
854
855 do {
856 error_free(local_err);
857 local_err = NULL;
858
859 fetch_cpuid = g_malloc0(sizeof(*fetch_cpuid) +
860 sizeof(struct kvm_cpuid_entry2) * size);
861 fetch_cpuid->nent = size;
862 r = tdx_vcpu_ioctl(cpu, KVM_TDX_GET_CPUID, 0, fetch_cpuid, &local_err);
863 if (r == -E2BIG) {
864 g_free(fetch_cpuid);
865 size *= 2;
866 }
867 } while (r == -E2BIG);
868
869 if (r < 0) {
870 error_report_err(local_err);
871 *ret = r;
872 return NULL;
873 }
874
875 return fetch_cpuid;
876 }
877
878 static int tdx_check_features(X86ConfidentialGuest *cg, CPUState *cs)
879 {
880 uint64_t actual, requested, unavailable, forced_on;
881 g_autofree struct kvm_cpuid2 *fetch_cpuid;
882 const char *forced_on_prefix = NULL;
883 const char *unav_prefix = NULL;
884 struct kvm_cpuid_entry2 *entry;
885 X86CPU *cpu = X86_CPU(cs);
886 CPUX86State *env = &cpu->env;
887 FeatureWordInfo *wi;
888 FeatureWord w;
889 bool mismatch = false;
890 int r = -1;
891
892 fetch_cpuid = tdx_fetch_cpuid(cs, &r);
893 if (!fetch_cpuid) {
894 return r;
895 }
896
897 if (cpu->check_cpuid || cpu->enforce_cpuid) {
898 unav_prefix = "TDX doesn't support requested feature";
899 forced_on_prefix = "TDX forcibly sets the feature";
900 }
901
902 for (w = 0; w < FEATURE_WORDS; w++) {
903 wi = &feature_word_info[w];
904 actual = 0;
905
906 switch (wi->type) {
907 case CPUID_FEATURE_WORD:
908 entry = cpuid_find_entry(fetch_cpuid, wi->cpuid.eax, wi->cpuid.ecx);
909 if (!entry) {
910 /*
911 * If KVM doesn't report it means it's totally configurable
912 * by QEMU
913 */
914 continue;
915 }
916
917 actual = cpuid_entry_get_reg(entry, wi->cpuid.reg);
918 break;
919 case MSR_FEATURE_WORD:
920 /*
921 * TODO:
922 * validate MSR features when KVM has interface report them.
923 */
924 continue;
925 }
926
927 /* Fixup for special cases */
928 switch (w) {
929 case FEAT_8000_0001_EDX:
930 /*
931 * Intel enumerates SYSCALL bit as 1 only when processor in 64-bit
932 * mode and before vcpu running it's not in 64-bit mode.
933 */
934 actual |= CPUID_EXT2_SYSCALL;
935 break;
936 default:
937 break;
938 }
939
940 requested = env->features[w];
941 unavailable = requested & ~actual;
942 mark_unavailable_features(cpu, w, unavailable, unav_prefix);
943 if (unavailable) {
944 mismatch = true;
945 }
946
947 forced_on = actual & ~requested;
948 mark_forced_on_features(cpu, w, forced_on, forced_on_prefix);
949 if (forced_on) {
950 mismatch = true;
951 }
952 }
953
954 if (cpu->enforce_cpuid && mismatch) {
955 return -EINVAL;
956 }
957
958 if (cpu->phys_bits != host_cpu_phys_bits()) {
959 error_report("TDX requires guest CPU physical bits (%u) "
960 "to match host CPU physical bits (%u)",
961 cpu->phys_bits, host_cpu_phys_bits());
962 return -EINVAL;
963 }
964
965 return 0;
966 }
967
968 static int tdx_validate_attributes(TdxGuest *tdx, Error **errp)
969 {
970 if ((tdx->attributes & ~tdx_caps->supported_attrs)) {
971 error_setg(errp, "Invalid attributes 0x%"PRIx64" for TDX VM "
972 "(KVM supported: 0x%"PRIx64")", tdx->attributes,
973 (uint64_t)tdx_caps->supported_attrs);
974 return -1;
975 }
976
977 if (tdx->attributes & ~TDX_SUPPORTED_TD_ATTRS) {
978 error_setg(errp, "Some QEMU unsupported TD attribute bits being "
979 "requested: 0x%"PRIx64" (QEMU supported: 0x%"PRIx64")",
980 tdx->attributes, (uint64_t)TDX_SUPPORTED_TD_ATTRS);
981 return -1;
982 }
983
984 return 0;
985 }
986
987 static int setup_td_guest_attributes(X86CPU *x86cpu, Error **errp)
988 {
989 CPUX86State *env = &x86cpu->env;
990
991 tdx_guest->attributes |= (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_PKS) ?
992 TDX_TD_ATTRIBUTES_PKS : 0;
993 tdx_guest->attributes |= x86cpu->enable_pmu ? TDX_TD_ATTRIBUTES_PERFMON : 0;
994
995 return tdx_validate_attributes(tdx_guest, errp);
996 }
997
998 static int setup_td_xfam(X86CPU *x86cpu, Error **errp)
999 {
1000 CPUX86State *env = &x86cpu->env;
1001 uint64_t xfam;
1002
1003 xfam = env->features[FEAT_XSAVE_XCR0_LO] |
1004 env->features[FEAT_XSAVE_XCR0_HI] |
1005 env->features[FEAT_XSAVE_XSS_LO] |
1006 env->features[FEAT_XSAVE_XSS_HI];
1007
1008 if (xfam & ~tdx_caps->supported_xfam) {
1009 error_setg(errp, "Invalid XFAM 0x%"PRIx64" for TDX VM (supported: 0x%"PRIx64"))",
1010 xfam, (uint64_t)tdx_caps->supported_xfam);
1011 return -1;
1012 }
1013
1014 tdx_guest->xfam = xfam;
1015 return 0;
1016 }
1017
1018 static void tdx_filter_cpuid(struct kvm_cpuid2 *cpuids)
1019 {
1020 int i, dest_cnt = 0;
1021 struct kvm_cpuid_entry2 *src, *dest, *conf;
1022
1023 for (i = 0; i < cpuids->nent; i++) {
1024 src = cpuids->entries + i;
1025 conf = cpuid_find_entry(&tdx_caps->cpuid, src->function, src->index);
1026 if (!conf) {
1027 continue;
1028 }
1029 dest = cpuids->entries + dest_cnt;
1030
1031 dest->function = src->function;
1032 dest->index = src->index;
1033 dest->flags = src->flags;
1034 dest->eax = src->eax & conf->eax;
1035 dest->ebx = src->ebx & conf->ebx;
1036 dest->ecx = src->ecx & conf->ecx;
1037 dest->edx = src->edx & conf->edx;
1038
1039 dest_cnt++;
1040 }
1041 cpuids->nent = dest_cnt++;
1042 }
1043
1044 int tdx_pre_create_vcpu(CPUState *cpu, Error **errp)
1045 {
1046 X86CPU *x86cpu = X86_CPU(cpu);
1047 CPUX86State *env = &x86cpu->env;
1048 g_autofree struct kvm_tdx_init_vm *init_vm = NULL;
1049 Error *local_err = NULL;
1050 size_t data_len;
1051 int retry = 10000;
1052 int r = 0;
1053
1054 QEMU_LOCK_GUARD(&tdx_guest->lock);
1055 if (tdx_guest->initialized) {
1056 return r;
1057 }
1058
1059 init_vm = g_malloc0(sizeof(struct kvm_tdx_init_vm) +
1060 sizeof(struct kvm_cpuid_entry2) * KVM_MAX_CPUID_ENTRIES);
1061
1062 if (!kvm_check_extension(kvm_state, KVM_CAP_X86_APIC_BUS_CYCLES_NS)) {
1063 error_setg(errp, "KVM doesn't support KVM_CAP_X86_APIC_BUS_CYCLES_NS");
1064 return -EOPNOTSUPP;
1065 }
1066
1067 r = kvm_vm_enable_cap(kvm_state, KVM_CAP_X86_APIC_BUS_CYCLES_NS,
1068 0, TDX_APIC_BUS_CYCLES_NS);
1069 if (r < 0) {
1070 error_setg_errno(errp, -r,
1071 "Unable to set core crystal clock frequency to 25MHz");
1072 return r;
1073 }
1074
1075 if (env->tsc_khz && (env->tsc_khz < TDX_MIN_TSC_FREQUENCY_KHZ ||
1076 env->tsc_khz > TDX_MAX_TSC_FREQUENCY_KHZ)) {
1077 error_setg(errp, "Invalid TSC %"PRId64" KHz, must specify cpu_frequency "
1078 "between [%d, %d] kHz", env->tsc_khz,
1079 TDX_MIN_TSC_FREQUENCY_KHZ, TDX_MAX_TSC_FREQUENCY_KHZ);
1080 return -EINVAL;
1081 }
1082
1083 if (env->tsc_khz % (25 * 1000)) {
1084 error_setg(errp, "Invalid TSC %"PRId64" KHz, it must be multiple of 25MHz",
1085 env->tsc_khz);
1086 return -EINVAL;
1087 }
1088
1089 /* it's safe even env->tsc_khz is 0. KVM uses host's tsc_khz in this case */
1090 r = kvm_vm_ioctl(kvm_state, KVM_SET_TSC_KHZ, env->tsc_khz);
1091 if (r < 0) {
1092 error_setg_errno(errp, -r, "Unable to set TSC frequency to %"PRId64" kHz",
1093 env->tsc_khz);
1094 return r;
1095 }
1096
1097 if (tdx_guest->mrconfigid) {
1098 g_autofree uint8_t *data = qbase64_decode(tdx_guest->mrconfigid,
1099 strlen(tdx_guest->mrconfigid), &data_len, errp);
1100 if (!data) {
1101 return -1;
1102 }
1103 if (data_len != QCRYPTO_HASH_DIGEST_LEN_SHA384) {
1104 error_setg(errp, "TDX 'mrconfigid' sha384 digest was %ld bytes, "
1105 "expected %d bytes", data_len,
1106 QCRYPTO_HASH_DIGEST_LEN_SHA384);
1107 return -1;
1108 }
1109 memcpy(init_vm->mrconfigid, data, data_len);
1110 }
1111
1112 if (tdx_guest->mrowner) {
1113 g_autofree uint8_t *data = qbase64_decode(tdx_guest->mrowner,
1114 strlen(tdx_guest->mrowner), &data_len, errp);
1115 if (!data) {
1116 return -1;
1117 }
1118 if (data_len != QCRYPTO_HASH_DIGEST_LEN_SHA384) {
1119 error_setg(errp, "TDX 'mrowner' sha384 digest was %ld bytes, "
1120 "expected %d bytes", data_len,
1121 QCRYPTO_HASH_DIGEST_LEN_SHA384);
1122 return -1;
1123 }
1124 memcpy(init_vm->mrowner, data, data_len);
1125 }
1126
1127 if (tdx_guest->mrownerconfig) {
1128 g_autofree uint8_t *data = qbase64_decode(tdx_guest->mrownerconfig,
1129 strlen(tdx_guest->mrownerconfig), &data_len, errp);
1130 if (!data) {
1131 return -1;
1132 }
1133 if (data_len != QCRYPTO_HASH_DIGEST_LEN_SHA384) {
1134 error_setg(errp, "TDX 'mrownerconfig' sha384 digest was %ld bytes, "
1135 "expected %d bytes", data_len,
1136 QCRYPTO_HASH_DIGEST_LEN_SHA384);
1137 return -1;
1138 }
1139 memcpy(init_vm->mrownerconfig, data, data_len);
1140 }
1141
1142 r = setup_td_guest_attributes(x86cpu, errp);
1143 if (r) {
1144 return r;
1145 }
1146
1147 r = setup_td_xfam(x86cpu, errp);
1148 if (r) {
1149 return r;
1150 }
1151
1152 init_vm->cpuid.nent = kvm_x86_build_cpuid(env, init_vm->cpuid.entries, 0);
1153 tdx_filter_cpuid(&init_vm->cpuid);
1154
1155 init_vm->attributes = tdx_guest->attributes;
1156 init_vm->xfam = tdx_guest->xfam;
1157
1158 /*
1159 * KVM_TDX_INIT_VM gets -EAGAIN when KVM side SEAMCALL(TDH_MNG_CREATE)
1160 * gets TDX_RND_NO_ENTROPY due to Random number generation (e.g., RDRAND or
1161 * RDSEED) is busy.
1162 *
1163 * Retry for the case.
1164 */
1165 do {
1166 error_free(local_err);
1167 local_err = NULL;
1168 r = tdx_vm_ioctl(KVM_TDX_INIT_VM, 0, init_vm, &local_err);
1169 } while (r == -EAGAIN && --retry);
1170
1171 if (r < 0) {
1172 if (!retry) {
1173 error_append_hint(&local_err, "Hardware RNG (Random Number "
1174 "Generator) is busy occupied by someone (via RDRAND/RDSEED) "
1175 "maliciously, which leads to KVM_TDX_INIT_VM keeping failure "
1176 "due to lack of entropy.\n");
1177 }
1178 error_propagate(errp, local_err);
1179 return r;
1180 }
1181
1182 tdx_guest->initialized = true;
1183
1184 return 0;
1185 }
1186
1187 int tdx_parse_tdvf(void *flash_ptr, int size)
1188 {
1189 return tdvf_parse_metadata(&tdx_guest->tdvf, flash_ptr, size);
1190 }
1191
1192 static void tdx_inject_interrupt(TdxGuest *tdx)
1193 {
1194 int ret;
1195 uint32_t apicid, vector;
1196
1197 qemu_mutex_lock(&tdx->lock);
1198 vector = tdx->event_notify_vector;
1199 apicid = tdx->event_notify_apicid;
1200 qemu_mutex_unlock(&tdx->lock);
1201 if (vector < 32 || vector > 255) {
1202 return;
1203 }
1204
1205 MSIMessage msg = {
1206 .address = ((apicid & 0xff) << MSI_ADDR_DEST_ID_SHIFT) |
1207 (((uint64_t)apicid & 0xffffff00) << 32),
1208 .data = vector | (APIC_DM_FIXED << MSI_DATA_DELIVERY_MODE_SHIFT),
1209 };
1210
1211 ret = kvm_irqchip_send_msi(kvm_state, msg);
1212 if (ret < 0) {
1213 /* In this case, no better way to tell it to guest. Log it. */
1214 error_report("TDX: injection interrupt %d failed, interrupt lost (%s).",
1215 vector, strerror(-ret));
1216 }
1217 }
1218
1219 static void tdx_get_quote_completion(TdxGenerateQuoteTask *task)
1220 {
1221 TdxGuest *tdx = task->opaque;
1222 int ret;
1223
1224 /* Maintain the number of in-flight requests. */
1225 qemu_mutex_lock(&tdx->lock);
1226 tdx->num--;
1227 qemu_mutex_unlock(&tdx->lock);
1228
1229 if (task->status_code == TDX_VP_GET_QUOTE_SUCCESS) {
1230 ret = address_space_write(&address_space_memory, task->payload_gpa,
1231 MEMTXATTRS_UNSPECIFIED, task->receive_buf,
1232 task->receive_buf_received);
1233 if (ret != MEMTX_OK) {
1234 error_report("TDX: get-quote: failed to write quote data.");
1235 } else {
1236 task->hdr.out_len = cpu_to_le64(task->receive_buf_received);
1237 }
1238 }
1239 task->hdr.error_code = cpu_to_le64(task->status_code);
1240
1241 /* Publish the response contents before marking this request completed. */
1242 smp_wmb();
1243 ret = address_space_write(&address_space_memory, task->buf_gpa,
1244 MEMTXATTRS_UNSPECIFIED, &task->hdr,
1245 TDX_GET_QUOTE_HDR_SIZE);
1246 if (ret != MEMTX_OK) {
1247 error_report("TDX: get-quote: failed to update GetQuote header.");
1248 }
1249
1250 tdx_inject_interrupt(tdx);
1251
1252 g_free(task->send_data);
1253 g_free(task->receive_buf);
1254 g_free(task);
1255 object_unref(tdx);
1256 }
1257
1258 void tdx_handle_get_quote(X86CPU *cpu, struct kvm_run *run)
1259 {
1260 TdxGenerateQuoteTask *task;
1261 struct tdx_get_quote_header hdr;
1262 hwaddr buf_gpa = run->tdx.get_quote.gpa;
1263 uint64_t buf_len = run->tdx.get_quote.size;
1264
1265 QEMU_BUILD_BUG_ON(sizeof(struct tdx_get_quote_header) != TDX_GET_QUOTE_HDR_SIZE);
1266
1267 run->tdx.get_quote.ret = TDG_VP_VMCALL_INVALID_OPERAND;
1268
1269 if (buf_len == 0) {
1270 return;
1271 }
1272
1273 if (!QEMU_IS_ALIGNED(buf_gpa, 4096) || !QEMU_IS_ALIGNED(buf_len, 4096)) {
1274 run->tdx.get_quote.ret = TDG_VP_VMCALL_ALIGN_ERROR;
1275 return;
1276 }
1277
1278 if (address_space_read(&address_space_memory, buf_gpa, MEMTXATTRS_UNSPECIFIED,
1279 &hdr, TDX_GET_QUOTE_HDR_SIZE) != MEMTX_OK) {
1280 error_report("TDX: get-quote: failed to read GetQuote header.");
1281 return;
1282 }
1283
1284 if (le64_to_cpu(hdr.structure_version) != TDX_GET_QUOTE_STRUCTURE_VERSION) {
1285 return;
1286 }
1287
1288 /* Only safe-guard check to avoid too large buffer size. */
1289 if (buf_len > TDX_GET_QUOTE_MAX_BUF_LEN ||
1290 le32_to_cpu(hdr.in_len) > buf_len - TDX_GET_QUOTE_HDR_SIZE) {
1291 return;
1292 }
1293
1294 if (!tdx_guest->qg_sock_addr) {
1295 hdr.error_code = cpu_to_le64(TDX_VP_GET_QUOTE_QGS_UNAVAILABLE);
1296 if (address_space_write(&address_space_memory, buf_gpa,
1297 MEMTXATTRS_UNSPECIFIED,
1298 &hdr, TDX_GET_QUOTE_HDR_SIZE) != MEMTX_OK) {
1299 error_report("TDX: failed to update GetQuote header.");
1300 return;
1301 }
1302 run->tdx.get_quote.ret = TDG_VP_VMCALL_SUCCESS;
1303 return;
1304 }
1305
1306 qemu_mutex_lock(&tdx_guest->lock);
1307 if (tdx_guest->num >= TDX_MAX_GET_QUOTE_REQUEST) {
1308 qemu_mutex_unlock(&tdx_guest->lock);
1309 run->tdx.get_quote.ret = TDG_VP_VMCALL_RETRY;
1310 return;
1311 }
1312 tdx_guest->num++;
1313 qemu_mutex_unlock(&tdx_guest->lock);
1314
1315 task = g_new(TdxGenerateQuoteTask, 1);
1316 task->buf_gpa = buf_gpa;
1317 task->payload_gpa = buf_gpa + TDX_GET_QUOTE_HDR_SIZE;
1318 task->payload_len = buf_len - TDX_GET_QUOTE_HDR_SIZE;
1319 task->hdr = hdr;
1320 task->completion = tdx_get_quote_completion;
1321
1322 task->send_data_size = le32_to_cpu(hdr.in_len);
1323 task->send_data = g_malloc(task->send_data_size);
1324 task->send_data_sent = 0;
1325
1326 if (address_space_read(&address_space_memory, task->payload_gpa,
1327 MEMTXATTRS_UNSPECIFIED, task->send_data,
1328 task->send_data_size) != MEMTX_OK) {
1329 goto out_free;
1330 }
1331
1332 /* Mark the buffer in-flight. */
1333 hdr.error_code = cpu_to_le64(TDX_VP_GET_QUOTE_IN_FLIGHT);
1334 if (address_space_write(&address_space_memory, buf_gpa,
1335 MEMTXATTRS_UNSPECIFIED,
1336 &hdr, TDX_GET_QUOTE_HDR_SIZE) != MEMTX_OK) {
1337 goto out_free;
1338 }
1339
1340 task->receive_buf = g_malloc0(task->payload_len);
1341 task->receive_buf_received = 0;
1342 task->opaque = tdx_guest;
1343
1344 object_ref(tdx_guest);
1345 tdx_generate_quote(task, tdx_guest->qg_sock_addr);
1346 run->tdx.get_quote.ret = TDG_VP_VMCALL_SUCCESS;
1347 return;
1348
1349 out_free:
1350 g_free(task->send_data);
1351 g_free(task);
1352 }
1353
1354 #define SUPPORTED_TDVMCALLINFO_1_R11 (TDG_VP_VMCALL_SUBFUNC_SET_EVENT_NOTIFY_INTERRUPT)
1355 #define SUPPORTED_TDVMCALLINFO_1_R12 (0)
1356
1357 void tdx_handle_get_tdvmcall_info(X86CPU *cpu, struct kvm_run *run)
1358 {
1359 if (run->tdx.get_tdvmcall_info.leaf != 1) {
1360 return;
1361 }
1362
1363 run->tdx.get_tdvmcall_info.r11 = (tdx_caps->user_tdvmcallinfo_1_r11 &
1364 SUPPORTED_TDVMCALLINFO_1_R11) |
1365 tdx_caps->kernel_tdvmcallinfo_1_r11;
1366 run->tdx.get_tdvmcall_info.r12 = (tdx_caps->user_tdvmcallinfo_1_r12 &
1367 SUPPORTED_TDVMCALLINFO_1_R12) |
1368 tdx_caps->kernel_tdvmcallinfo_1_r12;
1369 run->tdx.get_tdvmcall_info.r13 = 0;
1370 run->tdx.get_tdvmcall_info.r14 = 0;
1371
1372 run->tdx.get_tdvmcall_info.ret = TDG_VP_VMCALL_SUCCESS;
1373 }
1374
1375 void tdx_handle_setup_event_notify_interrupt(X86CPU *cpu, struct kvm_run *run)
1376 {
1377 uint64_t vector = run->tdx.setup_event_notify.vector;
1378
1379 if (vector >= 32 && vector < 256) {
1380 qemu_mutex_lock(&tdx_guest->lock);
1381 tdx_guest->event_notify_vector = vector;
1382 tdx_guest->event_notify_apicid = cpu->apic_id;
1383 qemu_mutex_unlock(&tdx_guest->lock);
1384 run->tdx.setup_event_notify.ret = TDG_VP_VMCALL_SUCCESS;
1385 } else {
1386 run->tdx.setup_event_notify.ret = TDG_VP_VMCALL_INVALID_OPERAND;
1387 }
1388 }
1389
1390 static void tdx_panicked_on_fatal_error(X86CPU *cpu, uint64_t error_code,
1391 char *message, bool has_gpa,
1392 uint64_t gpa)
1393 {
1394 GuestPanicInformation *panic_info;
1395
1396 panic_info = g_new0(GuestPanicInformation, 1);
1397 panic_info->type = GUEST_PANIC_INFORMATION_TYPE_TDX;
1398 panic_info->u.tdx.error_code = (uint32_t) error_code;
1399 panic_info->u.tdx.message = message;
1400 panic_info->u.tdx.gpa = gpa;
1401 panic_info->u.tdx.has_gpa = has_gpa;
1402
1403 qemu_system_guest_panicked(panic_info);
1404 }
1405
1406 /*
1407 * Only 8 registers can contain valid ASCII byte stream to form the fatal
1408 * message, and their sequence is: R14, R15, RBX, RDI, RSI, R8, R9, RDX
1409 */
1410 #define TDX_FATAL_MESSAGE_MAX 64
1411
1412 #define TDX_REPORT_FATAL_ERROR_GPA_VALID BIT_ULL(63)
1413
1414 int tdx_handle_report_fatal_error(X86CPU *cpu, struct kvm_run *run)
1415 {
1416 uint64_t error_code = run->system_event.data[R_R12];
1417 uint64_t reg_mask = run->system_event.data[R_ECX];
1418 char *message = NULL;
1419 uint64_t *tmp;
1420 uint64_t gpa = 0;
1421 bool has_gpa = false;
1422
1423 if (error_code & 0xffff) {
1424 error_report("TDX: REPORT_FATAL_ERROR: invalid error code: 0x%"PRIx64,
1425 error_code);
1426 return -1;
1427 }
1428
1429 if (reg_mask) {
1430 message = g_malloc0(TDX_FATAL_MESSAGE_MAX + 1);
1431 tmp = (uint64_t *)message;
1432
1433 #define COPY_REG(REG) \
1434 do { \
1435 if (reg_mask & BIT_ULL(REG)) { \
1436 *(tmp++) = run->system_event.data[REG]; \
1437 } \
1438 } while (0)
1439
1440 COPY_REG(R_R14);
1441 COPY_REG(R_R15);
1442 COPY_REG(R_EBX);
1443 COPY_REG(R_EDI);
1444 COPY_REG(R_ESI);
1445 COPY_REG(R_R8);
1446 COPY_REG(R_R9);
1447 COPY_REG(R_EDX);
1448 *((char *)tmp) = '\0';
1449 }
1450 #undef COPY_REG
1451
1452 if (error_code & TDX_REPORT_FATAL_ERROR_GPA_VALID) {
1453 gpa = run->system_event.data[R_R13];
1454 has_gpa = true;
1455 }
1456
1457 tdx_panicked_on_fatal_error(cpu, error_code, message, has_gpa, gpa);
1458
1459 return -1;
1460 }
1461
1462 static bool tdx_guest_get_sept_ve_disable(Object *obj, Error **errp)
1463 {
1464 TdxGuest *tdx = TDX_GUEST(obj);
1465
1466 return !!(tdx->attributes & TDX_TD_ATTRIBUTES_SEPT_VE_DISABLE);
1467 }
1468
1469 static void tdx_guest_set_sept_ve_disable(Object *obj, bool value, Error **errp)
1470 {
1471 TdxGuest *tdx = TDX_GUEST(obj);
1472
1473 if (value) {
1474 tdx->attributes |= TDX_TD_ATTRIBUTES_SEPT_VE_DISABLE;
1475 } else {
1476 tdx->attributes &= ~TDX_TD_ATTRIBUTES_SEPT_VE_DISABLE;
1477 }
1478 }
1479
1480 static char *tdx_guest_get_mrconfigid(Object *obj, Error **errp)
1481 {
1482 TdxGuest *tdx = TDX_GUEST(obj);
1483
1484 return g_strdup(tdx->mrconfigid);
1485 }
1486
1487 static void tdx_guest_set_mrconfigid(Object *obj, const char *value, Error **errp)
1488 {
1489 TdxGuest *tdx = TDX_GUEST(obj);
1490
1491 g_free(tdx->mrconfigid);
1492 tdx->mrconfigid = g_strdup(value);
1493 }
1494
1495 static char *tdx_guest_get_mrowner(Object *obj, Error **errp)
1496 {
1497 TdxGuest *tdx = TDX_GUEST(obj);
1498
1499 return g_strdup(tdx->mrowner);
1500 }
1501
1502 static void tdx_guest_set_mrowner(Object *obj, const char *value, Error **errp)
1503 {
1504 TdxGuest *tdx = TDX_GUEST(obj);
1505
1506 g_free(tdx->mrowner);
1507 tdx->mrowner = g_strdup(value);
1508 }
1509
1510 static char *tdx_guest_get_mrownerconfig(Object *obj, Error **errp)
1511 {
1512 TdxGuest *tdx = TDX_GUEST(obj);
1513
1514 return g_strdup(tdx->mrownerconfig);
1515 }
1516
1517 static void tdx_guest_set_mrownerconfig(Object *obj, const char *value, Error **errp)
1518 {
1519 TdxGuest *tdx = TDX_GUEST(obj);
1520
1521 g_free(tdx->mrownerconfig);
1522 tdx->mrownerconfig = g_strdup(value);
1523 }
1524
1525 static void tdx_guest_get_qgs(Object *obj, Visitor *v,
1526 const char *name, void *opaque,
1527 Error **errp)
1528 {
1529 TdxGuest *tdx = TDX_GUEST(obj);
1530
1531 if (!tdx->qg_sock_addr) {
1532 error_setg(errp, "quote-generation-socket is not set");
1533 return;
1534 }
1535 visit_type_SocketAddress(v, name, &tdx->qg_sock_addr, errp);
1536 }
1537
1538 static void tdx_guest_set_qgs(Object *obj, Visitor *v,
1539 const char *name, void *opaque,
1540 Error **errp)
1541 {
1542 TdxGuest *tdx = TDX_GUEST(obj);
1543 SocketAddress *sock = NULL;
1544
1545 if (!visit_type_SocketAddress(v, name, &sock, errp)) {
1546 return;
1547 }
1548
1549 if (tdx->qg_sock_addr) {
1550 qapi_free_SocketAddress(tdx->qg_sock_addr);
1551 }
1552
1553 tdx->qg_sock_addr = sock;
1554 }
1555
1556 /* tdx guest */
1557 OBJECT_DEFINE_TYPE_WITH_INTERFACES(TdxGuest,
1558 tdx_guest,
1559 TDX_GUEST,
1560 X86_CONFIDENTIAL_GUEST,
1561 { TYPE_USER_CREATABLE },
1562 { TYPE_RESETTABLE_INTERFACE },
1563 { NULL })
1564
1565 static void tdx_guest_init(Object *obj)
1566 {
1567 ConfidentialGuestSupport *cgs = CONFIDENTIAL_GUEST_SUPPORT(obj);
1568 TdxGuest *tdx = TDX_GUEST(obj);
1569
1570 qemu_mutex_init(&tdx->lock);
1571
1572 cgs->require_guest_memfd = true;
1573 tdx->attributes = TDX_TD_ATTRIBUTES_SEPT_VE_DISABLE;
1574
1575 object_property_add_uint64_ptr(obj, "attributes", &tdx->attributes,
1576 OBJ_PROP_FLAG_READWRITE);
1577 object_property_add_bool(obj, "sept-ve-disable",
1578 tdx_guest_get_sept_ve_disable,
1579 tdx_guest_set_sept_ve_disable);
1580 object_property_add_str(obj, "mrconfigid",
1581 tdx_guest_get_mrconfigid,
1582 tdx_guest_set_mrconfigid);
1583 object_property_add_str(obj, "mrowner",
1584 tdx_guest_get_mrowner, tdx_guest_set_mrowner);
1585 object_property_add_str(obj, "mrownerconfig",
1586 tdx_guest_get_mrownerconfig,
1587 tdx_guest_set_mrownerconfig);
1588
1589 object_property_add(obj, "quote-generation-socket", "SocketAddress",
1590 tdx_guest_get_qgs,
1591 tdx_guest_set_qgs,
1592 NULL, NULL);
1593
1594 tdx->event_notify_vector = -1;
1595 tdx->event_notify_apicid = -1;
1596 kvm_vmfd_add_change_notifier(&tdx_vmfd_change_notifier);
1597 qemu_register_resettable(obj);
1598 }
1599
1600 static void tdx_guest_finalize(Object *obj)
1601 {
1602 TdxGuest *tdx = TDX_GUEST(obj);
1603
1604 g_free(tdx->mrconfigid);
1605 g_free(tdx->mrowner);
1606 g_free(tdx->mrownerconfig);
1607 }
1608
1609 static ResettableState *tdx_reset_state(Object *obj)
1610 {
1611 TdxGuest *tdx = TDX_GUEST(obj);
1612 return &tdx->reset_state;
1613 }
1614
1615 static void tdx_guest_class_init(ObjectClass *oc, const void *data)
1616 {
1617 ConfidentialGuestSupportClass *klass = CONFIDENTIAL_GUEST_SUPPORT_CLASS(oc);
1618 X86ConfidentialGuestClass *x86_klass = X86_CONFIDENTIAL_GUEST_CLASS(oc);
1619 ResettableClass *rc = RESETTABLE_CLASS(oc);
1620
1621 klass->kvm_init = tdx_kvm_init;
1622 klass->can_rebuild_guest_state = true;
1623 x86_klass->kvm_type = tdx_kvm_type;
1624 x86_klass->cpu_instance_init = tdx_cpu_instance_init;
1625 x86_klass->adjust_cpuid_features = tdx_adjust_cpuid_features;
1626 x86_klass->check_features = tdx_check_features;
1627
1628 /*
1629 * the exit phase makes sure sev handles reset after all legacy resets
1630 * have taken place (in the hold phase) and IGVM has also properly
1631 * set up the boot state.
1632 */
1633 rc->phases.exit = tdx_handle_reset;
1634 rc->get_state = tdx_reset_state;
1635
1636 }