| 1 | #include "qemu/osdep.h" |
| 2 | #include "cpu.h" |
| 3 | #include "exec/cputlb.h" |
| 4 | #include "hw/isa/isa.h" |
| 5 | #include "migration/cpu.h" |
| 6 | #include "kvm/hyperv.h" |
| 7 | #include "hw/i386/x86.h" |
| 8 | #include "kvm/kvm_i386.h" |
| 9 | #include "hw/xen/xen.h" |
| 10 | #include "exec/watchpoint.h" |
| 11 | #include "system/kvm.h" |
| 12 | #include "system/kvm_xen.h" |
| 13 | #include "system/mshv.h" |
| 14 | #include "system/tcg.h" |
| 15 | |
| 16 | #include "qemu/error-report.h" |
| 17 | |
| 18 | static const VMStateDescription vmstate_segment = { |
| 19 | .name = "segment", |
| 20 | .version_id = 1, |
| 21 | .minimum_version_id = 1, |
| 22 | .fields = (const VMStateField[]) { |
| 23 | VMSTATE_UINT32(selector, SegmentCache), |
| 24 | VMSTATE_UINTTL(base, SegmentCache), |
| 25 | VMSTATE_UINT32(limit, SegmentCache), |
| 26 | VMSTATE_UINT32(flags, SegmentCache), |
| 27 | VMSTATE_END_OF_LIST() |
| 28 | } |
| 29 | }; |
| 30 | |
| 31 | #define VMSTATE_SEGMENT(_field, _state) { \ |
| 32 | .name = (stringify(_field)), \ |
| 33 | .size = sizeof(SegmentCache), \ |
| 34 | .vmsd = &vmstate_segment, \ |
| 35 | .flags = VMS_STRUCT, \ |
| 36 | .offset = offsetof(_state, _field) \ |
| 37 | + type_check(SegmentCache,typeof_field(_state, _field)) \ |
| 38 | } |
| 39 | |
| 40 | #define VMSTATE_SEGMENT_ARRAY(_field, _state, _n) \ |
| 41 | VMSTATE_STRUCT_ARRAY(_field, _state, _n, 0, vmstate_segment, SegmentCache) |
| 42 | |
| 43 | static const VMStateDescription vmstate_xmm_reg = { |
| 44 | .name = "xmm_reg", |
| 45 | .version_id = 1, |
| 46 | .minimum_version_id = 1, |
| 47 | .fields = (const VMStateField[]) { |
| 48 | VMSTATE_UINT64(ZMM_Q(0), ZMMReg), |
| 49 | VMSTATE_UINT64(ZMM_Q(1), ZMMReg), |
| 50 | VMSTATE_END_OF_LIST() |
| 51 | } |
| 52 | }; |
| 53 | |
| 54 | #define VMSTATE_XMM_REGS(_field, _state, _start) \ |
| 55 | VMSTATE_STRUCT_SUB_ARRAY(_field, _state, _start, CPU_NB_REGS, 0, \ |
| 56 | vmstate_xmm_reg, ZMMReg) |
| 57 | |
| 58 | /* YMMH format is the same as XMM, but for bits 128-255 */ |
| 59 | static const VMStateDescription vmstate_ymmh_reg = { |
| 60 | .name = "ymmh_reg", |
| 61 | .version_id = 1, |
| 62 | .minimum_version_id = 1, |
| 63 | .fields = (const VMStateField[]) { |
| 64 | VMSTATE_UINT64(ZMM_Q(2), ZMMReg), |
| 65 | VMSTATE_UINT64(ZMM_Q(3), ZMMReg), |
| 66 | VMSTATE_END_OF_LIST() |
| 67 | } |
| 68 | }; |
| 69 | |
| 70 | #define VMSTATE_YMMH_REGS_VARS(_field, _state, _start, _v) \ |
| 71 | VMSTATE_STRUCT_SUB_ARRAY(_field, _state, _start, CPU_NB_REGS, _v, \ |
| 72 | vmstate_ymmh_reg, ZMMReg) |
| 73 | |
| 74 | static const VMStateDescription vmstate_zmmh_reg = { |
| 75 | .name = "zmmh_reg", |
| 76 | .version_id = 1, |
| 77 | .minimum_version_id = 1, |
| 78 | .fields = (const VMStateField[]) { |
| 79 | VMSTATE_UINT64(ZMM_Q(4), ZMMReg), |
| 80 | VMSTATE_UINT64(ZMM_Q(5), ZMMReg), |
| 81 | VMSTATE_UINT64(ZMM_Q(6), ZMMReg), |
| 82 | VMSTATE_UINT64(ZMM_Q(7), ZMMReg), |
| 83 | VMSTATE_END_OF_LIST() |
| 84 | } |
| 85 | }; |
| 86 | |
| 87 | #define VMSTATE_ZMMH_REGS_VARS(_field, _state, _start) \ |
| 88 | VMSTATE_STRUCT_SUB_ARRAY(_field, _state, _start, CPU_NB_REGS, 0, \ |
| 89 | vmstate_zmmh_reg, ZMMReg) |
| 90 | |
| 91 | #ifdef TARGET_X86_64 |
| 92 | static const VMStateDescription vmstate_hi16_zmm_reg = { |
| 93 | .name = "hi16_zmm_reg", |
| 94 | .version_id = 1, |
| 95 | .minimum_version_id = 1, |
| 96 | .fields = (const VMStateField[]) { |
| 97 | VMSTATE_UINT64(ZMM_Q(0), ZMMReg), |
| 98 | VMSTATE_UINT64(ZMM_Q(1), ZMMReg), |
| 99 | VMSTATE_UINT64(ZMM_Q(2), ZMMReg), |
| 100 | VMSTATE_UINT64(ZMM_Q(3), ZMMReg), |
| 101 | VMSTATE_UINT64(ZMM_Q(4), ZMMReg), |
| 102 | VMSTATE_UINT64(ZMM_Q(5), ZMMReg), |
| 103 | VMSTATE_UINT64(ZMM_Q(6), ZMMReg), |
| 104 | VMSTATE_UINT64(ZMM_Q(7), ZMMReg), |
| 105 | VMSTATE_END_OF_LIST() |
| 106 | } |
| 107 | }; |
| 108 | |
| 109 | #define VMSTATE_Hi16_ZMM_REGS_VARS(_field, _state, _start) \ |
| 110 | VMSTATE_STRUCT_SUB_ARRAY(_field, _state, _start, CPU_NB_REGS, 0, \ |
| 111 | vmstate_hi16_zmm_reg, ZMMReg) |
| 112 | #endif |
| 113 | |
| 114 | static const VMStateDescription vmstate_bnd_regs = { |
| 115 | .name = "bnd_regs", |
| 116 | .version_id = 1, |
| 117 | .minimum_version_id = 1, |
| 118 | .fields = (const VMStateField[]) { |
| 119 | VMSTATE_UINT64(lb, BNDReg), |
| 120 | VMSTATE_UINT64(ub, BNDReg), |
| 121 | VMSTATE_END_OF_LIST() |
| 122 | } |
| 123 | }; |
| 124 | |
| 125 | #define VMSTATE_BND_REGS(_field, _state, _n) \ |
| 126 | VMSTATE_STRUCT_ARRAY(_field, _state, _n, 0, vmstate_bnd_regs, BNDReg) |
| 127 | |
| 128 | static const VMStateDescription vmstate_mtrr_var = { |
| 129 | .name = "mtrr_var", |
| 130 | .version_id = 1, |
| 131 | .minimum_version_id = 1, |
| 132 | .fields = (const VMStateField[]) { |
| 133 | VMSTATE_UINT64(base, MTRRVar), |
| 134 | VMSTATE_UINT64(mask, MTRRVar), |
| 135 | VMSTATE_END_OF_LIST() |
| 136 | } |
| 137 | }; |
| 138 | |
| 139 | #define VMSTATE_MTRR_VARS(_field, _state, _n, _v) \ |
| 140 | VMSTATE_STRUCT_ARRAY(_field, _state, _n, _v, vmstate_mtrr_var, MTRRVar) |
| 141 | |
| 142 | static const VMStateDescription vmstate_lbr_records_var = { |
| 143 | .name = "lbr_records_var", |
| 144 | .version_id = 1, |
| 145 | .minimum_version_id = 1, |
| 146 | .fields = (const VMStateField[]) { |
| 147 | VMSTATE_UINT64(from, LBREntry), |
| 148 | VMSTATE_UINT64(to, LBREntry), |
| 149 | VMSTATE_UINT64(info, LBREntry), |
| 150 | VMSTATE_END_OF_LIST() |
| 151 | } |
| 152 | }; |
| 153 | |
| 154 | #define VMSTATE_LBR_VARS(_field, _state, _n, _v) \ |
| 155 | VMSTATE_STRUCT_ARRAY(_field, _state, _n, _v, vmstate_lbr_records_var, \ |
| 156 | LBREntry) |
| 157 | |
| 158 | typedef struct x86_FPReg_tmp { |
| 159 | FPReg *parent; |
| 160 | uint64_t tmp_mant; |
| 161 | uint16_t tmp_exp; |
| 162 | } x86_FPReg_tmp; |
| 163 | |
| 164 | static void cpu_get_fp80(uint64_t *pmant, uint16_t *pexp, floatx80 f) |
| 165 | { |
| 166 | CPU_LDoubleU temp; |
| 167 | |
| 168 | temp.d = f; |
| 169 | *pmant = temp.l.lower; |
| 170 | *pexp = temp.l.upper; |
| 171 | } |
| 172 | |
| 173 | static floatx80 cpu_set_fp80(uint64_t mant, uint16_t upper) |
| 174 | { |
| 175 | CPU_LDoubleU temp; |
| 176 | |
| 177 | temp.l.upper = upper; |
| 178 | temp.l.lower = mant; |
| 179 | return temp.d; |
| 180 | } |
| 181 | |
| 182 | static int fpreg_pre_save(void *opaque) |
| 183 | { |
| 184 | x86_FPReg_tmp *tmp = opaque; |
| 185 | |
| 186 | /* we save the real CPU data (in case of MMX usage only 'mant' |
| 187 | contains the MMX register */ |
| 188 | cpu_get_fp80(&tmp->tmp_mant, &tmp->tmp_exp, tmp->parent->d); |
| 189 | |
| 190 | return 0; |
| 191 | } |
| 192 | |
| 193 | static int fpreg_post_load(void *opaque, int version) |
| 194 | { |
| 195 | x86_FPReg_tmp *tmp = opaque; |
| 196 | |
| 197 | tmp->parent->d = cpu_set_fp80(tmp->tmp_mant, tmp->tmp_exp); |
| 198 | return 0; |
| 199 | } |
| 200 | |
| 201 | static const VMStateDescription vmstate_fpreg_tmp = { |
| 202 | .name = "fpreg_tmp", |
| 203 | .post_load = fpreg_post_load, |
| 204 | .pre_save = fpreg_pre_save, |
| 205 | .fields = (const VMStateField[]) { |
| 206 | VMSTATE_UINT64(tmp_mant, x86_FPReg_tmp), |
| 207 | VMSTATE_UINT16(tmp_exp, x86_FPReg_tmp), |
| 208 | VMSTATE_END_OF_LIST() |
| 209 | } |
| 210 | }; |
| 211 | |
| 212 | static const VMStateDescription vmstate_fpreg = { |
| 213 | .name = "fpreg", |
| 214 | .fields = (const VMStateField[]) { |
| 215 | VMSTATE_WITH_TMP(FPReg, x86_FPReg_tmp, vmstate_fpreg_tmp), |
| 216 | VMSTATE_END_OF_LIST() |
| 217 | } |
| 218 | }; |
| 219 | |
| 220 | static int cpu_pre_save(void *opaque) |
| 221 | { |
| 222 | X86CPU *cpu = opaque; |
| 223 | CPUX86State *env = &cpu->env; |
| 224 | int i; |
| 225 | env->v_tpr = env->int_ctl & V_TPR_MASK; |
| 226 | /* FPU */ |
| 227 | env->fpus_vmstate = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11; |
| 228 | env->fptag_vmstate = 0; |
| 229 | for(i = 0; i < 8; i++) { |
| 230 | env->fptag_vmstate |= ((!env->fptags[i]) << i); |
| 231 | } |
| 232 | |
| 233 | env->fpregs_format_vmstate = 0; |
| 234 | |
| 235 | /* |
| 236 | * Real mode guest segments register DPL should be zero. |
| 237 | * Older KVM version were setting it wrongly. |
| 238 | * Fixing it will allow live migration to host with unrestricted guest |
| 239 | * support (otherwise the migration will fail with invalid guest state |
| 240 | * error). |
| 241 | */ |
| 242 | if (!(env->cr[0] & CR0_PE_MASK) && |
| 243 | (env->segs[R_CS].flags >> DESC_DPL_SHIFT & 3) != 0) { |
| 244 | env->segs[R_CS].flags &= ~(env->segs[R_CS].flags & DESC_DPL_MASK); |
| 245 | env->segs[R_DS].flags &= ~(env->segs[R_DS].flags & DESC_DPL_MASK); |
| 246 | env->segs[R_ES].flags &= ~(env->segs[R_ES].flags & DESC_DPL_MASK); |
| 247 | env->segs[R_FS].flags &= ~(env->segs[R_FS].flags & DESC_DPL_MASK); |
| 248 | env->segs[R_GS].flags &= ~(env->segs[R_GS].flags & DESC_DPL_MASK); |
| 249 | env->segs[R_SS].flags &= ~(env->segs[R_SS].flags & DESC_DPL_MASK); |
| 250 | } |
| 251 | |
| 252 | #ifdef CONFIG_KVM |
| 253 | /* |
| 254 | * In case vCPU may have enabled VMX, we need to make sure kernel have |
| 255 | * required capabilities in order to perform migration correctly: |
| 256 | * |
| 257 | * 1) We must be able to extract vCPU nested-state from KVM. |
| 258 | * |
| 259 | * 2) In case vCPU is running in guest-mode and it has a pending exception, |
| 260 | * we must be able to determine if it's in a pending or injected state. |
| 261 | * Note that in case KVM don't have required capability to do so, |
| 262 | * a pending/injected exception will always appear as an |
| 263 | * injected exception. |
| 264 | */ |
| 265 | if (kvm_enabled() && cpu_vmx_maybe_enabled(env) && |
| 266 | (!env->nested_state || |
| 267 | (!kvm_has_exception_payload() && (env->hflags & HF_GUEST_MASK) && |
| 268 | env->exception_injected))) { |
| 269 | error_report("Guest maybe enabled nested virtualization but kernel " |
| 270 | "does not support required capabilities to save vCPU " |
| 271 | "nested state"); |
| 272 | return -EINVAL; |
| 273 | } |
| 274 | #endif |
| 275 | |
| 276 | /* |
| 277 | * When vCPU is running L2 and exception is still pending, |
| 278 | * it can potentially be intercepted by L1 hypervisor. |
| 279 | * In contrast to an injected exception which cannot be |
| 280 | * intercepted anymore. |
| 281 | * |
| 282 | * Furthermore, when a L2 exception is intercepted by L1 |
| 283 | * hypervisor, its exception payload (CR2/DR6 on #PF/#DB) |
| 284 | * should not be set yet in the respective vCPU register. |
| 285 | * Thus, in case an exception is pending, it is |
| 286 | * important to save the exception payload separately. |
| 287 | * |
| 288 | * Therefore, if an exception is not in a pending state |
| 289 | * or vCPU is not in guest-mode, it is not important to |
| 290 | * distinguish between a pending and injected exception |
| 291 | * and we don't need to store separately the exception payload. |
| 292 | * |
| 293 | * In order to preserve better backwards-compatible migration, |
| 294 | * convert a pending exception to an injected exception in |
| 295 | * case it is not important to distinguish between them |
| 296 | * as described above. |
| 297 | */ |
| 298 | if (env->exception_pending && !(env->hflags & HF_GUEST_MASK)) { |
| 299 | env->exception_pending = 0; |
| 300 | env->exception_injected = 1; |
| 301 | |
| 302 | if (env->exception_has_payload) { |
| 303 | if (env->exception_nr == EXCP01_DB) { |
| 304 | env->dr[6] = env->exception_payload; |
| 305 | } else if (env->exception_nr == EXCP0E_PAGE) { |
| 306 | env->cr[2] = env->exception_payload; |
| 307 | } |
| 308 | } |
| 309 | } |
| 310 | |
| 311 | return 0; |
| 312 | } |
| 313 | |
| 314 | static int cpu_post_load(void *opaque, int version_id) |
| 315 | { |
| 316 | X86CPU *cpu = opaque; |
| 317 | CPUState *cs = CPU(cpu); |
| 318 | CPUX86State *env = &cpu->env; |
| 319 | int i; |
| 320 | |
| 321 | if (env->tsc_khz && env->user_tsc_khz && |
| 322 | env->tsc_khz != env->user_tsc_khz) { |
| 323 | error_report("Mismatch between user-specified TSC frequency and " |
| 324 | "migrated TSC frequency"); |
| 325 | return -EINVAL; |
| 326 | } |
| 327 | |
| 328 | if (env->fpregs_format_vmstate) { |
| 329 | error_report("Unsupported old non-softfloat CPU state"); |
| 330 | return -EINVAL; |
| 331 | } |
| 332 | /* |
| 333 | * Real mode guest segments register DPL should be zero. |
| 334 | * Older KVM version were setting it wrongly. |
| 335 | * Fixing it will allow live migration from such host that don't have |
| 336 | * restricted guest support to a host with unrestricted guest support |
| 337 | * (otherwise the migration will fail with invalid guest state |
| 338 | * error). |
| 339 | */ |
| 340 | if (!(env->cr[0] & CR0_PE_MASK) && |
| 341 | (env->segs[R_CS].flags >> DESC_DPL_SHIFT & 3) != 0) { |
| 342 | env->segs[R_CS].flags &= ~(env->segs[R_CS].flags & DESC_DPL_MASK); |
| 343 | env->segs[R_DS].flags &= ~(env->segs[R_DS].flags & DESC_DPL_MASK); |
| 344 | env->segs[R_ES].flags &= ~(env->segs[R_ES].flags & DESC_DPL_MASK); |
| 345 | env->segs[R_FS].flags &= ~(env->segs[R_FS].flags & DESC_DPL_MASK); |
| 346 | env->segs[R_GS].flags &= ~(env->segs[R_GS].flags & DESC_DPL_MASK); |
| 347 | env->segs[R_SS].flags &= ~(env->segs[R_SS].flags & DESC_DPL_MASK); |
| 348 | } |
| 349 | |
| 350 | /* Older versions of QEMU incorrectly used CS.DPL as the CPL when |
| 351 | * running under KVM. This is wrong for conforming code segments. |
| 352 | * Luckily, in our implementation the CPL field of hflags is redundant |
| 353 | * and we can get the right value from the SS descriptor privilege level. |
| 354 | */ |
| 355 | env->hflags &= ~HF_CPL_MASK; |
| 356 | env->hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK; |
| 357 | |
| 358 | #ifdef CONFIG_KVM |
| 359 | if ((env->hflags & HF_GUEST_MASK) && |
| 360 | (!env->nested_state || |
| 361 | !(env->nested_state->flags & KVM_STATE_NESTED_GUEST_MODE))) { |
| 362 | error_report("vCPU set in guest-mode inconsistent with " |
| 363 | "migrated kernel nested state"); |
| 364 | return -EINVAL; |
| 365 | } |
| 366 | #endif |
| 367 | |
| 368 | /* |
| 369 | * There are cases that we can get valid exception_nr with both |
| 370 | * exception_pending and exception_injected being cleared. |
| 371 | * This can happen in one of the following scenarios: |
| 372 | * 1) Source is older QEMU without KVM_CAP_EXCEPTION_PAYLOAD support. |
| 373 | * 2) Source is running on kernel without KVM_CAP_EXCEPTION_PAYLOAD support. |
| 374 | * 3) "cpu/exception_info" subsection not sent because there is no exception |
| 375 | * pending or guest wasn't running L2 (See comment in cpu_pre_save()). |
| 376 | * |
| 377 | * In those cases, we can just deduce that a valid exception_nr means |
| 378 | * we can treat the exception as already injected. |
| 379 | */ |
| 380 | if ((env->exception_nr != -1) && |
| 381 | !env->exception_pending && !env->exception_injected) { |
| 382 | env->exception_injected = 1; |
| 383 | } |
| 384 | |
| 385 | env->fpstt = (env->fpus_vmstate >> 11) & 7; |
| 386 | env->fpus = env->fpus_vmstate & ~0x3800; |
| 387 | env->fptag_vmstate ^= 0xff; |
| 388 | for(i = 0; i < 8; i++) { |
| 389 | env->fptags[i] = (env->fptag_vmstate >> i) & 1; |
| 390 | } |
| 391 | if (tcg_enabled()) { |
| 392 | target_ulong dr7; |
| 393 | update_fp_status(env); |
| 394 | update_mxcsr_status(env); |
| 395 | |
| 396 | cpu_breakpoint_remove_all(cs, BP_CPU); |
| 397 | cpu_watchpoint_remove_all(cs, BP_CPU); |
| 398 | |
| 399 | /* Indicate all breakpoints disabled, as they are, then |
| 400 | let the helper re-enable them. */ |
| 401 | dr7 = env->dr[7]; |
| 402 | env->dr[7] = dr7 & ~(DR7_GLOBAL_BP_MASK | DR7_LOCAL_BP_MASK); |
| 403 | cpu_x86_update_dr7(env, dr7); |
| 404 | } |
| 405 | return 0; |
| 406 | } |
| 407 | |
| 408 | static bool async_pf_msr_needed(void *opaque) |
| 409 | { |
| 410 | X86CPU *cpu = opaque; |
| 411 | |
| 412 | return cpu->env.async_pf_en_msr != 0; |
| 413 | } |
| 414 | |
| 415 | static bool async_pf_int_msr_needed(void *opaque) |
| 416 | { |
| 417 | X86CPU *cpu = opaque; |
| 418 | |
| 419 | return cpu->env.async_pf_int_msr != 0; |
| 420 | } |
| 421 | |
| 422 | static bool pv_eoi_msr_needed(void *opaque) |
| 423 | { |
| 424 | X86CPU *cpu = opaque; |
| 425 | |
| 426 | return cpu->env.pv_eoi_en_msr != 0; |
| 427 | } |
| 428 | |
| 429 | static bool steal_time_msr_needed(void *opaque) |
| 430 | { |
| 431 | X86CPU *cpu = opaque; |
| 432 | |
| 433 | return cpu->env.steal_time_msr != 0; |
| 434 | } |
| 435 | |
| 436 | static bool exception_info_needed(void *opaque) |
| 437 | { |
| 438 | X86CPU *cpu = opaque; |
| 439 | CPUX86State *env = &cpu->env; |
| 440 | |
| 441 | /* |
| 442 | * It is important to save exception-info only in case |
| 443 | * we need to distinguish between a pending and injected |
| 444 | * exception. Which is only required in case there is a |
| 445 | * pending exception and vCPU is running L2. |
| 446 | * For more info, refer to comment in cpu_pre_save(). |
| 447 | */ |
| 448 | return env->exception_pending && (env->hflags & HF_GUEST_MASK); |
| 449 | } |
| 450 | |
| 451 | static const VMStateDescription vmstate_exception_info = { |
| 452 | .name = "cpu/exception_info", |
| 453 | .version_id = 1, |
| 454 | .minimum_version_id = 1, |
| 455 | .needed = exception_info_needed, |
| 456 | .fields = (const VMStateField[]) { |
| 457 | VMSTATE_UINT8(env.exception_pending, X86CPU), |
| 458 | VMSTATE_UINT8(env.exception_injected, X86CPU), |
| 459 | VMSTATE_UINT8(env.exception_has_payload, X86CPU), |
| 460 | VMSTATE_UINT64(env.exception_payload, X86CPU), |
| 461 | VMSTATE_END_OF_LIST() |
| 462 | } |
| 463 | }; |
| 464 | |
| 465 | static bool cpu_errcode_needed(void *opaque) |
| 466 | { |
| 467 | X86CPU *cpu = opaque; |
| 468 | |
| 469 | return cpu->env.has_error_code != 0 && cpu->migrate_error_code; |
| 470 | } |
| 471 | |
| 472 | static const VMStateDescription vmstate_error_code = { |
| 473 | .name = "cpu/error_code", |
| 474 | .version_id = 1, |
| 475 | .minimum_version_id = 1, |
| 476 | .needed = cpu_errcode_needed, |
| 477 | .fields = (const VMStateField[]) { |
| 478 | VMSTATE_INT32(env.error_code, X86CPU), |
| 479 | VMSTATE_END_OF_LIST() |
| 480 | } |
| 481 | }; |
| 482 | |
| 483 | /* Poll control MSR enabled by default */ |
| 484 | static bool poll_control_msr_needed(void *opaque) |
| 485 | { |
| 486 | X86CPU *cpu = opaque; |
| 487 | |
| 488 | return cpu->env.poll_control_msr != 1; |
| 489 | } |
| 490 | |
| 491 | static const VMStateDescription vmstate_steal_time_msr = { |
| 492 | .name = "cpu/steal_time_msr", |
| 493 | .version_id = 1, |
| 494 | .minimum_version_id = 1, |
| 495 | .needed = steal_time_msr_needed, |
| 496 | .fields = (const VMStateField[]) { |
| 497 | VMSTATE_UINT64(env.steal_time_msr, X86CPU), |
| 498 | VMSTATE_END_OF_LIST() |
| 499 | } |
| 500 | }; |
| 501 | |
| 502 | static const VMStateDescription vmstate_async_pf_msr = { |
| 503 | .name = "cpu/async_pf_msr", |
| 504 | .version_id = 1, |
| 505 | .minimum_version_id = 1, |
| 506 | .needed = async_pf_msr_needed, |
| 507 | .fields = (const VMStateField[]) { |
| 508 | VMSTATE_UINT64(env.async_pf_en_msr, X86CPU), |
| 509 | VMSTATE_END_OF_LIST() |
| 510 | } |
| 511 | }; |
| 512 | |
| 513 | static const VMStateDescription vmstate_async_pf_int_msr = { |
| 514 | .name = "cpu/async_pf_int_msr", |
| 515 | .version_id = 1, |
| 516 | .minimum_version_id = 1, |
| 517 | .needed = async_pf_int_msr_needed, |
| 518 | .fields = (const VMStateField[]) { |
| 519 | VMSTATE_UINT64(env.async_pf_int_msr, X86CPU), |
| 520 | VMSTATE_END_OF_LIST() |
| 521 | } |
| 522 | }; |
| 523 | |
| 524 | static const VMStateDescription vmstate_pv_eoi_msr = { |
| 525 | .name = "cpu/async_pv_eoi_msr", |
| 526 | .version_id = 1, |
| 527 | .minimum_version_id = 1, |
| 528 | .needed = pv_eoi_msr_needed, |
| 529 | .fields = (const VMStateField[]) { |
| 530 | VMSTATE_UINT64(env.pv_eoi_en_msr, X86CPU), |
| 531 | VMSTATE_END_OF_LIST() |
| 532 | } |
| 533 | }; |
| 534 | |
| 535 | static const VMStateDescription vmstate_poll_control_msr = { |
| 536 | .name = "cpu/poll_control_msr", |
| 537 | .version_id = 1, |
| 538 | .minimum_version_id = 1, |
| 539 | .needed = poll_control_msr_needed, |
| 540 | .fields = (const VMStateField[]) { |
| 541 | VMSTATE_UINT64(env.poll_control_msr, X86CPU), |
| 542 | VMSTATE_END_OF_LIST() |
| 543 | } |
| 544 | }; |
| 545 | |
| 546 | static bool fpop_ip_dp_needed(void *opaque) |
| 547 | { |
| 548 | X86CPU *cpu = opaque; |
| 549 | CPUX86State *env = &cpu->env; |
| 550 | |
| 551 | return env->fpop != 0 || env->fpip != 0 || env->fpdp != 0; |
| 552 | } |
| 553 | |
| 554 | static const VMStateDescription vmstate_fpop_ip_dp = { |
| 555 | .name = "cpu/fpop_ip_dp", |
| 556 | .version_id = 1, |
| 557 | .minimum_version_id = 1, |
| 558 | .needed = fpop_ip_dp_needed, |
| 559 | .fields = (const VMStateField[]) { |
| 560 | VMSTATE_UINT16(env.fpop, X86CPU), |
| 561 | VMSTATE_UINT64(env.fpip, X86CPU), |
| 562 | VMSTATE_UINT64(env.fpdp, X86CPU), |
| 563 | VMSTATE_END_OF_LIST() |
| 564 | } |
| 565 | }; |
| 566 | |
| 567 | static bool tsc_adjust_needed(void *opaque) |
| 568 | { |
| 569 | X86CPU *cpu = opaque; |
| 570 | CPUX86State *env = &cpu->env; |
| 571 | |
| 572 | return env->tsc_adjust != 0; |
| 573 | } |
| 574 | |
| 575 | static const VMStateDescription vmstate_msr_tsc_adjust = { |
| 576 | .name = "cpu/msr_tsc_adjust", |
| 577 | .version_id = 1, |
| 578 | .minimum_version_id = 1, |
| 579 | .needed = tsc_adjust_needed, |
| 580 | .fields = (const VMStateField[]) { |
| 581 | VMSTATE_UINT64(env.tsc_adjust, X86CPU), |
| 582 | VMSTATE_END_OF_LIST() |
| 583 | } |
| 584 | }; |
| 585 | |
| 586 | static bool msr_smi_count_needed(void *opaque) |
| 587 | { |
| 588 | X86CPU *cpu = opaque; |
| 589 | CPUX86State *env = &cpu->env; |
| 590 | |
| 591 | return cpu->migrate_smi_count && env->msr_smi_count != 0; |
| 592 | } |
| 593 | |
| 594 | static const VMStateDescription vmstate_msr_smi_count = { |
| 595 | .name = "cpu/msr_smi_count", |
| 596 | .version_id = 1, |
| 597 | .minimum_version_id = 1, |
| 598 | .needed = msr_smi_count_needed, |
| 599 | .fields = (const VMStateField[]) { |
| 600 | VMSTATE_UINT64(env.msr_smi_count, X86CPU), |
| 601 | VMSTATE_END_OF_LIST() |
| 602 | } |
| 603 | }; |
| 604 | |
| 605 | static bool tscdeadline_needed(void *opaque) |
| 606 | { |
| 607 | X86CPU *cpu = opaque; |
| 608 | CPUX86State *env = &cpu->env; |
| 609 | |
| 610 | return env->tsc_deadline != 0; |
| 611 | } |
| 612 | |
| 613 | static const VMStateDescription vmstate_msr_tscdeadline = { |
| 614 | .name = "cpu/msr_tscdeadline", |
| 615 | .version_id = 1, |
| 616 | .minimum_version_id = 1, |
| 617 | .needed = tscdeadline_needed, |
| 618 | .fields = (const VMStateField[]) { |
| 619 | VMSTATE_UINT64(env.tsc_deadline, X86CPU), |
| 620 | VMSTATE_END_OF_LIST() |
| 621 | } |
| 622 | }; |
| 623 | |
| 624 | static bool misc_enable_needed(void *opaque) |
| 625 | { |
| 626 | X86CPU *cpu = opaque; |
| 627 | CPUX86State *env = &cpu->env; |
| 628 | |
| 629 | return env->msr_ia32_misc_enable != MSR_IA32_MISC_ENABLE_DEFAULT; |
| 630 | } |
| 631 | |
| 632 | static bool feature_control_needed(void *opaque) |
| 633 | { |
| 634 | X86CPU *cpu = opaque; |
| 635 | CPUX86State *env = &cpu->env; |
| 636 | |
| 637 | return env->msr_ia32_feature_control != 0; |
| 638 | } |
| 639 | |
| 640 | static const VMStateDescription vmstate_msr_ia32_misc_enable = { |
| 641 | .name = "cpu/msr_ia32_misc_enable", |
| 642 | .version_id = 1, |
| 643 | .minimum_version_id = 1, |
| 644 | .needed = misc_enable_needed, |
| 645 | .fields = (const VMStateField[]) { |
| 646 | VMSTATE_UINT64(env.msr_ia32_misc_enable, X86CPU), |
| 647 | VMSTATE_END_OF_LIST() |
| 648 | } |
| 649 | }; |
| 650 | |
| 651 | static const VMStateDescription vmstate_msr_ia32_feature_control = { |
| 652 | .name = "cpu/msr_ia32_feature_control", |
| 653 | .version_id = 1, |
| 654 | .minimum_version_id = 1, |
| 655 | .needed = feature_control_needed, |
| 656 | .fields = (const VMStateField[]) { |
| 657 | VMSTATE_UINT64(env.msr_ia32_feature_control, X86CPU), |
| 658 | VMSTATE_END_OF_LIST() |
| 659 | } |
| 660 | }; |
| 661 | |
| 662 | static bool pmu_enable_needed(void *opaque) |
| 663 | { |
| 664 | X86CPU *cpu = opaque; |
| 665 | CPUX86State *env = &cpu->env; |
| 666 | int i; |
| 667 | |
| 668 | if (env->msr_fixed_ctr_ctrl || env->msr_global_ctrl || |
| 669 | env->msr_global_status || env->msr_global_ovf_ctrl) { |
| 670 | return true; |
| 671 | } |
| 672 | for (i = 0; i < MAX_FIXED_COUNTERS; i++) { |
| 673 | if (env->msr_fixed_counters[i]) { |
| 674 | return true; |
| 675 | } |
| 676 | } |
| 677 | for (i = 0; i < MAX_GP_COUNTERS; i++) { |
| 678 | if (env->msr_gp_counters[i] || env->msr_gp_evtsel[i]) { |
| 679 | return true; |
| 680 | } |
| 681 | } |
| 682 | |
| 683 | return false; |
| 684 | } |
| 685 | |
| 686 | static const VMStateDescription vmstate_msr_architectural_pmu = { |
| 687 | .name = "cpu/msr_architectural_pmu", |
| 688 | .version_id = 1, |
| 689 | .minimum_version_id = 1, |
| 690 | .needed = pmu_enable_needed, |
| 691 | .fields = (const VMStateField[]) { |
| 692 | VMSTATE_UINT64(env.msr_fixed_ctr_ctrl, X86CPU), |
| 693 | VMSTATE_UINT64(env.msr_global_ctrl, X86CPU), |
| 694 | VMSTATE_UINT64(env.msr_global_status, X86CPU), |
| 695 | VMSTATE_UINT64(env.msr_global_ovf_ctrl, X86CPU), |
| 696 | VMSTATE_UINT64_ARRAY(env.msr_fixed_counters, X86CPU, MAX_FIXED_COUNTERS), |
| 697 | VMSTATE_UINT64_ARRAY(env.msr_gp_counters, X86CPU, MAX_GP_COUNTERS), |
| 698 | VMSTATE_UINT64_ARRAY(env.msr_gp_evtsel, X86CPU, MAX_GP_COUNTERS), |
| 699 | VMSTATE_END_OF_LIST() |
| 700 | } |
| 701 | }; |
| 702 | |
| 703 | static bool mpx_needed(void *opaque) |
| 704 | { |
| 705 | X86CPU *cpu = opaque; |
| 706 | CPUX86State *env = &cpu->env; |
| 707 | unsigned int i; |
| 708 | |
| 709 | for (i = 0; i < 4; i++) { |
| 710 | if (env->bnd_regs[i].lb || env->bnd_regs[i].ub) { |
| 711 | return true; |
| 712 | } |
| 713 | } |
| 714 | |
| 715 | if (env->bndcs_regs.cfgu || env->bndcs_regs.sts) { |
| 716 | return true; |
| 717 | } |
| 718 | |
| 719 | return !!env->msr_bndcfgs; |
| 720 | } |
| 721 | |
| 722 | static const VMStateDescription vmstate_mpx = { |
| 723 | .name = "cpu/mpx", |
| 724 | .version_id = 1, |
| 725 | .minimum_version_id = 1, |
| 726 | .needed = mpx_needed, |
| 727 | .fields = (const VMStateField[]) { |
| 728 | VMSTATE_BND_REGS(env.bnd_regs, X86CPU, 4), |
| 729 | VMSTATE_UINT64(env.bndcs_regs.cfgu, X86CPU), |
| 730 | VMSTATE_UINT64(env.bndcs_regs.sts, X86CPU), |
| 731 | VMSTATE_UINT64(env.msr_bndcfgs, X86CPU), |
| 732 | VMSTATE_END_OF_LIST() |
| 733 | } |
| 734 | }; |
| 735 | |
| 736 | static bool hyperv_hypercall_enable_needed(void *opaque) |
| 737 | { |
| 738 | X86CPU *cpu = opaque; |
| 739 | CPUX86State *env = &cpu->env; |
| 740 | |
| 741 | return env->msr_hv_hypercall != 0 || env->msr_hv_guest_os_id != 0; |
| 742 | } |
| 743 | |
| 744 | static const VMStateDescription vmstate_msr_hyperv_hypercall = { |
| 745 | .name = "cpu/msr_hyperv_hypercall", |
| 746 | .version_id = 1, |
| 747 | .minimum_version_id = 1, |
| 748 | .needed = hyperv_hypercall_enable_needed, |
| 749 | .fields = (const VMStateField[]) { |
| 750 | VMSTATE_UINT64(env.msr_hv_guest_os_id, X86CPU), |
| 751 | VMSTATE_UINT64(env.msr_hv_hypercall, X86CPU), |
| 752 | VMSTATE_END_OF_LIST() |
| 753 | } |
| 754 | }; |
| 755 | |
| 756 | static bool hyperv_vapic_enable_needed(void *opaque) |
| 757 | { |
| 758 | X86CPU *cpu = opaque; |
| 759 | CPUX86State *env = &cpu->env; |
| 760 | |
| 761 | return env->msr_hv_vapic != 0; |
| 762 | } |
| 763 | |
| 764 | static const VMStateDescription vmstate_msr_hyperv_vapic = { |
| 765 | .name = "cpu/msr_hyperv_vapic", |
| 766 | .version_id = 1, |
| 767 | .minimum_version_id = 1, |
| 768 | .needed = hyperv_vapic_enable_needed, |
| 769 | .fields = (const VMStateField[]) { |
| 770 | VMSTATE_UINT64(env.msr_hv_vapic, X86CPU), |
| 771 | VMSTATE_END_OF_LIST() |
| 772 | } |
| 773 | }; |
| 774 | |
| 775 | static bool hyperv_time_enable_needed(void *opaque) |
| 776 | { |
| 777 | X86CPU *cpu = opaque; |
| 778 | CPUX86State *env = &cpu->env; |
| 779 | |
| 780 | return env->msr_hv_tsc != 0; |
| 781 | } |
| 782 | |
| 783 | static const VMStateDescription vmstate_msr_hyperv_time = { |
| 784 | .name = "cpu/msr_hyperv_time", |
| 785 | .version_id = 1, |
| 786 | .minimum_version_id = 1, |
| 787 | .needed = hyperv_time_enable_needed, |
| 788 | .fields = (const VMStateField[]) { |
| 789 | VMSTATE_UINT64(env.msr_hv_tsc, X86CPU), |
| 790 | VMSTATE_END_OF_LIST() |
| 791 | } |
| 792 | }; |
| 793 | |
| 794 | static bool hyperv_crash_enable_needed(void *opaque) |
| 795 | { |
| 796 | X86CPU *cpu = opaque; |
| 797 | CPUX86State *env = &cpu->env; |
| 798 | int i; |
| 799 | |
| 800 | for (i = 0; i < HV_CRASH_PARAMS; i++) { |
| 801 | if (env->msr_hv_crash_params[i]) { |
| 802 | return true; |
| 803 | } |
| 804 | } |
| 805 | return false; |
| 806 | } |
| 807 | |
| 808 | static const VMStateDescription vmstate_msr_hyperv_crash = { |
| 809 | .name = "cpu/msr_hyperv_crash", |
| 810 | .version_id = 1, |
| 811 | .minimum_version_id = 1, |
| 812 | .needed = hyperv_crash_enable_needed, |
| 813 | .fields = (const VMStateField[]) { |
| 814 | VMSTATE_UINT64_ARRAY(env.msr_hv_crash_params, X86CPU, HV_CRASH_PARAMS), |
| 815 | VMSTATE_END_OF_LIST() |
| 816 | } |
| 817 | }; |
| 818 | |
| 819 | static bool hyperv_runtime_enable_needed(void *opaque) |
| 820 | { |
| 821 | X86CPU *cpu = opaque; |
| 822 | CPUX86State *env = &cpu->env; |
| 823 | |
| 824 | if (!hyperv_feat_enabled(cpu, HYPERV_FEAT_RUNTIME)) { |
| 825 | return false; |
| 826 | } |
| 827 | |
| 828 | return env->msr_hv_runtime != 0; |
| 829 | } |
| 830 | |
| 831 | static const VMStateDescription vmstate_msr_hyperv_runtime = { |
| 832 | .name = "cpu/msr_hyperv_runtime", |
| 833 | .version_id = 1, |
| 834 | .minimum_version_id = 1, |
| 835 | .needed = hyperv_runtime_enable_needed, |
| 836 | .fields = (const VMStateField[]) { |
| 837 | VMSTATE_UINT64(env.msr_hv_runtime, X86CPU), |
| 838 | VMSTATE_END_OF_LIST() |
| 839 | } |
| 840 | }; |
| 841 | |
| 842 | static bool hyperv_synic_enable_needed(void *opaque) |
| 843 | { |
| 844 | X86CPU *cpu = opaque; |
| 845 | CPUX86State *env = &cpu->env; |
| 846 | int i; |
| 847 | |
| 848 | if (env->msr_hv_synic_control != 0 || |
| 849 | env->msr_hv_synic_evt_page != 0 || |
| 850 | env->msr_hv_synic_msg_page != 0) { |
| 851 | return true; |
| 852 | } |
| 853 | |
| 854 | for (i = 0; i < ARRAY_SIZE(env->msr_hv_synic_sint); i++) { |
| 855 | if (env->msr_hv_synic_sint[i] != 0) { |
| 856 | return true; |
| 857 | } |
| 858 | } |
| 859 | |
| 860 | return false; |
| 861 | } |
| 862 | |
| 863 | static int hyperv_synic_post_load(void *opaque, int version_id) |
| 864 | { |
| 865 | X86CPU *cpu = opaque; |
| 866 | hyperv_x86_synic_update(cpu); |
| 867 | return 0; |
| 868 | } |
| 869 | |
| 870 | static const VMStateDescription vmstate_msr_hyperv_synic = { |
| 871 | .name = "cpu/msr_hyperv_synic", |
| 872 | .version_id = 1, |
| 873 | .minimum_version_id = 1, |
| 874 | .needed = hyperv_synic_enable_needed, |
| 875 | .post_load = hyperv_synic_post_load, |
| 876 | .fields = (const VMStateField[]) { |
| 877 | VMSTATE_UINT64(env.msr_hv_synic_control, X86CPU), |
| 878 | VMSTATE_UINT64(env.msr_hv_synic_evt_page, X86CPU), |
| 879 | VMSTATE_UINT64(env.msr_hv_synic_msg_page, X86CPU), |
| 880 | VMSTATE_UINT64_ARRAY(env.msr_hv_synic_sint, X86CPU, HV_SINT_COUNT), |
| 881 | VMSTATE_END_OF_LIST() |
| 882 | } |
| 883 | }; |
| 884 | |
| 885 | static bool hyperv_stimer_enable_needed(void *opaque) |
| 886 | { |
| 887 | X86CPU *cpu = opaque; |
| 888 | CPUX86State *env = &cpu->env; |
| 889 | int i; |
| 890 | |
| 891 | for (i = 0; i < ARRAY_SIZE(env->msr_hv_stimer_config); i++) { |
| 892 | if (env->msr_hv_stimer_config[i] || env->msr_hv_stimer_count[i]) { |
| 893 | return true; |
| 894 | } |
| 895 | } |
| 896 | return false; |
| 897 | } |
| 898 | |
| 899 | static const VMStateDescription vmstate_msr_hyperv_stimer = { |
| 900 | .name = "cpu/msr_hyperv_stimer", |
| 901 | .version_id = 1, |
| 902 | .minimum_version_id = 1, |
| 903 | .needed = hyperv_stimer_enable_needed, |
| 904 | .fields = (const VMStateField[]) { |
| 905 | VMSTATE_UINT64_ARRAY(env.msr_hv_stimer_config, X86CPU, |
| 906 | HV_STIMER_COUNT), |
| 907 | VMSTATE_UINT64_ARRAY(env.msr_hv_stimer_count, X86CPU, HV_STIMER_COUNT), |
| 908 | VMSTATE_END_OF_LIST() |
| 909 | } |
| 910 | }; |
| 911 | |
| 912 | static bool hyperv_reenlightenment_enable_needed(void *opaque) |
| 913 | { |
| 914 | X86CPU *cpu = opaque; |
| 915 | CPUX86State *env = &cpu->env; |
| 916 | |
| 917 | return env->msr_hv_reenlightenment_control != 0 || |
| 918 | env->msr_hv_tsc_emulation_control != 0 || |
| 919 | env->msr_hv_tsc_emulation_status != 0; |
| 920 | } |
| 921 | |
| 922 | static int hyperv_reenlightenment_post_load(void *opaque, int version_id) |
| 923 | { |
| 924 | X86CPU *cpu = opaque; |
| 925 | CPUX86State *env = &cpu->env; |
| 926 | |
| 927 | /* |
| 928 | * KVM doesn't fully support re-enlightenment notifications so we need to |
| 929 | * make sure TSC frequency doesn't change upon migration. |
| 930 | */ |
| 931 | if ((env->msr_hv_reenlightenment_control & HV_REENLIGHTENMENT_ENABLE_BIT) && |
| 932 | !env->user_tsc_khz) { |
| 933 | error_report("Guest enabled re-enlightenment notifications, " |
| 934 | "'tsc-frequency=' has to be specified"); |
| 935 | return -EINVAL; |
| 936 | } |
| 937 | |
| 938 | return 0; |
| 939 | } |
| 940 | |
| 941 | static const VMStateDescription vmstate_msr_hyperv_reenlightenment = { |
| 942 | .name = "cpu/msr_hyperv_reenlightenment", |
| 943 | .version_id = 1, |
| 944 | .minimum_version_id = 1, |
| 945 | .needed = hyperv_reenlightenment_enable_needed, |
| 946 | .post_load = hyperv_reenlightenment_post_load, |
| 947 | .fields = (const VMStateField[]) { |
| 948 | VMSTATE_UINT64(env.msr_hv_reenlightenment_control, X86CPU), |
| 949 | VMSTATE_UINT64(env.msr_hv_tsc_emulation_control, X86CPU), |
| 950 | VMSTATE_UINT64(env.msr_hv_tsc_emulation_status, X86CPU), |
| 951 | VMSTATE_END_OF_LIST() |
| 952 | } |
| 953 | }; |
| 954 | |
| 955 | #ifdef CONFIG_MSHV |
| 956 | |
| 957 | static bool mshv_synthetic_timers_needed(void *opaque) |
| 958 | { |
| 959 | /* Always migrate synthetic timers */ |
| 960 | return mshv_enabled(); |
| 961 | } |
| 962 | |
| 963 | static const VMStateDescription vmstate_mshv_synthetic_timers = { |
| 964 | .name = "cpu/mshv_synthetic_timers", |
| 965 | .version_id = 1, |
| 966 | .minimum_version_id = 1, |
| 967 | .needed = mshv_synthetic_timers_needed, |
| 968 | .fields = (const VMStateField[]) { |
| 969 | VMSTATE_BUFFER(env.hv_synthetic_timers_state, X86CPU), |
| 970 | VMSTATE_END_OF_LIST() |
| 971 | } |
| 972 | }; |
| 973 | |
| 974 | static bool mshv_synic_vp_state_needed(void *opaque) |
| 975 | { |
| 976 | X86CPU *cpu = opaque; |
| 977 | CPUX86State *env = &cpu->env; |
| 978 | |
| 979 | /* Only migrate SIMP/SIEFP if SynIC is enabled */ |
| 980 | return env->msr_hv_synic_control & 1; |
| 981 | } |
| 982 | |
| 983 | static const VMStateDescription vmstate_mshv_synic_vp_state = { |
| 984 | .name = "cpu/mshv_synic_vp_state", |
| 985 | .version_id = 1, |
| 986 | .minimum_version_id = 1, |
| 987 | .needed = mshv_synic_vp_state_needed, |
| 988 | .fields = (const VMStateField[]) { |
| 989 | VMSTATE_BUFFER(env.hv_simp_page, X86CPU), |
| 990 | VMSTATE_BUFFER(env.hv_siefp_page, X86CPU), |
| 991 | VMSTATE_END_OF_LIST() |
| 992 | } |
| 993 | }; |
| 994 | #endif |
| 995 | |
| 996 | static bool avx512_needed(void *opaque) |
| 997 | { |
| 998 | X86CPU *cpu = opaque; |
| 999 | CPUX86State *env = &cpu->env; |
| 1000 | unsigned int i; |
| 1001 | |
| 1002 | for (i = 0; i < NB_OPMASK_REGS; i++) { |
| 1003 | if (env->opmask_regs[i]) { |
| 1004 | return true; |
| 1005 | } |
| 1006 | } |
| 1007 | |
| 1008 | for (i = 0; i < CPU_NB_REGS; i++) { |
| 1009 | #define ENV_XMM(reg, field) (env->xmm_regs[reg].ZMM_Q(field)) |
| 1010 | if (ENV_XMM(i, 4) || ENV_XMM(i, 6) || |
| 1011 | ENV_XMM(i, 5) || ENV_XMM(i, 7)) { |
| 1012 | return true; |
| 1013 | } |
| 1014 | #ifdef TARGET_X86_64 |
| 1015 | if (ENV_XMM(i+16, 0) || ENV_XMM(i+16, 1) || |
| 1016 | ENV_XMM(i+16, 2) || ENV_XMM(i+16, 3) || |
| 1017 | ENV_XMM(i+16, 4) || ENV_XMM(i+16, 5) || |
| 1018 | ENV_XMM(i+16, 6) || ENV_XMM(i+16, 7)) { |
| 1019 | return true; |
| 1020 | } |
| 1021 | #endif |
| 1022 | } |
| 1023 | |
| 1024 | return false; |
| 1025 | } |
| 1026 | |
| 1027 | static const VMStateDescription vmstate_avx512 = { |
| 1028 | .name = "cpu/avx512", |
| 1029 | .version_id = 1, |
| 1030 | .minimum_version_id = 1, |
| 1031 | .needed = avx512_needed, |
| 1032 | .fields = (const VMStateField[]) { |
| 1033 | VMSTATE_UINT64_ARRAY(env.opmask_regs, X86CPU, NB_OPMASK_REGS), |
| 1034 | VMSTATE_ZMMH_REGS_VARS(env.xmm_regs, X86CPU, 0), |
| 1035 | #ifdef TARGET_X86_64 |
| 1036 | VMSTATE_Hi16_ZMM_REGS_VARS(env.xmm_regs, X86CPU, 16), |
| 1037 | #endif |
| 1038 | VMSTATE_END_OF_LIST() |
| 1039 | } |
| 1040 | }; |
| 1041 | |
| 1042 | static bool xss_needed(void *opaque) |
| 1043 | { |
| 1044 | X86CPU *cpu = opaque; |
| 1045 | CPUX86State *env = &cpu->env; |
| 1046 | |
| 1047 | return env->xss != 0; |
| 1048 | } |
| 1049 | |
| 1050 | static const VMStateDescription vmstate_xss = { |
| 1051 | .name = "cpu/xss", |
| 1052 | .version_id = 1, |
| 1053 | .minimum_version_id = 1, |
| 1054 | .needed = xss_needed, |
| 1055 | .fields = (const VMStateField[]) { |
| 1056 | VMSTATE_UINT64(env.xss, X86CPU), |
| 1057 | VMSTATE_END_OF_LIST() |
| 1058 | } |
| 1059 | }; |
| 1060 | |
| 1061 | static bool umwait_needed(void *opaque) |
| 1062 | { |
| 1063 | X86CPU *cpu = opaque; |
| 1064 | CPUX86State *env = &cpu->env; |
| 1065 | |
| 1066 | return env->umwait != 0; |
| 1067 | } |
| 1068 | |
| 1069 | static const VMStateDescription vmstate_umwait = { |
| 1070 | .name = "cpu/umwait", |
| 1071 | .version_id = 1, |
| 1072 | .minimum_version_id = 1, |
| 1073 | .needed = umwait_needed, |
| 1074 | .fields = (const VMStateField[]) { |
| 1075 | VMSTATE_UINT32(env.umwait, X86CPU), |
| 1076 | VMSTATE_END_OF_LIST() |
| 1077 | } |
| 1078 | }; |
| 1079 | |
| 1080 | static bool pkru_needed(void *opaque) |
| 1081 | { |
| 1082 | X86CPU *cpu = opaque; |
| 1083 | CPUX86State *env = &cpu->env; |
| 1084 | |
| 1085 | return env->pkru != 0; |
| 1086 | } |
| 1087 | |
| 1088 | static const VMStateDescription vmstate_pkru = { |
| 1089 | .name = "cpu/pkru", |
| 1090 | .version_id = 1, |
| 1091 | .minimum_version_id = 1, |
| 1092 | .needed = pkru_needed, |
| 1093 | .fields = (const VMStateField[]){ |
| 1094 | VMSTATE_UINT32(env.pkru, X86CPU), |
| 1095 | VMSTATE_END_OF_LIST() |
| 1096 | } |
| 1097 | }; |
| 1098 | |
| 1099 | static bool pkrs_needed(void *opaque) |
| 1100 | { |
| 1101 | X86CPU *cpu = opaque; |
| 1102 | CPUX86State *env = &cpu->env; |
| 1103 | |
| 1104 | return env->pkrs != 0; |
| 1105 | } |
| 1106 | |
| 1107 | static const VMStateDescription vmstate_pkrs = { |
| 1108 | .name = "cpu/pkrs", |
| 1109 | .version_id = 1, |
| 1110 | .minimum_version_id = 1, |
| 1111 | .needed = pkrs_needed, |
| 1112 | .fields = (const VMStateField[]){ |
| 1113 | VMSTATE_UINT32(env.pkrs, X86CPU), |
| 1114 | VMSTATE_END_OF_LIST() |
| 1115 | } |
| 1116 | }; |
| 1117 | |
| 1118 | static bool tsc_khz_needed(void *opaque) |
| 1119 | { |
| 1120 | X86CPU *cpu = opaque; |
| 1121 | CPUX86State *env = &cpu->env; |
| 1122 | |
| 1123 | return env->tsc_khz; |
| 1124 | } |
| 1125 | |
| 1126 | static const VMStateDescription vmstate_tsc_khz = { |
| 1127 | .name = "cpu/tsc_khz", |
| 1128 | .version_id = 1, |
| 1129 | .minimum_version_id = 1, |
| 1130 | .needed = tsc_khz_needed, |
| 1131 | .fields = (const VMStateField[]) { |
| 1132 | VMSTATE_INT64(env.tsc_khz, X86CPU), |
| 1133 | VMSTATE_END_OF_LIST() |
| 1134 | } |
| 1135 | }; |
| 1136 | |
| 1137 | #ifdef CONFIG_KVM |
| 1138 | |
| 1139 | static bool vmx_vmcs12_needed(void *opaque) |
| 1140 | { |
| 1141 | struct kvm_nested_state *nested_state = opaque; |
| 1142 | return (nested_state->size > |
| 1143 | offsetof(struct kvm_nested_state, data.vmx[0].vmcs12)); |
| 1144 | } |
| 1145 | |
| 1146 | static const VMStateDescription vmstate_vmx_vmcs12 = { |
| 1147 | .name = "cpu/kvm_nested_state/vmx/vmcs12", |
| 1148 | .version_id = 1, |
| 1149 | .minimum_version_id = 1, |
| 1150 | .needed = vmx_vmcs12_needed, |
| 1151 | .fields = (const VMStateField[]) { |
| 1152 | VMSTATE_UINT8_ARRAY(data.vmx[0].vmcs12, |
| 1153 | struct kvm_nested_state, |
| 1154 | KVM_STATE_NESTED_VMX_VMCS_SIZE), |
| 1155 | VMSTATE_END_OF_LIST() |
| 1156 | } |
| 1157 | }; |
| 1158 | |
| 1159 | static bool vmx_shadow_vmcs12_needed(void *opaque) |
| 1160 | { |
| 1161 | struct kvm_nested_state *nested_state = opaque; |
| 1162 | return (nested_state->size > |
| 1163 | offsetof(struct kvm_nested_state, data.vmx[0].shadow_vmcs12)); |
| 1164 | } |
| 1165 | |
| 1166 | static const VMStateDescription vmstate_vmx_shadow_vmcs12 = { |
| 1167 | .name = "cpu/kvm_nested_state/vmx/shadow_vmcs12", |
| 1168 | .version_id = 1, |
| 1169 | .minimum_version_id = 1, |
| 1170 | .needed = vmx_shadow_vmcs12_needed, |
| 1171 | .fields = (const VMStateField[]) { |
| 1172 | VMSTATE_UINT8_ARRAY(data.vmx[0].shadow_vmcs12, |
| 1173 | struct kvm_nested_state, |
| 1174 | KVM_STATE_NESTED_VMX_VMCS_SIZE), |
| 1175 | VMSTATE_END_OF_LIST() |
| 1176 | } |
| 1177 | }; |
| 1178 | |
| 1179 | static bool vmx_nested_state_needed(void *opaque) |
| 1180 | { |
| 1181 | struct kvm_nested_state *nested_state = opaque; |
| 1182 | |
| 1183 | return (nested_state->format == KVM_STATE_NESTED_FORMAT_VMX && |
| 1184 | nested_state->hdr.vmx.vmxon_pa != -1ull); |
| 1185 | } |
| 1186 | |
| 1187 | static const VMStateDescription vmstate_vmx_nested_state = { |
| 1188 | .name = "cpu/kvm_nested_state/vmx", |
| 1189 | .version_id = 1, |
| 1190 | .minimum_version_id = 1, |
| 1191 | .needed = vmx_nested_state_needed, |
| 1192 | .fields = (const VMStateField[]) { |
| 1193 | VMSTATE_U64(hdr.vmx.vmxon_pa, struct kvm_nested_state), |
| 1194 | VMSTATE_U64(hdr.vmx.vmcs12_pa, struct kvm_nested_state), |
| 1195 | VMSTATE_U16(hdr.vmx.smm.flags, struct kvm_nested_state), |
| 1196 | VMSTATE_END_OF_LIST() |
| 1197 | }, |
| 1198 | .subsections = (const VMStateDescription * const []) { |
| 1199 | &vmstate_vmx_vmcs12, |
| 1200 | &vmstate_vmx_shadow_vmcs12, |
| 1201 | NULL, |
| 1202 | } |
| 1203 | }; |
| 1204 | |
| 1205 | static bool svm_nested_state_needed(void *opaque) |
| 1206 | { |
| 1207 | struct kvm_nested_state *nested_state = opaque; |
| 1208 | |
| 1209 | /* |
| 1210 | * HF_GUEST_MASK and HF2_GIF_MASK are already serialized |
| 1211 | * via hflags and hflags2, all that's left is the opaque |
| 1212 | * nested state blob. |
| 1213 | */ |
| 1214 | return (nested_state->format == KVM_STATE_NESTED_FORMAT_SVM && |
| 1215 | nested_state->size > offsetof(struct kvm_nested_state, data)); |
| 1216 | } |
| 1217 | |
| 1218 | static const VMStateDescription vmstate_svm_nested_state = { |
| 1219 | .name = "cpu/kvm_nested_state/svm", |
| 1220 | .version_id = 1, |
| 1221 | .minimum_version_id = 1, |
| 1222 | .needed = svm_nested_state_needed, |
| 1223 | .fields = (const VMStateField[]) { |
| 1224 | VMSTATE_U64(hdr.svm.vmcb_pa, struct kvm_nested_state), |
| 1225 | VMSTATE_UINT8_ARRAY(data.svm[0].vmcb12, |
| 1226 | struct kvm_nested_state, |
| 1227 | KVM_STATE_NESTED_SVM_VMCB_SIZE), |
| 1228 | VMSTATE_END_OF_LIST() |
| 1229 | } |
| 1230 | }; |
| 1231 | |
| 1232 | static bool nested_state_needed(void *opaque) |
| 1233 | { |
| 1234 | X86CPU *cpu = opaque; |
| 1235 | CPUX86State *env = &cpu->env; |
| 1236 | |
| 1237 | return (env->nested_state && |
| 1238 | (vmx_nested_state_needed(env->nested_state) || |
| 1239 | svm_nested_state_needed(env->nested_state))); |
| 1240 | } |
| 1241 | |
| 1242 | static int nested_state_post_load(void *opaque, int version_id) |
| 1243 | { |
| 1244 | X86CPU *cpu = opaque; |
| 1245 | CPUX86State *env = &cpu->env; |
| 1246 | struct kvm_nested_state *nested_state = env->nested_state; |
| 1247 | int min_nested_state_len = offsetof(struct kvm_nested_state, data); |
| 1248 | int max_nested_state_len = kvm_max_nested_state_length(); |
| 1249 | |
| 1250 | /* |
| 1251 | * If our kernel don't support setting nested state |
| 1252 | * and we have received nested state from migration stream, |
| 1253 | * we need to fail migration |
| 1254 | */ |
| 1255 | if (max_nested_state_len <= 0) { |
| 1256 | error_report("Received nested state when kernel cannot restore it"); |
| 1257 | return -EINVAL; |
| 1258 | } |
| 1259 | |
| 1260 | /* |
| 1261 | * Verify that the size of received nested_state struct |
| 1262 | * at least cover required header and is not larger |
| 1263 | * than the max size that our kernel support |
| 1264 | */ |
| 1265 | if (nested_state->size < min_nested_state_len) { |
| 1266 | error_report("Received nested state size less than min: " |
| 1267 | "len=%d, min=%d", |
| 1268 | nested_state->size, min_nested_state_len); |
| 1269 | return -EINVAL; |
| 1270 | } |
| 1271 | if (nested_state->size > max_nested_state_len) { |
| 1272 | error_report("Received unsupported nested state size: " |
| 1273 | "nested_state->size=%d, max=%d", |
| 1274 | nested_state->size, max_nested_state_len); |
| 1275 | return -EINVAL; |
| 1276 | } |
| 1277 | |
| 1278 | /* Verify format is valid */ |
| 1279 | if ((nested_state->format != KVM_STATE_NESTED_FORMAT_VMX) && |
| 1280 | (nested_state->format != KVM_STATE_NESTED_FORMAT_SVM)) { |
| 1281 | error_report("Received invalid nested state format: %d", |
| 1282 | nested_state->format); |
| 1283 | return -EINVAL; |
| 1284 | } |
| 1285 | |
| 1286 | return 0; |
| 1287 | } |
| 1288 | |
| 1289 | static const VMStateDescription vmstate_kvm_nested_state = { |
| 1290 | .name = "cpu/kvm_nested_state", |
| 1291 | .version_id = 1, |
| 1292 | .minimum_version_id = 1, |
| 1293 | .fields = (const VMStateField[]) { |
| 1294 | VMSTATE_U16(flags, struct kvm_nested_state), |
| 1295 | VMSTATE_U16(format, struct kvm_nested_state), |
| 1296 | VMSTATE_U32(size, struct kvm_nested_state), |
| 1297 | VMSTATE_END_OF_LIST() |
| 1298 | }, |
| 1299 | .subsections = (const VMStateDescription * const []) { |
| 1300 | &vmstate_vmx_nested_state, |
| 1301 | &vmstate_svm_nested_state, |
| 1302 | NULL |
| 1303 | } |
| 1304 | }; |
| 1305 | |
| 1306 | static const VMStateDescription vmstate_nested_state = { |
| 1307 | .name = "cpu/nested_state", |
| 1308 | .version_id = 1, |
| 1309 | .minimum_version_id = 1, |
| 1310 | .needed = nested_state_needed, |
| 1311 | .post_load = nested_state_post_load, |
| 1312 | .fields = (const VMStateField[]) { |
| 1313 | VMSTATE_STRUCT_POINTER(env.nested_state, X86CPU, |
| 1314 | vmstate_kvm_nested_state, |
| 1315 | struct kvm_nested_state), |
| 1316 | VMSTATE_END_OF_LIST() |
| 1317 | } |
| 1318 | }; |
| 1319 | |
| 1320 | static bool xen_vcpu_needed(void *opaque) |
| 1321 | { |
| 1322 | return (xen_mode == XEN_EMULATE); |
| 1323 | } |
| 1324 | |
| 1325 | static const VMStateDescription vmstate_xen_vcpu = { |
| 1326 | .name = "cpu/xen_vcpu", |
| 1327 | .version_id = 1, |
| 1328 | .minimum_version_id = 1, |
| 1329 | .needed = xen_vcpu_needed, |
| 1330 | .fields = (const VMStateField[]) { |
| 1331 | VMSTATE_UINT64(env.xen_vcpu_info_gpa, X86CPU), |
| 1332 | VMSTATE_UINT64(env.xen_vcpu_info_default_gpa, X86CPU), |
| 1333 | VMSTATE_UINT64(env.xen_vcpu_time_info_gpa, X86CPU), |
| 1334 | VMSTATE_UINT64(env.xen_vcpu_runstate_gpa, X86CPU), |
| 1335 | VMSTATE_UINT8(env.xen_vcpu_callback_vector, X86CPU), |
| 1336 | VMSTATE_UINT16_ARRAY(env.xen_virq, X86CPU, XEN_NR_VIRQS), |
| 1337 | VMSTATE_UINT64(env.xen_singleshot_timer_ns, X86CPU), |
| 1338 | VMSTATE_UINT64(env.xen_periodic_timer_period, X86CPU), |
| 1339 | VMSTATE_END_OF_LIST() |
| 1340 | } |
| 1341 | }; |
| 1342 | #endif |
| 1343 | |
| 1344 | static bool mcg_ext_ctl_needed(void *opaque) |
| 1345 | { |
| 1346 | X86CPU *cpu = opaque; |
| 1347 | CPUX86State *env = &cpu->env; |
| 1348 | return cpu->enable_lmce && env->mcg_ext_ctl; |
| 1349 | } |
| 1350 | |
| 1351 | static const VMStateDescription vmstate_mcg_ext_ctl = { |
| 1352 | .name = "cpu/mcg_ext_ctl", |
| 1353 | .version_id = 1, |
| 1354 | .minimum_version_id = 1, |
| 1355 | .needed = mcg_ext_ctl_needed, |
| 1356 | .fields = (const VMStateField[]) { |
| 1357 | VMSTATE_UINT64(env.mcg_ext_ctl, X86CPU), |
| 1358 | VMSTATE_END_OF_LIST() |
| 1359 | } |
| 1360 | }; |
| 1361 | |
| 1362 | static bool spec_ctrl_needed(void *opaque) |
| 1363 | { |
| 1364 | X86CPU *cpu = opaque; |
| 1365 | CPUX86State *env = &cpu->env; |
| 1366 | |
| 1367 | return env->spec_ctrl != 0; |
| 1368 | } |
| 1369 | |
| 1370 | static const VMStateDescription vmstate_spec_ctrl = { |
| 1371 | .name = "cpu/spec_ctrl", |
| 1372 | .version_id = 1, |
| 1373 | .minimum_version_id = 1, |
| 1374 | .needed = spec_ctrl_needed, |
| 1375 | .fields = (const VMStateField[]){ |
| 1376 | VMSTATE_UINT64(env.spec_ctrl, X86CPU), |
| 1377 | VMSTATE_END_OF_LIST() |
| 1378 | } |
| 1379 | }; |
| 1380 | |
| 1381 | |
| 1382 | static bool amd_tsc_scale_msr_needed(void *opaque) |
| 1383 | { |
| 1384 | X86CPU *cpu = opaque; |
| 1385 | CPUX86State *env = &cpu->env; |
| 1386 | |
| 1387 | return (env->features[FEAT_SVM] & CPUID_SVM_TSCSCALE); |
| 1388 | } |
| 1389 | |
| 1390 | static const VMStateDescription amd_tsc_scale_msr_ctrl = { |
| 1391 | .name = "cpu/amd_tsc_scale_msr", |
| 1392 | .version_id = 1, |
| 1393 | .minimum_version_id = 1, |
| 1394 | .needed = amd_tsc_scale_msr_needed, |
| 1395 | .fields = (const VMStateField[]){ |
| 1396 | VMSTATE_UINT64(env.amd_tsc_scale_msr, X86CPU), |
| 1397 | VMSTATE_END_OF_LIST() |
| 1398 | } |
| 1399 | }; |
| 1400 | |
| 1401 | |
| 1402 | static bool intel_pt_enable_needed(void *opaque) |
| 1403 | { |
| 1404 | X86CPU *cpu = opaque; |
| 1405 | CPUX86State *env = &cpu->env; |
| 1406 | int i; |
| 1407 | |
| 1408 | if (env->msr_rtit_ctrl || env->msr_rtit_status || |
| 1409 | env->msr_rtit_output_base || env->msr_rtit_output_mask || |
| 1410 | env->msr_rtit_cr3_match) { |
| 1411 | return true; |
| 1412 | } |
| 1413 | |
| 1414 | for (i = 0; i < MAX_RTIT_ADDRS; i++) { |
| 1415 | if (env->msr_rtit_addrs[i]) { |
| 1416 | return true; |
| 1417 | } |
| 1418 | } |
| 1419 | |
| 1420 | return false; |
| 1421 | } |
| 1422 | |
| 1423 | static const VMStateDescription vmstate_msr_intel_pt = { |
| 1424 | .name = "cpu/intel_pt", |
| 1425 | .version_id = 1, |
| 1426 | .minimum_version_id = 1, |
| 1427 | .needed = intel_pt_enable_needed, |
| 1428 | .fields = (const VMStateField[]) { |
| 1429 | VMSTATE_UINT64(env.msr_rtit_ctrl, X86CPU), |
| 1430 | VMSTATE_UINT64(env.msr_rtit_status, X86CPU), |
| 1431 | VMSTATE_UINT64(env.msr_rtit_output_base, X86CPU), |
| 1432 | VMSTATE_UINT64(env.msr_rtit_output_mask, X86CPU), |
| 1433 | VMSTATE_UINT64(env.msr_rtit_cr3_match, X86CPU), |
| 1434 | VMSTATE_UINT64_ARRAY(env.msr_rtit_addrs, X86CPU, MAX_RTIT_ADDRS), |
| 1435 | VMSTATE_END_OF_LIST() |
| 1436 | } |
| 1437 | }; |
| 1438 | |
| 1439 | static bool virt_ssbd_needed(void *opaque) |
| 1440 | { |
| 1441 | X86CPU *cpu = opaque; |
| 1442 | CPUX86State *env = &cpu->env; |
| 1443 | |
| 1444 | return env->virt_ssbd != 0; |
| 1445 | } |
| 1446 | |
| 1447 | static const VMStateDescription vmstate_msr_virt_ssbd = { |
| 1448 | .name = "cpu/virt_ssbd", |
| 1449 | .version_id = 1, |
| 1450 | .minimum_version_id = 1, |
| 1451 | .needed = virt_ssbd_needed, |
| 1452 | .fields = (const VMStateField[]){ |
| 1453 | VMSTATE_UINT64(env.virt_ssbd, X86CPU), |
| 1454 | VMSTATE_END_OF_LIST() |
| 1455 | } |
| 1456 | }; |
| 1457 | |
| 1458 | static bool svm_npt_needed(void *opaque) |
| 1459 | { |
| 1460 | X86CPU *cpu = opaque; |
| 1461 | CPUX86State *env = &cpu->env; |
| 1462 | |
| 1463 | return !!(env->hflags2 & HF2_NPT_MASK); |
| 1464 | } |
| 1465 | |
| 1466 | static const VMStateDescription vmstate_svm_npt = { |
| 1467 | .name = "cpu/svn_npt", |
| 1468 | .version_id = 1, |
| 1469 | .minimum_version_id = 1, |
| 1470 | .needed = svm_npt_needed, |
| 1471 | .fields = (const VMStateField[]){ |
| 1472 | VMSTATE_UINT64(env.nested_cr3, X86CPU), |
| 1473 | VMSTATE_UINT32(env.nested_pg_mode, X86CPU), |
| 1474 | VMSTATE_END_OF_LIST() |
| 1475 | } |
| 1476 | }; |
| 1477 | |
| 1478 | static bool svm_guest_needed(void *opaque) |
| 1479 | { |
| 1480 | X86CPU *cpu = opaque; |
| 1481 | CPUX86State *env = &cpu->env; |
| 1482 | |
| 1483 | return tcg_enabled() && env->int_ctl; |
| 1484 | } |
| 1485 | |
| 1486 | static const VMStateDescription vmstate_svm_guest = { |
| 1487 | .name = "cpu/svm_guest", |
| 1488 | .version_id = 1, |
| 1489 | .minimum_version_id = 1, |
| 1490 | .needed = svm_guest_needed, |
| 1491 | .fields = (const VMStateField[]){ |
| 1492 | VMSTATE_UINT32(env.int_ctl, X86CPU), |
| 1493 | VMSTATE_END_OF_LIST() |
| 1494 | } |
| 1495 | }; |
| 1496 | |
| 1497 | #ifndef TARGET_X86_64 |
| 1498 | static bool intel_efer32_needed(void *opaque) |
| 1499 | { |
| 1500 | X86CPU *cpu = opaque; |
| 1501 | CPUX86State *env = &cpu->env; |
| 1502 | |
| 1503 | return env->efer != 0; |
| 1504 | } |
| 1505 | |
| 1506 | static const VMStateDescription vmstate_efer32 = { |
| 1507 | .name = "cpu/efer32", |
| 1508 | .version_id = 1, |
| 1509 | .minimum_version_id = 1, |
| 1510 | .needed = intel_efer32_needed, |
| 1511 | .fields = (const VMStateField[]) { |
| 1512 | VMSTATE_UINT64(env.efer, X86CPU), |
| 1513 | VMSTATE_END_OF_LIST() |
| 1514 | } |
| 1515 | }; |
| 1516 | #endif |
| 1517 | |
| 1518 | static bool msr_tsx_ctrl_needed(void *opaque) |
| 1519 | { |
| 1520 | X86CPU *cpu = opaque; |
| 1521 | CPUX86State *env = &cpu->env; |
| 1522 | |
| 1523 | return env->features[FEAT_ARCH_CAPABILITIES] & ARCH_CAP_TSX_CTRL_MSR; |
| 1524 | } |
| 1525 | |
| 1526 | static const VMStateDescription vmstate_msr_tsx_ctrl = { |
| 1527 | .name = "cpu/msr_tsx_ctrl", |
| 1528 | .version_id = 1, |
| 1529 | .minimum_version_id = 1, |
| 1530 | .needed = msr_tsx_ctrl_needed, |
| 1531 | .fields = (const VMStateField[]) { |
| 1532 | VMSTATE_UINT32(env.tsx_ctrl, X86CPU), |
| 1533 | VMSTATE_END_OF_LIST() |
| 1534 | } |
| 1535 | }; |
| 1536 | |
| 1537 | static bool intel_sgx_msrs_needed(void *opaque) |
| 1538 | { |
| 1539 | X86CPU *cpu = opaque; |
| 1540 | CPUX86State *env = &cpu->env; |
| 1541 | |
| 1542 | return !!(env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_SGX_LC); |
| 1543 | } |
| 1544 | |
| 1545 | static const VMStateDescription vmstate_msr_intel_sgx = { |
| 1546 | .name = "cpu/intel_sgx", |
| 1547 | .version_id = 1, |
| 1548 | .minimum_version_id = 1, |
| 1549 | .needed = intel_sgx_msrs_needed, |
| 1550 | .fields = (const VMStateField[]) { |
| 1551 | VMSTATE_UINT64_ARRAY(env.msr_ia32_sgxlepubkeyhash, X86CPU, 4), |
| 1552 | VMSTATE_END_OF_LIST() |
| 1553 | } |
| 1554 | }; |
| 1555 | |
| 1556 | static bool pdptrs_needed(void *opaque) |
| 1557 | { |
| 1558 | X86CPU *cpu = opaque; |
| 1559 | CPUX86State *env = &cpu->env; |
| 1560 | return env->pdptrs_valid; |
| 1561 | } |
| 1562 | |
| 1563 | static int pdptrs_post_load(void *opaque, int version_id) |
| 1564 | { |
| 1565 | X86CPU *cpu = opaque; |
| 1566 | CPUX86State *env = &cpu->env; |
| 1567 | env->pdptrs_valid = true; |
| 1568 | return 0; |
| 1569 | } |
| 1570 | |
| 1571 | |
| 1572 | static const VMStateDescription vmstate_pdptrs = { |
| 1573 | .name = "cpu/pdptrs", |
| 1574 | .version_id = 1, |
| 1575 | .minimum_version_id = 1, |
| 1576 | .needed = pdptrs_needed, |
| 1577 | .post_load = pdptrs_post_load, |
| 1578 | .fields = (const VMStateField[]) { |
| 1579 | VMSTATE_UINT64_ARRAY(env.pdptrs, X86CPU, 4), |
| 1580 | VMSTATE_END_OF_LIST() |
| 1581 | } |
| 1582 | }; |
| 1583 | |
| 1584 | static bool xfd_msrs_needed(void *opaque) |
| 1585 | { |
| 1586 | X86CPU *cpu = opaque; |
| 1587 | CPUX86State *env = &cpu->env; |
| 1588 | |
| 1589 | return !!(env->features[FEAT_XSAVE] & CPUID_D_1_EAX_XFD); |
| 1590 | } |
| 1591 | |
| 1592 | static const VMStateDescription vmstate_msr_xfd = { |
| 1593 | .name = "cpu/msr_xfd", |
| 1594 | .version_id = 1, |
| 1595 | .minimum_version_id = 1, |
| 1596 | .needed = xfd_msrs_needed, |
| 1597 | .fields = (const VMStateField[]) { |
| 1598 | VMSTATE_UINT64(env.msr_xfd, X86CPU), |
| 1599 | VMSTATE_UINT64(env.msr_xfd_err, X86CPU), |
| 1600 | VMSTATE_END_OF_LIST() |
| 1601 | } |
| 1602 | }; |
| 1603 | |
| 1604 | static bool msr_hwcr_needed(void *opaque) |
| 1605 | { |
| 1606 | X86CPU *cpu = opaque; |
| 1607 | CPUX86State *env = &cpu->env; |
| 1608 | |
| 1609 | return env->msr_hwcr != 0; |
| 1610 | } |
| 1611 | |
| 1612 | static const VMStateDescription vmstate_msr_hwcr = { |
| 1613 | .name = "cpu/msr_hwcr", |
| 1614 | .version_id = 1, |
| 1615 | .minimum_version_id = 1, |
| 1616 | .needed = msr_hwcr_needed, |
| 1617 | .fields = (VMStateField[]) { |
| 1618 | VMSTATE_UINT64(env.msr_hwcr, X86CPU), |
| 1619 | VMSTATE_END_OF_LIST() |
| 1620 | } |
| 1621 | }; |
| 1622 | |
| 1623 | #ifdef TARGET_X86_64 |
| 1624 | static bool intel_fred_msrs_needed(void *opaque) |
| 1625 | { |
| 1626 | X86CPU *cpu = opaque; |
| 1627 | CPUX86State *env = &cpu->env; |
| 1628 | |
| 1629 | return !!(env->features[FEAT_7_1_EAX] & CPUID_7_1_EAX_FRED); |
| 1630 | } |
| 1631 | |
| 1632 | static const VMStateDescription vmstate_msr_fred = { |
| 1633 | .name = "cpu/fred", |
| 1634 | .version_id = 1, |
| 1635 | .minimum_version_id = 1, |
| 1636 | .needed = intel_fred_msrs_needed, |
| 1637 | .fields = (VMStateField[]) { |
| 1638 | VMSTATE_UINT64(env.fred_rsp0, X86CPU), |
| 1639 | VMSTATE_UINT64(env.fred_rsp1, X86CPU), |
| 1640 | VMSTATE_UINT64(env.fred_rsp2, X86CPU), |
| 1641 | VMSTATE_UINT64(env.fred_rsp3, X86CPU), |
| 1642 | VMSTATE_UINT64(env.fred_stklvls, X86CPU), |
| 1643 | VMSTATE_UINT64(env.fred_ssp1, X86CPU), |
| 1644 | VMSTATE_UINT64(env.fred_ssp2, X86CPU), |
| 1645 | VMSTATE_UINT64(env.fred_ssp3, X86CPU), |
| 1646 | VMSTATE_UINT64(env.fred_config, X86CPU), |
| 1647 | VMSTATE_END_OF_LIST() |
| 1648 | } |
| 1649 | }; |
| 1650 | |
| 1651 | static bool amx_xtile_needed(void *opaque) |
| 1652 | { |
| 1653 | X86CPU *cpu = opaque; |
| 1654 | CPUX86State *env = &cpu->env; |
| 1655 | |
| 1656 | return !!(env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_AMX_TILE); |
| 1657 | } |
| 1658 | |
| 1659 | static const VMStateDescription vmstate_amx_xtile = { |
| 1660 | .name = "cpu/intel_amx_xtile", |
| 1661 | .version_id = 1, |
| 1662 | .minimum_version_id = 1, |
| 1663 | .needed = amx_xtile_needed, |
| 1664 | .fields = (const VMStateField[]) { |
| 1665 | VMSTATE_UINT8_ARRAY(env.xtilecfg, X86CPU, 64), |
| 1666 | VMSTATE_UINT8_ARRAY(env.xtiledata, X86CPU, 8192), |
| 1667 | VMSTATE_END_OF_LIST() |
| 1668 | } |
| 1669 | }; |
| 1670 | #endif |
| 1671 | |
| 1672 | static bool arch_lbr_needed(void *opaque) |
| 1673 | { |
| 1674 | X86CPU *cpu = opaque; |
| 1675 | CPUX86State *env = &cpu->env; |
| 1676 | |
| 1677 | return !!(env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR); |
| 1678 | } |
| 1679 | |
| 1680 | static const VMStateDescription vmstate_arch_lbr = { |
| 1681 | .name = "cpu/arch_lbr", |
| 1682 | .version_id = 1, |
| 1683 | .minimum_version_id = 1, |
| 1684 | .needed = arch_lbr_needed, |
| 1685 | .fields = (const VMStateField[]) { |
| 1686 | VMSTATE_UINT64(env.msr_lbr_ctl, X86CPU), |
| 1687 | VMSTATE_UINT64(env.msr_lbr_depth, X86CPU), |
| 1688 | VMSTATE_LBR_VARS(env.lbr_records, X86CPU, ARCH_LBR_NR_ENTRIES, 1), |
| 1689 | VMSTATE_END_OF_LIST() |
| 1690 | } |
| 1691 | }; |
| 1692 | |
| 1693 | static bool triple_fault_needed(void *opaque) |
| 1694 | { |
| 1695 | X86CPU *cpu = opaque; |
| 1696 | CPUX86State *env = &cpu->env; |
| 1697 | |
| 1698 | return env->triple_fault_pending; |
| 1699 | } |
| 1700 | |
| 1701 | static const VMStateDescription vmstate_triple_fault = { |
| 1702 | .name = "cpu/triple_fault", |
| 1703 | .version_id = 1, |
| 1704 | .minimum_version_id = 1, |
| 1705 | .needed = triple_fault_needed, |
| 1706 | .fields = (const VMStateField[]) { |
| 1707 | VMSTATE_UINT8(env.triple_fault_pending, X86CPU), |
| 1708 | VMSTATE_END_OF_LIST() |
| 1709 | } |
| 1710 | }; |
| 1711 | |
| 1712 | static bool pl0_ssp_needed(void *opaque) |
| 1713 | { |
| 1714 | X86CPU *cpu = opaque; |
| 1715 | |
| 1716 | /* |
| 1717 | * CPUID_7_1_EAX_FRED and CPUID_7_0_ECX_CET_SHSTK are checked because |
| 1718 | * if all of these bits are zero and the MSR will not be settable. |
| 1719 | */ |
| 1720 | return !!(cpu->env.pl0_ssp); |
| 1721 | } |
| 1722 | |
| 1723 | static const VMStateDescription vmstate_pl0_ssp = { |
| 1724 | .name = "cpu/msr_pl0_ssp", |
| 1725 | .version_id = 1, |
| 1726 | .minimum_version_id = 1, |
| 1727 | .needed = pl0_ssp_needed, |
| 1728 | .fields = (const VMStateField[]) { |
| 1729 | VMSTATE_UINT64(env.pl0_ssp, X86CPU), |
| 1730 | VMSTATE_END_OF_LIST() |
| 1731 | } |
| 1732 | }; |
| 1733 | |
| 1734 | static bool shstk_needed(void *opaque) |
| 1735 | { |
| 1736 | X86CPU *cpu = opaque; |
| 1737 | CPUX86State *env = &cpu->env; |
| 1738 | |
| 1739 | return !!(env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_CET_SHSTK); |
| 1740 | } |
| 1741 | |
| 1742 | static const VMStateDescription vmstate_shstk = { |
| 1743 | .name = "cpu/cet_shstk", |
| 1744 | .version_id = 1, |
| 1745 | .minimum_version_id = 1, |
| 1746 | .needed = shstk_needed, |
| 1747 | .fields = (VMStateField[]) { |
| 1748 | /* pl0_ssp has been covered by vmstate_pl0_ssp. */ |
| 1749 | VMSTATE_UINT64(env.pl1_ssp, X86CPU), |
| 1750 | VMSTATE_UINT64(env.pl2_ssp, X86CPU), |
| 1751 | VMSTATE_UINT64(env.pl3_ssp, X86CPU), |
| 1752 | #ifdef TARGET_X86_64 |
| 1753 | VMSTATE_UINT64(env.int_ssp_table, X86CPU), |
| 1754 | #endif |
| 1755 | VMSTATE_UINT64(env.guest_ssp, X86CPU), |
| 1756 | VMSTATE_END_OF_LIST() |
| 1757 | } |
| 1758 | }; |
| 1759 | |
| 1760 | static bool cet_needed(void *opaque) |
| 1761 | { |
| 1762 | X86CPU *cpu = opaque; |
| 1763 | CPUX86State *env = &cpu->env; |
| 1764 | |
| 1765 | return !!((env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_CET_SHSTK) || |
| 1766 | (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_CET_IBT)); |
| 1767 | } |
| 1768 | |
| 1769 | static const VMStateDescription vmstate_cet = { |
| 1770 | .name = "cpu/cet", |
| 1771 | .version_id = 1, |
| 1772 | .minimum_version_id = 1, |
| 1773 | .needed = cet_needed, |
| 1774 | .fields = (VMStateField[]) { |
| 1775 | VMSTATE_UINT64(env.u_cet, X86CPU), |
| 1776 | VMSTATE_UINT64(env.s_cet, X86CPU), |
| 1777 | VMSTATE_END_OF_LIST() |
| 1778 | }, |
| 1779 | .subsections = (const VMStateDescription * const []) { |
| 1780 | &vmstate_shstk, |
| 1781 | NULL, |
| 1782 | }, |
| 1783 | }; |
| 1784 | |
| 1785 | #ifdef TARGET_X86_64 |
| 1786 | static bool apx_needed(void *opaque) |
| 1787 | { |
| 1788 | X86CPU *cpu = opaque; |
| 1789 | CPUX86State *env = &cpu->env; |
| 1790 | |
| 1791 | return !!(env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_APXF); |
| 1792 | } |
| 1793 | |
| 1794 | static const VMStateDescription vmstate_apx = { |
| 1795 | .name = "cpu/apx", |
| 1796 | .version_id = 1, |
| 1797 | .minimum_version_id = 1, |
| 1798 | .needed = apx_needed, |
| 1799 | .fields = (VMStateField[]) { |
| 1800 | VMSTATE_UINT64_SUB_ARRAY(env.regs, X86CPU, CPU_NB_REGS, |
| 1801 | CPU_NB_EREGS - CPU_NB_REGS), |
| 1802 | VMSTATE_END_OF_LIST() |
| 1803 | } |
| 1804 | }; |
| 1805 | #endif |
| 1806 | |
| 1807 | const VMStateDescription vmstate_x86_cpu = { |
| 1808 | .name = "cpu", |
| 1809 | .version_id = 12, |
| 1810 | .minimum_version_id = 11, |
| 1811 | .pre_save = cpu_pre_save, |
| 1812 | .post_load = cpu_post_load, |
| 1813 | .fields = (const VMStateField[]) { |
| 1814 | VMSTATE_UINTTL_SUB_ARRAY(env.regs, X86CPU, 0, CPU_NB_REGS), |
| 1815 | VMSTATE_UINTTL(env.eip, X86CPU), |
| 1816 | VMSTATE_UINTTL(env.eflags, X86CPU), |
| 1817 | VMSTATE_UINT32(env.hflags, X86CPU), |
| 1818 | /* FPU */ |
| 1819 | VMSTATE_UINT16(env.fpuc, X86CPU), |
| 1820 | VMSTATE_UINT16(env.fpus_vmstate, X86CPU), |
| 1821 | VMSTATE_UINT16(env.fptag_vmstate, X86CPU), |
| 1822 | VMSTATE_UINT16(env.fpregs_format_vmstate, X86CPU), |
| 1823 | |
| 1824 | VMSTATE_STRUCT_ARRAY(env.fpregs, X86CPU, 8, 0, vmstate_fpreg, FPReg), |
| 1825 | |
| 1826 | VMSTATE_SEGMENT_ARRAY(env.segs, X86CPU, 6), |
| 1827 | VMSTATE_SEGMENT(env.ldt, X86CPU), |
| 1828 | VMSTATE_SEGMENT(env.tr, X86CPU), |
| 1829 | VMSTATE_SEGMENT(env.gdt, X86CPU), |
| 1830 | VMSTATE_SEGMENT(env.idt, X86CPU), |
| 1831 | |
| 1832 | VMSTATE_UINT32(env.sysenter_cs, X86CPU), |
| 1833 | VMSTATE_UINTTL(env.sysenter_esp, X86CPU), |
| 1834 | VMSTATE_UINTTL(env.sysenter_eip, X86CPU), |
| 1835 | |
| 1836 | VMSTATE_UINTTL(env.cr[0], X86CPU), |
| 1837 | VMSTATE_UINTTL(env.cr[2], X86CPU), |
| 1838 | VMSTATE_UINTTL(env.cr[3], X86CPU), |
| 1839 | VMSTATE_UINTTL(env.cr[4], X86CPU), |
| 1840 | VMSTATE_UINTTL_ARRAY(env.dr, X86CPU, 8), |
| 1841 | /* MMU */ |
| 1842 | VMSTATE_INT32(env.a20_mask, X86CPU), |
| 1843 | /* XMM */ |
| 1844 | VMSTATE_UINT32(env.mxcsr, X86CPU), |
| 1845 | VMSTATE_XMM_REGS(env.xmm_regs, X86CPU, 0), |
| 1846 | |
| 1847 | #ifdef TARGET_X86_64 |
| 1848 | VMSTATE_UINT64(env.efer, X86CPU), |
| 1849 | VMSTATE_UINT64(env.star, X86CPU), |
| 1850 | VMSTATE_UINT64(env.lstar, X86CPU), |
| 1851 | VMSTATE_UINT64(env.cstar, X86CPU), |
| 1852 | VMSTATE_UINT64(env.fmask, X86CPU), |
| 1853 | VMSTATE_UINT64(env.kernelgsbase, X86CPU), |
| 1854 | #endif |
| 1855 | VMSTATE_UINT32(env.smbase, X86CPU), |
| 1856 | |
| 1857 | VMSTATE_UINT64(env.pat, X86CPU), |
| 1858 | VMSTATE_UINT32(env.hflags2, X86CPU), |
| 1859 | |
| 1860 | VMSTATE_UINT64(env.vm_hsave, X86CPU), |
| 1861 | VMSTATE_UINT64(env.vm_vmcb, X86CPU), |
| 1862 | VMSTATE_UINT64(env.tsc_offset, X86CPU), |
| 1863 | VMSTATE_UINT64(env.intercept, X86CPU), |
| 1864 | VMSTATE_UINT16(env.intercept_cr_read, X86CPU), |
| 1865 | VMSTATE_UINT16(env.intercept_cr_write, X86CPU), |
| 1866 | VMSTATE_UINT16(env.intercept_dr_read, X86CPU), |
| 1867 | VMSTATE_UINT16(env.intercept_dr_write, X86CPU), |
| 1868 | VMSTATE_UINT32(env.intercept_exceptions, X86CPU), |
| 1869 | VMSTATE_UINT8(env.v_tpr, X86CPU), |
| 1870 | /* MTRRs */ |
| 1871 | VMSTATE_UINT64_ARRAY(env.mtrr_fixed, X86CPU, 11), |
| 1872 | VMSTATE_UINT64(env.mtrr_deftype, X86CPU), |
| 1873 | VMSTATE_MTRR_VARS(env.mtrr_var, X86CPU, MSR_MTRRcap_VCNT, 8), |
| 1874 | /* KVM-related states */ |
| 1875 | VMSTATE_INT32(env.interrupt_injected, X86CPU), |
| 1876 | VMSTATE_UINT32(env.mp_state, X86CPU), |
| 1877 | VMSTATE_UINT64(env.tsc, X86CPU), |
| 1878 | VMSTATE_INT32(env.exception_nr, X86CPU), |
| 1879 | VMSTATE_UINT8(env.soft_interrupt, X86CPU), |
| 1880 | VMSTATE_UINT8(env.nmi_injected, X86CPU), |
| 1881 | VMSTATE_UINT8(env.nmi_pending, X86CPU), |
| 1882 | VMSTATE_UINT8(env.has_error_code, X86CPU), |
| 1883 | VMSTATE_UINT32(env.sipi_vector, X86CPU), |
| 1884 | /* MCE */ |
| 1885 | VMSTATE_UINT64(env.mcg_cap, X86CPU), |
| 1886 | VMSTATE_UINT64(env.mcg_status, X86CPU), |
| 1887 | VMSTATE_UINT64(env.mcg_ctl, X86CPU), |
| 1888 | VMSTATE_UINT64_ARRAY(env.mce_banks, X86CPU, MCE_BANKS_DEF * 4), |
| 1889 | /* rdtscp */ |
| 1890 | VMSTATE_UINT64(env.tsc_aux, X86CPU), |
| 1891 | /* KVM pvclock msr */ |
| 1892 | VMSTATE_UINT64(env.system_time_msr, X86CPU), |
| 1893 | VMSTATE_UINT64(env.wall_clock_msr, X86CPU), |
| 1894 | /* XSAVE related fields */ |
| 1895 | VMSTATE_UINT64_V(env.xcr0, X86CPU, 12), |
| 1896 | VMSTATE_UINT64_V(env.xstate_bv, X86CPU, 12), |
| 1897 | VMSTATE_YMMH_REGS_VARS(env.xmm_regs, X86CPU, 0, 12), |
| 1898 | VMSTATE_END_OF_LIST() |
| 1899 | /* The above list is not sorted /wrt version numbers, watch out! */ |
| 1900 | }, |
| 1901 | .subsections = (const VMStateDescription * const []) { |
| 1902 | &vmstate_exception_info, |
| 1903 | &vmstate_error_code, |
| 1904 | &vmstate_async_pf_msr, |
| 1905 | &vmstate_async_pf_int_msr, |
| 1906 | &vmstate_pv_eoi_msr, |
| 1907 | &vmstate_steal_time_msr, |
| 1908 | &vmstate_poll_control_msr, |
| 1909 | &vmstate_fpop_ip_dp, |
| 1910 | &vmstate_msr_tsc_adjust, |
| 1911 | &vmstate_msr_tscdeadline, |
| 1912 | &vmstate_msr_ia32_misc_enable, |
| 1913 | &vmstate_msr_ia32_feature_control, |
| 1914 | &vmstate_msr_architectural_pmu, |
| 1915 | &vmstate_mpx, |
| 1916 | &vmstate_msr_hyperv_hypercall, |
| 1917 | &vmstate_msr_hyperv_vapic, |
| 1918 | &vmstate_msr_hyperv_time, |
| 1919 | &vmstate_msr_hyperv_crash, |
| 1920 | &vmstate_msr_hyperv_runtime, |
| 1921 | &vmstate_msr_hyperv_synic, |
| 1922 | &vmstate_msr_hyperv_stimer, |
| 1923 | &vmstate_msr_hyperv_reenlightenment, |
| 1924 | &vmstate_avx512, |
| 1925 | &vmstate_xss, |
| 1926 | &vmstate_umwait, |
| 1927 | &vmstate_tsc_khz, |
| 1928 | &vmstate_msr_smi_count, |
| 1929 | &vmstate_pkru, |
| 1930 | &vmstate_pkrs, |
| 1931 | &vmstate_spec_ctrl, |
| 1932 | &amd_tsc_scale_msr_ctrl, |
| 1933 | &vmstate_mcg_ext_ctl, |
| 1934 | &vmstate_msr_intel_pt, |
| 1935 | &vmstate_msr_virt_ssbd, |
| 1936 | &vmstate_svm_npt, |
| 1937 | &vmstate_svm_guest, |
| 1938 | #ifndef TARGET_X86_64 |
| 1939 | &vmstate_efer32, |
| 1940 | #endif |
| 1941 | #ifdef CONFIG_KVM |
| 1942 | &vmstate_nested_state, |
| 1943 | &vmstate_xen_vcpu, |
| 1944 | #endif |
| 1945 | &vmstate_msr_tsx_ctrl, |
| 1946 | &vmstate_msr_intel_sgx, |
| 1947 | &vmstate_pdptrs, |
| 1948 | &vmstate_msr_xfd, |
| 1949 | &vmstate_msr_hwcr, |
| 1950 | #ifdef TARGET_X86_64 |
| 1951 | &vmstate_msr_fred, |
| 1952 | &vmstate_amx_xtile, |
| 1953 | #endif |
| 1954 | &vmstate_arch_lbr, |
| 1955 | &vmstate_triple_fault, |
| 1956 | &vmstate_pl0_ssp, |
| 1957 | &vmstate_cet, |
| 1958 | #ifdef TARGET_X86_64 |
| 1959 | &vmstate_apx, |
| 1960 | #endif |
| 1961 | #ifdef CONFIG_MSHV |
| 1962 | &vmstate_mshv_synic_vp_state, |
| 1963 | &vmstate_mshv_synthetic_timers, |
| 1964 | #endif |
| 1965 | NULL |
| 1966 | } |
| 1967 | }; |