@samitouri / QOSamiQemu
Code Commits Issues Pulls Sessions CI/CD
master
master
c 177 lines 5.68 KB
Raw
1 /*
2 * x86 exception helpers
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "accel/tcg/cpu-loop.h"
22 #include "cpu.h"
23 #include "qemu/log.h"
24 #include "system/runstate.h"
25 #include "exec/helper-proto.h"
26 #include "helper-tcg.h"
27 #include "qemu/plugin.h"
28
29 G_NORETURN void helper_raise_interrupt(CPUX86State *env, int intno,
30 int next_eip_addend)
31 {
32 raise_interrupt(env, intno, next_eip_addend);
33 }
34
35 G_NORETURN void helper_raise_exception(CPUX86State *env, int exception_index)
36 {
37 raise_exception(env, exception_index);
38 }
39
40 /*
41 * Check nested exceptions and change to double or triple fault if
42 * needed. It should only be called, if this is not an interrupt.
43 * Returns the new exception number.
44 */
45 static int check_exception(CPUX86State *env, int intno, int *error_code,
46 uintptr_t retaddr)
47 {
48 int first_contributory = env->old_exception == 0 ||
49 (env->old_exception >= 10 &&
50 env->old_exception <= 13);
51 int second_contributory = intno == 0 ||
52 (intno >= 10 && intno <= 13);
53
54 qemu_log_mask(CPU_LOG_INT, "check_exception old: 0x%x new 0x%x\n",
55 env->old_exception, intno);
56
57 #if !defined(CONFIG_USER_ONLY)
58 if (env->old_exception == EXCP08_DBLE) {
59 if (env->hflags & HF_GUEST_MASK) {
60 cpu_vmexit(env, SVM_EXIT_SHUTDOWN, 0, retaddr); /* does not return */
61 }
62
63 qemu_log_mask(CPU_LOG_RESET, "Triple fault\n");
64
65 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
66 return EXCP_HLT;
67 }
68 #endif
69
70 if ((first_contributory && second_contributory)
71 || (env->old_exception == EXCP0E_PAGE &&
72 (second_contributory || (intno == EXCP0E_PAGE)))) {
73 intno = EXCP08_DBLE;
74 *error_code = 0;
75 }
76
77 if (second_contributory || (intno == EXCP0E_PAGE) ||
78 (intno == EXCP08_DBLE)) {
79 env->old_exception = intno;
80 }
81
82 return intno;
83 }
84
85 /*
86 * Signal an interruption. It is executed in the main CPU loop.
87 * is_int is TRUE if coming from the int instruction. next_eip is the
88 * env->eip value AFTER the interrupt instruction. It is only relevant if
89 * is_int is TRUE.
90 */
91 static G_NORETURN
92 void raise_interrupt2(CPUX86State *env, int intno,
93 int is_int, int error_code,
94 int next_eip_addend,
95 uintptr_t retaddr)
96 {
97 CPUState *cs = env_cpu(env);
98 uint64_t last_pc = env->eip + env->segs[R_CS].base;
99
100 if (!is_int) {
101 cpu_svm_check_intercept_param(env, SVM_EXIT_EXCP_BASE + intno,
102 error_code, retaddr);
103 intno = check_exception(env, intno, &error_code, retaddr);
104 } else {
105 cpu_svm_check_intercept_param(env, SVM_EXIT_SWINT, 0, retaddr);
106 }
107
108 cs->exception_index = intno;
109 env->error_code = error_code;
110 env->exception_is_int = is_int;
111 env->exception_next_eip = env->eip + next_eip_addend;
112 qemu_plugin_vcpu_exception_cb(cs, last_pc);
113 cpu_loop_exit_restore(cs, retaddr);
114 }
115
116 /* shortcuts to generate exceptions */
117
118 G_NORETURN void raise_interrupt(CPUX86State *env, int intno, int next_eip_addend)
119 {
120 raise_interrupt2(env, intno, 1, 0, next_eip_addend, 0);
121 }
122
123 G_NORETURN void raise_exception_err(CPUX86State *env, int exception_index,
124 int error_code)
125 {
126 raise_interrupt2(env, exception_index, 0, error_code, 0, 0);
127 }
128
129 G_NORETURN void raise_exception_err_ra(CPUX86State *env, int exception_index,
130 int error_code, uintptr_t retaddr)
131 {
132 raise_interrupt2(env, exception_index, 0, error_code, 0, retaddr);
133 }
134
135 G_NORETURN void raise_exception(CPUX86State *env, int exception_index)
136 {
137 raise_interrupt2(env, exception_index, 0, 0, 0, 0);
138 }
139
140 G_NORETURN void raise_exception_ra(CPUX86State *env, int exception_index,
141 uintptr_t retaddr)
142 {
143 raise_interrupt2(env, exception_index, 0, 0, 0, retaddr);
144 }
145
146 G_NORETURN void helper_icebp(CPUX86State *env)
147 {
148 CPUState *cs = env_cpu(env);
149
150 do_end_instruction(env);
151
152 /*
153 * INT1 aka ICEBP generates a trap-like #DB, but it is pretty special.
154 *
155 * "Although the ICEBP instruction dispatches through IDT vector 1,
156 * that event is not interceptable by means of the #DB exception
157 * intercept". Instead there is a separate fault-like ICEBP intercept.
158 */
159 cs->exception_index = EXCP01_DB;
160 env->error_code = 0;
161 env->exception_is_int = 0;
162 env->exception_next_eip = env->eip;
163 cpu_loop_exit(cs);
164 }
165
166 G_NORETURN void handle_unaligned_access(CPUX86State *env, vaddr vaddr,
167 MMUAccessType access_type,
168 uintptr_t retaddr)
169 {
170 /*
171 * Unaligned accesses are currently only triggered by SSE/AVX
172 * instructions that impose alignment requirements on memory
173 * operands. These instructions raise #GP(0) upon accessing an
174 * unaligned address.
175 */
176 raise_exception_ra(env, EXCP0D_GPF, retaddr);
177 }