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1 /*
2 * x86 misc helpers - system code
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "qemu/main-loop.h"
22 #include "cpu.h"
23 #include "exec/helper-proto.h"
24 #include "accel/tcg/cpu-ldst.h"
25 #include "accel/tcg/cpu-loop.h"
26 #include "system/address-spaces.h"
27 #include "system/memory.h"
28 #include "exec/cputlb.h"
29 #include "tcg/helper-tcg.h"
30 #include "hw/i386/apic.h"
31
32 void helper_outb(CPUX86State *env, uint32_t port, uint32_t data)
33 {
34 address_space_stb(&address_space_io, port, data,
35 cpu_get_mem_attrs(env), NULL);
36 }
37
38 target_ulong helper_inb(CPUX86State *env, uint32_t port)
39 {
40 return address_space_ldub(&address_space_io, port,
41 cpu_get_mem_attrs(env), NULL);
42 }
43
44 void helper_outw(CPUX86State *env, uint32_t port, uint32_t data)
45 {
46 address_space_stw_le(&address_space_io, port, data,
47 cpu_get_mem_attrs(env), NULL);
48 }
49
50 target_ulong helper_inw(CPUX86State *env, uint32_t port)
51 {
52 return address_space_lduw_le(&address_space_io, port,
53 cpu_get_mem_attrs(env), NULL);
54 }
55
56 void helper_outl(CPUX86State *env, uint32_t port, uint32_t data)
57 {
58 address_space_stl_le(&address_space_io, port, data,
59 cpu_get_mem_attrs(env), NULL);
60 }
61
62 target_ulong helper_inl(CPUX86State *env, uint32_t port)
63 {
64 return address_space_ldl_le(&address_space_io, port,
65 cpu_get_mem_attrs(env), NULL);
66 }
67
68 target_ulong helper_read_cr8(CPUX86State *env)
69 {
70 if (!(env->hflags2 & HF2_VINTR_MASK)) {
71 return cpu_get_apic_tpr(env_archcpu(env)->apic_state);
72 } else {
73 return env->int_ctl & V_TPR_MASK;
74 }
75 }
76
77 void helper_write_crN(CPUX86State *env, int reg, target_ulong t0)
78 {
79 switch (reg) {
80 case 0:
81 /*
82 * If we reach this point, the CR0 write intercept is disabled.
83 * But we could still exit if the hypervisor has requested the selective
84 * intercept for bits other than TS and MP
85 */
86 if (cpu_svm_has_intercept(env, SVM_EXIT_CR0_SEL_WRITE) &&
87 ((env->cr[0] ^ t0) & ~(CR0_TS_MASK | CR0_MP_MASK))) {
88 cpu_vmexit(env, SVM_EXIT_CR0_SEL_WRITE, 0, GETPC());
89 }
90 cpu_x86_update_cr0(env, t0);
91 break;
92 case 3:
93 if ((env->efer & MSR_EFER_LMA) &&
94 (t0 & ((~0ULL) << env_archcpu(env)->phys_bits))) {
95 cpu_vmexit(env, SVM_EXIT_ERR, 0, GETPC());
96 }
97 if (!(env->efer & MSR_EFER_LMA)) {
98 t0 &= 0xffffffffUL;
99 }
100 cpu_x86_update_cr3(env, t0);
101 break;
102 case 4:
103 if (t0 & cr4_reserved_bits(env)) {
104 cpu_vmexit(env, SVM_EXIT_ERR, 0, GETPC());
105 }
106 if (((t0 ^ env->cr[4]) & CR4_LA57_MASK) &&
107 (env->hflags & HF_CS64_MASK)) {
108 raise_exception_ra(env, EXCP0D_GPF, GETPC());
109 }
110 cpu_x86_update_cr4(env, t0);
111 break;
112 case 8:
113 if (!(env->hflags2 & HF2_VINTR_MASK)) {
114 bql_lock();
115 cpu_set_apic_tpr(env_archcpu(env)->apic_state, t0);
116 bql_unlock();
117 }
118 env->int_ctl = (env->int_ctl & ~V_TPR_MASK) | (t0 & V_TPR_MASK);
119
120 CPUState *cs = env_cpu(env);
121 if (ctl_has_irq(env)) {
122 cpu_interrupt(cs, CPU_INTERRUPT_VIRQ);
123 } else {
124 cpu_reset_interrupt(cs, CPU_INTERRUPT_VIRQ);
125 }
126 break;
127 default:
128 env->cr[reg] = t0;
129 break;
130 }
131 }
132
133 void helper_wrmsr(CPUX86State *env)
134 {
135 uint64_t val;
136 CPUState *cs = env_cpu(env);
137
138 cpu_svm_check_intercept_param(env, SVM_EXIT_MSR, 1, GETPC());
139
140 val = ((uint32_t)env->regs[R_EAX]) |
141 ((uint64_t)((uint32_t)env->regs[R_EDX]) << 32);
142
143 switch ((uint32_t)env->regs[R_ECX]) {
144 case MSR_IA32_SYSENTER_CS:
145 env->sysenter_cs = val & 0xffff;
146 break;
147 case MSR_IA32_SYSENTER_ESP:
148 env->sysenter_esp = val;
149 break;
150 case MSR_IA32_SYSENTER_EIP:
151 env->sysenter_eip = val;
152 break;
153 case MSR_IA32_APICBASE: {
154 int ret;
155
156 if (val & MSR_IA32_APICBASE_RESERVED) {
157 goto error;
158 }
159
160 ret = cpu_set_apic_base(env_archcpu(env)->apic_state, val);
161 if (ret < 0) {
162 goto error;
163 }
164 break;
165 }
166 case MSR_EFER:
167 {
168 uint64_t update_mask;
169
170 update_mask = 0;
171 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_SYSCALL) {
172 update_mask |= MSR_EFER_SCE;
173 }
174 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
175 update_mask |= MSR_EFER_LME;
176 }
177 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_FFXSR) {
178 update_mask |= MSR_EFER_FFXSR;
179 }
180 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_NX) {
181 update_mask |= MSR_EFER_NXE;
182 }
183 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
184 update_mask |= MSR_EFER_SVME;
185 }
186 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_FFXSR) {
187 update_mask |= MSR_EFER_FFXSR;
188 }
189 cpu_load_efer(env, (env->efer & ~update_mask) |
190 (val & update_mask));
191 }
192 break;
193 case MSR_STAR:
194 env->star = val;
195 break;
196 case MSR_PAT:
197 env->pat = val;
198 break;
199 case MSR_IA32_PKRS:
200 if (val & 0xFFFFFFFF00000000ull) {
201 goto error;
202 }
203 env->pkrs = val;
204 tlb_flush(cs);
205 break;
206 case MSR_VM_HSAVE_PA:
207 if (val & (0xfff | ((~0ULL) << env_archcpu(env)->phys_bits))) {
208 goto error;
209 }
210 env->vm_hsave = val;
211 break;
212 #ifdef TARGET_X86_64
213 case MSR_LSTAR:
214 env->lstar = val;
215 break;
216 case MSR_CSTAR:
217 env->cstar = val;
218 break;
219 case MSR_FMASK:
220 env->fmask = val;
221 break;
222 case MSR_FSBASE:
223 env->segs[R_FS].base = val;
224 break;
225 case MSR_GSBASE:
226 env->segs[R_GS].base = val;
227 break;
228 case MSR_KERNELGSBASE:
229 env->kernelgsbase = val;
230 break;
231 #endif
232 case MSR_MTRRphysBase(0):
233 case MSR_MTRRphysBase(1):
234 case MSR_MTRRphysBase(2):
235 case MSR_MTRRphysBase(3):
236 case MSR_MTRRphysBase(4):
237 case MSR_MTRRphysBase(5):
238 case MSR_MTRRphysBase(6):
239 case MSR_MTRRphysBase(7):
240 env->mtrr_var[((uint32_t)env->regs[R_ECX] -
241 MSR_MTRRphysBase(0)) / 2].base = val;
242 break;
243 case MSR_MTRRphysMask(0):
244 case MSR_MTRRphysMask(1):
245 case MSR_MTRRphysMask(2):
246 case MSR_MTRRphysMask(3):
247 case MSR_MTRRphysMask(4):
248 case MSR_MTRRphysMask(5):
249 case MSR_MTRRphysMask(6):
250 case MSR_MTRRphysMask(7):
251 env->mtrr_var[((uint32_t)env->regs[R_ECX] -
252 MSR_MTRRphysMask(0)) / 2].mask = val;
253 break;
254 case MSR_MTRRfix64K_00000:
255 env->mtrr_fixed[(uint32_t)env->regs[R_ECX] -
256 MSR_MTRRfix64K_00000] = val;
257 break;
258 case MSR_MTRRfix16K_80000:
259 case MSR_MTRRfix16K_A0000:
260 env->mtrr_fixed[(uint32_t)env->regs[R_ECX] -
261 MSR_MTRRfix16K_80000 + 1] = val;
262 break;
263 case MSR_MTRRfix4K_C0000:
264 case MSR_MTRRfix4K_C8000:
265 case MSR_MTRRfix4K_D0000:
266 case MSR_MTRRfix4K_D8000:
267 case MSR_MTRRfix4K_E0000:
268 case MSR_MTRRfix4K_E8000:
269 case MSR_MTRRfix4K_F0000:
270 case MSR_MTRRfix4K_F8000:
271 env->mtrr_fixed[(uint32_t)env->regs[R_ECX] -
272 MSR_MTRRfix4K_C0000 + 3] = val;
273 break;
274 case MSR_MTRRdefType:
275 env->mtrr_deftype = val;
276 break;
277 case MSR_MCG_STATUS:
278 env->mcg_status = val;
279 break;
280 case MSR_MCG_CTL:
281 if ((env->mcg_cap & MCG_CTL_P)
282 && (val == 0 || val == ~(uint64_t)0)) {
283 env->mcg_ctl = val;
284 }
285 break;
286 case MSR_TSC_AUX:
287 env->tsc_aux = val;
288 break;
289 case MSR_IA32_MISC_ENABLE:
290 env->msr_ia32_misc_enable = val;
291 break;
292 case MSR_IA32_BNDCFGS:
293 /* FIXME: #GP if reserved bits are set. */
294 /* FIXME: Extend highest implemented bit of linear address. */
295 env->msr_bndcfgs = val;
296 cpu_sync_bndcs_hflags(env);
297 break;
298 case MSR_APIC_START ... MSR_APIC_END: {
299 int ret;
300 int index = (uint32_t)env->regs[R_ECX] - MSR_APIC_START;
301
302 bql_lock();
303 ret = apic_msr_write(env_archcpu(env)->apic_state, index, val);
304 bql_unlock();
305 if (ret < 0) {
306 goto error;
307 }
308
309 break;
310 }
311 default:
312 if ((uint32_t)env->regs[R_ECX] >= MSR_MC0_CTL
313 && (uint32_t)env->regs[R_ECX] < MSR_MC0_CTL +
314 (4 * env->mcg_cap & 0xff)) {
315 uint32_t offset = (uint32_t)env->regs[R_ECX] - MSR_MC0_CTL;
316 if ((offset & 0x3) != 0
317 || (val == 0 || val == ~(uint64_t)0)) {
318 env->mce_banks[offset] = val;
319 }
320 break;
321 }
322 /* XXX: exception? */
323 break;
324 }
325 return;
326 error:
327 raise_exception_err_ra(env, EXCP0D_GPF, 0, GETPC());
328 }
329
330 void helper_rdmsr(CPUX86State *env)
331 {
332 X86CPU *x86_cpu = env_archcpu(env);
333 uint64_t val;
334
335 cpu_svm_check_intercept_param(env, SVM_EXIT_MSR, 0, GETPC());
336
337 switch ((uint32_t)env->regs[R_ECX]) {
338 case MSR_IA32_SYSENTER_CS:
339 val = env->sysenter_cs;
340 break;
341 case MSR_IA32_SYSENTER_ESP:
342 val = env->sysenter_esp;
343 break;
344 case MSR_IA32_SYSENTER_EIP:
345 val = env->sysenter_eip;
346 break;
347 case MSR_IA32_APICBASE:
348 val = cpu_get_apic_base(env_archcpu(env)->apic_state);
349 break;
350 case MSR_EFER:
351 val = env->efer;
352 break;
353 case MSR_STAR:
354 val = env->star;
355 break;
356 case MSR_PAT:
357 val = env->pat;
358 break;
359 case MSR_IA32_PKRS:
360 val = env->pkrs;
361 break;
362 case MSR_VM_HSAVE_PA:
363 val = env->vm_hsave;
364 break;
365 case MSR_IA32_PERF_STATUS:
366 /* tsc_increment_by_tick */
367 val = 1000ULL;
368 /* CPU multiplier */
369 val |= (((uint64_t)4ULL) << 40);
370 break;
371 #ifdef TARGET_X86_64
372 case MSR_LSTAR:
373 val = env->lstar;
374 break;
375 case MSR_CSTAR:
376 val = env->cstar;
377 break;
378 case MSR_FMASK:
379 val = env->fmask;
380 break;
381 case MSR_FSBASE:
382 val = env->segs[R_FS].base;
383 break;
384 case MSR_GSBASE:
385 val = env->segs[R_GS].base;
386 break;
387 case MSR_KERNELGSBASE:
388 val = env->kernelgsbase;
389 break;
390 case MSR_TSC_AUX:
391 val = env->tsc_aux;
392 break;
393 #endif
394 case MSR_SMI_COUNT:
395 val = env->msr_smi_count;
396 break;
397 case MSR_MTRRphysBase(0):
398 case MSR_MTRRphysBase(1):
399 case MSR_MTRRphysBase(2):
400 case MSR_MTRRphysBase(3):
401 case MSR_MTRRphysBase(4):
402 case MSR_MTRRphysBase(5):
403 case MSR_MTRRphysBase(6):
404 case MSR_MTRRphysBase(7):
405 val = env->mtrr_var[((uint32_t)env->regs[R_ECX] -
406 MSR_MTRRphysBase(0)) / 2].base;
407 break;
408 case MSR_MTRRphysMask(0):
409 case MSR_MTRRphysMask(1):
410 case MSR_MTRRphysMask(2):
411 case MSR_MTRRphysMask(3):
412 case MSR_MTRRphysMask(4):
413 case MSR_MTRRphysMask(5):
414 case MSR_MTRRphysMask(6):
415 case MSR_MTRRphysMask(7):
416 val = env->mtrr_var[((uint32_t)env->regs[R_ECX] -
417 MSR_MTRRphysMask(0)) / 2].mask;
418 break;
419 case MSR_MTRRfix64K_00000:
420 val = env->mtrr_fixed[0];
421 break;
422 case MSR_MTRRfix16K_80000:
423 case MSR_MTRRfix16K_A0000:
424 val = env->mtrr_fixed[(uint32_t)env->regs[R_ECX] -
425 MSR_MTRRfix16K_80000 + 1];
426 break;
427 case MSR_MTRRfix4K_C0000:
428 case MSR_MTRRfix4K_C8000:
429 case MSR_MTRRfix4K_D0000:
430 case MSR_MTRRfix4K_D8000:
431 case MSR_MTRRfix4K_E0000:
432 case MSR_MTRRfix4K_E8000:
433 case MSR_MTRRfix4K_F0000:
434 case MSR_MTRRfix4K_F8000:
435 val = env->mtrr_fixed[(uint32_t)env->regs[R_ECX] -
436 MSR_MTRRfix4K_C0000 + 3];
437 break;
438 case MSR_MTRRdefType:
439 val = env->mtrr_deftype;
440 break;
441 case MSR_MTRRcap:
442 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
443 val = MSR_MTRRcap_VCNT | MSR_MTRRcap_FIXRANGE_SUPPORT |
444 MSR_MTRRcap_WC_SUPPORTED;
445 } else {
446 /* XXX: exception? */
447 val = 0;
448 }
449 break;
450 case MSR_MCG_CAP:
451 val = env->mcg_cap;
452 break;
453 case MSR_MCG_CTL:
454 if (env->mcg_cap & MCG_CTL_P) {
455 val = env->mcg_ctl;
456 } else {
457 val = 0;
458 }
459 break;
460 case MSR_MCG_STATUS:
461 val = env->mcg_status;
462 break;
463 case MSR_IA32_MISC_ENABLE:
464 val = env->msr_ia32_misc_enable;
465 break;
466 case MSR_IA32_BNDCFGS:
467 val = env->msr_bndcfgs;
468 break;
469 case MSR_IA32_UCODE_REV:
470 val = x86_cpu->ucode_rev;
471 break;
472 case MSR_CORE_THREAD_COUNT: {
473 val = cpu_x86_get_msr_core_thread_count(x86_cpu);
474 break;
475 }
476 case MSR_APIC_START ... MSR_APIC_END: {
477 int ret;
478 int index = (uint32_t)env->regs[R_ECX] - MSR_APIC_START;
479
480 bql_lock();
481 ret = apic_msr_read(x86_cpu->apic_state, index, &val);
482 bql_unlock();
483 if (ret < 0) {
484 raise_exception_err_ra(env, EXCP0D_GPF, 0, GETPC());
485 }
486
487 break;
488 }
489 default:
490 if ((uint32_t)env->regs[R_ECX] >= MSR_MC0_CTL
491 && (uint32_t)env->regs[R_ECX] < MSR_MC0_CTL +
492 (4 * env->mcg_cap & 0xff)) {
493 uint32_t offset = (uint32_t)env->regs[R_ECX] - MSR_MC0_CTL;
494 val = env->mce_banks[offset];
495 break;
496 }
497 /* XXX: exception? */
498 val = 0;
499 break;
500 }
501 env->regs[R_EAX] = (uint32_t)(val);
502 env->regs[R_EDX] = (uint32_t)(val >> 32);
503 }
504
505 void helper_flush_page(CPUX86State *env, target_ulong addr)
506 {
507 tlb_flush_page(env_cpu(env), addr);
508 }
509
510 G_NORETURN void helper_hlt(CPUX86State *env)
511 {
512 CPUState *cs = env_cpu(env);
513
514 do_end_instruction(env);
515 cs->halted = 1;
516 cs->exception_index = EXCP_HLT;
517 cpu_loop_exit(cs);
518 }
519
520 void helper_monitor(CPUX86State *env, target_ulong ptr)
521 {
522 if ((uint32_t)env->regs[R_ECX] != 0) {
523 raise_exception_ra(env, EXCP0D_GPF, GETPC());
524 }
525 /* XXX: store address? */
526 cpu_svm_check_intercept_param(env, SVM_EXIT_MONITOR, 0, GETPC());
527 }
528
529 G_NORETURN void helper_mwait(CPUX86State *env, int next_eip_addend)
530 {
531 CPUState *cs = env_cpu(env);
532
533 if ((uint32_t)env->regs[R_ECX] != 0) {
534 raise_exception_ra(env, EXCP0D_GPF, GETPC());
535 }
536 cpu_svm_check_intercept_param(env, SVM_EXIT_MWAIT, 0, GETPC());
537 env->eip += next_eip_addend;
538
539 /* XXX: not complete but not completely erroneous */
540 if (cs->cpu_index != 0 || CPU_NEXT(cs) != NULL) {
541 helper_pause(env);
542 } else {
543 helper_hlt(env);
544 }
545 }