| 1 | /* |
| 2 | * x86 segmentation related helpers: (system-only code) |
| 3 | * TSS, interrupts, system calls, jumps and call/task gates, descriptors |
| 4 | * |
| 5 | * Copyright (c) 2003 Fabrice Bellard |
| 6 | * |
| 7 | * This library is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU Lesser General Public |
| 9 | * License as published by the Free Software Foundation; either |
| 10 | * version 2.1 of the License, or (at your option) any later version. |
| 11 | * |
| 12 | * This library is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 15 | * Lesser General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU Lesser General Public |
| 18 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
| 19 | */ |
| 20 | |
| 21 | #include "qemu/osdep.h" |
| 22 | #include "qemu/log.h" |
| 23 | #include "qemu/main-loop.h" |
| 24 | #include "cpu.h" |
| 25 | #include "exec/helper-proto.h" |
| 26 | #include "accel/tcg/cpu-ldst.h" |
| 27 | #include "tcg/helper-tcg.h" |
| 28 | #include "../seg_helper.h" |
| 29 | |
| 30 | void helper_syscall(CPUX86State *env, int next_eip_addend) |
| 31 | { |
| 32 | int selector; |
| 33 | |
| 34 | if (!(env->efer & MSR_EFER_SCE)) { |
| 35 | raise_exception_err_ra(env, EXCP06_ILLOP, 0, GETPC()); |
| 36 | } |
| 37 | selector = (env->star >> 32) & 0xffff; |
| 38 | #ifdef TARGET_X86_64 |
| 39 | if (env->hflags & HF_LMA_MASK) { |
| 40 | int code64; |
| 41 | |
| 42 | env->regs[R_ECX] = env->eip + next_eip_addend; |
| 43 | env->regs[11] = cpu_compute_eflags(env) & ~RF_MASK; |
| 44 | |
| 45 | code64 = env->hflags & HF_CS64_MASK; |
| 46 | |
| 47 | env->eflags &= ~(env->fmask | RF_MASK); |
| 48 | cpu_load_eflags(env, env->eflags, 0); |
| 49 | cpu_x86_load_seg_cache(env, R_CS, selector & 0xfffc, |
| 50 | 0, 0xffffffff, |
| 51 | DESC_G_MASK | DESC_P_MASK | |
| 52 | DESC_S_MASK | |
| 53 | DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK | |
| 54 | DESC_L_MASK); |
| 55 | cpu_x86_load_seg_cache(env, R_SS, (selector + 8) & 0xfffc, |
| 56 | 0, 0xffffffff, |
| 57 | DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | |
| 58 | DESC_S_MASK | |
| 59 | DESC_W_MASK | DESC_A_MASK); |
| 60 | if (code64) { |
| 61 | env->eip = env->lstar; |
| 62 | } else { |
| 63 | env->eip = env->cstar; |
| 64 | } |
| 65 | } else |
| 66 | #endif |
| 67 | { |
| 68 | env->regs[R_ECX] = (uint32_t)(env->eip + next_eip_addend); |
| 69 | |
| 70 | env->eflags &= ~(IF_MASK | RF_MASK | VM_MASK); |
| 71 | cpu_x86_load_seg_cache(env, R_CS, selector & 0xfffc, |
| 72 | 0, 0xffffffff, |
| 73 | DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | |
| 74 | DESC_S_MASK | |
| 75 | DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK); |
| 76 | cpu_x86_load_seg_cache(env, R_SS, (selector + 8) & 0xfffc, |
| 77 | 0, 0xffffffff, |
| 78 | DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | |
| 79 | DESC_S_MASK | |
| 80 | DESC_W_MASK | DESC_A_MASK); |
| 81 | env->eip = (uint32_t)env->star; |
| 82 | } |
| 83 | } |
| 84 | |
| 85 | void handle_even_inj(CPUX86State *env, int intno, int is_int, |
| 86 | int error_code, int is_hw, int rm) |
| 87 | { |
| 88 | CPUState *cs = env_cpu(env); |
| 89 | uint32_t event_inj = x86_ldl_phys(cs, env->vm_vmcb + offsetof(struct vmcb, |
| 90 | control.event_inj)); |
| 91 | |
| 92 | if (!(event_inj & SVM_EVTINJ_VALID)) { |
| 93 | int type; |
| 94 | |
| 95 | if (is_int) { |
| 96 | type = SVM_EVTINJ_TYPE_SOFT; |
| 97 | } else { |
| 98 | type = SVM_EVTINJ_TYPE_EXEPT; |
| 99 | } |
| 100 | event_inj = intno | type | SVM_EVTINJ_VALID; |
| 101 | if (!rm && exception_has_error_code(intno)) { |
| 102 | event_inj |= SVM_EVTINJ_VALID_ERR; |
| 103 | x86_stl_phys(cs, env->vm_vmcb + offsetof(struct vmcb, |
| 104 | control.event_inj_err), |
| 105 | error_code); |
| 106 | } |
| 107 | x86_stl_phys(cs, |
| 108 | env->vm_vmcb + offsetof(struct vmcb, control.event_inj), |
| 109 | event_inj); |
| 110 | } |
| 111 | } |
| 112 | |
| 113 | void x86_cpu_do_interrupt(CPUState *cs) |
| 114 | { |
| 115 | X86CPU *cpu = X86_CPU(cs); |
| 116 | CPUX86State *env = &cpu->env; |
| 117 | |
| 118 | if (cs->exception_index == EXCP_VMEXIT) { |
| 119 | assert(env->old_exception == -1); |
| 120 | do_vmexit(env); |
| 121 | } else { |
| 122 | do_interrupt_all(cpu, cs->exception_index, |
| 123 | env->exception_is_int, |
| 124 | env->error_code, |
| 125 | env->exception_next_eip, 0); |
| 126 | /* successfully delivered */ |
| 127 | env->old_exception = -1; |
| 128 | } |
| 129 | } |
| 130 | |
| 131 | bool x86_cpu_exec_halt(CPUState *cpu) |
| 132 | { |
| 133 | X86CPU *x86_cpu = X86_CPU(cpu); |
| 134 | CPUX86State *env = &x86_cpu->env; |
| 135 | |
| 136 | if (cpu_test_interrupt(cpu, CPU_INTERRUPT_POLL)) { |
| 137 | bql_lock(); |
| 138 | apic_poll_irq(x86_cpu->apic_state); |
| 139 | cpu_reset_interrupt(cpu, CPU_INTERRUPT_POLL); |
| 140 | bql_unlock(); |
| 141 | } |
| 142 | |
| 143 | if (!cpu_has_work(cpu)) { |
| 144 | return false; |
| 145 | } |
| 146 | |
| 147 | /* Complete HLT instruction. */ |
| 148 | if (env->eflags & TF_MASK) { |
| 149 | env->dr[6] |= DR6_BS; |
| 150 | do_interrupt_all(x86_cpu, EXCP01_DB, 0, 0, env->eip, 0); |
| 151 | } |
| 152 | return true; |
| 153 | } |
| 154 | |
| 155 | bool x86_need_replay_interrupt(int interrupt_request) |
| 156 | { |
| 157 | /* |
| 158 | * CPU_INTERRUPT_POLL is a virtual event which gets converted into a |
| 159 | * "real" interrupt event later. It does not need to be recorded for |
| 160 | * replay purposes. |
| 161 | */ |
| 162 | return !(interrupt_request & CPU_INTERRUPT_POLL); |
| 163 | } |
| 164 | |
| 165 | bool x86_cpu_exec_interrupt(CPUState *cs, int interrupt_request) |
| 166 | { |
| 167 | X86CPU *cpu = X86_CPU(cs); |
| 168 | CPUX86State *env = &cpu->env; |
| 169 | int intno; |
| 170 | |
| 171 | interrupt_request = x86_cpu_pending_interrupt(cs, interrupt_request); |
| 172 | if (!interrupt_request) { |
| 173 | return false; |
| 174 | } |
| 175 | |
| 176 | /* Don't process multiple interrupt requests in a single call. |
| 177 | * This is required to make icount-driven execution deterministic. |
| 178 | */ |
| 179 | switch (interrupt_request) { |
| 180 | case CPU_INTERRUPT_POLL: |
| 181 | cpu_reset_interrupt(cs, CPU_INTERRUPT_POLL); |
| 182 | apic_poll_irq(cpu->apic_state); |
| 183 | break; |
| 184 | case CPU_INTERRUPT_SIPI: |
| 185 | cpu_reset_interrupt(cs, CPU_INTERRUPT_SIPI); |
| 186 | do_cpu_sipi(cpu); |
| 187 | break; |
| 188 | case CPU_INTERRUPT_SMI: |
| 189 | cpu_svm_check_intercept_param(env, SVM_EXIT_SMI, 0, 0); |
| 190 | cpu_reset_interrupt(cs, CPU_INTERRUPT_SMI); |
| 191 | do_smm_enter(cpu); |
| 192 | break; |
| 193 | case CPU_INTERRUPT_NMI: |
| 194 | cpu_svm_check_intercept_param(env, SVM_EXIT_NMI, 0, 0); |
| 195 | cpu_reset_interrupt(cs, CPU_INTERRUPT_NMI); |
| 196 | env->hflags2 |= HF2_NMI_MASK; |
| 197 | do_interrupt_x86_hardirq(env, EXCP02_NMI, 1); |
| 198 | break; |
| 199 | case CPU_INTERRUPT_MCE: |
| 200 | cpu_reset_interrupt(cs, CPU_INTERRUPT_MCE); |
| 201 | do_interrupt_x86_hardirq(env, EXCP12_MCHK, 0); |
| 202 | break; |
| 203 | case CPU_INTERRUPT_HARD: |
| 204 | cpu_svm_check_intercept_param(env, SVM_EXIT_INTR, 0, 0); |
| 205 | cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD | CPU_INTERRUPT_VIRQ); |
| 206 | intno = cpu_get_pic_interrupt(env); |
| 207 | qemu_log_mask(CPU_LOG_INT, |
| 208 | "Servicing hardware INT=0x%02x\n", intno); |
| 209 | do_interrupt_x86_hardirq(env, intno, 1); |
| 210 | break; |
| 211 | case CPU_INTERRUPT_VIRQ: |
| 212 | cpu_svm_check_intercept_param(env, SVM_EXIT_VINTR, 0, 0); |
| 213 | intno = x86_ldl_phys(cs, env->vm_vmcb |
| 214 | + offsetof(struct vmcb, control.int_vector)); |
| 215 | qemu_log_mask(CPU_LOG_INT, |
| 216 | "Servicing virtual hardware INT=0x%02x\n", intno); |
| 217 | do_interrupt_x86_hardirq(env, intno, 1); |
| 218 | cpu_reset_interrupt(cs, CPU_INTERRUPT_VIRQ); |
| 219 | env->int_ctl &= ~V_IRQ_MASK; |
| 220 | break; |
| 221 | } |
| 222 | |
| 223 | /* Ensure that no TB jump will be modified as the program flow was changed. */ |
| 224 | return true; |
| 225 | } |
| 226 | |
| 227 | /* check if Port I/O is allowed in TSS */ |
| 228 | void helper_check_io(CPUX86State *env, uint32_t addr, uint32_t size) |
| 229 | { |
| 230 | uintptr_t retaddr = GETPC(); |
| 231 | uint32_t io_offset, val, mask; |
| 232 | |
| 233 | /* TSS must be a valid 32 bit one */ |
| 234 | if (!(env->tr.flags & DESC_P_MASK) || |
| 235 | ((env->tr.flags >> DESC_TYPE_SHIFT) & 0xf) != 9 || |
| 236 | env->tr.limit < 103) { |
| 237 | goto fail; |
| 238 | } |
| 239 | io_offset = cpu_lduw_kernel_ra(env, env->tr.base + 0x66, retaddr); |
| 240 | io_offset += (addr >> 3); |
| 241 | /* Note: the check needs two bytes */ |
| 242 | if ((io_offset + 1) > env->tr.limit) { |
| 243 | goto fail; |
| 244 | } |
| 245 | val = cpu_lduw_kernel_ra(env, env->tr.base + io_offset, retaddr); |
| 246 | val >>= (addr & 7); |
| 247 | mask = (1 << size) - 1; |
| 248 | /* all bits must be zero to allow the I/O */ |
| 249 | if ((val & mask) != 0) { |
| 250 | fail: |
| 251 | raise_exception_err_ra(env, EXCP0D_GPF, 0, retaddr); |
| 252 | } |
| 253 | } |