| 1 | /* |
| 2 | * x86 SMM helpers (system-only) |
| 3 | * |
| 4 | * Copyright (c) 2003 Fabrice Bellard |
| 5 | * |
| 6 | * This library is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU Lesser General Public |
| 8 | * License as published by the Free Software Foundation; either |
| 9 | * version 2.1 of the License, or (at your option) any later version. |
| 10 | * |
| 11 | * This library is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 14 | * Lesser General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU Lesser General Public |
| 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
| 18 | */ |
| 19 | |
| 20 | #include "qemu/osdep.h" |
| 21 | #include "cpu.h" |
| 22 | #include "exec/helper-proto.h" |
| 23 | #include "exec/log.h" |
| 24 | #include "tcg/helper-tcg.h" |
| 25 | |
| 26 | static void sm_state_init_64(X86CPU *cpu) |
| 27 | { |
| 28 | #ifdef TARGET_X86_64 |
| 29 | CPUX86State *env = &cpu->env; |
| 30 | CPUState *cs = CPU(cpu); |
| 31 | SegmentCache *dt; |
| 32 | int i, offset; |
| 33 | target_ulong sm_state = env->smbase + 0x8000; |
| 34 | |
| 35 | for (i = 0; i < 6; i++) { |
| 36 | dt = &env->segs[i]; |
| 37 | offset = 0x7e00 + i * 16; |
| 38 | x86_stw_phys(cs, sm_state + offset, dt->selector); |
| 39 | x86_stw_phys(cs, sm_state + offset + 2, (dt->flags >> 8) & 0xf0ff); |
| 40 | x86_stl_phys(cs, sm_state + offset + 4, dt->limit); |
| 41 | x86_stq_phys(cs, sm_state + offset + 8, dt->base); |
| 42 | } |
| 43 | |
| 44 | x86_stq_phys(cs, sm_state + 0x7e68, env->gdt.base); |
| 45 | x86_stl_phys(cs, sm_state + 0x7e64, env->gdt.limit); |
| 46 | |
| 47 | x86_stw_phys(cs, sm_state + 0x7e70, env->ldt.selector); |
| 48 | x86_stq_phys(cs, sm_state + 0x7e78, env->ldt.base); |
| 49 | x86_stl_phys(cs, sm_state + 0x7e74, env->ldt.limit); |
| 50 | x86_stw_phys(cs, sm_state + 0x7e72, (env->ldt.flags >> 8) & 0xf0ff); |
| 51 | |
| 52 | x86_stq_phys(cs, sm_state + 0x7e88, env->idt.base); |
| 53 | x86_stl_phys(cs, sm_state + 0x7e84, env->idt.limit); |
| 54 | |
| 55 | x86_stw_phys(cs, sm_state + 0x7e90, env->tr.selector); |
| 56 | x86_stq_phys(cs, sm_state + 0x7e98, env->tr.base); |
| 57 | x86_stl_phys(cs, sm_state + 0x7e94, env->tr.limit); |
| 58 | x86_stw_phys(cs, sm_state + 0x7e92, (env->tr.flags >> 8) & 0xf0ff); |
| 59 | |
| 60 | /* ??? Vol 1, 16.5.6 Intel MPX and SMM says that IA32_BNDCFGS |
| 61 | is saved at offset 7ED0. Vol 3, 34.4.1.1, Table 32-2, has |
| 62 | 7EA0-7ED7 as "reserved". What's this, and what's really |
| 63 | supposed to happen? */ |
| 64 | x86_stq_phys(cs, sm_state + 0x7ed0, env->efer); |
| 65 | |
| 66 | x86_stq_phys(cs, sm_state + 0x7ff8, env->regs[R_EAX]); |
| 67 | x86_stq_phys(cs, sm_state + 0x7ff0, env->regs[R_ECX]); |
| 68 | x86_stq_phys(cs, sm_state + 0x7fe8, env->regs[R_EDX]); |
| 69 | x86_stq_phys(cs, sm_state + 0x7fe0, env->regs[R_EBX]); |
| 70 | x86_stq_phys(cs, sm_state + 0x7fd8, env->regs[R_ESP]); |
| 71 | x86_stq_phys(cs, sm_state + 0x7fd0, env->regs[R_EBP]); |
| 72 | x86_stq_phys(cs, sm_state + 0x7fc8, env->regs[R_ESI]); |
| 73 | x86_stq_phys(cs, sm_state + 0x7fc0, env->regs[R_EDI]); |
| 74 | for (i = 8; i < 16; i++) { |
| 75 | x86_stq_phys(cs, sm_state + 0x7ff8 - i * 8, env->regs[i]); |
| 76 | } |
| 77 | x86_stq_phys(cs, sm_state + 0x7f78, env->eip); |
| 78 | x86_stl_phys(cs, sm_state + 0x7f70, cpu_compute_eflags(env)); |
| 79 | x86_stl_phys(cs, sm_state + 0x7f68, env->dr[6]); |
| 80 | x86_stl_phys(cs, sm_state + 0x7f60, env->dr[7]); |
| 81 | |
| 82 | x86_stl_phys(cs, sm_state + 0x7f48, env->cr[4]); |
| 83 | x86_stq_phys(cs, sm_state + 0x7f50, env->cr[3]); |
| 84 | x86_stl_phys(cs, sm_state + 0x7f58, env->cr[0]); |
| 85 | |
| 86 | x86_stl_phys(cs, sm_state + 0x7efc, 0x00020064); /* SMM revision ID */ |
| 87 | x86_stl_phys(cs, sm_state + 0x7f00, env->smbase); |
| 88 | #else |
| 89 | g_assert_not_reached(); |
| 90 | #endif |
| 91 | } |
| 92 | |
| 93 | static void sm_state_init_32(X86CPU *cpu) |
| 94 | { |
| 95 | CPUX86State *env = &cpu->env; |
| 96 | CPUState *cs = CPU(cpu); |
| 97 | SegmentCache *dt; |
| 98 | int i, offset; |
| 99 | target_ulong sm_state = env->smbase + 0x8000; |
| 100 | |
| 101 | x86_stl_phys(cs, sm_state + 0x7ffc, env->cr[0]); |
| 102 | x86_stl_phys(cs, sm_state + 0x7ff8, env->cr[3]); |
| 103 | x86_stl_phys(cs, sm_state + 0x7ff4, cpu_compute_eflags(env)); |
| 104 | x86_stl_phys(cs, sm_state + 0x7ff0, env->eip); |
| 105 | x86_stl_phys(cs, sm_state + 0x7fec, env->regs[R_EDI]); |
| 106 | x86_stl_phys(cs, sm_state + 0x7fe8, env->regs[R_ESI]); |
| 107 | x86_stl_phys(cs, sm_state + 0x7fe4, env->regs[R_EBP]); |
| 108 | x86_stl_phys(cs, sm_state + 0x7fe0, env->regs[R_ESP]); |
| 109 | x86_stl_phys(cs, sm_state + 0x7fdc, env->regs[R_EBX]); |
| 110 | x86_stl_phys(cs, sm_state + 0x7fd8, env->regs[R_EDX]); |
| 111 | x86_stl_phys(cs, sm_state + 0x7fd4, env->regs[R_ECX]); |
| 112 | x86_stl_phys(cs, sm_state + 0x7fd0, env->regs[R_EAX]); |
| 113 | x86_stl_phys(cs, sm_state + 0x7fcc, env->dr[6]); |
| 114 | x86_stl_phys(cs, sm_state + 0x7fc8, env->dr[7]); |
| 115 | |
| 116 | x86_stl_phys(cs, sm_state + 0x7fc4, env->tr.selector); |
| 117 | x86_stl_phys(cs, sm_state + 0x7f64, env->tr.base); |
| 118 | x86_stl_phys(cs, sm_state + 0x7f60, env->tr.limit); |
| 119 | x86_stl_phys(cs, sm_state + 0x7f5c, (env->tr.flags >> 8) & 0xf0ff); |
| 120 | |
| 121 | x86_stl_phys(cs, sm_state + 0x7fc0, env->ldt.selector); |
| 122 | x86_stl_phys(cs, sm_state + 0x7f80, env->ldt.base); |
| 123 | x86_stl_phys(cs, sm_state + 0x7f7c, env->ldt.limit); |
| 124 | x86_stl_phys(cs, sm_state + 0x7f78, (env->ldt.flags >> 8) & 0xf0ff); |
| 125 | |
| 126 | x86_stl_phys(cs, sm_state + 0x7f74, env->gdt.base); |
| 127 | x86_stl_phys(cs, sm_state + 0x7f70, env->gdt.limit); |
| 128 | |
| 129 | x86_stl_phys(cs, sm_state + 0x7f58, env->idt.base); |
| 130 | x86_stl_phys(cs, sm_state + 0x7f54, env->idt.limit); |
| 131 | |
| 132 | for (i = 0; i < 6; i++) { |
| 133 | dt = &env->segs[i]; |
| 134 | if (i < 3) { |
| 135 | offset = 0x7f84 + i * 12; |
| 136 | } else { |
| 137 | offset = 0x7f2c + (i - 3) * 12; |
| 138 | } |
| 139 | x86_stl_phys(cs, sm_state + 0x7fa8 + i * 4, dt->selector); |
| 140 | x86_stl_phys(cs, sm_state + offset + 8, dt->base); |
| 141 | x86_stl_phys(cs, sm_state + offset + 4, dt->limit); |
| 142 | x86_stl_phys(cs, sm_state + offset, (dt->flags >> 8) & 0xf0ff); |
| 143 | } |
| 144 | x86_stl_phys(cs, sm_state + 0x7f14, env->cr[4]); |
| 145 | |
| 146 | x86_stl_phys(cs, sm_state + 0x7efc, 0x00020000); /* SMM revision ID */ |
| 147 | x86_stl_phys(cs, sm_state + 0x7ef8, env->smbase); |
| 148 | } |
| 149 | |
| 150 | void do_smm_enter(X86CPU *cpu) |
| 151 | { |
| 152 | CPUX86State *env = &cpu->env; |
| 153 | |
| 154 | qemu_log_mask(CPU_LOG_INT, "SMM: enter\n"); |
| 155 | log_cpu_state_mask(CPU_LOG_INT, CPU(cpu), CPU_DUMP_CCOP); |
| 156 | |
| 157 | env->msr_smi_count++; |
| 158 | env->hflags |= HF_SMM_MASK; |
| 159 | if (env->hflags2 & HF2_NMI_MASK) { |
| 160 | env->hflags2 |= HF2_SMM_INSIDE_NMI_MASK; |
| 161 | } else { |
| 162 | env->hflags2 |= HF2_NMI_MASK; |
| 163 | } |
| 164 | |
| 165 | if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { |
| 166 | sm_state_init_64(cpu); |
| 167 | cpu_load_efer(env, 0); |
| 168 | } else { |
| 169 | sm_state_init_32(cpu); |
| 170 | } |
| 171 | |
| 172 | /* init SMM cpu state */ |
| 173 | |
| 174 | cpu_load_eflags(env, 0, ~(CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C | |
| 175 | DF_MASK)); |
| 176 | env->eip = 0x00008000; |
| 177 | cpu_x86_update_cr0(env, |
| 178 | env->cr[0] & ~(CR0_PE_MASK | CR0_EM_MASK | CR0_TS_MASK | |
| 179 | CR0_PG_MASK)); |
| 180 | cpu_x86_update_cr4(env, 0); |
| 181 | helper_set_dr(env, 7, 0x00000400); |
| 182 | |
| 183 | cpu_x86_load_seg_cache(env, R_CS, (env->smbase >> 4) & 0xffff, env->smbase, |
| 184 | 0xffffffff, |
| 185 | DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | |
| 186 | DESC_G_MASK | DESC_A_MASK); |
| 187 | cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffffffff, |
| 188 | DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | |
| 189 | DESC_G_MASK | DESC_A_MASK); |
| 190 | cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffffffff, |
| 191 | DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | |
| 192 | DESC_G_MASK | DESC_A_MASK); |
| 193 | cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffffffff, |
| 194 | DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | |
| 195 | DESC_G_MASK | DESC_A_MASK); |
| 196 | cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffffffff, |
| 197 | DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | |
| 198 | DESC_G_MASK | DESC_A_MASK); |
| 199 | cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffffffff, |
| 200 | DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | |
| 201 | DESC_G_MASK | DESC_A_MASK); |
| 202 | } |
| 203 | |
| 204 | static void rsm_load_regs_64(CPUX86State *env) |
| 205 | { |
| 206 | #ifdef TARGET_X86_64 |
| 207 | CPUState *cs = env_cpu(env); |
| 208 | target_ulong sm_state; |
| 209 | int i, offset; |
| 210 | uint32_t val; |
| 211 | |
| 212 | sm_state = env->smbase + 0x8000; |
| 213 | |
| 214 | cpu_load_efer(env, x86_ldq_phys(cs, sm_state + 0x7ed0)); |
| 215 | |
| 216 | env->gdt.base = x86_ldq_phys(cs, sm_state + 0x7e68); |
| 217 | env->gdt.limit = x86_ldl_phys(cs, sm_state + 0x7e64); |
| 218 | |
| 219 | env->ldt.selector = x86_lduw_phys(cs, sm_state + 0x7e70); |
| 220 | env->ldt.base = x86_ldq_phys(cs, sm_state + 0x7e78); |
| 221 | env->ldt.limit = x86_ldl_phys(cs, sm_state + 0x7e74); |
| 222 | env->ldt.flags = (x86_lduw_phys(cs, sm_state + 0x7e72) & 0xf0ff) << 8; |
| 223 | |
| 224 | env->idt.base = x86_ldq_phys(cs, sm_state + 0x7e88); |
| 225 | env->idt.limit = x86_ldl_phys(cs, sm_state + 0x7e84); |
| 226 | |
| 227 | env->tr.selector = x86_lduw_phys(cs, sm_state + 0x7e90); |
| 228 | env->tr.base = x86_ldq_phys(cs, sm_state + 0x7e98); |
| 229 | env->tr.limit = x86_ldl_phys(cs, sm_state + 0x7e94); |
| 230 | env->tr.flags = (x86_lduw_phys(cs, sm_state + 0x7e92) & 0xf0ff) << 8; |
| 231 | |
| 232 | env->regs[R_EAX] = x86_ldq_phys(cs, sm_state + 0x7ff8); |
| 233 | env->regs[R_ECX] = x86_ldq_phys(cs, sm_state + 0x7ff0); |
| 234 | env->regs[R_EDX] = x86_ldq_phys(cs, sm_state + 0x7fe8); |
| 235 | env->regs[R_EBX] = x86_ldq_phys(cs, sm_state + 0x7fe0); |
| 236 | env->regs[R_ESP] = x86_ldq_phys(cs, sm_state + 0x7fd8); |
| 237 | env->regs[R_EBP] = x86_ldq_phys(cs, sm_state + 0x7fd0); |
| 238 | env->regs[R_ESI] = x86_ldq_phys(cs, sm_state + 0x7fc8); |
| 239 | env->regs[R_EDI] = x86_ldq_phys(cs, sm_state + 0x7fc0); |
| 240 | for (i = 8; i < 16; i++) { |
| 241 | env->regs[i] = x86_ldq_phys(cs, sm_state + 0x7ff8 - i * 8); |
| 242 | } |
| 243 | env->eip = x86_ldq_phys(cs, sm_state + 0x7f78); |
| 244 | cpu_load_eflags(env, x86_ldl_phys(cs, sm_state + 0x7f70), |
| 245 | ~(CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C | DF_MASK)); |
| 246 | helper_set_dr(env, 6, x86_ldl_phys(cs, sm_state + 0x7f68)); |
| 247 | helper_set_dr(env, 7, x86_ldl_phys(cs, sm_state + 0x7f60)); |
| 248 | |
| 249 | cpu_x86_update_cr4(env, x86_ldl_phys(cs, sm_state + 0x7f48)); |
| 250 | cpu_x86_update_cr3(env, x86_ldq_phys(cs, sm_state + 0x7f50)); |
| 251 | cpu_x86_update_cr0(env, x86_ldl_phys(cs, sm_state + 0x7f58)); |
| 252 | |
| 253 | for (i = 0; i < 6; i++) { |
| 254 | offset = 0x7e00 + i * 16; |
| 255 | cpu_x86_load_seg_cache(env, i, |
| 256 | x86_lduw_phys(cs, sm_state + offset), |
| 257 | x86_ldq_phys(cs, sm_state + offset + 8), |
| 258 | x86_ldl_phys(cs, sm_state + offset + 4), |
| 259 | (x86_lduw_phys(cs, sm_state + offset + 2) & |
| 260 | 0xf0ff) << 8); |
| 261 | } |
| 262 | |
| 263 | val = x86_ldl_phys(cs, sm_state + 0x7efc); /* revision ID */ |
| 264 | if (val & 0x20000) { |
| 265 | env->smbase = x86_ldl_phys(cs, sm_state + 0x7f00); |
| 266 | } |
| 267 | #else |
| 268 | g_assert_not_reached(); |
| 269 | #endif |
| 270 | } |
| 271 | |
| 272 | static void rsm_load_regs_32(CPUX86State *env) |
| 273 | { |
| 274 | CPUState *cs = env_cpu(env); |
| 275 | target_ulong sm_state; |
| 276 | int i, offset; |
| 277 | uint32_t val; |
| 278 | |
| 279 | sm_state = env->smbase + 0x8000; |
| 280 | |
| 281 | cpu_x86_update_cr0(env, x86_ldl_phys(cs, sm_state + 0x7ffc)); |
| 282 | cpu_x86_update_cr3(env, x86_ldl_phys(cs, sm_state + 0x7ff8)); |
| 283 | cpu_load_eflags(env, x86_ldl_phys(cs, sm_state + 0x7ff4), |
| 284 | ~(CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C | DF_MASK)); |
| 285 | env->eip = x86_ldl_phys(cs, sm_state + 0x7ff0); |
| 286 | env->regs[R_EDI] = x86_ldl_phys(cs, sm_state + 0x7fec); |
| 287 | env->regs[R_ESI] = x86_ldl_phys(cs, sm_state + 0x7fe8); |
| 288 | env->regs[R_EBP] = x86_ldl_phys(cs, sm_state + 0x7fe4); |
| 289 | env->regs[R_ESP] = x86_ldl_phys(cs, sm_state + 0x7fe0); |
| 290 | env->regs[R_EBX] = x86_ldl_phys(cs, sm_state + 0x7fdc); |
| 291 | env->regs[R_EDX] = x86_ldl_phys(cs, sm_state + 0x7fd8); |
| 292 | env->regs[R_ECX] = x86_ldl_phys(cs, sm_state + 0x7fd4); |
| 293 | env->regs[R_EAX] = x86_ldl_phys(cs, sm_state + 0x7fd0); |
| 294 | helper_set_dr(env, 6, x86_ldl_phys(cs, sm_state + 0x7fcc)); |
| 295 | helper_set_dr(env, 7, x86_ldl_phys(cs, sm_state + 0x7fc8)); |
| 296 | |
| 297 | env->tr.selector = x86_ldl_phys(cs, sm_state + 0x7fc4) & 0xffff; |
| 298 | env->tr.base = x86_ldl_phys(cs, sm_state + 0x7f64); |
| 299 | env->tr.limit = x86_ldl_phys(cs, sm_state + 0x7f60); |
| 300 | env->tr.flags = (x86_ldl_phys(cs, sm_state + 0x7f5c) & 0xf0ff) << 8; |
| 301 | |
| 302 | env->ldt.selector = x86_ldl_phys(cs, sm_state + 0x7fc0) & 0xffff; |
| 303 | env->ldt.base = x86_ldl_phys(cs, sm_state + 0x7f80); |
| 304 | env->ldt.limit = x86_ldl_phys(cs, sm_state + 0x7f7c); |
| 305 | env->ldt.flags = (x86_ldl_phys(cs, sm_state + 0x7f78) & 0xf0ff) << 8; |
| 306 | |
| 307 | env->gdt.base = x86_ldl_phys(cs, sm_state + 0x7f74); |
| 308 | env->gdt.limit = x86_ldl_phys(cs, sm_state + 0x7f70); |
| 309 | |
| 310 | env->idt.base = x86_ldl_phys(cs, sm_state + 0x7f58); |
| 311 | env->idt.limit = x86_ldl_phys(cs, sm_state + 0x7f54); |
| 312 | |
| 313 | for (i = 0; i < 6; i++) { |
| 314 | if (i < 3) { |
| 315 | offset = 0x7f84 + i * 12; |
| 316 | } else { |
| 317 | offset = 0x7f2c + (i - 3) * 12; |
| 318 | } |
| 319 | cpu_x86_load_seg_cache(env, i, |
| 320 | x86_ldl_phys(cs, |
| 321 | sm_state + 0x7fa8 + i * 4) & 0xffff, |
| 322 | x86_ldl_phys(cs, sm_state + offset + 8), |
| 323 | x86_ldl_phys(cs, sm_state + offset + 4), |
| 324 | (x86_ldl_phys(cs, |
| 325 | sm_state + offset) & 0xf0ff) << 8); |
| 326 | } |
| 327 | cpu_x86_update_cr4(env, x86_ldl_phys(cs, sm_state + 0x7f14)); |
| 328 | |
| 329 | val = x86_ldl_phys(cs, sm_state + 0x7efc); /* revision ID */ |
| 330 | if (val & 0x20000) { |
| 331 | env->smbase = x86_ldl_phys(cs, sm_state + 0x7ef8); |
| 332 | } |
| 333 | } |
| 334 | |
| 335 | void helper_rsm(CPUX86State *env) |
| 336 | { |
| 337 | X86CPU *cpu = env_archcpu(env); |
| 338 | |
| 339 | if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { |
| 340 | rsm_load_regs_64(env); |
| 341 | } else { |
| 342 | rsm_load_regs_32(env); |
| 343 | } |
| 344 | |
| 345 | if ((env->hflags2 & HF2_SMM_INSIDE_NMI_MASK) == 0) { |
| 346 | env->hflags2 &= ~HF2_NMI_MASK; |
| 347 | } |
| 348 | env->hflags2 &= ~HF2_SMM_INSIDE_NMI_MASK; |
| 349 | env->hflags &= ~HF_SMM_MASK; |
| 350 | |
| 351 | qemu_log_mask(CPU_LOG_INT, "SMM: after RSM\n"); |
| 352 | log_cpu_state_mask(CPU_LOG_INT, CPU(cpu), CPU_DUMP_CCOP); |
| 353 | } |