| 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
| 2 | /* |
| 3 | * QEMU LoongArch CPU |
| 4 | * |
| 5 | * Copyright (c) 2021 Loongson Technology Corporation Limited |
| 6 | */ |
| 7 | |
| 8 | #ifndef LOONGARCH_CPU_H |
| 9 | #define LOONGARCH_CPU_H |
| 10 | |
| 11 | #include "qemu/int128.h" |
| 12 | #include "exec/cpu-common.h" |
| 13 | #include "exec/cpu-interrupt.h" |
| 14 | #include "fpu/softfloat-types.h" |
| 15 | #include "hw/core/registerfields.h" |
| 16 | #include "qemu/timer.h" |
| 17 | #ifndef CONFIG_USER_ONLY |
| 18 | #include "system/memory.h" |
| 19 | #endif |
| 20 | #include "cpu-csr.h" |
| 21 | #include "cpu-qom.h" |
| 22 | |
| 23 | #define FCSR0_M1 0x1f /* FCSR1 mask, Enables */ |
| 24 | #define FCSR0_M2 0x1f1f0000 /* FCSR2 mask, Cause and Flags */ |
| 25 | #define FCSR0_M3 0x300 /* FCSR3 mask, Round Mode */ |
| 26 | #define FCSR0_RM 8 /* Round Mode bit num on fcsr0 */ |
| 27 | |
| 28 | FIELD(FCSR0, ENABLES, 0, 5) |
| 29 | FIELD(FCSR0, RM, 8, 2) |
| 30 | FIELD(FCSR0, FLAGS, 16, 5) |
| 31 | FIELD(FCSR0, CAUSE, 24, 5) |
| 32 | |
| 33 | #define GET_FP_CAUSE(REG) FIELD_EX32(REG, FCSR0, CAUSE) |
| 34 | #define SET_FP_CAUSE(REG, V) \ |
| 35 | do { \ |
| 36 | (REG) = FIELD_DP32(REG, FCSR0, CAUSE, V); \ |
| 37 | } while (0) |
| 38 | #define UPDATE_FP_CAUSE(REG, V) \ |
| 39 | do { \ |
| 40 | (REG) |= FIELD_DP32(0, FCSR0, CAUSE, V); \ |
| 41 | } while (0) |
| 42 | |
| 43 | #define GET_FP_ENABLES(REG) FIELD_EX32(REG, FCSR0, ENABLES) |
| 44 | #define SET_FP_ENABLES(REG, V) \ |
| 45 | do { \ |
| 46 | (REG) = FIELD_DP32(REG, FCSR0, ENABLES, V); \ |
| 47 | } while (0) |
| 48 | |
| 49 | #define GET_FP_FLAGS(REG) FIELD_EX32(REG, FCSR0, FLAGS) |
| 50 | #define SET_FP_FLAGS(REG, V) \ |
| 51 | do { \ |
| 52 | (REG) = FIELD_DP32(REG, FCSR0, FLAGS, V); \ |
| 53 | } while (0) |
| 54 | |
| 55 | #define UPDATE_FP_FLAGS(REG, V) \ |
| 56 | do { \ |
| 57 | (REG) |= FIELD_DP32(0, FCSR0, FLAGS, V); \ |
| 58 | } while (0) |
| 59 | |
| 60 | #define FP_INEXACT 1 |
| 61 | #define FP_UNDERFLOW 2 |
| 62 | #define FP_OVERFLOW 4 |
| 63 | #define FP_DIV0 8 |
| 64 | #define FP_INVALID 16 |
| 65 | |
| 66 | #define EXCODE(code, subcode) ( ((subcode) << 6) | (code) ) |
| 67 | #define EXCODE_MCODE(code) ( (code) & 0x3f ) |
| 68 | #define EXCODE_SUBCODE(code) ( (code) >> 6 ) |
| 69 | |
| 70 | #define EXCCODE_EXTERNAL_INT 64 /* plus external interrupt number */ |
| 71 | #define EXCCODE_INT EXCODE(0, 0) |
| 72 | #define EXCCODE_PIL EXCODE(1, 0) |
| 73 | #define EXCCODE_PIS EXCODE(2, 0) |
| 74 | #define EXCCODE_PIF EXCODE(3, 0) |
| 75 | #define EXCCODE_PME EXCODE(4, 0) |
| 76 | #define EXCCODE_PNR EXCODE(5, 0) |
| 77 | #define EXCCODE_PNX EXCODE(6, 0) |
| 78 | #define EXCCODE_PPI EXCODE(7, 0) |
| 79 | #define EXCCODE_ADEF EXCODE(8, 0) /* Different exception subcode */ |
| 80 | #define EXCCODE_ADEM EXCODE(8, 1) |
| 81 | #define EXCCODE_ALE EXCODE(9, 0) |
| 82 | #define EXCCODE_BCE EXCODE(10, 0) |
| 83 | #define EXCCODE_SYS EXCODE(11, 0) |
| 84 | #define EXCCODE_BRK EXCODE(12, 0) |
| 85 | #define EXCCODE_INE EXCODE(13, 0) |
| 86 | #define EXCCODE_IPE EXCODE(14, 0) |
| 87 | #define EXCCODE_FPD EXCODE(15, 0) |
| 88 | #define EXCCODE_SXD EXCODE(16, 0) |
| 89 | #define EXCCODE_ASXD EXCODE(17, 0) |
| 90 | #define EXCCODE_FPE EXCODE(18, 0) /* Different exception subcode */ |
| 91 | #define EXCCODE_VFPE EXCODE(18, 1) |
| 92 | #define EXCCODE_WPEF EXCODE(19, 0) /* Different exception subcode */ |
| 93 | #define EXCCODE_WPEM EXCODE(19, 1) |
| 94 | #define EXCCODE_BTD EXCODE(20, 0) |
| 95 | #define EXCCODE_BTE EXCODE(21, 0) |
| 96 | #define EXCCODE_DBP EXCODE(26, 0) /* Reserved subcode used for debug */ |
| 97 | |
| 98 | /* cpucfg[0] bits */ |
| 99 | FIELD(CPUCFG0, PRID, 0, 12) |
| 100 | FIELD(CPUCFG0, SERID, 12, 4) |
| 101 | FIELD(CPUCFG0, VENID, 16, 8) |
| 102 | #define PRID_SERIES_LA132 0x8 /* Loongson 32bit */ |
| 103 | #define PRID_SERIES_LA264 0xa /* Loongson 64bit, 2-issue */ |
| 104 | #define PRID_SERIES_LA364 0xb /* Loongson 64bit, 3-issue */ |
| 105 | #define PRID_SERIES_LA464 0xc /* Loongson 64bit, 4-issue */ |
| 106 | #define PRID_SERIES_LA664 0xd /* Loongson 64bit, 6-issue */ |
| 107 | #define PRID_VENDOR_LOONGSON 0x14 |
| 108 | |
| 109 | /* cpucfg[1] bits */ |
| 110 | FIELD(CPUCFG1, ARCH, 0, 2) |
| 111 | FIELD(CPUCFG1, PGMMU, 2, 1) |
| 112 | FIELD(CPUCFG1, IOCSR, 3, 1) |
| 113 | FIELD(CPUCFG1, PALEN, 4, 8) |
| 114 | FIELD(CPUCFG1, VALEN, 12, 8) |
| 115 | FIELD(CPUCFG1, UAL, 20, 1) |
| 116 | FIELD(CPUCFG1, RI, 21, 1) |
| 117 | FIELD(CPUCFG1, EP, 22, 1) |
| 118 | FIELD(CPUCFG1, RPLV, 23, 1) |
| 119 | FIELD(CPUCFG1, HP, 24, 1) |
| 120 | FIELD(CPUCFG1, CRC, 25, 1) |
| 121 | FIELD(CPUCFG1, MSG_INT, 26, 1) |
| 122 | |
| 123 | /* cpucfg[1].arch */ |
| 124 | #define CPUCFG1_ARCH_LA32R 0 |
| 125 | #define CPUCFG1_ARCH_LA32 1 |
| 126 | #define CPUCFG1_ARCH_LA64 2 |
| 127 | |
| 128 | /* cpucfg[2] bits */ |
| 129 | FIELD(CPUCFG2, FP, 0, 1) |
| 130 | FIELD(CPUCFG2, FP_SP, 1, 1) |
| 131 | FIELD(CPUCFG2, FP_DP, 2, 1) |
| 132 | FIELD(CPUCFG2, FP_VER, 3, 3) |
| 133 | FIELD(CPUCFG2, LSX, 6, 1) |
| 134 | FIELD(CPUCFG2, LASX, 7, 1) |
| 135 | FIELD(CPUCFG2, COMPLEX, 8, 1) |
| 136 | FIELD(CPUCFG2, CRYPTO, 9, 1) |
| 137 | FIELD(CPUCFG2, LVZ, 10, 1) |
| 138 | FIELD(CPUCFG2, LVZ_VER, 11, 3) |
| 139 | FIELD(CPUCFG2, LLFTP, 14, 1) |
| 140 | FIELD(CPUCFG2, LLFTP_VER, 15, 3) |
| 141 | FIELD(CPUCFG2, LBT_X86, 18, 1) |
| 142 | FIELD(CPUCFG2, LBT_ARM, 19, 1) |
| 143 | FIELD(CPUCFG2, LBT_MIPS, 20, 1) |
| 144 | FIELD(CPUCFG2, LBT_ALL, 18, 3) |
| 145 | FIELD(CPUCFG2, LSPW, 21, 1) |
| 146 | FIELD(CPUCFG2, LAM, 22, 1) |
| 147 | FIELD(CPUCFG2, HPTW, 24, 1) |
| 148 | FIELD(CPUCFG2, FRECIPE, 25, 1) |
| 149 | FIELD(CPUCFG2, DIV32, 26, 1) |
| 150 | FIELD(CPUCFG2, LAM_BH, 27, 1) |
| 151 | FIELD(CPUCFG2, LAMCAS, 28, 1) |
| 152 | FIELD(CPUCFG2, LLACQ_SCREL, 29, 1) |
| 153 | FIELD(CPUCFG2, SCQ, 30, 1) |
| 154 | |
| 155 | /* cpucfg[3] bits */ |
| 156 | FIELD(CPUCFG3, CCDMA, 0, 1) |
| 157 | FIELD(CPUCFG3, SFB, 1, 1) |
| 158 | FIELD(CPUCFG3, UCACC, 2, 1) |
| 159 | FIELD(CPUCFG3, LLEXC, 3, 1) |
| 160 | FIELD(CPUCFG3, SCDLY, 4, 1) |
| 161 | FIELD(CPUCFG3, LLDBAR, 5, 1) |
| 162 | FIELD(CPUCFG3, ITLBHMC, 6, 1) |
| 163 | FIELD(CPUCFG3, ICHMC, 7, 1) |
| 164 | FIELD(CPUCFG3, SPW_LVL, 8, 3) |
| 165 | FIELD(CPUCFG3, SPW_HP_HF, 11, 1) |
| 166 | FIELD(CPUCFG3, RVA, 12, 1) |
| 167 | FIELD(CPUCFG3, RVAMAX, 13, 4) |
| 168 | FIELD(CPUCFG3, DBAR_HINTS, 17, 1) |
| 169 | FIELD(CPUCFG3, ALDORDER_CAP, 18, 1) |
| 170 | FIELD(CPUCFG3, ASTORDER_CAP, 19, 1) |
| 171 | FIELD(CPUCFG3, ALDORDER_STA, 20, 1) |
| 172 | FIELD(CPUCFG3, ASTORDER_STA, 21, 1) |
| 173 | FIELD(CPUCFG3, SLDORDER_CAP, 22, 1) |
| 174 | FIELD(CPUCFG3, SLDORDER_STA, 23, 1) |
| 175 | |
| 176 | /* cpucfg[4] bits */ |
| 177 | FIELD(CPUCFG4, CC_FREQ, 0, 32) |
| 178 | |
| 179 | /* cpucfg[5] bits */ |
| 180 | FIELD(CPUCFG5, CC_MUL, 0, 16) |
| 181 | FIELD(CPUCFG5, CC_DIV, 16, 16) |
| 182 | |
| 183 | /* cpucfg[6] bits */ |
| 184 | FIELD(CPUCFG6, PMP, 0, 1) |
| 185 | FIELD(CPUCFG6, PMVER, 1, 3) |
| 186 | FIELD(CPUCFG6, PMNUM, 4, 4) |
| 187 | FIELD(CPUCFG6, PMBITS, 8, 6) |
| 188 | FIELD(CPUCFG6, UPM, 14, 1) |
| 189 | |
| 190 | /* cpucfg[16] bits */ |
| 191 | FIELD(CPUCFG16, L1_IUPRE, 0, 1) |
| 192 | FIELD(CPUCFG16, L1_IUUNIFY, 1, 1) |
| 193 | FIELD(CPUCFG16, L1_DPRE, 2, 1) |
| 194 | FIELD(CPUCFG16, L2_IUPRE, 3, 1) |
| 195 | FIELD(CPUCFG16, L2_IUUNIFY, 4, 1) |
| 196 | FIELD(CPUCFG16, L2_IUPRIV, 5, 1) |
| 197 | FIELD(CPUCFG16, L2_IUINCL, 6, 1) |
| 198 | FIELD(CPUCFG16, L2_DPRE, 7, 1) |
| 199 | FIELD(CPUCFG16, L2_DPRIV, 8, 1) |
| 200 | FIELD(CPUCFG16, L2_DINCL, 9, 1) |
| 201 | FIELD(CPUCFG16, L3_IUPRE, 10, 1) |
| 202 | FIELD(CPUCFG16, L3_IUUNIFY, 11, 1) |
| 203 | FIELD(CPUCFG16, L3_IUPRIV, 12, 1) |
| 204 | FIELD(CPUCFG16, L3_IUINCL, 13, 1) |
| 205 | FIELD(CPUCFG16, L3_DPRE, 14, 1) |
| 206 | FIELD(CPUCFG16, L3_DPRIV, 15, 1) |
| 207 | FIELD(CPUCFG16, L3_DINCL, 16, 1) |
| 208 | |
| 209 | /* cpucfg[17] bits */ |
| 210 | FIELD(CPUCFG17, L1IU_WAYS, 0, 16) |
| 211 | FIELD(CPUCFG17, L1IU_SETS, 16, 8) |
| 212 | FIELD(CPUCFG17, L1IU_SIZE, 24, 7) |
| 213 | |
| 214 | /* cpucfg[18] bits */ |
| 215 | FIELD(CPUCFG18, L1D_WAYS, 0, 16) |
| 216 | FIELD(CPUCFG18, L1D_SETS, 16, 8) |
| 217 | FIELD(CPUCFG18, L1D_SIZE, 24, 7) |
| 218 | |
| 219 | /* cpucfg[19] bits */ |
| 220 | FIELD(CPUCFG19, L2IU_WAYS, 0, 16) |
| 221 | FIELD(CPUCFG19, L2IU_SETS, 16, 8) |
| 222 | FIELD(CPUCFG19, L2IU_SIZE, 24, 7) |
| 223 | |
| 224 | /* cpucfg[20] bits */ |
| 225 | FIELD(CPUCFG20, L3IU_WAYS, 0, 16) |
| 226 | FIELD(CPUCFG20, L3IU_SETS, 16, 8) |
| 227 | FIELD(CPUCFG20, L3IU_SIZE, 24, 7) |
| 228 | |
| 229 | /*CSR_CRMD */ |
| 230 | FIELD(CSR_CRMD, PLV, 0, 2) |
| 231 | FIELD(CSR_CRMD, IE, 2, 1) |
| 232 | FIELD(CSR_CRMD, DA, 3, 1) |
| 233 | FIELD(CSR_CRMD, PG, 4, 1) |
| 234 | FIELD(CSR_CRMD, DATF, 5, 2) |
| 235 | FIELD(CSR_CRMD, DATM, 7, 2) |
| 236 | FIELD(CSR_CRMD, WE, 9, 1) |
| 237 | |
| 238 | extern const char * const regnames[32]; |
| 239 | extern const char * const fregnames[32]; |
| 240 | |
| 241 | #define N_IRQS 15 |
| 242 | #define IRQ_TIMER 11 |
| 243 | #define IRQ_IPI 12 |
| 244 | #define INT_DMSI 14 |
| 245 | |
| 246 | #define MAX_PERF_EVENTS 16 |
| 247 | #define LOONGARCH_STLB 2048 /* 2048 STLB */ |
| 248 | #define LOONGARCH_MTLB 64 /* 64 MTLB */ |
| 249 | #define LOONGARCH_TLB_MAX (LOONGARCH_STLB + LOONGARCH_MTLB) |
| 250 | |
| 251 | /* |
| 252 | * define the ASID PS E VPPN field of TLB |
| 253 | */ |
| 254 | FIELD(TLB_MISC, E, 0, 1) |
| 255 | FIELD(TLB_MISC, ASID, 1, 10) |
| 256 | FIELD(TLB_MISC, VPPN, 13, 35) |
| 257 | FIELD(TLB_MISC, PS, 48, 6) |
| 258 | |
| 259 | /*Msg interrupt registers */ |
| 260 | #define N_MSGIS 4 |
| 261 | FIELD(CSR_MSGIS, IS, 0, 63) |
| 262 | FIELD(CSR_MSGIR, INTNUM, 0, 8) |
| 263 | FIELD(CSR_MSGIR, ACTIVE, 31, 1) |
| 264 | FIELD(CSR_MSGIE, PT, 0, 8) |
| 265 | |
| 266 | #define LSX_LEN (128) |
| 267 | #define LASX_LEN (256) |
| 268 | |
| 269 | typedef union VReg { |
| 270 | int8_t B[LASX_LEN / 8]; |
| 271 | int16_t H[LASX_LEN / 16]; |
| 272 | int32_t W[LASX_LEN / 32]; |
| 273 | int64_t D[LASX_LEN / 64]; |
| 274 | uint8_t UB[LASX_LEN / 8]; |
| 275 | uint16_t UH[LASX_LEN / 16]; |
| 276 | uint32_t UW[LASX_LEN / 32]; |
| 277 | uint64_t UD[LASX_LEN / 64]; |
| 278 | Int128 Q[LASX_LEN / 128]; |
| 279 | } VReg; |
| 280 | |
| 281 | typedef union fpr_t fpr_t; |
| 282 | union fpr_t { |
| 283 | VReg vreg; |
| 284 | }; |
| 285 | |
| 286 | #ifdef CONFIG_TCG |
| 287 | struct LoongArchTLB { |
| 288 | uint64_t tlb_misc; |
| 289 | /* Fields corresponding to CSR_TLBELO0/1 */ |
| 290 | uint64_t tlb_entry0; |
| 291 | uint64_t tlb_entry1; |
| 292 | }; |
| 293 | typedef struct LoongArchTLB LoongArchTLB; |
| 294 | #endif |
| 295 | |
| 296 | enum loongarch_features { |
| 297 | LOONGARCH_FEATURE_LSX, |
| 298 | LOONGARCH_FEATURE_LASX, |
| 299 | LOONGARCH_FEATURE_LBT, /* loongson binary translation extension */ |
| 300 | LOONGARCH_FEATURE_PMU, |
| 301 | LOONGARCH_FEATURE_PV_IPI, |
| 302 | LOONGARCH_FEATURE_STEALTIME, |
| 303 | LOONGARCH_FEATURE_PTW, |
| 304 | LOONGARCH_FEATURE_MSGINT, |
| 305 | }; |
| 306 | |
| 307 | typedef struct LoongArchBT { |
| 308 | /* scratch registers */ |
| 309 | uint64_t scr0; |
| 310 | uint64_t scr1; |
| 311 | uint64_t scr2; |
| 312 | uint64_t scr3; |
| 313 | /* loongarch eflags */ |
| 314 | uint32_t eflags; |
| 315 | uint32_t ftop; |
| 316 | } lbt_t; |
| 317 | |
| 318 | #define CPU_VENDOR_LOONGSON "Loongson" |
| 319 | #define CPU_MODEL_3A5000 "3A5000" |
| 320 | #define CPU_MODEL_1C101 "1C101" |
| 321 | typedef struct CPUSysState { |
| 322 | /* LoongArch CSRs */ |
| 323 | uint64_t CSR_CRMD; |
| 324 | uint64_t CSR_PRMD; |
| 325 | uint64_t CSR_EUEN; |
| 326 | uint64_t CSR_MISC; |
| 327 | uint64_t CSR_ECFG; |
| 328 | uint64_t CSR_ESTAT; |
| 329 | uint64_t CSR_ERA; |
| 330 | uint64_t CSR_BADV; |
| 331 | uint64_t CSR_BADI; |
| 332 | uint64_t CSR_EENTRY; |
| 333 | uint64_t CSR_TLBIDX; |
| 334 | uint64_t CSR_TLBEHI; |
| 335 | uint64_t CSR_TLBELO0; |
| 336 | uint64_t CSR_TLBELO1; |
| 337 | uint64_t CSR_ASID; |
| 338 | uint64_t CSR_PGDL; |
| 339 | uint64_t CSR_PGDH; |
| 340 | uint64_t CSR_PGD; |
| 341 | uint64_t CSR_PWCL; |
| 342 | uint64_t CSR_PWCH; |
| 343 | uint64_t CSR_STLBPS; |
| 344 | uint64_t CSR_RVACFG; |
| 345 | uint64_t CSR_CPUID; |
| 346 | uint64_t CSR_PRCFG1; |
| 347 | uint64_t CSR_PRCFG2; |
| 348 | uint64_t CSR_PRCFG3; |
| 349 | uint64_t CSR_SAVE[16]; |
| 350 | uint64_t CSR_TID; |
| 351 | uint64_t CSR_TCFG; |
| 352 | uint64_t CSR_TVAL; |
| 353 | uint64_t CSR_CNTC; |
| 354 | uint64_t CSR_TICLR; |
| 355 | uint64_t CSR_LLBCTL; |
| 356 | uint64_t CSR_IMPCTL1; |
| 357 | uint64_t CSR_IMPCTL2; |
| 358 | uint64_t CSR_TLBRENTRY; |
| 359 | uint64_t CSR_TLBRBADV; |
| 360 | uint64_t CSR_TLBRERA; |
| 361 | uint64_t CSR_TLBRSAVE; |
| 362 | uint64_t CSR_TLBRELO0; |
| 363 | uint64_t CSR_TLBRELO1; |
| 364 | uint64_t CSR_TLBREHI; |
| 365 | uint64_t CSR_TLBRPRMD; |
| 366 | uint64_t CSR_MERRCTL; |
| 367 | uint64_t CSR_MERRINFO1; |
| 368 | uint64_t CSR_MERRINFO2; |
| 369 | uint64_t CSR_MERRENTRY; |
| 370 | uint64_t CSR_MERRERA; |
| 371 | uint64_t CSR_MERRSAVE; |
| 372 | uint64_t CSR_CTAG; |
| 373 | uint64_t CSR_DMW[4]; |
| 374 | uint64_t CSR_PERFCTRL[MAX_PERF_EVENTS]; |
| 375 | uint64_t CSR_PERFCNTR[MAX_PERF_EVENTS]; |
| 376 | uint64_t CSR_DBG; |
| 377 | uint64_t CSR_DERA; |
| 378 | uint64_t CSR_DSAVE; |
| 379 | /* Msg interrupt registers */ |
| 380 | uint64_t CSR_MSGIS[N_MSGIS]; |
| 381 | uint64_t CSR_MSGIR; |
| 382 | uint64_t CSR_MSGIE; |
| 383 | } CPUSysState; |
| 384 | |
| 385 | typedef struct CPUArchState { |
| 386 | uint64_t gpr[32]; |
| 387 | uint64_t pc; |
| 388 | |
| 389 | fpr_t fpr[32]; |
| 390 | bool cf[8]; |
| 391 | uint32_t fcsr0; |
| 392 | lbt_t lbt; |
| 393 | |
| 394 | uint32_t cpucfg[21]; |
| 395 | uint32_t pv_features; |
| 396 | uint64_t vendor_id; |
| 397 | uint64_t cpu_id; |
| 398 | CPUSysState sys_states[1]; |
| 399 | |
| 400 | struct { |
| 401 | uint64_t guest_addr; |
| 402 | } stealtime; |
| 403 | uint32_t perf_event_num; |
| 404 | |
| 405 | #ifdef CONFIG_TCG |
| 406 | float_status fp_status; |
| 407 | uint32_t fcsr0_mask; |
| 408 | uint64_t lladdr; /* LL virtual address compared against SC */ |
| 409 | uint64_t llval; |
| 410 | uint64_t llval_high; /* For 128-bit atomic SC.Q */ |
| 411 | uint64_t llbit_scq; /* Potential LL.D+LD.D+SC.Q sequence in effect */ |
| 412 | uint64_t hw_pte_mask; /* Mask of architecturally-defined (hardware) PTE bits. */ |
| 413 | #endif |
| 414 | #ifndef CONFIG_USER_ONLY |
| 415 | #ifdef CONFIG_TCG |
| 416 | LoongArchTLB tlb[LOONGARCH_TLB_MAX]; |
| 417 | #endif |
| 418 | |
| 419 | AddressSpace *address_space_iocsr; |
| 420 | uint32_t mp_state; |
| 421 | #endif |
| 422 | CPUSysState *sys_state; |
| 423 | } CPULoongArchState; |
| 424 | |
| 425 | typedef struct LoongArchCPUTopo { |
| 426 | int32_t socket_id; /* socket-id of this VCPU */ |
| 427 | int32_t core_id; /* core-id of this VCPU */ |
| 428 | int32_t thread_id; /* thread-id of this VCPU */ |
| 429 | } LoongArchCPUTopo; |
| 430 | |
| 431 | /** |
| 432 | * LoongArchCPU: |
| 433 | * @env: #CPULoongArchState |
| 434 | * |
| 435 | * A LoongArch CPU. |
| 436 | */ |
| 437 | struct ArchCPU { |
| 438 | CPUState parent_obj; |
| 439 | |
| 440 | CPULoongArchState env; |
| 441 | QEMUTimer timer; |
| 442 | uint32_t phy_id; |
| 443 | OnOffAuto lbt; |
| 444 | OnOffAuto pmu; |
| 445 | OnOffAuto ptw; |
| 446 | OnOffAuto lsx; |
| 447 | OnOffAuto lasx; |
| 448 | OnOffAuto msgint; |
| 449 | OnOffAuto kvm_pv_ipi; |
| 450 | OnOffAuto kvm_steal_time; |
| 451 | int32_t socket_id; /* socket-id of this CPU */ |
| 452 | int32_t core_id; /* core-id of this CPU */ |
| 453 | int32_t thread_id; /* thread-id of this CPU */ |
| 454 | int32_t node_id; /* NUMA node of this CPU */ |
| 455 | |
| 456 | /* 'compatible' string for this CPU for Linux device trees */ |
| 457 | const char *dtb_compatible; |
| 458 | /* used by KVM_REG_LOONGARCH_COUNTER ioctl to access guest time counters */ |
| 459 | uint64_t kvm_state_counter; |
| 460 | VMChangeStateEntry *vmsentry; |
| 461 | }; |
| 462 | |
| 463 | /** |
| 464 | * LoongArchCPUClass: |
| 465 | * @parent_realize: The parent class' realize handler. |
| 466 | * @parent_phases: The parent class' reset phase handlers. |
| 467 | * |
| 468 | * A LoongArch CPU model. |
| 469 | */ |
| 470 | struct LoongArchCPUClass { |
| 471 | CPUClass parent_class; |
| 472 | |
| 473 | DeviceRealize parent_realize; |
| 474 | DeviceUnrealize parent_unrealize; |
| 475 | ResettablePhases parent_phases; |
| 476 | }; |
| 477 | |
| 478 | /* |
| 479 | * LoongArch CPUs has 4 privilege levels. |
| 480 | * 0 for kernel mode, 3 for user mode. |
| 481 | * Define an extra index for DA(direct addressing) mode. |
| 482 | */ |
| 483 | #define MMU_PLV_KERNEL 0 |
| 484 | #define MMU_PLV_USER 3 |
| 485 | #define MMU_KERNEL_IDX MMU_PLV_KERNEL |
| 486 | #define MMU_USER_IDX MMU_PLV_USER |
| 487 | #define MMU_DA_IDX 4 |
| 488 | |
| 489 | static inline CPUSysState *env_sys(CPULoongArchState *env) |
| 490 | { |
| 491 | return env->sys_state; |
| 492 | } |
| 493 | |
| 494 | static inline void set_sys_state(CPULoongArchState *env, CPUSysState *sys) |
| 495 | { |
| 496 | env->sys_state = sys; |
| 497 | } |
| 498 | |
| 499 | static inline bool is_la64(CPULoongArchState *env) |
| 500 | { |
| 501 | return FIELD_EX32(env->cpucfg[1], CPUCFG1, ARCH) == CPUCFG1_ARCH_LA64; |
| 502 | } |
| 503 | |
| 504 | static inline bool is_va32(CPULoongArchState *env) |
| 505 | { |
| 506 | /* VA32 if !LA64 or VA32L[1-3] */ |
| 507 | bool va32 = !is_la64(env); |
| 508 | CPUSysState *sys = env_sys(env); |
| 509 | uint64_t plv = FIELD_EX64(sys->CSR_CRMD, CSR_CRMD, PLV); |
| 510 | if (plv >= 1 && (FIELD_EX64(sys->CSR_MISC, CSR_MISC, VA32) & (1 << plv))) { |
| 511 | va32 = true; |
| 512 | } |
| 513 | return va32; |
| 514 | } |
| 515 | |
| 516 | static inline void set_pc(CPULoongArchState *env, uint64_t value) |
| 517 | { |
| 518 | if (is_va32(env)) { |
| 519 | env->pc = (uint32_t)value; |
| 520 | } else { |
| 521 | env->pc = value; |
| 522 | } |
| 523 | } |
| 524 | |
| 525 | /* |
| 526 | * LoongArch CPUs hardware flags. |
| 527 | */ |
| 528 | #define HW_FLAGS_PLV_MASK R_CSR_CRMD_PLV_MASK /* 0x03 */ |
| 529 | #define HW_FLAGS_EUEN_FPE 0x04 |
| 530 | #define HW_FLAGS_EUEN_SXE 0x08 |
| 531 | #define HW_FLAGS_CRMD_PG R_CSR_CRMD_PG_MASK /* 0x10 */ |
| 532 | #define HW_FLAGS_VA32 0x20 |
| 533 | #define HW_FLAGS_EUEN_ASXE 0x40 |
| 534 | |
| 535 | #define CPU_RESOLVING_TYPE TYPE_LOONGARCH_CPU |
| 536 | |
| 537 | #endif /* LOONGARCH_CPU_H */ |