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1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3 * LoongArch emulation helpers for QEMU.
4 *
5 * Copyright (c) 2021 Loongson Technology Corporation Limited
6 */
7
8 #include "qemu/osdep.h"
9 #include "qemu/log.h"
10 #include "cpu.h"
11 #include "qemu/host-utils.h"
12 #include "exec/helper-proto.h"
13 #include "accel/tcg/cpu-ldst.h"
14 #include "internals.h"
15 #include "qemu/crc32c.h"
16 #include <zlib.h> /* for crc32 */
17 #include "cpu-csr.h"
18
19 /* Exceptions helpers */
20 void helper_raise_exception(CPULoongArchState *env, uint32_t exception)
21 {
22 do_raise_exception(env, exception, GETPC());
23 }
24
25 /* loongarch assert op */
26 void helper_asrtle_d(CPULoongArchState *env, target_ulong rj, target_ulong rk)
27 {
28 CPUSysState *sys = env_sys(env);
29
30 if (rj > rk) {
31 sys->CSR_BADV = rj;
32 do_raise_exception(env, EXCCODE_BCE, GETPC());
33 }
34 }
35
36 void helper_asrtgt_d(CPULoongArchState *env, target_ulong rj, target_ulong rk)
37 {
38 CPUSysState *sys = env_sys(env);
39
40 if (rj <= rk) {
41 sys->CSR_BADV = rj;
42 do_raise_exception(env, EXCCODE_BCE, GETPC());
43 }
44 }
45
46 target_ulong helper_crc32(target_ulong val, target_ulong m, uint64_t sz)
47 {
48 uint8_t buf[8];
49 target_ulong mask = ((sz * 8) == 64) ? -1ULL : ((1ULL << (sz * 8)) - 1);
50
51 m &= mask;
52 stq_le_p(buf, m);
53 return (int32_t) (crc32(val ^ 0xffffffff, buf, sz) ^ 0xffffffff);
54 }
55
56 target_ulong helper_crc32c(target_ulong val, target_ulong m, uint64_t sz)
57 {
58 uint8_t buf[8];
59 target_ulong mask = ((sz * 8) == 64) ? -1ULL : ((1ULL << (sz * 8)) - 1);
60 m &= mask;
61 stq_le_p(buf, m);
62 return (int32_t) (crc32c(val, buf, sz) ^ 0xffffffff);
63 }
64
65 target_ulong helper_cpucfg(CPULoongArchState *env, target_ulong rj)
66 {
67 return rj >= ARRAY_SIZE(env->cpucfg) ? 0 : env->cpucfg[rj];
68 }
69
70 uint64_t helper_rdtime_d(CPULoongArchState *env)
71 {
72 #ifdef CONFIG_USER_ONLY
73 return cpu_get_host_ticks();
74 #else
75 uint64_t plv;
76 LoongArchCPU *cpu = env_archcpu(env);
77 CPUSysState *sys = env_sys(env);
78
79 plv = FIELD_EX64(sys->CSR_CRMD, CSR_CRMD, PLV);
80 if (extract64(sys->CSR_MISC, R_CSR_MISC_DRDTL_SHIFT + plv, 1)) {
81 do_raise_exception(env, EXCCODE_IPE, GETPC());
82 }
83
84 return cpu_loongarch_get_constant_timer_counter(cpu);
85 #endif
86 }
87
88 #ifndef CONFIG_USER_ONLY
89 void helper_ertn(CPULoongArchState *env)
90 {
91 uint64_t csr_pplv, csr_pie;
92 CPUSysState *sys = env_sys(env);
93
94 if (FIELD_EX64(sys->CSR_TLBRERA, CSR_TLBRERA, ISTLBR)) {
95 csr_pplv = FIELD_EX64(sys->CSR_TLBRPRMD, CSR_TLBRPRMD, PPLV);
96 csr_pie = FIELD_EX64(sys->CSR_TLBRPRMD, CSR_TLBRPRMD, PIE);
97
98 sys->CSR_TLBRERA = FIELD_DP64(sys->CSR_TLBRERA, CSR_TLBRERA, ISTLBR, 0);
99 sys->CSR_CRMD = FIELD_DP64(sys->CSR_CRMD, CSR_CRMD, DA, 0);
100 sys->CSR_CRMD = FIELD_DP64(sys->CSR_CRMD, CSR_CRMD, PG, 1);
101 set_pc(env, sys->CSR_TLBRERA);
102 qemu_log_mask(CPU_LOG_INT, "%s: TLBRERA " TARGET_FMT_lx "\n",
103 __func__, sys->CSR_TLBRERA);
104 } else {
105 csr_pplv = FIELD_EX64(sys->CSR_PRMD, CSR_PRMD, PPLV);
106 csr_pie = FIELD_EX64(sys->CSR_PRMD, CSR_PRMD, PIE);
107
108 set_pc(env, sys->CSR_ERA);
109 qemu_log_mask(CPU_LOG_INT, "%s: ERA " TARGET_FMT_lx "\n",
110 __func__, sys->CSR_ERA);
111 }
112 sys->CSR_CRMD = FIELD_DP64(sys->CSR_CRMD, CSR_CRMD, PLV, csr_pplv);
113 sys->CSR_CRMD = FIELD_DP64(sys->CSR_CRMD, CSR_CRMD, IE, csr_pie);
114
115 env->lladdr = 1;
116 }
117
118 void helper_idle(CPULoongArchState *env)
119 {
120 CPUState *cs = env_cpu(env);
121
122 cs->halted = 1;
123 do_raise_exception(env, EXCP_HLT, 0);
124 }
125 #endif