| 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
| 2 | /* |
| 3 | * LoongArch emulation for QEMU - main translation routines. |
| 4 | * |
| 5 | * Copyright (c) 2021 Loongson Technology Corporation Limited |
| 6 | */ |
| 7 | |
| 8 | #include "qemu/osdep.h" |
| 9 | #include "cpu.h" |
| 10 | #include "tcg/tcg-op.h" |
| 11 | #include "tcg/tcg-op-gvec.h" |
| 12 | #include "exec/translation-block.h" |
| 13 | #include "exec/translator.h" |
| 14 | #include "exec/target_page.h" |
| 15 | #include "exec/helper-proto.h" |
| 16 | #include "exec/helper-gen.h" |
| 17 | #include "exec/log.h" |
| 18 | #include "qemu/qemu-print.h" |
| 19 | #include "fpu/softfloat.h" |
| 20 | #include "tcg_loongarch.h" |
| 21 | #include "translate.h" |
| 22 | #include "internals.h" |
| 23 | #include "vec.h" |
| 24 | |
| 25 | /* Global register indices */ |
| 26 | TCGv cpu_gpr[32], cpu_pc; |
| 27 | static TCGv cpu_lladdr, cpu_llval, cpu_llval_high, cpu_llbit_scq; |
| 28 | |
| 29 | #define HELPER_H "helper.h" |
| 30 | #include "exec/helper-info.c.inc" |
| 31 | #undef HELPER_H |
| 32 | |
| 33 | #define DISAS_STOP DISAS_TARGET_0 |
| 34 | #define DISAS_EXIT DISAS_TARGET_1 |
| 35 | #define DISAS_EXIT_UPDATE DISAS_TARGET_2 |
| 36 | |
| 37 | static inline int vec_full_offset(int regno) |
| 38 | { |
| 39 | return offsetof(CPULoongArchState, fpr[regno]); |
| 40 | } |
| 41 | |
| 42 | static inline int vec_reg_offset(int regno, int index, MemOp mop) |
| 43 | { |
| 44 | const uint8_t size = 1 << mop; |
| 45 | int offs = index * size; |
| 46 | |
| 47 | if (HOST_BIG_ENDIAN && size < 8 ) { |
| 48 | offs ^= (8 - size); |
| 49 | } |
| 50 | |
| 51 | return offs + vec_full_offset(regno); |
| 52 | } |
| 53 | |
| 54 | static inline void get_vreg64(TCGv_i64 dest, int regno, int index) |
| 55 | { |
| 56 | tcg_gen_ld_i64(dest, tcg_env, |
| 57 | offsetof(CPULoongArchState, fpr[regno].vreg.D(index))); |
| 58 | } |
| 59 | |
| 60 | static inline void set_vreg64(TCGv_i64 src, int regno, int index) |
| 61 | { |
| 62 | tcg_gen_st_i64(src, tcg_env, |
| 63 | offsetof(CPULoongArchState, fpr[regno].vreg.D(index))); |
| 64 | } |
| 65 | |
| 66 | static inline int plus_1(DisasContext *ctx, int x) |
| 67 | { |
| 68 | return x + 1; |
| 69 | } |
| 70 | |
| 71 | static inline int shl_1(DisasContext *ctx, int x) |
| 72 | { |
| 73 | return x << 1; |
| 74 | } |
| 75 | |
| 76 | static inline int shl_2(DisasContext *ctx, int x) |
| 77 | { |
| 78 | return x << 2; |
| 79 | } |
| 80 | |
| 81 | static inline int shl_3(DisasContext *ctx, int x) |
| 82 | { |
| 83 | return x << 3; |
| 84 | } |
| 85 | |
| 86 | /* |
| 87 | * LoongArch the upper 32 bits are undefined ("can be any value"). |
| 88 | * QEMU chooses to nanbox, because it is most likely to show guest bugs early. |
| 89 | */ |
| 90 | static void gen_nanbox_s(TCGv_i64 out, TCGv_i64 in) |
| 91 | { |
| 92 | tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(32, 32)); |
| 93 | } |
| 94 | |
| 95 | void generate_exception(DisasContext *ctx, int excp) |
| 96 | { |
| 97 | tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); |
| 98 | gen_helper_raise_exception(tcg_env, tcg_constant_i32(excp)); |
| 99 | ctx->base.is_jmp = DISAS_NORETURN; |
| 100 | } |
| 101 | |
| 102 | static void gen_goto_tb(DisasContext *ctx, unsigned tb_slot_idx, vaddr dest) |
| 103 | { |
| 104 | if (ctx->va32) { |
| 105 | dest = (uint32_t) dest; |
| 106 | } |
| 107 | |
| 108 | if (translator_use_goto_tb(&ctx->base, dest)) { |
| 109 | tcg_gen_goto_tb(tb_slot_idx); |
| 110 | tcg_gen_movi_tl(cpu_pc, dest); |
| 111 | tcg_gen_exit_tb(ctx->base.tb, tb_slot_idx); |
| 112 | } else { |
| 113 | tcg_gen_movi_tl(cpu_pc, dest); |
| 114 | tcg_gen_lookup_and_goto_ptr(); |
| 115 | } |
| 116 | } |
| 117 | |
| 118 | static void loongarch_tr_init_disas_context(DisasContextBase *dcbase, |
| 119 | CPUState *cs) |
| 120 | { |
| 121 | int64_t bound; |
| 122 | CPULoongArchState *env = cpu_env(cs); |
| 123 | DisasContext *ctx = container_of(dcbase, DisasContext, base); |
| 124 | |
| 125 | ctx->page_start = ctx->base.pc_first & TARGET_PAGE_MASK; |
| 126 | ctx->plv = ctx->base.tb->flags & HW_FLAGS_PLV_MASK; |
| 127 | if (ctx->base.tb->flags & HW_FLAGS_CRMD_PG) { |
| 128 | ctx->mem_idx = ctx->plv; |
| 129 | } else { |
| 130 | ctx->mem_idx = MMU_DA_IDX; |
| 131 | } |
| 132 | |
| 133 | /* Bound the number of insns to execute to those left on the page. */ |
| 134 | bound = -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4; |
| 135 | ctx->base.max_insns = MIN(ctx->base.max_insns, bound); |
| 136 | |
| 137 | if (FIELD_EX64(env->cpucfg[2], CPUCFG2, LSX)) { |
| 138 | ctx->vl = LSX_LEN; |
| 139 | } |
| 140 | |
| 141 | if (FIELD_EX64(env->cpucfg[2], CPUCFG2, LASX)) { |
| 142 | ctx->vl = LASX_LEN; |
| 143 | } |
| 144 | |
| 145 | ctx->la64 = is_la64(env); |
| 146 | ctx->va32 = (ctx->base.tb->flags & HW_FLAGS_VA32) != 0; |
| 147 | |
| 148 | ctx->zero = tcg_constant_tl(0); |
| 149 | |
| 150 | ctx->cpucfg1 = env->cpucfg[1]; |
| 151 | ctx->cpucfg2 = env->cpucfg[2]; |
| 152 | ctx->cpucfg3 = env->cpucfg[3]; |
| 153 | } |
| 154 | |
| 155 | static void loongarch_tr_tb_start(DisasContextBase *dcbase, CPUState *cs) |
| 156 | { |
| 157 | } |
| 158 | |
| 159 | static void loongarch_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) |
| 160 | { |
| 161 | DisasContext *ctx = container_of(dcbase, DisasContext, base); |
| 162 | |
| 163 | tcg_gen_insn_start(ctx->base.pc_next, 0, 0); |
| 164 | } |
| 165 | |
| 166 | /* |
| 167 | * Wrappers for getting reg values. |
| 168 | * |
| 169 | * The $zero register does not have cpu_gpr[0] allocated -- we supply the |
| 170 | * constant zero as a source, and an uninitialized sink as destination. |
| 171 | * |
| 172 | * Further, we may provide an extension for word operations. |
| 173 | */ |
| 174 | static TCGv gpr_src(DisasContext *ctx, int reg_num, DisasExtend src_ext) |
| 175 | { |
| 176 | TCGv t; |
| 177 | |
| 178 | if (reg_num == 0) { |
| 179 | return ctx->zero; |
| 180 | } |
| 181 | |
| 182 | switch (src_ext) { |
| 183 | case EXT_NONE: |
| 184 | return cpu_gpr[reg_num]; |
| 185 | case EXT_SIGN: |
| 186 | t = tcg_temp_new(); |
| 187 | tcg_gen_ext32s_tl(t, cpu_gpr[reg_num]); |
| 188 | return t; |
| 189 | case EXT_ZERO: |
| 190 | t = tcg_temp_new(); |
| 191 | tcg_gen_ext32u_tl(t, cpu_gpr[reg_num]); |
| 192 | return t; |
| 193 | } |
| 194 | g_assert_not_reached(); |
| 195 | } |
| 196 | |
| 197 | static TCGv gpr_dst(DisasContext *ctx, int reg_num, DisasExtend dst_ext) |
| 198 | { |
| 199 | if (reg_num == 0 || dst_ext) { |
| 200 | return tcg_temp_new(); |
| 201 | } |
| 202 | return cpu_gpr[reg_num]; |
| 203 | } |
| 204 | |
| 205 | static void gen_set_gpr(int reg_num, TCGv t, DisasExtend dst_ext) |
| 206 | { |
| 207 | if (reg_num != 0) { |
| 208 | switch (dst_ext) { |
| 209 | case EXT_NONE: |
| 210 | tcg_gen_mov_tl(cpu_gpr[reg_num], t); |
| 211 | break; |
| 212 | case EXT_SIGN: |
| 213 | tcg_gen_ext32s_tl(cpu_gpr[reg_num], t); |
| 214 | break; |
| 215 | case EXT_ZERO: |
| 216 | tcg_gen_ext32u_tl(cpu_gpr[reg_num], t); |
| 217 | break; |
| 218 | default: |
| 219 | g_assert_not_reached(); |
| 220 | } |
| 221 | } |
| 222 | } |
| 223 | |
| 224 | static TCGv get_fpr(DisasContext *ctx, int reg_num) |
| 225 | { |
| 226 | TCGv t = tcg_temp_new(); |
| 227 | tcg_gen_ld_i64(t, tcg_env, |
| 228 | offsetof(CPULoongArchState, fpr[reg_num].vreg.D(0))); |
| 229 | return t; |
| 230 | } |
| 231 | |
| 232 | static void set_fpr(int reg_num, TCGv val) |
| 233 | { |
| 234 | tcg_gen_st_i64(val, tcg_env, |
| 235 | offsetof(CPULoongArchState, fpr[reg_num].vreg.D(0))); |
| 236 | } |
| 237 | |
| 238 | static TCGv make_address_x(DisasContext *ctx, TCGv base, TCGv addend) |
| 239 | { |
| 240 | TCGv temp = NULL; |
| 241 | |
| 242 | if (addend || ctx->va32) { |
| 243 | temp = tcg_temp_new(); |
| 244 | } |
| 245 | if (addend) { |
| 246 | tcg_gen_add_tl(temp, base, addend); |
| 247 | base = temp; |
| 248 | } |
| 249 | if (ctx->va32) { |
| 250 | tcg_gen_ext32u_tl(temp, base); |
| 251 | base = temp; |
| 252 | } |
| 253 | return base; |
| 254 | } |
| 255 | |
| 256 | static TCGv make_address_i(DisasContext *ctx, TCGv base, target_long ofs) |
| 257 | { |
| 258 | TCGv addend = ofs ? tcg_constant_tl(ofs) : NULL; |
| 259 | return make_address_x(ctx, base, addend); |
| 260 | } |
| 261 | |
| 262 | static uint64_t make_address_pc(DisasContext *ctx, uint64_t addr) |
| 263 | { |
| 264 | if (ctx->va32) { |
| 265 | addr = (int32_t)addr; |
| 266 | } |
| 267 | return addr; |
| 268 | } |
| 269 | |
| 270 | #include "decode-insns.c.inc" |
| 271 | #include "insn_trans/trans_arith.c.inc" |
| 272 | #include "insn_trans/trans_shift.c.inc" |
| 273 | #include "insn_trans/trans_bit.c.inc" |
| 274 | #include "insn_trans/trans_memory.c.inc" |
| 275 | #include "insn_trans/trans_atomic.c.inc" |
| 276 | #include "insn_trans/trans_extra.c.inc" |
| 277 | #include "insn_trans/trans_farith.c.inc" |
| 278 | #include "insn_trans/trans_fcmp.c.inc" |
| 279 | #include "insn_trans/trans_fcnv.c.inc" |
| 280 | #include "insn_trans/trans_fmov.c.inc" |
| 281 | #include "insn_trans/trans_fmemory.c.inc" |
| 282 | #include "insn_trans/trans_branch.c.inc" |
| 283 | #include "insn_trans/trans_privileged.c.inc" |
| 284 | #include "insn_trans/trans_vec.c.inc" |
| 285 | |
| 286 | static void loongarch_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) |
| 287 | { |
| 288 | DisasContext *ctx = container_of(dcbase, DisasContext, base); |
| 289 | |
| 290 | ctx->opcode = translator_ldl_end(cpu_env(cs), &ctx->base, |
| 291 | ctx->base.pc_next, MO_LE); |
| 292 | |
| 293 | if (!decode(ctx, ctx->opcode)) { |
| 294 | qemu_log_mask(LOG_UNIMP, "Error: unknown opcode. " |
| 295 | "0x%" VADDR_PRIx ": 0x%x\n", |
| 296 | ctx->base.pc_next, ctx->opcode); |
| 297 | generate_exception(ctx, EXCCODE_INE); |
| 298 | } |
| 299 | |
| 300 | ctx->base.pc_next += 4; |
| 301 | |
| 302 | if (ctx->va32) { |
| 303 | ctx->base.pc_next = (uint32_t)ctx->base.pc_next; |
| 304 | } |
| 305 | } |
| 306 | |
| 307 | static void loongarch_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) |
| 308 | { |
| 309 | DisasContext *ctx = container_of(dcbase, DisasContext, base); |
| 310 | |
| 311 | switch (ctx->base.is_jmp) { |
| 312 | case DISAS_STOP: |
| 313 | tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); |
| 314 | tcg_gen_lookup_and_goto_ptr(); |
| 315 | break; |
| 316 | case DISAS_TOO_MANY: |
| 317 | gen_goto_tb(ctx, 0, ctx->base.pc_next); |
| 318 | break; |
| 319 | case DISAS_NORETURN: |
| 320 | break; |
| 321 | case DISAS_EXIT_UPDATE: |
| 322 | tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); |
| 323 | QEMU_FALLTHROUGH; |
| 324 | case DISAS_EXIT: |
| 325 | tcg_gen_exit_tb(NULL, 0); |
| 326 | break; |
| 327 | default: |
| 328 | g_assert_not_reached(); |
| 329 | } |
| 330 | } |
| 331 | |
| 332 | static const TranslatorOps loongarch_tr_ops = { |
| 333 | .init_disas_context = loongarch_tr_init_disas_context, |
| 334 | .tb_start = loongarch_tr_tb_start, |
| 335 | .insn_start = loongarch_tr_insn_start, |
| 336 | .translate_insn = loongarch_tr_translate_insn, |
| 337 | .tb_stop = loongarch_tr_tb_stop, |
| 338 | }; |
| 339 | |
| 340 | void loongarch_translate_code(CPUState *cs, TranslationBlock *tb, |
| 341 | int *max_insns, vaddr pc, void *host_pc) |
| 342 | { |
| 343 | DisasContext ctx; |
| 344 | |
| 345 | translator_loop(cs, tb, max_insns, pc, host_pc, |
| 346 | &loongarch_tr_ops, &ctx.base, |
| 347 | TCG_TYPE_VA); |
| 348 | } |
| 349 | |
| 350 | void loongarch_translate_init(void) |
| 351 | { |
| 352 | int i; |
| 353 | |
| 354 | cpu_gpr[0] = NULL; |
| 355 | for (i = 1; i < 32; i++) { |
| 356 | cpu_gpr[i] = tcg_global_mem_new(tcg_env, |
| 357 | offsetof(CPULoongArchState, gpr[i]), |
| 358 | regnames[i]); |
| 359 | } |
| 360 | |
| 361 | cpu_pc = tcg_global_mem_new(tcg_env, offsetof(CPULoongArchState, pc), "pc"); |
| 362 | cpu_lladdr = tcg_global_mem_new(tcg_env, |
| 363 | offsetof(CPULoongArchState, lladdr), "lladdr"); |
| 364 | cpu_llval = tcg_global_mem_new(tcg_env, |
| 365 | offsetof(CPULoongArchState, llval), "llval"); |
| 366 | cpu_llval_high = tcg_global_mem_new(tcg_env, |
| 367 | offsetof(CPULoongArchState, llval_high), "llval_high"); |
| 368 | cpu_llbit_scq = tcg_global_mem_new(tcg_env, |
| 369 | offsetof(CPULoongArchState, llbit_scq), "llbit_scq"); |
| 370 | |
| 371 | #ifndef CONFIG_USER_ONLY |
| 372 | loongarch_csr_translate_init(); |
| 373 | #endif |
| 374 | } |