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1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3 * LoongArch translation routines.
4 *
5 * Copyright (c) 2021 Loongson Technology Corporation Limited
6 */
7
8 #ifndef TARGET_LOONGARCH_TRANSLATE_H
9 #define TARGET_LOONGARCH_TRANSLATE_H
10
11 #include "exec/translator.h"
12
13 #define TRANS(NAME, AVAIL, FUNC, ...) \
14 static bool trans_##NAME(DisasContext *ctx, arg_##NAME * a) \
15 { return avail_##AVAIL(ctx) && FUNC(ctx, a, __VA_ARGS__); }
16
17 #define TRANS64(NAME, AVAIL, FUNC, ...) \
18 static bool trans_##NAME(DisasContext *ctx, arg_##NAME * a) \
19 { return avail_64(ctx) && avail_##AVAIL(ctx) && FUNC(ctx, a, __VA_ARGS__); }
20
21 #define avail_ALL(C) true
22 #define avail_64(C) (FIELD_EX32((C)->cpucfg1, CPUCFG1, ARCH) == \
23 CPUCFG1_ARCH_LA64)
24 #define avail_FP(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, FP))
25 #define avail_FP_SP(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, FP_SP))
26 #define avail_FP_DP(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, FP_DP))
27 #define avail_LSPW(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, LSPW))
28 #define avail_LAM(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, LAM))
29 #define avail_LAM_BH(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, LAM_BH))
30 #define avail_LAMCAS(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, LAMCAS))
31 #define avail_LSX(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, LSX))
32 #define avail_LASX(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, LASX))
33 #define avail_SCQ(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, SCQ))
34 #define avail_IOCSR(C) (FIELD_EX32((C)->cpucfg1, CPUCFG1, IOCSR))
35 #define avail_CRC(C) (FIELD_EX32((C)->cpucfg1, CPUCFG1, CRC))
36
37 #define avail_FRECIPE(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, FRECIPE))
38 #define avail_FRECIPE_FP_SP(C) (avail_FRECIPE(C) && avail_FP_SP(C))
39 #define avail_FRECIPE_FP_DP(C) (avail_FRECIPE(C) && avail_FP_DP(C))
40 #define avail_FRECIPE_LSX(C) (avail_FRECIPE(C) && avail_LSX(C))
41 #define avail_FRECIPE_LASX(C) (avail_FRECIPE(C) && avail_LASX(C))
42
43 #define avail_LLACQ_SCREL(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, LLACQ_SCREL))
44 #define avail_LLACQ_SCREL_64(C) (avail_64(C) && avail_LLACQ_SCREL(C))
45
46 #define avail_DBAR_HINT(C) (FIELD_EX32((C)->cpucfg3, CPUCFG3, DBAR_HINTS))
47
48 /*
49 * If an operation is being performed on less than TARGET_LONG_BITS,
50 * it may require the inputs to be sign- or zero-extended; which will
51 * depend on the exact operation being performed.
52 */
53 typedef enum {
54 EXT_NONE,
55 EXT_SIGN,
56 EXT_ZERO,
57 } DisasExtend;
58
59 typedef struct DisasContext {
60 DisasContextBase base;
61 target_ulong page_start;
62 uint32_t opcode;
63 uint16_t mem_idx;
64 uint16_t plv;
65 int vl; /* Vector length */
66 TCGv zero;
67 bool la64; /* LoongArch64 mode */
68 bool va32; /* 32-bit virtual address */
69 uint32_t cpucfg1;
70 uint32_t cpucfg2;
71 uint32_t cpucfg3;
72 } DisasContext;
73
74 void generate_exception(DisasContext *ctx, int excp);
75
76 extern TCGv cpu_gpr[32], cpu_pc;
77 extern TCGv_i32 cpu_fscr0;
78 extern TCGv_i64 cpu_fpr[32];
79
80 #endif