@samitouri / QOSamiQemu
Code Commits Issues Pulls Sessions CI/CD
master
master
c 1,137 lines 30.9 KB
Raw
1 /*
2 * M68K helper routines
3 *
4 * Copyright (c) 2007 CodeSourcery
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include "qemu/osdep.h"
20 #include "qemu/log.h"
21 #include "cpu.h"
22 #include "exec/helper-proto.h"
23 #include "accel/tcg/cpu-ldst.h"
24 #include "accel/tcg/cpu-loop.h"
25 #include "semihosting/semihost.h"
26 #include "qemu/plugin.h"
27
28 #if !defined(CONFIG_USER_ONLY)
29
30 static void cf_rte(CPUM68KState *env)
31 {
32 uint32_t sp;
33 uint32_t fmt;
34
35 sp = env->aregs[7];
36 fmt = cpu_ldl_be_mmuidx_ra(env, sp, MMU_KERNEL_IDX, 0);
37 env->pc = cpu_ldl_be_mmuidx_ra(env, sp + 4, MMU_KERNEL_IDX, 0);
38 sp |= (fmt >> 28) & 3;
39 env->aregs[7] = sp + 8;
40
41 cpu_m68k_set_sr(env, fmt);
42 }
43
44 static void m68k_rte(CPUM68KState *env)
45 {
46 uint32_t sp;
47 uint16_t fmt;
48 uint16_t sr;
49
50 sp = env->aregs[7];
51 throwaway:
52 sr = cpu_lduw_be_mmuidx_ra(env, sp, MMU_KERNEL_IDX, 0);
53 sp += 2;
54 env->pc = cpu_ldl_be_mmuidx_ra(env, sp, MMU_KERNEL_IDX, 0);
55 sp += 4;
56 if (m68k_feature(env, M68K_FEATURE_EXCEPTION_FORMAT_VEC)) {
57 /* all except 68000 */
58 fmt = cpu_lduw_be_mmuidx_ra(env, sp, MMU_KERNEL_IDX, 0);
59 sp += 2;
60 switch (fmt >> 12) {
61 case 0:
62 break;
63 case 1:
64 env->aregs[7] = sp;
65 cpu_m68k_set_sr(env, sr);
66 goto throwaway;
67 case 2:
68 case 3:
69 sp += 4;
70 break;
71 case 4:
72 sp += 8;
73 break;
74 case 7:
75 sp += 52;
76 break;
77 }
78 }
79 env->aregs[7] = sp;
80 cpu_m68k_set_sr(env, sr);
81 }
82
83 static const char *m68k_exception_name(int index)
84 {
85 switch (index) {
86 case EXCP_ACCESS:
87 return "Access Fault";
88 case EXCP_ADDRESS:
89 return "Address Error";
90 case EXCP_ILLEGAL:
91 return "Illegal Instruction";
92 case EXCP_DIV0:
93 return "Divide by Zero";
94 case EXCP_CHK:
95 return "CHK/CHK2";
96 case EXCP_TRAPCC:
97 return "FTRAPcc, TRAPcc, TRAPV";
98 case EXCP_PRIVILEGE:
99 return "Privilege Violation";
100 case EXCP_TRACE:
101 return "Trace";
102 case EXCP_LINEA:
103 return "A-Line";
104 case EXCP_LINEF:
105 return "F-Line";
106 case EXCP_DEBEGBP: /* 68020/030 only */
107 return "Copro Protocol Violation";
108 case EXCP_FORMAT:
109 return "Format Error";
110 case EXCP_UNINITIALIZED:
111 return "Uninitialized Interrupt";
112 case EXCP_SPURIOUS:
113 return "Spurious Interrupt";
114 case EXCP_INT_LEVEL_1:
115 return "Level 1 Interrupt";
116 case EXCP_INT_LEVEL_1 + 1:
117 return "Level 2 Interrupt";
118 case EXCP_INT_LEVEL_1 + 2:
119 return "Level 3 Interrupt";
120 case EXCP_INT_LEVEL_1 + 3:
121 return "Level 4 Interrupt";
122 case EXCP_INT_LEVEL_1 + 4:
123 return "Level 5 Interrupt";
124 case EXCP_INT_LEVEL_1 + 5:
125 return "Level 6 Interrupt";
126 case EXCP_INT_LEVEL_1 + 6:
127 return "Level 7 Interrupt";
128 case EXCP_TRAP0:
129 return "TRAP #0";
130 case EXCP_TRAP0 + 1:
131 return "TRAP #1";
132 case EXCP_TRAP0 + 2:
133 return "TRAP #2";
134 case EXCP_TRAP0 + 3:
135 return "TRAP #3";
136 case EXCP_TRAP0 + 4:
137 return "TRAP #4";
138 case EXCP_TRAP0 + 5:
139 return "TRAP #5";
140 case EXCP_TRAP0 + 6:
141 return "TRAP #6";
142 case EXCP_TRAP0 + 7:
143 return "TRAP #7";
144 case EXCP_TRAP0 + 8:
145 return "TRAP #8";
146 case EXCP_TRAP0 + 9:
147 return "TRAP #9";
148 case EXCP_TRAP0 + 10:
149 return "TRAP #10";
150 case EXCP_TRAP0 + 11:
151 return "TRAP #11";
152 case EXCP_TRAP0 + 12:
153 return "TRAP #12";
154 case EXCP_TRAP0 + 13:
155 return "TRAP #13";
156 case EXCP_TRAP0 + 14:
157 return "TRAP #14";
158 case EXCP_TRAP0 + 15:
159 return "TRAP #15";
160 case EXCP_FP_BSUN:
161 return "FP Branch/Set on unordered condition";
162 case EXCP_FP_INEX:
163 return "FP Inexact Result";
164 case EXCP_FP_DZ:
165 return "FP Divide by Zero";
166 case EXCP_FP_UNFL:
167 return "FP Underflow";
168 case EXCP_FP_OPERR:
169 return "FP Operand Error";
170 case EXCP_FP_OVFL:
171 return "FP Overflow";
172 case EXCP_FP_SNAN:
173 return "FP Signaling NAN";
174 case EXCP_FP_UNIMP:
175 return "FP Unimplemented Data Type";
176 case EXCP_MMU_CONF: /* 68030/68851 only */
177 return "MMU Configuration Error";
178 case EXCP_MMU_ILLEGAL: /* 68851 only */
179 return "MMU Illegal Operation";
180 case EXCP_MMU_ACCESS: /* 68851 only */
181 return "MMU Access Level Violation";
182 case 64 ... 255:
183 return "User Defined Vector";
184 }
185 return "Unassigned";
186 }
187
188 static void do_plugin_vcpu_interrupt_cb(CPUState *cs, uint64_t from)
189 {
190 switch (cs->exception_index) {
191 case EXCP_SPURIOUS ... EXCP_INT_LEVEL_7:
192 qemu_plugin_vcpu_interrupt_cb(cs, from);
193 break;
194 case EXCP_SEMIHOSTING:
195 qemu_plugin_vcpu_hostcall_cb(cs, from);
196 break;
197 default:
198 qemu_plugin_vcpu_exception_cb(cs, from);
199 break;
200 }
201 }
202
203 static void cf_interrupt_all(CPUM68KState *env, int is_hw)
204 {
205 CPUState *cs = env_cpu(env);
206 uint32_t sp;
207 uint32_t sr;
208 uint32_t fmt;
209 uint32_t retaddr;
210 uint32_t vector;
211
212 fmt = 0;
213 retaddr = env->pc;
214
215 if (!is_hw) {
216 switch (cs->exception_index) {
217 case EXCP_RTE:
218 /* Return from an exception. */
219 cf_rte(env);
220 return;
221 case EXCP_SEMIHOSTING:
222 do_m68k_semihosting(env, env->dregs[0]);
223 qemu_plugin_vcpu_hostcall_cb(cs, retaddr);
224 return;
225 }
226 }
227
228 vector = cs->exception_index << 2;
229
230 sr = env->sr | cpu_m68k_get_ccr(env);
231 if (qemu_loglevel_mask(CPU_LOG_INT)) {
232 static int count;
233 qemu_log("INT %6d: %s(%#x) pc=%08x sp=%08x sr=%04x\n",
234 ++count, m68k_exception_name(cs->exception_index),
235 vector, env->pc, env->aregs[7], sr);
236 }
237
238 fmt |= 0x40000000;
239 fmt |= vector << 16;
240 fmt |= sr;
241
242 env->sr |= SR_S;
243 if (is_hw) {
244 env->sr = (env->sr & ~SR_I) | (env->pending_level << SR_I_SHIFT);
245 env->sr &= ~SR_M;
246 }
247 m68k_switch_sp(env);
248 sp = env->aregs[7];
249 fmt |= (sp & 3) << 28;
250
251 /* ??? This could cause MMU faults. */
252 sp &= ~3;
253 sp -= 4;
254 cpu_stl_be_mmuidx_ra(env, sp, retaddr, MMU_KERNEL_IDX, 0);
255 sp -= 4;
256 cpu_stl_be_mmuidx_ra(env, sp, fmt, MMU_KERNEL_IDX, 0);
257 env->aregs[7] = sp;
258 /* Jump to vector. */
259 env->pc = cpu_ldl_be_mmuidx_ra(env, env->vbr + vector, MMU_KERNEL_IDX, 0);
260
261 do_plugin_vcpu_interrupt_cb(cs, retaddr);
262 }
263
264 static inline void do_stack_frame(CPUM68KState *env, uint32_t *sp,
265 uint16_t format, uint16_t sr,
266 uint32_t addr, uint32_t retaddr)
267 {
268 if (m68k_feature(env, M68K_FEATURE_EXCEPTION_FORMAT_VEC)) {
269 /* all except 68000 */
270 CPUState *cs = env_cpu(env);
271 switch (format) {
272 case 4:
273 *sp -= 4;
274 cpu_stl_be_mmuidx_ra(env, *sp, env->pc, MMU_KERNEL_IDX, 0);
275 *sp -= 4;
276 cpu_stl_be_mmuidx_ra(env, *sp, addr, MMU_KERNEL_IDX, 0);
277 break;
278 case 3:
279 case 2:
280 *sp -= 4;
281 cpu_stl_be_mmuidx_ra(env, *sp, addr, MMU_KERNEL_IDX, 0);
282 break;
283 }
284 *sp -= 2;
285 cpu_stw_be_mmuidx_ra(env, *sp,
286 (format << 12) + (cs->exception_index << 2),
287 MMU_KERNEL_IDX, 0);
288 }
289 *sp -= 4;
290 cpu_stl_be_mmuidx_ra(env, *sp, retaddr, MMU_KERNEL_IDX, 0);
291 *sp -= 2;
292 cpu_stw_be_mmuidx_ra(env, *sp, sr, MMU_KERNEL_IDX, 0);
293 }
294
295 static void m68k_interrupt_all(CPUM68KState *env, int is_hw)
296 {
297 CPUState *cs = env_cpu(env);
298 uint32_t sp;
299 uint32_t vector;
300 uint16_t sr, oldsr;
301 uint64_t last_pc = env->pc;
302
303 if (!is_hw) {
304 switch (cs->exception_index) {
305 case EXCP_RTE:
306 /* Return from an exception. */
307 m68k_rte(env);
308 return;
309 }
310 }
311
312 vector = cs->exception_index << 2;
313
314 sr = env->sr | cpu_m68k_get_ccr(env);
315 if (qemu_loglevel_mask(CPU_LOG_INT)) {
316 static int count;
317 qemu_log("INT %6d: %s(%#x) pc=%08x sp=%08x sr=%04x\n",
318 ++count, m68k_exception_name(cs->exception_index),
319 vector, env->pc, env->aregs[7], sr);
320 }
321
322 /*
323 * MC68040UM/AD, chapter 9.3.10
324 */
325
326 /* "the processor first make an internal copy" */
327 oldsr = sr;
328 /* "set the mode to supervisor" */
329 sr |= SR_S;
330 /* "suppress tracing" */
331 sr &= ~SR_T;
332 /* "sets the processor interrupt mask" */
333 if (is_hw) {
334 sr |= (env->sr & ~SR_I) | (env->pending_level << SR_I_SHIFT);
335 }
336 cpu_m68k_set_sr(env, sr);
337 sp = env->aregs[7];
338
339 if (!m68k_feature(env, M68K_FEATURE_UNALIGNED_DATA)) {
340 sp &= ~1;
341 }
342
343 switch (cs->exception_index) {
344 case EXCP_ACCESS:
345 if (env->mmu.fault) {
346 cpu_abort(cs, "DOUBLE MMU FAULT\n");
347 }
348 env->mmu.fault = true;
349 /* push data 3 */
350 sp -= 4;
351 cpu_stl_be_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);
352 /* push data 2 */
353 sp -= 4;
354 cpu_stl_be_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);
355 /* push data 1 */
356 sp -= 4;
357 cpu_stl_be_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);
358 /* write back 1 / push data 0 */
359 sp -= 4;
360 cpu_stl_be_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);
361 /* write back 1 address */
362 sp -= 4;
363 cpu_stl_be_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);
364 /* write back 2 data */
365 sp -= 4;
366 cpu_stl_be_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);
367 /* write back 2 address */
368 sp -= 4;
369 cpu_stl_be_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);
370 /* write back 3 data */
371 sp -= 4;
372 cpu_stl_be_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);
373 /* write back 3 address */
374 sp -= 4;
375 cpu_stl_be_mmuidx_ra(env, sp, env->mmu.ar, MMU_KERNEL_IDX, 0);
376 /* fault address */
377 sp -= 4;
378 cpu_stl_be_mmuidx_ra(env, sp, env->mmu.ar, MMU_KERNEL_IDX, 0);
379 /* write back 1 status */
380 sp -= 2;
381 cpu_stw_be_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);
382 /* write back 2 status */
383 sp -= 2;
384 cpu_stw_be_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);
385 /* write back 3 status */
386 sp -= 2;
387 cpu_stw_be_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);
388 /* special status word */
389 sp -= 2;
390 cpu_stw_be_mmuidx_ra(env, sp, env->mmu.ssw, MMU_KERNEL_IDX, 0);
391 /* effective address */
392 sp -= 4;
393 cpu_stl_be_mmuidx_ra(env, sp, env->mmu.ar, MMU_KERNEL_IDX, 0);
394
395 do_stack_frame(env, &sp, 7, oldsr, 0, env->pc);
396 env->mmu.fault = false;
397 if (qemu_loglevel_mask(CPU_LOG_INT)) {
398 qemu_log(" "
399 "ssw: %08x ea: %08x sfc: %d dfc: %d\n",
400 env->mmu.ssw, env->mmu.ar, env->sfc, env->dfc);
401 }
402 break;
403
404 case EXCP_ILLEGAL:
405 do_stack_frame(env, &sp, 0, oldsr, 0, env->pc);
406 break;
407
408 case EXCP_ADDRESS:
409 do_stack_frame(env, &sp, 2, oldsr, 0, env->pc);
410 break;
411
412 case EXCP_CHK:
413 case EXCP_DIV0:
414 case EXCP_TRACE:
415 case EXCP_TRAPCC:
416 do_stack_frame(env, &sp, 2, oldsr, env->mmu.ar, env->pc);
417 break;
418
419 case EXCP_SPURIOUS ... EXCP_INT_LEVEL_7:
420 if (is_hw && (oldsr & SR_M)) {
421 do_stack_frame(env, &sp, 0, oldsr, 0, env->pc);
422 oldsr = sr;
423 env->aregs[7] = sp;
424 cpu_m68k_set_sr(env, sr & ~SR_M);
425 sp = env->aregs[7];
426 if (!m68k_feature(env, M68K_FEATURE_UNALIGNED_DATA)) {
427 sp &= ~1;
428 }
429 do_stack_frame(env, &sp, 1, oldsr, 0, env->pc);
430 break;
431 }
432 /* fall through */
433
434 default:
435 do_stack_frame(env, &sp, 0, oldsr, 0, env->pc);
436 break;
437 }
438
439 env->aregs[7] = sp;
440 /* Jump to vector. */
441 env->pc = cpu_ldl_be_mmuidx_ra(env, env->vbr + vector, MMU_KERNEL_IDX, 0);
442
443 do_plugin_vcpu_interrupt_cb(cs, last_pc);
444 }
445
446 static void do_interrupt_all(CPUM68KState *env, int is_hw)
447 {
448 if (m68k_feature(env, M68K_FEATURE_M68K)) {
449 m68k_interrupt_all(env, is_hw);
450 return;
451 }
452 cf_interrupt_all(env, is_hw);
453 }
454
455 void m68k_cpu_do_interrupt(CPUState *cs)
456 {
457 do_interrupt_all(cpu_env(cs), 0);
458 }
459
460 static inline void do_interrupt_m68k_hardirq(CPUM68KState *env)
461 {
462 do_interrupt_all(env, 1);
463 }
464
465 void m68k_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr,
466 unsigned size, MMUAccessType access_type,
467 int mmu_idx, MemTxAttrs attrs,
468 MemTxResult response, uintptr_t retaddr)
469 {
470 CPUM68KState *env = cpu_env(cs);
471
472 cpu_restore_state(cs, retaddr);
473
474 if (m68k_feature(env, M68K_FEATURE_M68040)) {
475 env->mmu.mmusr = 0;
476
477 /*
478 * According to the MC68040 users manual the ATC bit of the SSW is
479 * used to distinguish between ATC faults and physical bus errors.
480 * In the case of a bus error e.g. during nubus read from an empty
481 * slot this bit should not be set
482 */
483 if (response != MEMTX_DECODE_ERROR) {
484 env->mmu.ssw |= M68K_ATC_040;
485 }
486
487 /* FIXME: manage MMU table access error */
488 env->mmu.ssw &= ~M68K_TM_040;
489 if (env->sr & SR_S) { /* SUPERVISOR */
490 env->mmu.ssw |= M68K_TM_040_SUPER;
491 }
492 if (access_type == MMU_INST_FETCH) { /* instruction or data */
493 env->mmu.ssw |= M68K_TM_040_CODE;
494 } else {
495 env->mmu.ssw |= M68K_TM_040_DATA;
496 }
497 env->mmu.ssw &= ~M68K_BA_SIZE_MASK;
498 switch (size) {
499 case 1:
500 env->mmu.ssw |= M68K_BA_SIZE_BYTE;
501 break;
502 case 2:
503 env->mmu.ssw |= M68K_BA_SIZE_WORD;
504 break;
505 case 4:
506 env->mmu.ssw |= M68K_BA_SIZE_LONG;
507 break;
508 }
509
510 if (access_type != MMU_DATA_STORE) {
511 env->mmu.ssw |= M68K_RW_040;
512 }
513
514 env->mmu.ar = addr;
515
516 cs->exception_index = EXCP_ACCESS;
517 cpu_loop_exit(cs);
518 }
519 }
520
521 bool m68k_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
522 {
523 CPUM68KState *env = cpu_env(cs);
524
525 if (interrupt_request & CPU_INTERRUPT_HARD
526 && ((env->sr & SR_I) >> SR_I_SHIFT) < env->pending_level) {
527 /*
528 * Real hardware gets the interrupt vector via an IACK cycle
529 * at this point. Current emulated hardware doesn't rely on
530 * this, so we provide/save the vector when the interrupt is
531 * first signalled.
532 */
533 cs->exception_index = env->pending_vector;
534 do_interrupt_m68k_hardirq(env);
535 return true;
536 }
537 return false;
538 }
539
540 #endif /* !CONFIG_USER_ONLY */
541
542 G_NORETURN static void
543 raise_exception_ra(CPUM68KState *env, int tt, uintptr_t raddr)
544 {
545 CPUState *cs = env_cpu(env);
546
547 cs->exception_index = tt;
548 cpu_loop_exit_restore(cs, raddr);
549 }
550
551 G_NORETURN static void raise_exception(CPUM68KState *env, int tt)
552 {
553 raise_exception_ra(env, tt, 0);
554 }
555
556 void HELPER(raise_exception)(CPUM68KState *env, uint32_t tt)
557 {
558 raise_exception(env, tt);
559 }
560
561 G_NORETURN static void
562 raise_exception_format2(CPUM68KState *env, int tt, int ilen, uintptr_t raddr)
563 {
564 CPUState *cs = env_cpu(env);
565
566 cs->exception_index = tt;
567
568 /* Recover PC and CC_OP for the beginning of the insn. */
569 cpu_restore_state(cs, raddr);
570
571 /* Flags are current in env->cc_*, or are undefined. */
572 env->cc_op = CC_OP_FLAGS;
573
574 /*
575 * Remember original pc in mmu.ar, for the Format 2 stack frame.
576 * Adjust PC to end of the insn.
577 */
578 env->mmu.ar = env->pc;
579 env->pc += ilen;
580
581 cpu_loop_exit(cs);
582 }
583
584 void HELPER(divuw)(CPUM68KState *env, int destr, uint32_t den, int ilen)
585 {
586 uint32_t num = env->dregs[destr];
587 uint32_t quot, rem;
588
589 env->cc_c = 0; /* always cleared, even if div0 */
590
591 if (den == 0) {
592 raise_exception_format2(env, EXCP_DIV0, ilen, GETPC());
593 }
594 quot = num / den;
595 rem = num % den;
596
597 if (quot > 0xffff) {
598 env->cc_v = -1;
599 /*
600 * real 68040 keeps N and unset Z on overflow,
601 * whereas documentation says "undefined"
602 */
603 env->cc_z = 1;
604 return;
605 }
606 env->dregs[destr] = deposit32(quot, 16, 16, rem);
607 env->cc_z = (int16_t)quot;
608 env->cc_n = (int16_t)quot;
609 env->cc_v = 0;
610 }
611
612 void HELPER(divsw)(CPUM68KState *env, int destr, int32_t den, int ilen)
613 {
614 int32_t num = env->dregs[destr];
615 uint32_t quot, rem;
616
617 env->cc_c = 0; /* always cleared, even if overflow/div0 */
618
619 if (den == 0) {
620 raise_exception_format2(env, EXCP_DIV0, ilen, GETPC());
621 }
622 quot = num / den;
623 rem = num % den;
624
625 if (quot != (int16_t)quot) {
626 env->cc_v = -1;
627 /* nothing else is modified */
628 /*
629 * real 68040 keeps N and unset Z on overflow,
630 * whereas documentation says "undefined"
631 */
632 env->cc_z = 1;
633 return;
634 }
635 env->dregs[destr] = deposit32(quot, 16, 16, rem);
636 env->cc_z = (int16_t)quot;
637 env->cc_n = (int16_t)quot;
638 env->cc_v = 0;
639 }
640
641 void HELPER(divul)(CPUM68KState *env, int numr, int regr,
642 uint32_t den, int ilen)
643 {
644 uint32_t num = env->dregs[numr];
645 uint32_t quot, rem;
646
647 env->cc_c = 0; /* always cleared, even if div0 */
648
649 if (den == 0) {
650 raise_exception_format2(env, EXCP_DIV0, ilen, GETPC());
651 }
652 quot = num / den;
653 rem = num % den;
654
655 env->cc_z = quot;
656 env->cc_n = quot;
657 env->cc_v = 0;
658
659 if (m68k_feature(env, M68K_FEATURE_CF_ISA_A)) {
660 if (numr == regr) {
661 env->dregs[numr] = quot;
662 } else {
663 env->dregs[regr] = rem;
664 }
665 } else {
666 env->dregs[regr] = rem;
667 env->dregs[numr] = quot;
668 }
669 }
670
671 void HELPER(divsl)(CPUM68KState *env, int numr, int regr,
672 int32_t den, int ilen)
673 {
674 int32_t num = env->dregs[numr];
675 int32_t quot, rem;
676
677 env->cc_c = 0; /* always cleared, even if overflow/div0 */
678
679 if (den == 0) {
680 raise_exception_format2(env, EXCP_DIV0, ilen, GETPC());
681 }
682 quot = num / den;
683 rem = num % den;
684
685 env->cc_z = quot;
686 env->cc_n = quot;
687 env->cc_v = 0;
688
689 if (m68k_feature(env, M68K_FEATURE_CF_ISA_A)) {
690 if (numr == regr) {
691 env->dregs[numr] = quot;
692 } else {
693 env->dregs[regr] = rem;
694 }
695 } else {
696 env->dregs[regr] = rem;
697 env->dregs[numr] = quot;
698 }
699 }
700
701 void HELPER(divull)(CPUM68KState *env, int numr, int regr,
702 uint32_t den, int ilen)
703 {
704 uint64_t num = deposit64(env->dregs[numr], 32, 32, env->dregs[regr]);
705 uint64_t quot;
706 uint32_t rem;
707
708 env->cc_c = 0; /* always cleared, even if overflow/div0 */
709
710 if (den == 0) {
711 raise_exception_format2(env, EXCP_DIV0, ilen, GETPC());
712 }
713 quot = num / den;
714 rem = num % den;
715
716 if (quot > 0xffffffffULL) {
717 env->cc_v = -1;
718 /*
719 * real 68040 keeps N and unset Z on overflow,
720 * whereas documentation says "undefined"
721 */
722 env->cc_z = 1;
723 return;
724 }
725 env->cc_z = quot;
726 env->cc_n = quot;
727 env->cc_v = 0;
728
729 /*
730 * If Dq and Dr are the same, the quotient is returned.
731 * therefore we set Dq last.
732 */
733
734 env->dregs[regr] = rem;
735 env->dregs[numr] = quot;
736 }
737
738 void HELPER(divsll)(CPUM68KState *env, int numr, int regr,
739 int32_t den, int ilen)
740 {
741 int64_t num = deposit64(env->dregs[numr], 32, 32, env->dregs[regr]);
742 int64_t quot;
743 int32_t rem;
744
745 env->cc_c = 0; /* always cleared, even if overflow/div0 */
746
747 if (den == 0) {
748 raise_exception_format2(env, EXCP_DIV0, ilen, GETPC());
749 }
750 quot = num / den;
751 rem = num % den;
752
753 if (quot != (int32_t)quot) {
754 env->cc_v = -1;
755 /*
756 * real 68040 keeps N and unset Z on overflow,
757 * whereas documentation says "undefined"
758 */
759 env->cc_z = 1;
760 return;
761 }
762 env->cc_z = quot;
763 env->cc_n = quot;
764 env->cc_v = 0;
765
766 /*
767 * If Dq and Dr are the same, the quotient is returned.
768 * therefore we set Dq last.
769 */
770
771 env->dregs[regr] = rem;
772 env->dregs[numr] = quot;
773 }
774
775 /* We're executing in a serial context -- no need to be atomic. */
776 void HELPER(cas2w)(CPUM68KState *env, uint32_t regs, uint32_t a1, uint32_t a2)
777 {
778 uint32_t Dc1 = extract32(regs, 9, 3);
779 uint32_t Dc2 = extract32(regs, 6, 3);
780 uint32_t Du1 = extract32(regs, 3, 3);
781 uint32_t Du2 = extract32(regs, 0, 3);
782 int16_t c1 = env->dregs[Dc1];
783 int16_t c2 = env->dregs[Dc2];
784 int16_t u1 = env->dregs[Du1];
785 int16_t u2 = env->dregs[Du2];
786 int16_t l1, l2;
787 uintptr_t ra = GETPC();
788
789 l1 = cpu_lduw_be_data_ra(env, a1, ra);
790 l2 = cpu_lduw_be_data_ra(env, a2, ra);
791 if (l1 == c1 && l2 == c2) {
792 cpu_stw_be_data_ra(env, a1, u1, ra);
793 cpu_stw_be_data_ra(env, a2, u2, ra);
794 }
795
796 if (c1 != l1) {
797 env->cc_n = l1;
798 env->cc_v = c1;
799 } else {
800 env->cc_n = l2;
801 env->cc_v = c2;
802 }
803 env->cc_op = CC_OP_CMPW;
804 env->dregs[Dc2] = deposit32(env->dregs[Dc2], 0, 16, l2);
805 env->dregs[Dc1] = deposit32(env->dregs[Dc1], 0, 16, l1);
806 }
807
808 static void do_cas2l(CPUM68KState *env, uint32_t regs, uint32_t a1, uint32_t a2,
809 bool parallel)
810 {
811 uint32_t Dc1 = extract32(regs, 9, 3);
812 uint32_t Dc2 = extract32(regs, 6, 3);
813 uint32_t Du1 = extract32(regs, 3, 3);
814 uint32_t Du2 = extract32(regs, 0, 3);
815 uint32_t c1 = env->dregs[Dc1];
816 uint32_t c2 = env->dregs[Dc2];
817 uint32_t u1 = env->dregs[Du1];
818 uint32_t u2 = env->dregs[Du2];
819 uint32_t l1, l2;
820 uintptr_t ra = GETPC();
821 int mmu_idx = cpu_mmu_index(env_cpu(env), 0);
822 MemOpIdx oi = make_memop_idx(MO_BEUQ, mmu_idx);
823
824 if (parallel) {
825 /* We're executing in a parallel context -- must be atomic. */
826 uint64_t c, u, l;
827 if ((a1 & 7) == 0 && a2 == a1 + 4) {
828 c = deposit64(c2, 32, 32, c1);
829 u = deposit64(u2, 32, 32, u1);
830 l = cpu_atomic_cmpxchgq_be_mmu(env, a1, c, u, oi, ra);
831 l1 = l >> 32;
832 l2 = l;
833 } else if ((a2 & 7) == 0 && a1 == a2 + 4) {
834 c = deposit64(c1, 32, 32, c2);
835 u = deposit64(u1, 32, 32, u2);
836 l = cpu_atomic_cmpxchgq_be_mmu(env, a2, c, u, oi, ra);
837 l2 = l >> 32;
838 l1 = l;
839 } else {
840 /* Tell the main loop we need to serialize this insn. */
841 cpu_loop_exit_atomic(env_cpu(env), ra);
842 }
843 } else {
844 /* We're executing in a serial context -- no need to be atomic. */
845 l1 = cpu_ldl_be_data_ra(env, a1, ra);
846 l2 = cpu_ldl_be_data_ra(env, a2, ra);
847 if (l1 == c1 && l2 == c2) {
848 cpu_stl_be_data_ra(env, a1, u1, ra);
849 cpu_stl_be_data_ra(env, a2, u2, ra);
850 }
851 }
852
853 if (c1 != l1) {
854 env->cc_n = l1;
855 env->cc_v = c1;
856 } else {
857 env->cc_n = l2;
858 env->cc_v = c2;
859 }
860 env->cc_op = CC_OP_CMPL;
861 env->dregs[Dc2] = l2;
862 env->dregs[Dc1] = l1;
863 }
864
865 void HELPER(cas2l)(CPUM68KState *env, uint32_t regs, uint32_t a1, uint32_t a2)
866 {
867 do_cas2l(env, regs, a1, a2, false);
868 }
869
870 void HELPER(cas2l_parallel)(CPUM68KState *env, uint32_t regs, uint32_t a1,
871 uint32_t a2)
872 {
873 do_cas2l(env, regs, a1, a2, true);
874 }
875
876 struct bf_data {
877 uint32_t addr;
878 uint32_t bofs;
879 uint32_t blen;
880 uint32_t len;
881 };
882
883 static struct bf_data bf_prep(uint32_t addr, int32_t ofs, uint32_t len)
884 {
885 int bofs, blen;
886
887 /* Bound length; map 0 to 32. */
888 len = ((len - 1) & 31) + 1;
889
890 /* Note that ofs is signed. */
891 addr += ofs / 8;
892 bofs = ofs % 8;
893 if (bofs < 0) {
894 bofs += 8;
895 addr -= 1;
896 }
897
898 /*
899 * Compute the number of bytes required (minus one) to
900 * satisfy the bitfield.
901 */
902 blen = (bofs + len - 1) / 8;
903
904 /*
905 * Canonicalize the bit offset for data loaded into a 64-bit big-endian
906 * word. For the cases where BLEN is not a power of 2, adjust ADDR so
907 * that we can use the next power of two sized load without crossing a
908 * page boundary, unless the field itself crosses the boundary.
909 */
910 switch (blen) {
911 case 0:
912 bofs += 56;
913 break;
914 case 1:
915 bofs += 48;
916 break;
917 case 2:
918 if (addr & 1) {
919 bofs += 8;
920 addr -= 1;
921 }
922 /* fallthru */
923 case 3:
924 bofs += 32;
925 break;
926 case 4:
927 if (addr & 3) {
928 bofs += 8 * (addr & 3);
929 addr &= -4;
930 }
931 break;
932 default:
933 g_assert_not_reached();
934 }
935
936 return (struct bf_data){
937 .addr = addr,
938 .bofs = bofs,
939 .blen = blen,
940 .len = len,
941 };
942 }
943
944 static uint64_t bf_load(CPUM68KState *env, uint32_t addr, int blen,
945 uintptr_t ra)
946 {
947 switch (blen) {
948 case 0:
949 return cpu_ldub_data_ra(env, addr, ra);
950 case 1:
951 return cpu_lduw_be_data_ra(env, addr, ra);
952 case 2:
953 case 3:
954 return cpu_ldl_be_data_ra(env, addr, ra);
955 case 4:
956 return cpu_ldq_be_data_ra(env, addr, ra);
957 default:
958 g_assert_not_reached();
959 }
960 }
961
962 static void bf_store(CPUM68KState *env, uint32_t addr, int blen,
963 uint64_t data, uintptr_t ra)
964 {
965 switch (blen) {
966 case 0:
967 cpu_stb_data_ra(env, addr, data, ra);
968 break;
969 case 1:
970 cpu_stw_be_data_ra(env, addr, data, ra);
971 break;
972 case 2:
973 case 3:
974 cpu_stl_be_data_ra(env, addr, data, ra);
975 break;
976 case 4:
977 cpu_stq_be_data_ra(env, addr, data, ra);
978 break;
979 default:
980 g_assert_not_reached();
981 }
982 }
983
984 uint32_t HELPER(bfexts_mem)(CPUM68KState *env, uint32_t addr,
985 int32_t ofs, uint32_t len)
986 {
987 uintptr_t ra = GETPC();
988 struct bf_data d = bf_prep(addr, ofs, len);
989 uint64_t data = bf_load(env, d.addr, d.blen, ra);
990
991 return (int64_t)(data << d.bofs) >> (64 - d.len);
992 }
993
994 uint64_t HELPER(bfextu_mem)(CPUM68KState *env, uint32_t addr,
995 int32_t ofs, uint32_t len)
996 {
997 uintptr_t ra = GETPC();
998 struct bf_data d = bf_prep(addr, ofs, len);
999 uint64_t data = bf_load(env, d.addr, d.blen, ra);
1000
1001 /*
1002 * Put CC_N at the top of the high word; put the zero-extended value
1003 * at the bottom of the low word.
1004 */
1005 data <<= d.bofs;
1006 data >>= 64 - d.len;
1007 data |= data << (64 - d.len);
1008
1009 return data;
1010 }
1011
1012 uint32_t HELPER(bfins_mem)(CPUM68KState *env, uint32_t addr, uint32_t val,
1013 int32_t ofs, uint32_t len)
1014 {
1015 uintptr_t ra = GETPC();
1016 struct bf_data d = bf_prep(addr, ofs, len);
1017 uint64_t data = bf_load(env, d.addr, d.blen, ra);
1018 uint64_t mask = -1ull << (64 - d.len) >> d.bofs;
1019
1020 data = (data & ~mask) | (((uint64_t)val << (64 - d.len)) >> d.bofs);
1021
1022 bf_store(env, d.addr, d.blen, data, ra);
1023
1024 /* The field at the top of the word is also CC_N for CC_OP_LOGIC. */
1025 return val << (32 - d.len);
1026 }
1027
1028 uint32_t HELPER(bfchg_mem)(CPUM68KState *env, uint32_t addr,
1029 int32_t ofs, uint32_t len)
1030 {
1031 uintptr_t ra = GETPC();
1032 struct bf_data d = bf_prep(addr, ofs, len);
1033 uint64_t data = bf_load(env, d.addr, d.blen, ra);
1034 uint64_t mask = -1ull << (64 - d.len) >> d.bofs;
1035
1036 bf_store(env, d.addr, d.blen, data ^ mask, ra);
1037
1038 return ((data & mask) << d.bofs) >> 32;
1039 }
1040
1041 uint32_t HELPER(bfclr_mem)(CPUM68KState *env, uint32_t addr,
1042 int32_t ofs, uint32_t len)
1043 {
1044 uintptr_t ra = GETPC();
1045 struct bf_data d = bf_prep(addr, ofs, len);
1046 uint64_t data = bf_load(env, d.addr, d.blen, ra);
1047 uint64_t mask = -1ull << (64 - d.len) >> d.bofs;
1048
1049 bf_store(env, d.addr, d.blen, data & ~mask, ra);
1050
1051 return ((data & mask) << d.bofs) >> 32;
1052 }
1053
1054 uint32_t HELPER(bfset_mem)(CPUM68KState *env, uint32_t addr,
1055 int32_t ofs, uint32_t len)
1056 {
1057 uintptr_t ra = GETPC();
1058 struct bf_data d = bf_prep(addr, ofs, len);
1059 uint64_t data = bf_load(env, d.addr, d.blen, ra);
1060 uint64_t mask = -1ull << (64 - d.len) >> d.bofs;
1061
1062 bf_store(env, d.addr, d.blen, data | mask, ra);
1063
1064 return ((data & mask) << d.bofs) >> 32;
1065 }
1066
1067 uint32_t HELPER(bfffo_reg)(uint32_t n, uint32_t ofs, uint32_t len)
1068 {
1069 return (n ? clz32(n) : len) + ofs;
1070 }
1071
1072 uint64_t HELPER(bfffo_mem)(CPUM68KState *env, uint32_t addr,
1073 int32_t ofs, uint32_t len)
1074 {
1075 uintptr_t ra = GETPC();
1076 struct bf_data d = bf_prep(addr, ofs, len);
1077 uint64_t data = bf_load(env, d.addr, d.blen, ra);
1078 uint64_t mask = -1ull << (64 - d.len) >> d.bofs;
1079 uint64_t n = (data & mask) << d.bofs;
1080 uint32_t ffo = helper_bfffo_reg(n >> 32, ofs, d.len);
1081
1082 /*
1083 * Return FFO in the low word and N in the high word.
1084 * Note that because of MASK and the shift, the low word
1085 * is already zero.
1086 */
1087 return n | ffo;
1088 }
1089
1090 void HELPER(chk)(CPUM68KState *env, int32_t val, int32_t ub, int ilen)
1091 {
1092 /*
1093 * From the specs:
1094 * X: Not affected, C,V,Z: Undefined,
1095 * N: Set if val < 0; cleared if val > ub, undefined otherwise
1096 * We implement here values found from a real MC68040:
1097 * X,V,Z: Not affected
1098 * N: Set if val < 0; cleared if val >= 0
1099 * C: if 0 <= ub: set if val < 0 or val > ub, cleared otherwise
1100 * if 0 > ub: set if val > ub and val < 0, cleared otherwise
1101 */
1102 env->cc_n = val;
1103 env->cc_c = 0 <= ub ? val < 0 || val > ub : val > ub && val < 0;
1104
1105 if (val < 0 || val > ub) {
1106 raise_exception_format2(env, EXCP_CHK, ilen, GETPC());
1107 }
1108 }
1109
1110 void HELPER(chk2)(CPUM68KState *env, int32_t val, int32_t lb, int32_t ub,
1111 int ilen)
1112 {
1113 /*
1114 * From the specs:
1115 * X: Not affected, N,V: Undefined,
1116 * Z: Set if val is equal to lb or ub
1117 * C: Set if val < lb or val > ub, cleared otherwise
1118 * We implement here values found from a real MC68040:
1119 * X,N,V: Not affected
1120 * Z: Set if val is equal to lb or ub
1121 * C: if lb <= ub: set if val < lb or val > ub, cleared otherwise
1122 * if lb > ub: set if val > ub and val < lb, cleared otherwise
1123 */
1124 env->cc_z = val != lb && val != ub;
1125 env->cc_c = lb <= ub ? val < lb || val > ub : val > ub && val < lb;
1126
1127 if (env->cc_c) {
1128 raise_exception_format2(env, EXCP_CHK, ilen, GETPC());
1129 }
1130 }
1131
1132 void HELPER(cmp2)(CPUM68KState *env, int32_t val, int32_t lb, int32_t ub)
1133 {
1134 /* Identical to CHK2 (above) but doesn't raise an exception */
1135 env->cc_z = val != lb && val != ub;
1136 env->cc_c = lb <= ub ? val < lb || val > ub : val > ub && val < lb;
1137 }