| 1 | /* |
| 2 | * MicroBlaze virtual CPU header |
| 3 | * |
| 4 | * Copyright (c) 2009 Edgar E. Iglesias |
| 5 | * |
| 6 | * This library is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU Lesser General Public |
| 8 | * License as published by the Free Software Foundation; either |
| 9 | * version 2.1 of the License, or (at your option) any later version. |
| 10 | * |
| 11 | * This library is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 14 | * General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU Lesser General Public |
| 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
| 18 | */ |
| 19 | |
| 20 | #ifndef MICROBLAZE_CPU_H |
| 21 | #define MICROBLAZE_CPU_H |
| 22 | |
| 23 | #include "cpu-qom.h" |
| 24 | #include "exec/cpu-common.h" |
| 25 | #include "qemu/cpu-float.h" |
| 26 | #include "exec/cpu-interrupt.h" |
| 27 | |
| 28 | typedef struct CPUArchState CPUMBState; |
| 29 | #if !defined(CONFIG_USER_ONLY) |
| 30 | #include "mmu.h" |
| 31 | #endif |
| 32 | |
| 33 | #define EXCP_MMU 1 |
| 34 | #define EXCP_IRQ 2 |
| 35 | #define EXCP_SYSCALL 3 /* user-only */ |
| 36 | #define EXCP_HW_BREAK 4 |
| 37 | #define EXCP_HW_EXCP 5 |
| 38 | |
| 39 | /* MicroBlaze-specific interrupt pending bits. */ |
| 40 | #define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3 |
| 41 | |
| 42 | /* Meanings of the MBCPU object's two inbound GPIO lines */ |
| 43 | #define MB_CPU_IRQ 0 |
| 44 | #define MB_CPU_FIR 1 |
| 45 | |
| 46 | /* Register aliases. R0 - R15 */ |
| 47 | #define R_SP 1 |
| 48 | #define SR_PC 0 |
| 49 | #define SR_MSR 1 |
| 50 | #define SR_EAR 3 |
| 51 | #define SR_ESR 5 |
| 52 | #define SR_FSR 7 |
| 53 | #define SR_BTR 0xb |
| 54 | #define SR_EDR 0xd |
| 55 | |
| 56 | /* MSR flags. */ |
| 57 | #define MSR_BE (1<<0) /* 0x001 */ |
| 58 | #define MSR_IE (1<<1) /* 0x002 */ |
| 59 | #define MSR_C (1<<2) /* 0x004 */ |
| 60 | #define MSR_BIP (1<<3) /* 0x008 */ |
| 61 | #define MSR_FSL (1<<4) /* 0x010 */ |
| 62 | #define MSR_ICE (1<<5) /* 0x020 */ |
| 63 | #define MSR_DZ (1<<6) /* 0x040 */ |
| 64 | #define MSR_DCE (1<<7) /* 0x080 */ |
| 65 | #define MSR_EE (1<<8) /* 0x100 */ |
| 66 | #define MSR_EIP (1<<9) /* 0x200 */ |
| 67 | #define MSR_PVR (1<<10) /* 0x400 */ |
| 68 | #define MSR_CC (1<<31) |
| 69 | |
| 70 | /* Machine State Register (MSR) Fields */ |
| 71 | #define MSR_UM (1<<11) /* User Mode */ |
| 72 | #define MSR_UMS (1<<12) /* User Mode Save */ |
| 73 | #define MSR_VM (1<<13) /* Virtual Mode */ |
| 74 | #define MSR_VMS (1<<14) /* Virtual Mode Save */ |
| 75 | |
| 76 | #define MSR_KERNEL MSR_EE|MSR_VM |
| 77 | //#define MSR_USER MSR_KERNEL|MSR_UM|MSR_IE |
| 78 | #define MSR_KERNEL_VMS MSR_EE|MSR_VMS |
| 79 | //#define MSR_USER_VMS MSR_KERNEL_VMS|MSR_UMS|MSR_IE |
| 80 | |
| 81 | /* Exception State Register (ESR) Fields */ |
| 82 | #define ESR_DIZ (1<<11) /* Zone Protection */ |
| 83 | #define ESR_W (1<<11) /* Unaligned word access */ |
| 84 | #define ESR_S (1<<10) /* Store instruction */ |
| 85 | |
| 86 | #define ESR_ESS_FSL_OFFSET 5 |
| 87 | |
| 88 | #define ESR_ESS_MASK (0x7f << 5) |
| 89 | #define ESR_ESS_DEC_OF (1 << 11) /* DEC: 0=DBZ, 1=OF */ |
| 90 | |
| 91 | #define ESR_EC_FSL 0 |
| 92 | #define ESR_EC_UNALIGNED_DATA 1 |
| 93 | #define ESR_EC_ILLEGAL_OP 2 |
| 94 | #define ESR_EC_INSN_BUS 3 |
| 95 | #define ESR_EC_DATA_BUS 4 |
| 96 | #define ESR_EC_DIVZERO 5 |
| 97 | #define ESR_EC_FPU 6 |
| 98 | #define ESR_EC_PRIVINSN 7 |
| 99 | #define ESR_EC_STACKPROT 7 /* Same as PRIVINSN. */ |
| 100 | #define ESR_EC_DATA_STORAGE 8 |
| 101 | #define ESR_EC_INSN_STORAGE 9 |
| 102 | #define ESR_EC_DATA_TLB 10 |
| 103 | #define ESR_EC_INSN_TLB 11 |
| 104 | #define ESR_EC_MASK 31 |
| 105 | |
| 106 | /* Floating Point Status Register (FSR) Bits */ |
| 107 | #define FSR_IO (1<<4) /* Invalid operation */ |
| 108 | #define FSR_DZ (1<<3) /* Divide-by-zero */ |
| 109 | #define FSR_OF (1<<2) /* Overflow */ |
| 110 | #define FSR_UF (1<<1) /* Underflow */ |
| 111 | #define FSR_DO (1<<0) /* Denormalized operand error */ |
| 112 | |
| 113 | /* Version reg. */ |
| 114 | /* Basic PVR mask */ |
| 115 | #define PVR0_PVR_FULL_MASK 0x80000000 |
| 116 | #define PVR0_USE_BARREL_MASK 0x40000000 |
| 117 | #define PVR0_USE_DIV_MASK 0x20000000 |
| 118 | #define PVR0_USE_HW_MUL_MASK 0x10000000 |
| 119 | #define PVR0_USE_FPU_MASK 0x08000000 |
| 120 | #define PVR0_USE_EXC_MASK 0x04000000 |
| 121 | #define PVR0_USE_ICACHE_MASK 0x02000000 |
| 122 | #define PVR0_USE_DCACHE_MASK 0x01000000 |
| 123 | #define PVR0_USE_MMU_MASK 0x00800000 |
| 124 | #define PVR0_USE_BTC 0x00400000 |
| 125 | #define PVR0_ENDI_MASK 0x00200000 |
| 126 | #define PVR0_FAULT 0x00100000 |
| 127 | #define PVR0_VERSION_MASK 0x0000FF00 |
| 128 | #define PVR0_USER1_MASK 0x000000FF |
| 129 | #define PVR0_SPROT_MASK 0x00000001 |
| 130 | |
| 131 | #define PVR0_VERSION_SHIFT 8 |
| 132 | |
| 133 | /* User 2 PVR mask */ |
| 134 | #define PVR1_USER2_MASK 0xFFFFFFFF |
| 135 | |
| 136 | /* Configuration PVR masks */ |
| 137 | #define PVR2_D_OPB_MASK 0x80000000 |
| 138 | #define PVR2_D_LMB_MASK 0x40000000 |
| 139 | #define PVR2_I_OPB_MASK 0x20000000 |
| 140 | #define PVR2_I_LMB_MASK 0x10000000 |
| 141 | #define PVR2_INTERRUPT_IS_EDGE_MASK 0x08000000 |
| 142 | #define PVR2_EDGE_IS_POSITIVE_MASK 0x04000000 |
| 143 | #define PVR2_D_PLB_MASK 0x02000000 /* new */ |
| 144 | #define PVR2_I_PLB_MASK 0x01000000 /* new */ |
| 145 | #define PVR2_INTERCONNECT 0x00800000 /* new */ |
| 146 | #define PVR2_USE_EXTEND_FSL 0x00080000 /* new */ |
| 147 | #define PVR2_USE_FSL_EXC 0x00040000 /* new */ |
| 148 | #define PVR2_USE_MSR_INSTR 0x00020000 |
| 149 | #define PVR2_USE_PCMP_INSTR 0x00010000 |
| 150 | #define PVR2_AREA_OPTIMISED 0x00008000 |
| 151 | #define PVR2_USE_BARREL_MASK 0x00004000 |
| 152 | #define PVR2_USE_DIV_MASK 0x00002000 |
| 153 | #define PVR2_USE_HW_MUL_MASK 0x00001000 |
| 154 | #define PVR2_USE_FPU_MASK 0x00000800 |
| 155 | #define PVR2_USE_MUL64_MASK 0x00000400 |
| 156 | #define PVR2_USE_FPU2_MASK 0x00000200 /* new */ |
| 157 | #define PVR2_USE_IPLBEXC 0x00000100 |
| 158 | #define PVR2_USE_DPLBEXC 0x00000080 |
| 159 | #define PVR2_OPCODE_0x0_ILL_MASK 0x00000040 |
| 160 | #define PVR2_UNALIGNED_EXC_MASK 0x00000020 |
| 161 | #define PVR2_ILL_OPCODE_EXC_MASK 0x00000010 |
| 162 | #define PVR2_IOPB_BUS_EXC_MASK 0x00000008 |
| 163 | #define PVR2_DOPB_BUS_EXC_MASK 0x00000004 |
| 164 | #define PVR2_DIV_ZERO_EXC_MASK 0x00000002 |
| 165 | #define PVR2_FPU_EXC_MASK 0x00000001 |
| 166 | |
| 167 | /* Debug and exception PVR masks */ |
| 168 | #define PVR3_DEBUG_ENABLED_MASK 0x80000000 |
| 169 | #define PVR3_NUMBER_OF_PC_BRK_MASK 0x1E000000 |
| 170 | #define PVR3_NUMBER_OF_RD_ADDR_BRK_MASK 0x00380000 |
| 171 | #define PVR3_NUMBER_OF_WR_ADDR_BRK_MASK 0x0000E000 |
| 172 | #define PVR3_FSL_LINKS_MASK 0x00000380 |
| 173 | |
| 174 | /* ICache config PVR masks */ |
| 175 | #define PVR4_USE_ICACHE_MASK 0x80000000 |
| 176 | #define PVR4_ICACHE_ADDR_TAG_BITS_MASK 0x7C000000 |
| 177 | #define PVR4_ICACHE_USE_FSL_MASK 0x02000000 |
| 178 | #define PVR4_ICACHE_ALLOW_WR_MASK 0x01000000 |
| 179 | #define PVR4_ICACHE_LINE_LEN_MASK 0x00E00000 |
| 180 | #define PVR4_ICACHE_BYTE_SIZE_MASK 0x001F0000 |
| 181 | |
| 182 | /* DCache config PVR masks */ |
| 183 | #define PVR5_USE_DCACHE_MASK 0x80000000 |
| 184 | #define PVR5_DCACHE_ADDR_TAG_BITS_MASK 0x7C000000 |
| 185 | #define PVR5_DCACHE_USE_FSL_MASK 0x02000000 |
| 186 | #define PVR5_DCACHE_ALLOW_WR_MASK 0x01000000 |
| 187 | #define PVR5_DCACHE_LINE_LEN_MASK 0x00E00000 |
| 188 | #define PVR5_DCACHE_BYTE_SIZE_MASK 0x001F0000 |
| 189 | #define PVR5_DCACHE_WRITEBACK_MASK 0x00004000 |
| 190 | |
| 191 | /* ICache base address PVR mask */ |
| 192 | #define PVR6_ICACHE_BASEADDR_MASK 0xFFFFFFFF |
| 193 | |
| 194 | /* ICache high address PVR mask */ |
| 195 | #define PVR7_ICACHE_HIGHADDR_MASK 0xFFFFFFFF |
| 196 | |
| 197 | /* DCache base address PVR mask */ |
| 198 | #define PVR8_DCACHE_BASEADDR_MASK 0xFFFFFFFF |
| 199 | |
| 200 | /* DCache high address PVR mask */ |
| 201 | #define PVR9_DCACHE_HIGHADDR_MASK 0xFFFFFFFF |
| 202 | |
| 203 | /* Target family PVR mask */ |
| 204 | #define PVR10_TARGET_FAMILY_MASK 0xFF000000 |
| 205 | #define PVR10_ASIZE_SHIFT 18 |
| 206 | |
| 207 | /* MMU description */ |
| 208 | #define PVR11_USE_MMU 0xC0000000 |
| 209 | #define PVR11_MMU_ITLB_SIZE 0x38000000 |
| 210 | #define PVR11_MMU_DTLB_SIZE 0x07000000 |
| 211 | #define PVR11_MMU_TLB_ACCESS 0x00C00000 |
| 212 | #define PVR11_MMU_ZONES 0x003E0000 |
| 213 | /* MSR Reset value PVR mask */ |
| 214 | #define PVR11_MSR_RESET_VALUE_MASK 0x000007FF |
| 215 | |
| 216 | #define C_PVR_NONE 0 |
| 217 | #define C_PVR_BASIC 1 |
| 218 | #define C_PVR_FULL 2 |
| 219 | |
| 220 | /* CPU flags. */ |
| 221 | |
| 222 | /* Condition codes. */ |
| 223 | #define CC_GE 5 |
| 224 | #define CC_GT 4 |
| 225 | #define CC_LE 3 |
| 226 | #define CC_LT 2 |
| 227 | #define CC_NE 1 |
| 228 | #define CC_EQ 0 |
| 229 | |
| 230 | #define STREAM_EXCEPTION (1 << 0) |
| 231 | #define STREAM_ATOMIC (1 << 1) |
| 232 | #define STREAM_TEST (1 << 2) |
| 233 | #define STREAM_CONTROL (1 << 3) |
| 234 | #define STREAM_NONBLOCK (1 << 4) |
| 235 | |
| 236 | /* use-non-secure property masks */ |
| 237 | #define USE_NON_SECURE_M_AXI_DP_MASK 0x1 |
| 238 | #define USE_NON_SECURE_M_AXI_IP_MASK 0x2 |
| 239 | #define USE_NON_SECURE_M_AXI_DC_MASK 0x4 |
| 240 | #define USE_NON_SECURE_M_AXI_IC_MASK 0x8 |
| 241 | |
| 242 | struct CPUArchState { |
| 243 | uint32_t bvalue; /* TCG temporary, only valid during a TB */ |
| 244 | uint32_t btarget; /* Full resolved branch destination */ |
| 245 | |
| 246 | uint32_t imm; |
| 247 | uint32_t regs[32]; |
| 248 | uint32_t pc; |
| 249 | uint32_t msr; /* All bits of MSR except MSR[C] and MSR[CC] */ |
| 250 | uint32_t msr_c; /* MSR[C], in low bit; other bits must be 0 */ |
| 251 | uint64_t ear; |
| 252 | uint32_t esr; |
| 253 | uint32_t fsr; |
| 254 | uint32_t btr; |
| 255 | uint32_t edr; |
| 256 | float_status fp_status; |
| 257 | /* Stack protectors. Yes, it's a hw feature. */ |
| 258 | uint32_t slr, shr; |
| 259 | |
| 260 | /* lwx/swx reserved address */ |
| 261 | #define RES_ADDR_NONE 0xffffffff /* Use 0xffffffff to indicate no reservation */ |
| 262 | uint32_t res_addr; |
| 263 | uint32_t res_val; |
| 264 | |
| 265 | /* Internal flags. */ |
| 266 | #define IMM_FLAG (1 << 0) |
| 267 | #define BIMM_FLAG (1 << 1) |
| 268 | #define ESR_ESS_FLAG (1 << 2) /* indicates ESR_ESS_MASK is present */ |
| 269 | /* MSR_EE (1 << 8) -- these 3 are not in iflags but tb_flags */ |
| 270 | /* MSR_UM (1 << 11) */ |
| 271 | /* MSR_VM (1 << 13) */ |
| 272 | /* ESR_ESS_MASK [11:5] -- unwind into iflags for unaligned excp */ |
| 273 | #define D_FLAG (1 << 12) /* Bit in ESR. */ |
| 274 | #define DRTI_FLAG (1 << 16) |
| 275 | #define DRTE_FLAG (1 << 17) |
| 276 | #define DRTB_FLAG (1 << 18) |
| 277 | |
| 278 | /* TB dependent CPUMBState. */ |
| 279 | #define IFLAGS_TB_MASK (D_FLAG | BIMM_FLAG | IMM_FLAG | \ |
| 280 | DRTI_FLAG | DRTE_FLAG | DRTB_FLAG) |
| 281 | #define MSR_TB_MASK (MSR_UM | MSR_VM | MSR_EE) |
| 282 | |
| 283 | uint32_t iflags; |
| 284 | |
| 285 | #if !defined(CONFIG_USER_ONLY) |
| 286 | /* Unified MMU. */ |
| 287 | MicroBlazeMMU mmu; |
| 288 | #endif |
| 289 | |
| 290 | /* Fields up to this point are cleared by a CPU reset */ |
| 291 | struct {} end_reset_fields; |
| 292 | |
| 293 | /* These fields are preserved on reset. */ |
| 294 | }; |
| 295 | |
| 296 | /* |
| 297 | * Microblaze Configuration Settings |
| 298 | * |
| 299 | * Note that the structure is sorted by type and size to minimize holes. |
| 300 | */ |
| 301 | typedef struct { |
| 302 | char *version; |
| 303 | |
| 304 | uint64_t addr_mask; |
| 305 | |
| 306 | uint32_t base_vectors; |
| 307 | uint32_t pvr_user2; |
| 308 | uint32_t pvr_regs[13]; |
| 309 | |
| 310 | uint8_t addr_size; |
| 311 | uint8_t use_fpu; |
| 312 | uint8_t use_hw_mul; |
| 313 | uint8_t pvr_user1; |
| 314 | uint8_t pvr; |
| 315 | uint8_t mmu; |
| 316 | uint8_t mmu_tlb_access; |
| 317 | uint8_t mmu_zones; |
| 318 | |
| 319 | bool stackprot; |
| 320 | bool use_barrel; |
| 321 | bool use_div; |
| 322 | bool use_msr_instr; |
| 323 | bool use_pcmp_instr; |
| 324 | bool use_mmu; |
| 325 | uint8_t use_non_secure; |
| 326 | bool dcache_writeback; |
| 327 | bool endi; |
| 328 | bool dopb_bus_exception; |
| 329 | bool iopb_bus_exception; |
| 330 | bool illegal_opcode_exception; |
| 331 | bool opcode_0_illegal; |
| 332 | bool div_zero_exception; |
| 333 | bool unaligned_exceptions; |
| 334 | } MicroBlazeCPUConfig; |
| 335 | |
| 336 | /** |
| 337 | * MicroBlazeCPU: |
| 338 | * @env: #CPUMBState |
| 339 | * |
| 340 | * A MicroBlaze CPU. |
| 341 | */ |
| 342 | struct ArchCPU { |
| 343 | CPUState parent_obj; |
| 344 | |
| 345 | CPUMBState env; |
| 346 | |
| 347 | bool ns_axi_dp; |
| 348 | bool ns_axi_ip; |
| 349 | bool ns_axi_dc; |
| 350 | bool ns_axi_ic; |
| 351 | |
| 352 | MicroBlazeCPUConfig cfg; |
| 353 | }; |
| 354 | |
| 355 | /** |
| 356 | * MicroBlazeCPUClass: |
| 357 | * @parent_realize: The parent class' realize handler. |
| 358 | * @parent_phases: The parent class' reset phase handlers. |
| 359 | * |
| 360 | * A MicroBlaze CPU model. |
| 361 | */ |
| 362 | struct MicroBlazeCPUClass { |
| 363 | CPUClass parent_class; |
| 364 | |
| 365 | DeviceRealize parent_realize; |
| 366 | ResettablePhases parent_phases; |
| 367 | }; |
| 368 | |
| 369 | #ifndef CONFIG_USER_ONLY |
| 370 | void mb_cpu_do_interrupt(CPUState *cs); |
| 371 | bool mb_cpu_exec_interrupt(CPUState *cs, int int_req); |
| 372 | bool mb_cpu_translate_for_debug(CPUState *cs, vaddr addr, |
| 373 | TranslateForDebugResult *result); |
| 374 | #endif /* !CONFIG_USER_ONLY */ |
| 375 | G_NORETURN void mb_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, |
| 376 | MMUAccessType access_type, |
| 377 | int mmu_idx, uintptr_t retaddr); |
| 378 | void mb_cpu_dump_state(CPUState *cpu, FILE *f, int flags); |
| 379 | int mb_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); |
| 380 | int mb_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); |
| 381 | int mb_cpu_gdb_read_stack_protect(CPUState *cs, GByteArray *buf, int reg); |
| 382 | int mb_cpu_gdb_write_stack_protect(CPUState *cs, uint8_t *buf, int reg); |
| 383 | |
| 384 | static inline uint32_t mb_cpu_read_msr(const CPUMBState *env) |
| 385 | { |
| 386 | /* Replicate MSR[C] to MSR[CC]. */ |
| 387 | return env->msr | (env->msr_c * (MSR_C | MSR_CC)); |
| 388 | } |
| 389 | |
| 390 | static inline void mb_cpu_write_msr(CPUMBState *env, uint32_t val) |
| 391 | { |
| 392 | env->msr_c = (val >> 2) & 1; |
| 393 | /* |
| 394 | * Clear both MSR[C] and MSR[CC] from the saved copy. |
| 395 | * MSR_PVR is not writable and is always clear. |
| 396 | */ |
| 397 | env->msr = val & ~(MSR_C | MSR_CC | MSR_PVR); |
| 398 | } |
| 399 | |
| 400 | void mb_tcg_init(void); |
| 401 | void mb_translate_code(CPUState *cs, TranslationBlock *tb, |
| 402 | int *max_insns, vaddr pc, void *host_pc); |
| 403 | |
| 404 | #define CPU_RESOLVING_TYPE TYPE_MICROBLAZE_CPU |
| 405 | |
| 406 | /* MMU modes definitions */ |
| 407 | #define MMU_NOMMU_IDX 0 |
| 408 | #define MMU_KERNEL_IDX 1 |
| 409 | #define MMU_USER_IDX 2 |
| 410 | /* See NB_MMU_MODES in cpu-defs.h. */ |
| 411 | |
| 412 | /* Ensure there is no overlap between the two masks. */ |
| 413 | QEMU_BUILD_BUG_ON(MSR_TB_MASK & IFLAGS_TB_MASK); |
| 414 | |
| 415 | #if !defined(CONFIG_USER_ONLY) |
| 416 | bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size, |
| 417 | MMUAccessType access_type, int mmu_idx, |
| 418 | bool probe, uintptr_t retaddr); |
| 419 | |
| 420 | void mb_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, |
| 421 | unsigned size, MMUAccessType access_type, |
| 422 | int mmu_idx, MemTxAttrs attrs, |
| 423 | MemTxResult response, uintptr_t retaddr); |
| 424 | #endif |
| 425 | |
| 426 | #ifndef CONFIG_USER_ONLY |
| 427 | extern const VMStateDescription vmstate_mb_cpu; |
| 428 | #endif |
| 429 | |
| 430 | #endif |