| 1 | /* |
| 2 | * MIPS emulation for qemu: CPU initialisation routines. |
| 3 | * |
| 4 | * Copyright (c) 2004-2005 Jocelyn Mayer |
| 5 | * Copyright (c) 2007 Herve Poussineau |
| 6 | * |
| 7 | * This library is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU Lesser General Public |
| 9 | * License as published by the Free Software Foundation; either |
| 10 | * version 2.1 of the License, or (at your option) any later version. |
| 11 | * |
| 12 | * This library is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 15 | * Lesser General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU Lesser General Public |
| 18 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
| 19 | */ |
| 20 | |
| 21 | /* CPU / CPU family specific config register values. */ |
| 22 | |
| 23 | /* Have config1, uncached coherency */ |
| 24 | #define MIPS_CONFIG0 \ |
| 25 | ((1U << CP0C0_M) | (0x2 << CP0C0_K0)) |
| 26 | |
| 27 | /* Have config2, no coprocessor2 attached, no MDMX support attached, |
| 28 | no performance counters, watch registers present, |
| 29 | no code compression, EJTAG present, no FPU */ |
| 30 | #define MIPS_CONFIG1 \ |
| 31 | ((1U << CP0C1_M) | \ |
| 32 | (0 << CP0C1_C2) | (0 << CP0C1_MD) | (0 << CP0C1_PC) | \ |
| 33 | (1 << CP0C1_WR) | (0 << CP0C1_CA) | (1 << CP0C1_EP) | \ |
| 34 | (0 << CP0C1_FP)) |
| 35 | |
| 36 | /* Have config3, no tertiary/secondary caches implemented */ |
| 37 | #define MIPS_CONFIG2 \ |
| 38 | ((1U << CP0C2_M)) |
| 39 | |
| 40 | /* No config4, no DSP ASE, no large physaddr (PABITS), |
| 41 | no external interrupt controller, no vectored interrupts, |
| 42 | no 1kb pages, no SmartMIPS ASE, no trace logic */ |
| 43 | #define MIPS_CONFIG3 \ |
| 44 | ((0 << CP0C3_M) | (0 << CP0C3_DSPP) | (0 << CP0C3_LPA) | \ |
| 45 | (0 << CP0C3_VEIC) | (0 << CP0C3_VInt) | (0 << CP0C3_SP) | \ |
| 46 | (0 << CP0C3_SM) | (0 << CP0C3_TL)) |
| 47 | |
| 48 | #define MIPS_CONFIG4 \ |
| 49 | ((0 << CP0C4_M)) |
| 50 | |
| 51 | #define MIPS_CONFIG5 \ |
| 52 | ((0 << CP0C5_M)) |
| 53 | |
| 54 | /*****************************************************************************/ |
| 55 | /* MIPS CPU definitions */ |
| 56 | const mips_def_t mips_defs[] = |
| 57 | { |
| 58 | { |
| 59 | .name = "4Kc", |
| 60 | .CP0_PRid = 0x00018000, |
| 61 | .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT), |
| 62 | .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) | |
| 63 | (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | |
| 64 | (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | |
| 65 | (0 << CP0C1_CA), |
| 66 | .CP0_Config2 = MIPS_CONFIG2, |
| 67 | .CP0_Config3 = MIPS_CONFIG3, |
| 68 | .CP0_LLAddr_rw_bitmask = 0, |
| 69 | .CP0_LLAddr_shift = 4, |
| 70 | .SYNCI_Step = 32, |
| 71 | .CCRes = 2, |
| 72 | .CP0_Status_rw_bitmask = 0x1278FF17, |
| 73 | .SEGBITS = 32, |
| 74 | .PABITS = 32, |
| 75 | .insn_flags = CPU_MIPS32R1, |
| 76 | .mmu_type = MMU_TYPE_R4000, |
| 77 | }, |
| 78 | { |
| 79 | .name = "4Km", |
| 80 | .CP0_PRid = 0x00018300, |
| 81 | /* Config1 implemented, fixed mapping MMU, |
| 82 | no virtual icache, uncached coherency. */ |
| 83 | .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_FMT << CP0C0_MT), |
| 84 | .CP0_Config1 = MIPS_CONFIG1 | |
| 85 | (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | |
| 86 | (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | |
| 87 | (1 << CP0C1_CA), |
| 88 | .CP0_Config2 = MIPS_CONFIG2, |
| 89 | .CP0_Config3 = MIPS_CONFIG3, |
| 90 | .CP0_LLAddr_rw_bitmask = 0, |
| 91 | .CP0_LLAddr_shift = 4, |
| 92 | .SYNCI_Step = 32, |
| 93 | .CCRes = 2, |
| 94 | .CP0_Status_rw_bitmask = 0x1258FF17, |
| 95 | .SEGBITS = 32, |
| 96 | .PABITS = 32, |
| 97 | .insn_flags = CPU_MIPS32R1 | ASE_MIPS16, |
| 98 | .mmu_type = MMU_TYPE_FMT, |
| 99 | }, |
| 100 | { |
| 101 | .name = "4KEcR1", |
| 102 | .CP0_PRid = 0x00018400, |
| 103 | .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT), |
| 104 | .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) | |
| 105 | (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | |
| 106 | (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | |
| 107 | (0 << CP0C1_CA), |
| 108 | .CP0_Config2 = MIPS_CONFIG2, |
| 109 | .CP0_Config3 = MIPS_CONFIG3, |
| 110 | .CP0_LLAddr_rw_bitmask = 0, |
| 111 | .CP0_LLAddr_shift = 4, |
| 112 | .SYNCI_Step = 32, |
| 113 | .CCRes = 2, |
| 114 | .CP0_Status_rw_bitmask = 0x1278FF17, |
| 115 | .SEGBITS = 32, |
| 116 | .PABITS = 32, |
| 117 | .insn_flags = CPU_MIPS32R1, |
| 118 | .mmu_type = MMU_TYPE_R4000, |
| 119 | }, |
| 120 | { |
| 121 | .name = "XBurstR1", |
| 122 | .CP0_PRid = 0x1ed0024f, |
| 123 | .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT), |
| 124 | .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) | |
| 125 | (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | |
| 126 | (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | |
| 127 | (0 << CP0C1_CA), |
| 128 | .CP0_Config2 = MIPS_CONFIG2, |
| 129 | .CP0_Config3 = MIPS_CONFIG3, |
| 130 | .CP0_LLAddr_rw_bitmask = 0, |
| 131 | .CP0_LLAddr_shift = 4, |
| 132 | .SYNCI_Step = 32, |
| 133 | .CCRes = 2, |
| 134 | .CP0_Status_rw_bitmask = 0x1278FF17, |
| 135 | .SEGBITS = 32, |
| 136 | .PABITS = 32, |
| 137 | .insn_flags = CPU_MIPS32R1 | ASE_MXU, |
| 138 | .mmu_type = MMU_TYPE_R4000, |
| 139 | }, |
| 140 | { |
| 141 | .name = "4KEmR1", |
| 142 | .CP0_PRid = 0x00018500, |
| 143 | .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_FMT << CP0C0_MT), |
| 144 | .CP0_Config1 = MIPS_CONFIG1 | |
| 145 | (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | |
| 146 | (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | |
| 147 | (1 << CP0C1_CA), |
| 148 | .CP0_Config2 = MIPS_CONFIG2, |
| 149 | .CP0_Config3 = MIPS_CONFIG3, |
| 150 | .CP0_LLAddr_rw_bitmask = 0, |
| 151 | .CP0_LLAddr_shift = 4, |
| 152 | .SYNCI_Step = 32, |
| 153 | .CCRes = 2, |
| 154 | .CP0_Status_rw_bitmask = 0x1258FF17, |
| 155 | .SEGBITS = 32, |
| 156 | .PABITS = 32, |
| 157 | .insn_flags = CPU_MIPS32R1 | ASE_MIPS16, |
| 158 | .mmu_type = MMU_TYPE_FMT, |
| 159 | }, |
| 160 | { |
| 161 | .name = "4KEc", |
| 162 | .CP0_PRid = 0x00019000, |
| 163 | .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | |
| 164 | (MMU_TYPE_R4000 << CP0C0_MT), |
| 165 | .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) | |
| 166 | (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | |
| 167 | (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | |
| 168 | (0 << CP0C1_CA), |
| 169 | .CP0_Config2 = MIPS_CONFIG2, |
| 170 | .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt), |
| 171 | .CP0_LLAddr_rw_bitmask = 0, |
| 172 | .CP0_LLAddr_shift = 4, |
| 173 | .SYNCI_Step = 32, |
| 174 | .CCRes = 2, |
| 175 | .CP0_Status_rw_bitmask = 0x1278FF17, |
| 176 | .SEGBITS = 32, |
| 177 | .PABITS = 32, |
| 178 | .insn_flags = CPU_MIPS32R2, |
| 179 | .mmu_type = MMU_TYPE_R4000, |
| 180 | }, |
| 181 | { |
| 182 | .name = "4KEm", |
| 183 | .CP0_PRid = 0x00019100, |
| 184 | .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | |
| 185 | (MMU_TYPE_FMT << CP0C0_MT), |
| 186 | .CP0_Config1 = MIPS_CONFIG1 | |
| 187 | (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | |
| 188 | (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | |
| 189 | (1 << CP0C1_CA), |
| 190 | .CP0_Config2 = MIPS_CONFIG2, |
| 191 | .CP0_Config3 = MIPS_CONFIG3, |
| 192 | .CP0_LLAddr_rw_bitmask = 0, |
| 193 | .CP0_LLAddr_shift = 4, |
| 194 | .SYNCI_Step = 32, |
| 195 | .CCRes = 2, |
| 196 | .CP0_Status_rw_bitmask = 0x1258FF17, |
| 197 | .SEGBITS = 32, |
| 198 | .PABITS = 32, |
| 199 | .insn_flags = CPU_MIPS32R2 | ASE_MIPS16, |
| 200 | .mmu_type = MMU_TYPE_FMT, |
| 201 | }, |
| 202 | { |
| 203 | .name = "24Kc", |
| 204 | .CP0_PRid = 0x00019300, |
| 205 | .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | |
| 206 | (MMU_TYPE_R4000 << CP0C0_MT), |
| 207 | .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) | |
| 208 | (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | |
| 209 | (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | |
| 210 | (1 << CP0C1_CA), |
| 211 | .CP0_Config2 = MIPS_CONFIG2, |
| 212 | .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt), |
| 213 | .CP0_LLAddr_rw_bitmask = 0, |
| 214 | .CP0_LLAddr_shift = 4, |
| 215 | .SYNCI_Step = 32, |
| 216 | .CCRes = 2, |
| 217 | /* No DSP implemented. */ |
| 218 | .CP0_Status_rw_bitmask = 0x1278FF1F, |
| 219 | .SEGBITS = 32, |
| 220 | .PABITS = 32, |
| 221 | .insn_flags = CPU_MIPS32R2 | ASE_MIPS16, |
| 222 | .mmu_type = MMU_TYPE_R4000, |
| 223 | }, |
| 224 | { |
| 225 | .name = "24KEc", |
| 226 | .CP0_PRid = 0x00019600, |
| 227 | .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | |
| 228 | (MMU_TYPE_R4000 << CP0C0_MT), |
| 229 | .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) | |
| 230 | (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | |
| 231 | (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | |
| 232 | (1 << CP0C1_CA), |
| 233 | .CP0_Config2 = MIPS_CONFIG2, |
| 234 | .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_DSPP) | (0 << CP0C3_VInt), |
| 235 | .CP0_LLAddr_rw_bitmask = 0, |
| 236 | .CP0_LLAddr_shift = 4, |
| 237 | .SYNCI_Step = 32, |
| 238 | .CCRes = 2, |
| 239 | /* we have a DSP, but no FPU */ |
| 240 | .CP0_Status_rw_bitmask = 0x1378FF1F, |
| 241 | .SEGBITS = 32, |
| 242 | .PABITS = 32, |
| 243 | .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP, |
| 244 | .mmu_type = MMU_TYPE_R4000, |
| 245 | }, |
| 246 | { |
| 247 | .name = "24Kf", |
| 248 | .CP0_PRid = 0x00019300, |
| 249 | .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | |
| 250 | (MMU_TYPE_R4000 << CP0C0_MT), |
| 251 | .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) | |
| 252 | (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | |
| 253 | (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | |
| 254 | (1 << CP0C1_CA), |
| 255 | .CP0_Config2 = MIPS_CONFIG2, |
| 256 | .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt), |
| 257 | .CP0_LLAddr_rw_bitmask = 0, |
| 258 | .CP0_LLAddr_shift = 4, |
| 259 | .SYNCI_Step = 32, |
| 260 | .CCRes = 2, |
| 261 | /* No DSP implemented. */ |
| 262 | .CP0_Status_rw_bitmask = 0x3678FF1F, |
| 263 | .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) | |
| 264 | (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID), |
| 265 | .CP1_fcr31 = 0, |
| 266 | .CP1_fcr31_rw_bitmask = 0xFF83FFFF, |
| 267 | .SEGBITS = 32, |
| 268 | .PABITS = 32, |
| 269 | .insn_flags = CPU_MIPS32R2 | ASE_MIPS16, |
| 270 | .mmu_type = MMU_TYPE_R4000, |
| 271 | }, |
| 272 | { |
| 273 | .name = "34Kf", |
| 274 | .CP0_PRid = 0x00019500, |
| 275 | .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | |
| 276 | (MMU_TYPE_R4000 << CP0C0_MT), |
| 277 | .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) | |
| 278 | (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | |
| 279 | (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | |
| 280 | (1 << CP0C1_CA), |
| 281 | .CP0_Config2 = MIPS_CONFIG2, |
| 282 | .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_VInt) | (1 << CP0C3_MT) | |
| 283 | (1 << CP0C3_DSPP), |
| 284 | .CP0_LLAddr_rw_bitmask = 0, |
| 285 | .CP0_LLAddr_shift = 0, |
| 286 | .SYNCI_Step = 32, |
| 287 | .CCRes = 2, |
| 288 | .CP0_Status_rw_bitmask = 0x3778FF1F, |
| 289 | .CP0_TCStatus_rw_bitmask = (0 << CP0TCSt_TCU3) | (0 << CP0TCSt_TCU2) | |
| 290 | (1 << CP0TCSt_TCU1) | (1 << CP0TCSt_TCU0) | |
| 291 | (0 << CP0TCSt_TMX) | (1 << CP0TCSt_DT) | |
| 292 | (1 << CP0TCSt_DA) | (1 << CP0TCSt_A) | |
| 293 | (0x3 << CP0TCSt_TKSU) | (1 << CP0TCSt_IXMT) | |
| 294 | (0xff << CP0TCSt_TASID), |
| 295 | .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) | |
| 296 | (1 << FCR0_D) | (1 << FCR0_S) | (0x95 << FCR0_PRID), |
| 297 | .CP1_fcr31 = 0, |
| 298 | .CP1_fcr31_rw_bitmask = 0xFF83FFFF, |
| 299 | .CP0_SRSCtl = (0xf << CP0SRSCtl_HSS), |
| 300 | .CP0_SRSConf0_rw_bitmask = 0x3fffffff, |
| 301 | .CP0_SRSConf0 = (1U << CP0SRSC0_M) | (0x3fe << CP0SRSC0_SRS3) | |
| 302 | (0x3fe << CP0SRSC0_SRS2) | (0x3fe << CP0SRSC0_SRS1), |
| 303 | .CP0_SRSConf1_rw_bitmask = 0x3fffffff, |
| 304 | .CP0_SRSConf1 = (1U << CP0SRSC1_M) | (0x3fe << CP0SRSC1_SRS6) | |
| 305 | (0x3fe << CP0SRSC1_SRS5) | (0x3fe << CP0SRSC1_SRS4), |
| 306 | .CP0_SRSConf2_rw_bitmask = 0x3fffffff, |
| 307 | .CP0_SRSConf2 = (1U << CP0SRSC2_M) | (0x3fe << CP0SRSC2_SRS9) | |
| 308 | (0x3fe << CP0SRSC2_SRS8) | (0x3fe << CP0SRSC2_SRS7), |
| 309 | .CP0_SRSConf3_rw_bitmask = 0x3fffffff, |
| 310 | .CP0_SRSConf3 = (1U << CP0SRSC3_M) | (0x3fe << CP0SRSC3_SRS12) | |
| 311 | (0x3fe << CP0SRSC3_SRS11) | (0x3fe << CP0SRSC3_SRS10), |
| 312 | .CP0_SRSConf4_rw_bitmask = 0x3fffffff, |
| 313 | .CP0_SRSConf4 = (0x3fe << CP0SRSC4_SRS15) | |
| 314 | (0x3fe << CP0SRSC4_SRS14) | (0x3fe << CP0SRSC4_SRS13), |
| 315 | .SEGBITS = 32, |
| 316 | .PABITS = 32, |
| 317 | .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP, |
| 318 | .mmu_type = MMU_TYPE_R4000, |
| 319 | }, |
| 320 | { |
| 321 | .name = "74Kf", |
| 322 | .CP0_PRid = 0x00019700, |
| 323 | .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | |
| 324 | (MMU_TYPE_R4000 << CP0C0_MT), |
| 325 | .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) | |
| 326 | (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | |
| 327 | (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | |
| 328 | (1 << CP0C1_CA), |
| 329 | .CP0_Config2 = MIPS_CONFIG2, |
| 330 | .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_DSP2P) | (1 << CP0C3_DSPP) | |
| 331 | (1 << CP0C3_VInt), |
| 332 | .CP0_LLAddr_rw_bitmask = 0, |
| 333 | .CP0_LLAddr_shift = 4, |
| 334 | .SYNCI_Step = 32, |
| 335 | .CCRes = 2, |
| 336 | .CP0_Status_rw_bitmask = 0x3778FF1F, |
| 337 | .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) | |
| 338 | (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID), |
| 339 | .CP1_fcr31 = 0, |
| 340 | .CP1_fcr31_rw_bitmask = 0xFF83FFFF, |
| 341 | .SEGBITS = 32, |
| 342 | .PABITS = 32, |
| 343 | .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_DSP_R2, |
| 344 | .mmu_type = MMU_TYPE_R4000, |
| 345 | }, |
| 346 | { |
| 347 | .name = "XBurstR2", |
| 348 | .CP0_PRid = 0x2ed1024f, |
| 349 | .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | |
| 350 | (MMU_TYPE_R4000 << CP0C0_MT), |
| 351 | .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) | |
| 352 | (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | |
| 353 | (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | |
| 354 | (1 << CP0C1_CA), |
| 355 | .CP0_Config2 = MIPS_CONFIG2, |
| 356 | .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_DSP2P) | (1 << CP0C3_DSPP) | |
| 357 | (1 << CP0C3_VInt), |
| 358 | .CP0_LLAddr_rw_bitmask = 0, |
| 359 | .CP0_LLAddr_shift = 4, |
| 360 | .SYNCI_Step = 32, |
| 361 | .CCRes = 2, |
| 362 | .CP0_Status_rw_bitmask = 0x3778FF1F, |
| 363 | .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) | |
| 364 | (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID), |
| 365 | .CP1_fcr31 = 0, |
| 366 | .CP1_fcr31_rw_bitmask = 0xFF83FFFF, |
| 367 | .SEGBITS = 32, |
| 368 | .PABITS = 32, |
| 369 | .insn_flags = CPU_MIPS32R2 | ASE_MXU, |
| 370 | .mmu_type = MMU_TYPE_R4000, |
| 371 | }, |
| 372 | { |
| 373 | .name = "M14K", |
| 374 | .CP0_PRid = 0x00019b00, |
| 375 | /* Config1 implemented, fixed mapping MMU, |
| 376 | no virtual icache, uncached coherency. */ |
| 377 | .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_KU) | (0x2 << CP0C0_K23) | |
| 378 | (0x1 << CP0C0_AR) | (MMU_TYPE_FMT << CP0C0_MT), |
| 379 | .CP0_Config1 = MIPS_CONFIG1, |
| 380 | .CP0_Config2 = MIPS_CONFIG2, |
| 381 | .CP0_Config3 = MIPS_CONFIG3 | (0x2 << CP0C3_ISA) | (1 << CP0C3_VInt) | |
| 382 | (1 << CP0C3_M), |
| 383 | .CP0_Config4 = MIPS_CONFIG4 | (1 << CP0C4_M), |
| 384 | .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_NFExists), |
| 385 | .CP0_Config7 = 1 << CP0C7_WII, |
| 386 | .CP0_LLAddr_rw_bitmask = 0, |
| 387 | .CP0_LLAddr_shift = 4, |
| 388 | .SYNCI_Step = 32, |
| 389 | .CCRes = 2, |
| 390 | .CP0_Status_rw_bitmask = 0x1258FF17, |
| 391 | .SEGBITS = 32, |
| 392 | .PABITS = 32, |
| 393 | .insn_flags = CPU_MIPS32R2 | ASE_MICROMIPS, |
| 394 | .mmu_type = MMU_TYPE_FMT, |
| 395 | }, |
| 396 | { |
| 397 | .name = "M14Kc", |
| 398 | /* This is the TLB-based MMU core. */ |
| 399 | .CP0_PRid = 0x00019c00, |
| 400 | .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | |
| 401 | (MMU_TYPE_R4000 << CP0C0_MT), |
| 402 | .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) | |
| 403 | (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | |
| 404 | (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA), |
| 405 | .CP0_Config2 = MIPS_CONFIG2, |
| 406 | .CP0_Config3 = MIPS_CONFIG3 | (0x2 << CP0C3_ISA) | (0 << CP0C3_VInt) | |
| 407 | (1 << CP0C3_M), |
| 408 | .CP0_Config4 = MIPS_CONFIG4 | (1 << CP0C4_M), |
| 409 | .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_NFExists), |
| 410 | .CP0_Config7 = 1 << CP0C7_WII, |
| 411 | .CP0_LLAddr_rw_bitmask = 0, |
| 412 | .CP0_LLAddr_shift = 4, |
| 413 | .SYNCI_Step = 32, |
| 414 | .CCRes = 2, |
| 415 | .CP0_Status_rw_bitmask = 0x1278FF17, |
| 416 | .SEGBITS = 32, |
| 417 | .PABITS = 32, |
| 418 | .insn_flags = CPU_MIPS32R2 | ASE_MICROMIPS, |
| 419 | .mmu_type = MMU_TYPE_R4000, |
| 420 | }, |
| 421 | { |
| 422 | /* FIXME: |
| 423 | * Config3: VZ, CTXTC, CDMM, TL |
| 424 | * Config4: MMUExtDef |
| 425 | * Config5: MRP |
| 426 | * */ |
| 427 | .name = "P5600", |
| 428 | .CP0_PRid = 0x0001A800, |
| 429 | .CP0_Config0 = MIPS_CONFIG0 | (1 << CP0C0_MM) | (1 << CP0C0_AR) | |
| 430 | (MMU_TYPE_R4000 << CP0C0_MT), |
| 431 | .CP0_Config1 = MIPS_CONFIG1 | (0x3F << CP0C1_MMU) | |
| 432 | (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) | |
| 433 | (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) | |
| 434 | (1 << CP0C1_PC) | (1 << CP0C1_FP), |
| 435 | .CP0_Config2 = MIPS_CONFIG2, |
| 436 | .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | |
| 437 | (1 << CP0C3_CMGCR) | (1 << CP0C3_MSAP) | |
| 438 | (1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_SC) | |
| 439 | (1 << CP0C3_PW) | (1 << CP0C3_ULRI) | (1 << CP0C3_RXI) | |
| 440 | (1 << CP0C3_LPA) | (1 << CP0C3_VInt), |
| 441 | .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (2 << CP0C4_IE) | |
| 442 | (0x1c << CP0C4_KScrExist), |
| 443 | .CP0_Config4_rw_bitmask = 0, |
| 444 | .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_EVA) | (1 << CP0C5_MVH) | |
| 445 | (1 << CP0C5_LLB) | (1 << CP0C5_MRP), |
| 446 | .CP0_Config5_rw_bitmask = (1 << CP0C5_K) | (1 << CP0C5_CV) | |
| 447 | (1 << CP0C5_MSAEn) | (1 << CP0C5_UFE) | |
| 448 | (1 << CP0C5_FRE) | (1 << CP0C5_UFR), |
| 449 | .CP0_Config7 = 1 << CP0C7_WII, |
| 450 | .CP0_LLAddr_rw_bitmask = 0, |
| 451 | .CP0_LLAddr_shift = 0, |
| 452 | .SYNCI_Step = 32, |
| 453 | .CCRes = 2, |
| 454 | .CP0_Status_rw_bitmask = 0x3C68FF1F, |
| 455 | .CP0_PageGrain_rw_bitmask = (1U << CP0PG_RIE) | (1 << CP0PG_XIE) | |
| 456 | (1 << CP0PG_ELPA) | (1 << CP0PG_IEC), |
| 457 | .CP0_EBaseWG_rw_bitmask = (1 << CP0EBase_WG), |
| 458 | .CP1_fcr0 = (1 << FCR0_FREP) | (1 << FCR0_UFRP) | (1 << FCR0_HAS2008) | |
| 459 | (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) | |
| 460 | (1 << FCR0_D) | (1 << FCR0_S) | (0x03 << FCR0_PRID), |
| 461 | .CP1_fcr31 = (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008), |
| 462 | .CP1_fcr31_rw_bitmask = 0xFF83FFFF, |
| 463 | .SEGBITS = 32, |
| 464 | .PABITS = 40, |
| 465 | .insn_flags = CPU_MIPS32R5, |
| 466 | .mmu_type = MMU_TYPE_R4000, |
| 467 | }, |
| 468 | { |
| 469 | /* A generic CPU supporting MIPS32 Release 6 ISA. |
| 470 | FIXME: Support IEEE 754-2008 FP. |
| 471 | Eventually this should be replaced by a real CPU model. */ |
| 472 | .name = "mips32r6-generic", |
| 473 | .CP0_PRid = 0x00010000, |
| 474 | .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AR) | |
| 475 | (MMU_TYPE_R4000 << CP0C0_MT), |
| 476 | .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (31 << CP0C1_MMU) | |
| 477 | (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) | |
| 478 | (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) | |
| 479 | (0 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), |
| 480 | .CP0_Config2 = MIPS_CONFIG2, |
| 481 | .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_MSAP) | |
| 482 | (1 << CP0C3_BP) | (1 << CP0C3_BI) | |
| 483 | (2 << CP0C3_ISA) | (1 << CP0C3_ULRI) | |
| 484 | (1 << CP0C3_RXI) | (1U << CP0C3_M), |
| 485 | .CP0_Config4 = MIPS_CONFIG4 | (0xfc << CP0C4_KScrExist) | |
| 486 | (3 << CP0C4_IE) | (1U << CP0C4_M), |
| 487 | .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_XNP) | (1 << CP0C5_LLB), |
| 488 | .CP0_Config5_rw_bitmask = (1 << CP0C5_MSAEn) | (1 << CP0C5_UFE) | |
| 489 | (1 << CP0C5_FRE) | (1 << CP0C5_SBRI), |
| 490 | .CP0_LLAddr_rw_bitmask = 0, |
| 491 | .CP0_LLAddr_shift = 0, |
| 492 | .SYNCI_Step = 32, |
| 493 | .CCRes = 2, |
| 494 | .CP0_Status_rw_bitmask = 0x3058FF1F, |
| 495 | .CP0_PageGrain = (1 << CP0PG_IEC) | (1 << CP0PG_XIE) | |
| 496 | (1U << CP0PG_RIE), |
| 497 | .CP0_PageGrain_rw_bitmask = 0, |
| 498 | .CP1_fcr0 = (1 << FCR0_FREP) | (1 << FCR0_HAS2008) | (1 << FCR0_F64) | |
| 499 | (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) | |
| 500 | (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV), |
| 501 | .CP1_fcr31 = (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008), |
| 502 | .CP1_fcr31_rw_bitmask = 0x0103FFFF, |
| 503 | .MSAIR = 0x03 << MSAIR_ProcID, |
| 504 | .SEGBITS = 32, |
| 505 | .PABITS = 32, |
| 506 | .insn_flags = CPU_MIPS32R6 | ASE_MICROMIPS, |
| 507 | .mmu_type = MMU_TYPE_R4000, |
| 508 | }, |
| 509 | { |
| 510 | .name = "I7200", |
| 511 | .CP0_PRid = 0x00010000, |
| 512 | .CP0_Config0 = MIPS_CONFIG0 | (1 << CP0C0_MM) | (0x2 << CP0C0_AR) | |
| 513 | (MMU_TYPE_R4000 << CP0C0_MT), |
| 514 | .CP0_Config1 = (1U << CP0C1_M) | (15 << CP0C1_MMU) | (2 << CP0C1_IS) | |
| 515 | (4 << CP0C1_IL) | (3 << CP0C1_IA) | (2 << CP0C1_DS) | |
| 516 | (4 << CP0C1_DL) | (3 << CP0C1_DA) | (1 << CP0C1_PC) | |
| 517 | (1 << CP0C1_EP), |
| 518 | .CP0_Config2 = MIPS_CONFIG2, |
| 519 | .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_CMGCR) | |
| 520 | (1 << CP0C3_BI) | (1 << CP0C3_SC) | (3 << CP0C3_MMAR) | |
| 521 | (1 << CP0C3_ISA_ON_EXC) | (1 << CP0C3_ISA) | |
| 522 | (1 << CP0C3_ULRI) | (1 << CP0C3_RXI) | |
| 523 | (1 << CP0C3_DSP2P) | (1 << CP0C3_DSPP) | |
| 524 | (1 << CP0C3_CTXTC) | (1 << CP0C3_VInt) | |
| 525 | (1 << CP0C3_CDMM) | (1 << CP0C3_MT) | (1 << CP0C3_TL), |
| 526 | .CP0_Config4 = MIPS_CONFIG4 | (0xfc << CP0C4_KScrExist) | |
| 527 | (2 << CP0C4_IE) | (1U << CP0C4_M), |
| 528 | .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_MVH) | (1 << CP0C5_LLB), |
| 529 | .CP0_Config5_rw_bitmask = (1 << CP0C5_SBRI) | (1 << CP0C5_FRE) | |
| 530 | (1 << CP0C5_UFE), |
| 531 | .CP0_LLAddr_rw_bitmask = 0, |
| 532 | .CP0_LLAddr_shift = 0, |
| 533 | .SYNCI_Step = 32, |
| 534 | .CCRes = 2, |
| 535 | .CP0_Status_rw_bitmask = 0x3158FF1F, |
| 536 | .CP0_PageGrain = (1 << CP0PG_IEC) | (1 << CP0PG_XIE) | |
| 537 | (1U << CP0PG_RIE), |
| 538 | .CP0_PageGrain_rw_bitmask = 0, |
| 539 | .CP1_fcr0 = (1 << FCR0_FREP) | (1 << FCR0_HAS2008) | (1 << FCR0_F64) | |
| 540 | (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) | |
| 541 | (1 << FCR0_S) | (0x02 << FCR0_PRID) | (0x0 << FCR0_REV), |
| 542 | .CP1_fcr31 = (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008), |
| 543 | .SEGBITS = 32, |
| 544 | .PABITS = 32, |
| 545 | .insn_flags = CPU_MIPS32R6 | ISA_NANOMIPS32 | |
| 546 | ASE_DSP | ASE_DSP_R2 | ASE_DSP_R3, |
| 547 | .mmu_type = MMU_TYPE_R4000, |
| 548 | }, |
| 549 | #if defined(TARGET_MIPS64) |
| 550 | { |
| 551 | .name = "R4000", |
| 552 | .CP0_PRid = 0x00000400, |
| 553 | /* No L2 cache, icache size 8k, dcache size 8k, uncached coherency. */ |
| 554 | .CP0_Config0 = (2 << CP0C0_Impl) | (1 << CP0C0_IC) | (1 << CP0C0_DC) | |
| 555 | (2 << CP0C0_K0), |
| 556 | /* Note: Config1 is only used internally, the R4000 has only Config0. */ |
| 557 | .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU), |
| 558 | .CP0_LLAddr_rw_bitmask = 0xFFFFFFFF, |
| 559 | .CP0_LLAddr_shift = 4, |
| 560 | .SYNCI_Step = 16, |
| 561 | .CCRes = 2, |
| 562 | .CP0_Status_rw_bitmask = 0x3678FFFF, |
| 563 | /* The R4000 has a full 64bit FPU but doesn't use the fcr0 bits. */ |
| 564 | .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x0 << FCR0_REV), |
| 565 | .CP1_fcr31 = 0, |
| 566 | .CP1_fcr31_rw_bitmask = 0x0183FFFF, |
| 567 | .SEGBITS = 40, |
| 568 | .PABITS = 36, |
| 569 | .insn_flags = CPU_MIPS3, |
| 570 | .mmu_type = MMU_TYPE_R4000, |
| 571 | }, |
| 572 | { |
| 573 | .name = "VR5432", |
| 574 | .CP0_PRid = 0x00005400, |
| 575 | /* No L2 cache, icache size 8k, dcache size 8k, uncached coherency. */ |
| 576 | .CP0_Config0 = (2 << CP0C0_Impl) | (1 << CP0C0_IC) | (1 << CP0C0_DC) | |
| 577 | (2 << CP0C0_K0), |
| 578 | .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU), |
| 579 | .CP0_LLAddr_rw_bitmask = 0xFFFFFFFFL, |
| 580 | .CP0_LLAddr_shift = 4, |
| 581 | .SYNCI_Step = 16, |
| 582 | .CCRes = 2, |
| 583 | .CP0_Status_rw_bitmask = 0x3678FFFF, |
| 584 | /* The VR5432 has a full 64bit FPU but doesn't use the fcr0 bits. */ |
| 585 | .CP1_fcr0 = (0x54 << FCR0_PRID) | (0x0 << FCR0_REV), |
| 586 | .CP1_fcr31 = 0, |
| 587 | .CP1_fcr31_rw_bitmask = 0xFF83FFFF, |
| 588 | .SEGBITS = 40, |
| 589 | .PABITS = 32, |
| 590 | .insn_flags = CPU_MIPS4 | INSN_VR54XX, |
| 591 | .mmu_type = MMU_TYPE_R4000, |
| 592 | }, |
| 593 | { |
| 594 | .name = "5Kc", |
| 595 | .CP0_PRid = 0x00018100, |
| 596 | .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) | |
| 597 | (MMU_TYPE_R4000 << CP0C0_MT), |
| 598 | .CP0_Config1 = MIPS_CONFIG1 | (31 << CP0C1_MMU) | |
| 599 | (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) | |
| 600 | (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) | |
| 601 | (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), |
| 602 | .CP0_Config2 = MIPS_CONFIG2, |
| 603 | .CP0_Config3 = MIPS_CONFIG3, |
| 604 | .CP0_LLAddr_rw_bitmask = 0, |
| 605 | .CP0_LLAddr_shift = 4, |
| 606 | .SYNCI_Step = 32, |
| 607 | .CCRes = 2, |
| 608 | .CP0_Status_rw_bitmask = 0x12F8FFFF, |
| 609 | .SEGBITS = 42, |
| 610 | .PABITS = 36, |
| 611 | .insn_flags = CPU_MIPS64R1, |
| 612 | .mmu_type = MMU_TYPE_R4000, |
| 613 | }, |
| 614 | { |
| 615 | .name = "5Kf", |
| 616 | .CP0_PRid = 0x00018100, |
| 617 | .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) | |
| 618 | (MMU_TYPE_R4000 << CP0C0_MT), |
| 619 | .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (31 << CP0C1_MMU) | |
| 620 | (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) | |
| 621 | (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) | |
| 622 | (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), |
| 623 | .CP0_Config2 = MIPS_CONFIG2, |
| 624 | .CP0_Config3 = MIPS_CONFIG3, |
| 625 | .CP0_LLAddr_rw_bitmask = 0, |
| 626 | .CP0_LLAddr_shift = 4, |
| 627 | .SYNCI_Step = 32, |
| 628 | .CCRes = 2, |
| 629 | .CP0_Status_rw_bitmask = 0x36F8FFFF, |
| 630 | /* The 5Kf has F64 / L / W but doesn't use the fcr0 bits. */ |
| 631 | .CP1_fcr0 = (1 << FCR0_D) | (1 << FCR0_S) | |
| 632 | (0x81 << FCR0_PRID) | (0x0 << FCR0_REV), |
| 633 | .CP1_fcr31 = 0, |
| 634 | .CP1_fcr31_rw_bitmask = 0xFF83FFFF, |
| 635 | .SEGBITS = 42, |
| 636 | .PABITS = 36, |
| 637 | .insn_flags = CPU_MIPS64R1, |
| 638 | .mmu_type = MMU_TYPE_R4000, |
| 639 | }, |
| 640 | { |
| 641 | .name = "20Kc", |
| 642 | /* We emulate a later version of the 20Kc, earlier ones had a broken |
| 643 | WAIT instruction. */ |
| 644 | .CP0_PRid = 0x000182a0, |
| 645 | .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) | |
| 646 | (MMU_TYPE_R4000 << CP0C0_MT) | (1 << CP0C0_VI), |
| 647 | .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (47 << CP0C1_MMU) | |
| 648 | (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) | |
| 649 | (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) | |
| 650 | (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), |
| 651 | .CP0_Config2 = MIPS_CONFIG2, |
| 652 | .CP0_Config3 = MIPS_CONFIG3, |
| 653 | .CP0_LLAddr_rw_bitmask = 0, |
| 654 | .CP0_LLAddr_shift = 0, |
| 655 | .SYNCI_Step = 32, |
| 656 | .CCRes = 1, |
| 657 | .CP0_Status_rw_bitmask = 0x36FBFFFF, |
| 658 | /* The 20Kc has F64 / L / W but doesn't use the fcr0 bits. */ |
| 659 | .CP1_fcr0 = (1 << FCR0_3D) | (1 << FCR0_PS) | |
| 660 | (1 << FCR0_D) | (1 << FCR0_S) | |
| 661 | (0x82 << FCR0_PRID) | (0x0 << FCR0_REV), |
| 662 | .CP1_fcr31 = 0, |
| 663 | .CP1_fcr31_rw_bitmask = 0xFF83FFFF, |
| 664 | .SEGBITS = 40, |
| 665 | .PABITS = 36, |
| 666 | .insn_flags = CPU_MIPS64R1, |
| 667 | .mmu_type = MMU_TYPE_R4000, |
| 668 | }, |
| 669 | { |
| 670 | /* A generic CPU providing MIPS64 Release 2 features. |
| 671 | FIXME: Eventually this should be replaced by a real CPU model. */ |
| 672 | .name = "MIPS64R2-generic", |
| 673 | .CP0_PRid = 0x00010000, |
| 674 | .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) | |
| 675 | (MMU_TYPE_R4000 << CP0C0_MT), |
| 676 | .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) | |
| 677 | (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) | |
| 678 | (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) | |
| 679 | (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), |
| 680 | .CP0_Config2 = MIPS_CONFIG2, |
| 681 | .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA), |
| 682 | .CP0_LLAddr_rw_bitmask = 0, |
| 683 | .CP0_LLAddr_shift = 0, |
| 684 | .SYNCI_Step = 32, |
| 685 | .CCRes = 2, |
| 686 | .CP0_Status_rw_bitmask = 0x36FBFFFF, |
| 687 | .CP0_EBaseWG_rw_bitmask = (1 << CP0EBase_WG), |
| 688 | .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_3D) | (1 << FCR0_PS) | |
| 689 | (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) | |
| 690 | (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV), |
| 691 | .CP1_fcr31 = 0, |
| 692 | .CP1_fcr31_rw_bitmask = 0xFF83FFFF, |
| 693 | .SEGBITS = 42, |
| 694 | .PABITS = 36, |
| 695 | .insn_flags = CPU_MIPS64R2, |
| 696 | .mmu_type = MMU_TYPE_R4000, |
| 697 | }, |
| 698 | { |
| 699 | .name = "5KEc", |
| 700 | .CP0_PRid = 0x00018900, |
| 701 | .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) | |
| 702 | (MMU_TYPE_R4000 << CP0C0_MT), |
| 703 | .CP0_Config1 = MIPS_CONFIG1 | (31 << CP0C1_MMU) | |
| 704 | (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) | |
| 705 | (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) | |
| 706 | (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), |
| 707 | .CP0_Config2 = MIPS_CONFIG2, |
| 708 | .CP0_Config3 = MIPS_CONFIG3, |
| 709 | .CP0_LLAddr_rw_bitmask = 0, |
| 710 | .CP0_LLAddr_shift = 4, |
| 711 | .SYNCI_Step = 32, |
| 712 | .CCRes = 2, |
| 713 | .CP0_Status_rw_bitmask = 0x12F8FFFF, |
| 714 | .SEGBITS = 42, |
| 715 | .PABITS = 36, |
| 716 | .insn_flags = CPU_MIPS64R2, |
| 717 | .mmu_type = MMU_TYPE_R4000, |
| 718 | }, |
| 719 | { |
| 720 | .name = "5KEf", |
| 721 | .CP0_PRid = 0x00018900, |
| 722 | .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) | |
| 723 | (MMU_TYPE_R4000 << CP0C0_MT), |
| 724 | .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (31 << CP0C1_MMU) | |
| 725 | (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) | |
| 726 | (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) | |
| 727 | (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), |
| 728 | .CP0_Config2 = MIPS_CONFIG2, |
| 729 | .CP0_Config3 = MIPS_CONFIG3, |
| 730 | .CP0_LLAddr_rw_bitmask = 0, |
| 731 | .CP0_LLAddr_shift = 4, |
| 732 | .SYNCI_Step = 32, |
| 733 | .CCRes = 2, |
| 734 | .CP0_Status_rw_bitmask = 0x36F8FFFF, |
| 735 | .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) | |
| 736 | (1 << FCR0_D) | (1 << FCR0_S) | |
| 737 | (0x89 << FCR0_PRID) | (0x0 << FCR0_REV), |
| 738 | .SEGBITS = 42, |
| 739 | .PABITS = 36, |
| 740 | .insn_flags = CPU_MIPS64R2, |
| 741 | .mmu_type = MMU_TYPE_R4000, |
| 742 | }, |
| 743 | { |
| 744 | .name = "I6400", |
| 745 | .CP0_PRid = 0x1A900, |
| 746 | .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AR) | (0x2 << CP0C0_AT) | |
| 747 | (MMU_TYPE_R4000 << CP0C0_MT), |
| 748 | .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) | |
| 749 | (2 << CP0C1_IS) | (5 << CP0C1_IL) | (3 << CP0C1_IA) | |
| 750 | (2 << CP0C1_DS) | (5 << CP0C1_DL) | (3 << CP0C1_DA) | |
| 751 | (0 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), |
| 752 | .CP0_Config2 = MIPS_CONFIG2, |
| 753 | .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | |
| 754 | (1 << CP0C3_CMGCR) | (1 << CP0C3_MSAP) | |
| 755 | (1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_ULRI) | |
| 756 | (1 << CP0C3_RXI) | (1 << CP0C3_LPA) | (1 << CP0C3_VInt), |
| 757 | .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (3 << CP0C4_IE) | |
| 758 | (1 << CP0C4_AE) | (0xfc << CP0C4_KScrExist), |
| 759 | .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_CRCP) | (1 << CP0C5_XNP) | |
| 760 | (1 << CP0C5_VP) | (1 << CP0C5_LLB) | (1 << CP0C5_MRP) | |
| 761 | (3 << CP0C5_GI), |
| 762 | .CP0_Config5_rw_bitmask = (1 << CP0C5_MSAEn) | (1 << CP0C5_SBRI) | |
| 763 | (1 << CP0C5_FRE) | (1 << CP0C5_UFE), |
| 764 | .CP0_LLAddr_rw_bitmask = 0, |
| 765 | .CP0_LLAddr_shift = 0, |
| 766 | .SYNCI_Step = 32, |
| 767 | .CCRes = 2, |
| 768 | .CP0_Status_rw_bitmask = 0x30D8FFFF, |
| 769 | .CP0_PageGrain = (1 << CP0PG_IEC) | (1 << CP0PG_XIE) | |
| 770 | (1U << CP0PG_RIE), |
| 771 | .CP0_PageGrain_rw_bitmask = (1 << CP0PG_ELPA), |
| 772 | .CP0_EBaseWG_rw_bitmask = (1 << CP0EBase_WG), |
| 773 | .CP1_fcr0 = (1 << FCR0_FREP) | (1 << FCR0_HAS2008) | (1 << FCR0_F64) | |
| 774 | (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) | |
| 775 | (1 << FCR0_S) | (0x03 << FCR0_PRID) | (0x0 << FCR0_REV), |
| 776 | .CP1_fcr31 = (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008), |
| 777 | .CP1_fcr31_rw_bitmask = 0x0103FFFF, |
| 778 | .MSAIR = 0x03 << MSAIR_ProcID, |
| 779 | .SEGBITS = 48, |
| 780 | .PABITS = 48, |
| 781 | .insn_flags = CPU_MIPS64R6, |
| 782 | .mmu_type = MMU_TYPE_R4000, |
| 783 | }, |
| 784 | { |
| 785 | .name = "I6500", |
| 786 | .CP0_PRid = 0x1B000, |
| 787 | .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AR) | (0x2 << CP0C0_AT) | |
| 788 | (MMU_TYPE_R4000 << CP0C0_MT), |
| 789 | .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) | |
| 790 | (2 << CP0C1_IS) | (5 << CP0C1_IL) | (3 << CP0C1_IA) | |
| 791 | (2 << CP0C1_DS) | (5 << CP0C1_DL) | (3 << CP0C1_DA) | |
| 792 | (0 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), |
| 793 | .CP0_Config2 = MIPS_CONFIG2, |
| 794 | .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | |
| 795 | (1 << CP0C3_CMGCR) | (1 << CP0C3_MSAP) | |
| 796 | (1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_ULRI) | |
| 797 | (1 << CP0C3_RXI) | (1 << CP0C3_LPA) | (1 << CP0C3_VInt), |
| 798 | .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (3 << CP0C4_IE) | |
| 799 | (1 << CP0C4_AE) | (0xfc << CP0C4_KScrExist), |
| 800 | .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_CRCP) | (1 << CP0C5_XNP) | |
| 801 | (1 << CP0C5_VP) | (1 << CP0C5_LLB) | (1 << CP0C5_MRP) | |
| 802 | (3 << CP0C5_GI), |
| 803 | .CP0_Config5_rw_bitmask = (1 << CP0C5_MSAEn) | (1 << CP0C5_SBRI) | |
| 804 | (1 << CP0C5_FRE) | (1 << CP0C5_UFE), |
| 805 | .CP0_LLAddr_rw_bitmask = 0, |
| 806 | .CP0_LLAddr_shift = 0, |
| 807 | .SYNCI_Step = 64, |
| 808 | .CCRes = 2, |
| 809 | .CP0_Status_rw_bitmask = 0x30D8FFFF, |
| 810 | .CP0_PageGrain = (1 << CP0PG_IEC) | (1 << CP0PG_XIE) | |
| 811 | (1U << CP0PG_RIE), |
| 812 | .CP0_PageGrain_rw_bitmask = (1 << CP0PG_ELPA), |
| 813 | .CP0_EBaseWG_rw_bitmask = (1 << CP0EBase_WG), |
| 814 | .CP1_fcr0 = (1 << FCR0_FREP) | (1 << FCR0_HAS2008) | (1 << FCR0_F64) | |
| 815 | (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) | |
| 816 | (1 << FCR0_S) | (0x03 << FCR0_PRID) | (0x0 << FCR0_REV), |
| 817 | .CP1_fcr31 = (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008), |
| 818 | .CP1_fcr31_rw_bitmask = 0x0103FFFF, |
| 819 | .MSAIR = 0x03 << MSAIR_ProcID, |
| 820 | .SEGBITS = 48, |
| 821 | .PABITS = 48, |
| 822 | .insn_flags = CPU_MIPS64R6, |
| 823 | .mmu_type = MMU_TYPE_R4000, |
| 824 | }, |
| 825 | { |
| 826 | .name = "Loongson-2E", |
| 827 | .CP0_PRid = 0x6302, |
| 828 | /* 64KB I-cache and d-cache. 4 way with 32 bit cache line size. */ |
| 829 | .CP0_Config0 = (3 << CP0C0_Impl) | (4 << CP0C0_IC) | (4 << CP0C0_DC) | |
| 830 | (1 << CP0C0_IB) | (1 << CP0C0_DB) | (0x2 << CP0C0_K0), |
| 831 | /* Note: Config1 is only used internally, |
| 832 | Loongson-2E has only Config0. */ |
| 833 | .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU), |
| 834 | .SYNCI_Step = 16, |
| 835 | .CCRes = 2, |
| 836 | .CP0_Status_rw_bitmask = 0x35D0FFFF, |
| 837 | .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV), |
| 838 | .CP1_fcr31 = 0, |
| 839 | .CP1_fcr31_rw_bitmask = 0xFF83FFFF, |
| 840 | .SEGBITS = 40, |
| 841 | .PABITS = 40, |
| 842 | .insn_flags = CPU_MIPS3 | INSN_LOONGSON2E, |
| 843 | .mmu_type = MMU_TYPE_R4000, |
| 844 | }, |
| 845 | { |
| 846 | .name = "Loongson-2F", |
| 847 | .CP0_PRid = 0x6303, |
| 848 | /* 64KB I-cache and d-cache. 4 way with 32 bit cache line size. */ |
| 849 | .CP0_Config0 = (3 << CP0C0_Impl) | (4 << CP0C0_IC) | (4 << CP0C0_DC) | |
| 850 | (1 << CP0C0_IB) | (1 << CP0C0_DB) | (0x2 << CP0C0_K0), |
| 851 | /* Note: Config1 is only used internally, |
| 852 | Loongson-2F has only Config0. */ |
| 853 | .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU), |
| 854 | .SYNCI_Step = 16, |
| 855 | .CCRes = 2, |
| 856 | .CP0_Status_rw_bitmask = 0xF5D0FF1F, /* Bits 7:5 not writable. */ |
| 857 | .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV), |
| 858 | .CP1_fcr31 = 0, |
| 859 | .CP1_fcr31_rw_bitmask = 0xFF83FFFF, |
| 860 | .SEGBITS = 40, |
| 861 | .PABITS = 40, |
| 862 | .insn_flags = CPU_MIPS3 | INSN_LOONGSON2F | ASE_LMMI, |
| 863 | .mmu_type = MMU_TYPE_R4000, |
| 864 | }, |
| 865 | { |
| 866 | .name = "Loongson-3A1000", /* Loongson-3A R1, GS464-based */ |
| 867 | .CP0_PRid = 0x6305, |
| 868 | /* 64KB I-cache and d-cache. 4 way with 32 bit cache line size. */ |
| 869 | .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) | |
| 870 | (MMU_TYPE_R4000 << CP0C0_MT), |
| 871 | .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) | |
| 872 | (3 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) | |
| 873 | (3 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) | |
| 874 | (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), |
| 875 | .CP0_Config2 = MIPS_CONFIG2 | (7 << CP0C2_SS) | (4 << CP0C2_SL) | |
| 876 | (3 << CP0C2_SA), |
| 877 | .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA), |
| 878 | .CP0_LLAddr_rw_bitmask = 0, |
| 879 | .SYNCI_Step = 32, |
| 880 | .CCRes = 2, |
| 881 | .CP0_Status_rw_bitmask = 0x74D8FFFF, |
| 882 | .CP0_PageGrain = (1 << CP0PG_ELPA), |
| 883 | .CP0_PageGrain_rw_bitmask = (1 << CP0PG_ELPA), |
| 884 | .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV) | (0x1 << FCR0_F64) | |
| 885 | (0x1 << FCR0_PS) | (0x1 << FCR0_L) | (0x1 << FCR0_W) | |
| 886 | (0x1 << FCR0_D) | (0x1 << FCR0_S), |
| 887 | .CP1_fcr31 = 0, |
| 888 | .CP1_fcr31_rw_bitmask = 0xFF83FFFF, |
| 889 | .SEGBITS = 48, |
| 890 | .PABITS = 48, |
| 891 | .insn_flags = CPU_MIPS64R2 | INSN_LOONGSON3A | |
| 892 | ASE_LMMI | ASE_LEXT, |
| 893 | .mmu_type = MMU_TYPE_R4000, |
| 894 | }, |
| 895 | { |
| 896 | .name = "Loongson-3A4000", /* Loongson-3A R4, GS464V-based */ |
| 897 | .CP0_PRid = 0x14C000, |
| 898 | /* 64KB I-cache and d-cache. 4 way with 32 bit cache line size. */ |
| 899 | .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) | |
| 900 | (MMU_TYPE_R4000 << CP0C0_MT), |
| 901 | .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) | |
| 902 | (2 << CP0C1_IS) | (5 << CP0C1_IL) | (3 << CP0C1_IA) | |
| 903 | (2 << CP0C1_DS) | (5 << CP0C1_DL) | (3 << CP0C1_DA) | |
| 904 | (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), |
| 905 | .CP0_Config2 = MIPS_CONFIG2 | (5 << CP0C2_SS) | (5 << CP0C2_SL) | |
| 906 | (15 << CP0C2_SA), |
| 907 | .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_MSAP) | |
| 908 | (1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_ULRI) | |
| 909 | (1 << CP0C3_RXI) | (1 << CP0C3_LPA) | (1 << CP0C3_VInt), |
| 910 | .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (2 << CP0C4_IE) | |
| 911 | (1 << CP0C4_AE) | (0x1c << CP0C4_KScrExist), |
| 912 | .CP0_Config4_rw_bitmask = 0, |
| 913 | .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_CRCP) | (1 << CP0C5_NFExists), |
| 914 | .CP0_Config5_rw_bitmask = (1 << CP0C5_K) | (1 << CP0C5_CV) | |
| 915 | (1 << CP0C5_MSAEn) | (1 << CP0C5_UFE) | |
| 916 | (1 << CP0C5_FRE) | (1 << CP0C5_SBRI), |
| 917 | .CP0_Config6 = (1 << CP0C6_VCLRU) | (1 << CP0C6_DCLRU) | |
| 918 | (1 << CP0C6_SFBEN) | (1 << CP0C6_VLTINT) | |
| 919 | (1 << CP0C6_INSTPREF) | (1 << CP0C6_DATAPREF), |
| 920 | .CP0_Config6_rw_bitmask = (1 << CP0C6_BPPASS) | (0x3f << CP0C6_KPOS) | |
| 921 | (1 << CP0C6_KE) | (1 << CP0C6_VTLBONLY) | |
| 922 | (1 << CP0C6_LASX) | (1 << CP0C6_SSEN) | |
| 923 | (1 << CP0C6_DISDRTIME) | (1 << CP0C6_PIXNUEN) | |
| 924 | (1 << CP0C6_SCRAND) | (1 << CP0C6_LLEXCEN) | |
| 925 | (1 << CP0C6_DISVC) | (1 << CP0C6_VCLRU) | |
| 926 | (1 << CP0C6_DCLRU) | (1 << CP0C6_PIXUEN) | |
| 927 | (1 << CP0C6_DISBLKLYEN) | (1 << CP0C6_UMEMUALEN) | |
| 928 | (1 << CP0C6_SFBEN) | (1 << CP0C6_FLTINT) | |
| 929 | (1 << CP0C6_VLTINT) | (1 << CP0C6_DISBTB) | |
| 930 | (3 << CP0C6_STPREFCTL) | (1 << CP0C6_INSTPREF) | |
| 931 | (1 << CP0C6_DATAPREF), |
| 932 | .CP0_Config7 = 0, |
| 933 | .CP0_Config7_rw_bitmask = (1 << CP0C7_NAPCGEN) | (1 << CP0C7_UNIMUEN) | |
| 934 | (1 << CP0C7_VFPUCGEN), |
| 935 | .CP0_LLAddr_rw_bitmask = 1, |
| 936 | .SYNCI_Step = 16, |
| 937 | .CCRes = 2, |
| 938 | .CP0_Status_rw_bitmask = 0x7DDBFFFF, |
| 939 | .CP0_PageGrain = (1 << CP0PG_ELPA), |
| 940 | .CP0_PageGrain_rw_bitmask = (1U << CP0PG_RIE) | (1 << CP0PG_XIE) | |
| 941 | (1 << CP0PG_ELPA) | (1 << CP0PG_IEC), |
| 942 | .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV) | (0x1 << FCR0_F64) | |
| 943 | (0x1 << FCR0_PS) | (0x1 << FCR0_L) | (0x1 << FCR0_W) | |
| 944 | (0x1 << FCR0_D) | (0x1 << FCR0_S), |
| 945 | .CP1_fcr31 = 0, |
| 946 | .CP1_fcr31_rw_bitmask = 0xFF83FFFF, |
| 947 | .MSAIR = (0x01 << MSAIR_ProcID) | (0x40 << MSAIR_Rev), |
| 948 | .lcsr_cpucfg1 = (1 << CPUCFG1_FP) | (2 << CPUCFG1_FPREV) | |
| 949 | (1 << CPUCFG1_MSA1) | (1 << CPUCFG1_LSLDR0) | |
| 950 | (1 << CPUCFG1_LSPERF) | (1 << CPUCFG1_LSPERFX) | |
| 951 | (1 << CPUCFG1_LSSYNCI) | (1 << CPUCFG1_LLEXC) | |
| 952 | (1 << CPUCFG1_SCRAND) | (1 << CPUCFG1_MUALP) | |
| 953 | (1 << CPUCFG1_KMUALEN) | (1 << CPUCFG1_ITLBT) | |
| 954 | (1 << CPUCFG1_SFBP) | (1 << CPUCFG1_CDMAP), |
| 955 | .lcsr_cpucfg2 = (1 << CPUCFG2_LEXT1) | (1 << CPUCFG2_LCSRP) | |
| 956 | (1 << CPUCFG2_LDISBLIKELY), |
| 957 | .SEGBITS = 48, |
| 958 | .PABITS = 48, |
| 959 | .insn_flags = CPU_MIPS64R2 | INSN_LOONGSON3A | |
| 960 | ASE_LMMI | ASE_LEXT, |
| 961 | .mmu_type = MMU_TYPE_R4000, |
| 962 | }, |
| 963 | { |
| 964 | /* A generic CPU providing MIPS64 DSP R2 ASE features. |
| 965 | FIXME: Eventually this should be replaced by a real CPU model. */ |
| 966 | .name = "mips64dspr2", |
| 967 | .CP0_PRid = 0x00010000, |
| 968 | .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) | |
| 969 | (MMU_TYPE_R4000 << CP0C0_MT), |
| 970 | .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) | |
| 971 | (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) | |
| 972 | (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) | |
| 973 | (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), |
| 974 | .CP0_Config2 = MIPS_CONFIG2, |
| 975 | .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_DSP2P) | |
| 976 | (1 << CP0C3_DSPP) | (1 << CP0C3_LPA), |
| 977 | .CP0_LLAddr_rw_bitmask = 0, |
| 978 | .CP0_LLAddr_shift = 0, |
| 979 | .SYNCI_Step = 32, |
| 980 | .CCRes = 2, |
| 981 | .CP0_Status_rw_bitmask = 0x37FBFFFF, |
| 982 | .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_3D) | (1 << FCR0_PS) | |
| 983 | (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) | |
| 984 | (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV), |
| 985 | .CP1_fcr31 = 0, |
| 986 | .CP1_fcr31_rw_bitmask = 0xFF83FFFF, |
| 987 | .SEGBITS = 42, |
| 988 | .PABITS = 36, |
| 989 | .insn_flags = CPU_MIPS64R2 | ASE_DSP | ASE_DSP_R2, |
| 990 | .mmu_type = MMU_TYPE_R4000, |
| 991 | }, |
| 992 | { |
| 993 | /* |
| 994 | * Octeon 68xx with MIPS64 Cavium Octeon features. |
| 995 | */ |
| 996 | .name = "Octeon68XX", |
| 997 | .CP0_PRid = 0x000D9100, |
| 998 | .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) | |
| 999 | (MMU_TYPE_R4000 << CP0C0_MT), |
| 1000 | .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | |
| 1001 | (0x3F << CP0C1_MMU) | |
| 1002 | (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) | |
| 1003 | (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) | |
| 1004 | (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), |
| 1005 | .CP0_Config2 = MIPS_CONFIG2, |
| 1006 | .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA), |
| 1007 | .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | |
| 1008 | (0x3c << CP0C4_KScrExist) | (1U << CP0C4_MMUExtDef) | |
| 1009 | (3U << CP0C4_MMUSizeExt), |
| 1010 | .CP0_LLAddr_rw_bitmask = 0, |
| 1011 | .CP0_LLAddr_shift = 4, |
| 1012 | .CP0_PageGrain = (1 << CP0PG_ELPA), |
| 1013 | .SYNCI_Step = 32, |
| 1014 | .CCRes = 2, |
| 1015 | .CP0_Status_rw_bitmask = 0x36F8FFFF, |
| 1016 | .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_3D) | (1 << FCR0_PS) | |
| 1017 | (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) | |
| 1018 | (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV), |
| 1019 | .CP1_fcr31 = 0, |
| 1020 | .CP1_fcr31_rw_bitmask = 0xFF83FFFF, |
| 1021 | .SEGBITS = 42, |
| 1022 | .PABITS = 49, |
| 1023 | .insn_flags = CPU_MIPS64R2 | INSN_OCTEON, |
| 1024 | .mmu_type = MMU_TYPE_R4000, |
| 1025 | }, |
| 1026 | |
| 1027 | #endif |
| 1028 | }; |
| 1029 | const int mips_defs_number = ARRAY_SIZE(mips_defs); |
| 1030 | |
| 1031 | static void fpu_init (CPUMIPSState *env, const mips_def_t *def) |
| 1032 | { |
| 1033 | int i; |
| 1034 | |
| 1035 | for (i = 0; i < MIPS_FPU_MAX; i++) |
| 1036 | env->fpus[i].fcr0 = def->CP1_fcr0; |
| 1037 | |
| 1038 | memcpy(&env->active_fpu, &env->fpus[0], sizeof(env->active_fpu)); |
| 1039 | } |
| 1040 | |
| 1041 | static void mvp_init(CPUMIPSState *env) |
| 1042 | { |
| 1043 | MIPSCPU *cpu = env_archcpu(env); |
| 1044 | |
| 1045 | cpu->mvp = g_malloc0(sizeof(CPUMIPSMVPContext)); |
| 1046 | |
| 1047 | if (!ase_mt_available(env)) { |
| 1048 | return; |
| 1049 | } |
| 1050 | |
| 1051 | /* MVPConf1 implemented, TLB shareable, no gating storage support, |
| 1052 | programmable cache partitioning implemented, number of allocatable |
| 1053 | and shareable TLB entries, MVP has allocatable TCs, 2 VPEs |
| 1054 | implemented, 5 TCs implemented. */ |
| 1055 | cpu->mvp->CP0_MVPConf0 = (1U << CP0MVPC0_M) | (1 << CP0MVPC0_TLBS) | |
| 1056 | (0 << CP0MVPC0_GS) | (1 << CP0MVPC0_PCP) | |
| 1057 | // TODO: actually do 2 VPEs. |
| 1058 | // (1 << CP0MVPC0_TCA) | (0x1 << CP0MVPC0_PVPE) | |
| 1059 | // (0x04 << CP0MVPC0_PTC); |
| 1060 | (1 << CP0MVPC0_TCA) | (0x0 << CP0MVPC0_PVPE) | |
| 1061 | (0x00 << CP0MVPC0_PTC); |
| 1062 | #if !defined(CONFIG_USER_ONLY) |
| 1063 | /* Usermode has no TLB support */ |
| 1064 | cpu->mvp->CP0_MVPConf0 |= (env->tlb->nb_tlb << CP0MVPC0_PTLBE); |
| 1065 | #endif |
| 1066 | |
| 1067 | /* Allocatable CP1 have media extensions, allocatable CP1 have FP support, |
| 1068 | no UDI implemented, no CP2 implemented, 1 CP1 implemented. */ |
| 1069 | cpu->mvp->CP0_MVPConf1 = (1U << CP0MVPC1_CIM) | (1 << CP0MVPC1_CIF) | |
| 1070 | (0x0 << CP0MVPC1_PCX) | (0x0 << CP0MVPC1_PCP2) | |
| 1071 | (0x1 << CP0MVPC1_PCP1); |
| 1072 | } |