| 1 | /* |
| 2 | * QEMU MIPS CPU |
| 3 | * |
| 4 | * Copyright (c) 2012 SUSE LINUX Products GmbH |
| 5 | * |
| 6 | * This library is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU Lesser General Public |
| 8 | * License as published by the Free Software Foundation; either |
| 9 | * version 2.1 of the License, or (at your option) any later version. |
| 10 | * |
| 11 | * This library is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 14 | * Lesser General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU Lesser General Public |
| 17 | * License along with this library; if not, see |
| 18 | * <http://www.gnu.org/licenses/lgpl-2.1.html> |
| 19 | */ |
| 20 | |
| 21 | #include "qemu/osdep.h" |
| 22 | #include "qemu/cutils.h" |
| 23 | #include "qemu/qemu-print.h" |
| 24 | #include "qemu/error-report.h" |
| 25 | #include "qapi/error.h" |
| 26 | #include "cpu.h" |
| 27 | #include "internal.h" |
| 28 | #include "qemu/module.h" |
| 29 | #include "qemu/qtree.h" |
| 30 | #include "system/qtest.h" |
| 31 | #include "hw/core/qdev-properties.h" |
| 32 | #include "hw/core/qdev-clock.h" |
| 33 | #include "disas/capstone.h" |
| 34 | #include "fpu_helper.h" |
| 35 | #ifndef CONFIG_USER_ONLY |
| 36 | #include "semihosting/semihost.h" |
| 37 | #endif |
| 38 | |
| 39 | const char regnames[32][3] = { |
| 40 | "r0", "at", "v0", "v1", "a0", "a1", "a2", "a3", |
| 41 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", |
| 42 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", |
| 43 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", |
| 44 | }; |
| 45 | |
| 46 | static void fpu_dump_fpr(fpr_t *fpr, FILE *f, bool is_fpu64) |
| 47 | { |
| 48 | if (is_fpu64) { |
| 49 | qemu_fprintf(f, "w:%08x d:%016" PRIx64 " fd:%13g fs:%13g psu: %13g\n", |
| 50 | fpr->w[FP_ENDIAN_IDX], fpr->d, |
| 51 | (double)fpr->fd, |
| 52 | (double)fpr->fs[FP_ENDIAN_IDX], |
| 53 | (double)fpr->fs[!FP_ENDIAN_IDX]); |
| 54 | } else { |
| 55 | fpr_t tmp; |
| 56 | |
| 57 | tmp.w[FP_ENDIAN_IDX] = fpr->w[FP_ENDIAN_IDX]; |
| 58 | tmp.w[!FP_ENDIAN_IDX] = (fpr + 1)->w[FP_ENDIAN_IDX]; |
| 59 | qemu_fprintf(f, "w:%08x d:%016" PRIx64 " fd:%13g fs:%13g psu:%13g\n", |
| 60 | tmp.w[FP_ENDIAN_IDX], tmp.d, |
| 61 | (double)tmp.fd, |
| 62 | (double)tmp.fs[FP_ENDIAN_IDX], |
| 63 | (double)tmp.fs[!FP_ENDIAN_IDX]); |
| 64 | } |
| 65 | } |
| 66 | |
| 67 | static void fpu_dump_state(CPUMIPSState *env, FILE *f, int flags) |
| 68 | { |
| 69 | int i; |
| 70 | bool is_fpu64 = !!(env->hflags & MIPS_HFLAG_F64); |
| 71 | |
| 72 | qemu_fprintf(f, |
| 73 | "CP1 FCR0 0x%08x FCR31 0x%08x SR.FR %d fp_status 0x%02x\n", |
| 74 | env->active_fpu.fcr0, env->active_fpu.fcr31, is_fpu64, |
| 75 | get_float_exception_flags(&env->active_fpu.fp_status)); |
| 76 | for (i = 0; i < 32; (is_fpu64) ? i++ : (i += 2)) { |
| 77 | qemu_fprintf(f, "%3s: ", fregnames[i]); |
| 78 | fpu_dump_fpr(&env->active_fpu.fpr[i], f, is_fpu64); |
| 79 | } |
| 80 | } |
| 81 | |
| 82 | static void mips_cpu_dump_state(CPUState *cs, FILE *f, int flags) |
| 83 | { |
| 84 | CPUMIPSState *env = cpu_env(cs); |
| 85 | int i; |
| 86 | |
| 87 | qemu_fprintf(f, "pc=0x" TARGET_FMT_lx " HI=0x" TARGET_FMT_lx |
| 88 | " LO=0x" TARGET_FMT_lx " ds %04x " |
| 89 | TARGET_FMT_lx " " TARGET_FMT_ld "\n", |
| 90 | env->active_tc.PC, env->active_tc.HI[0], env->active_tc.LO[0], |
| 91 | env->hflags, env->btarget, env->bcond); |
| 92 | for (i = 0; i < 32; i++) { |
| 93 | if ((i & 3) == 0) { |
| 94 | qemu_fprintf(f, "GPR%02d:", i); |
| 95 | } |
| 96 | qemu_fprintf(f, " %s " TARGET_FMT_lx, |
| 97 | regnames[i], env->active_tc.gpr[i]); |
| 98 | if ((i & 3) == 3) { |
| 99 | qemu_fprintf(f, "\n"); |
| 100 | } |
| 101 | } |
| 102 | |
| 103 | qemu_fprintf(f, "CP0 Status 0x%08x Cause 0x%08x EPC 0x" |
| 104 | TARGET_FMT_lx "\n", |
| 105 | env->CP0_Status, env->CP0_Cause, env->CP0_EPC); |
| 106 | qemu_fprintf(f, " Config0 0x%08x Config1 0x%08x LLAddr 0x%016" |
| 107 | PRIx64 "\n", |
| 108 | env->CP0_Config0, env->CP0_Config1, env->CP0_LLAddr); |
| 109 | qemu_fprintf(f, " Config2 0x%08x Config3 0x%08x\n", |
| 110 | env->CP0_Config2, env->CP0_Config3); |
| 111 | qemu_fprintf(f, " Config4 0x%08x Config5 0x%08x\n", |
| 112 | env->CP0_Config4, env->CP0_Config5); |
| 113 | if ((flags & CPU_DUMP_FPU) && (env->hflags & MIPS_HFLAG_FPU)) { |
| 114 | fpu_dump_state(env, f, flags); |
| 115 | } |
| 116 | } |
| 117 | |
| 118 | void cpu_set_exception_base(int vp_index, target_ulong address) |
| 119 | { |
| 120 | MIPSCPU *vp = MIPS_CPU(qemu_get_cpu(vp_index)); |
| 121 | vp->env.exception_base = address; |
| 122 | } |
| 123 | |
| 124 | static void mips_cpu_set_pc(CPUState *cs, vaddr value) |
| 125 | { |
| 126 | mips_env_set_pc(cpu_env(cs), value); |
| 127 | } |
| 128 | |
| 129 | static vaddr mips_cpu_get_pc(CPUState *cs) |
| 130 | { |
| 131 | MIPSCPU *cpu = MIPS_CPU(cs); |
| 132 | |
| 133 | return cpu->env.active_tc.PC; |
| 134 | } |
| 135 | |
| 136 | #if !defined(CONFIG_USER_ONLY) |
| 137 | static bool mips_cpu_has_work(CPUState *cs) |
| 138 | { |
| 139 | CPUMIPSState *env = cpu_env(cs); |
| 140 | bool has_work = false; |
| 141 | |
| 142 | /* |
| 143 | * Prior to MIPS Release 6 it is implementation dependent if non-enabled |
| 144 | * interrupts wake-up the CPU, however most of the implementations only |
| 145 | * check for interrupts that can be taken. For pre-release 6 CPUs, |
| 146 | * check for CP0 Config7 'Wait IE ignore' bit. |
| 147 | */ |
| 148 | if (cpu_test_interrupt(cs, CPU_INTERRUPT_HARD) && |
| 149 | cpu_mips_hw_interrupts_pending(env)) { |
| 150 | if (cpu_mips_hw_interrupts_enabled(env) || |
| 151 | (env->CP0_Config7 & (1 << CP0C7_WII)) || |
| 152 | (env->insn_flags & ISA_MIPS_R6)) { |
| 153 | has_work = true; |
| 154 | } |
| 155 | } |
| 156 | |
| 157 | /* MIPS-MT has the ability to halt the CPU. */ |
| 158 | if (ase_mt_available(env)) { |
| 159 | /* |
| 160 | * The QEMU model will issue an _WAKE request whenever the CPUs |
| 161 | * should be woken up. |
| 162 | */ |
| 163 | if (cpu_test_interrupt(cs, CPU_INTERRUPT_WAKE)) { |
| 164 | has_work = true; |
| 165 | } |
| 166 | |
| 167 | if (!mips_vpe_active(env)) { |
| 168 | has_work = false; |
| 169 | } |
| 170 | } |
| 171 | /* MIPS Release 6 has the ability to halt the CPU. */ |
| 172 | if (env->CP0_Config5 & (1 << CP0C5_VP)) { |
| 173 | if (cpu_test_interrupt(cs, CPU_INTERRUPT_WAKE)) { |
| 174 | has_work = true; |
| 175 | } |
| 176 | if (!mips_vp_active(env)) { |
| 177 | has_work = false; |
| 178 | } |
| 179 | } |
| 180 | return has_work; |
| 181 | } |
| 182 | #endif /* !CONFIG_USER_ONLY */ |
| 183 | |
| 184 | #include "cpu-defs.c.inc" |
| 185 | |
| 186 | static gint mips_octeon_u64_tree_compare(gconstpointer a, gconstpointer b, |
| 187 | gpointer user_data) |
| 188 | { |
| 189 | uint64_t av = *(const uint64_t *)a; |
| 190 | uint64_t bv = *(const uint64_t *)b; |
| 191 | |
| 192 | return (av > bv) - (av < bv); |
| 193 | } |
| 194 | |
| 195 | QTree *mips_octeon_llm_tree_new(void) |
| 196 | { |
| 197 | return q_tree_new_full(mips_octeon_u64_tree_compare, |
| 198 | NULL, g_free, g_free); |
| 199 | } |
| 200 | |
| 201 | uint64_t mips_octeon_llm_load(QTree *tree, uint64_t addr) |
| 202 | { |
| 203 | uint64_t key = addr; |
| 204 | uint64_t *value = tree ? q_tree_lookup(tree, &key) : NULL; |
| 205 | |
| 206 | return value ? *value : 0; |
| 207 | } |
| 208 | |
| 209 | void mips_octeon_llm_store(QTree **treep, uint64_t addr, uint64_t value) |
| 210 | { |
| 211 | uint64_t *key; |
| 212 | uint64_t *stored; |
| 213 | |
| 214 | if (!*treep) { |
| 215 | *treep = mips_octeon_llm_tree_new(); |
| 216 | } |
| 217 | |
| 218 | key = g_new(uint64_t, 1); |
| 219 | stored = g_new(uint64_t, 1); |
| 220 | *key = addr; |
| 221 | *stored = value; |
| 222 | q_tree_replace(*treep, key, stored); |
| 223 | } |
| 224 | |
| 225 | static void mips_octeon_destroy_llm_state(MIPSOcteonCryptoState *crypto) |
| 226 | { |
| 227 | if (crypto->llm36) { |
| 228 | q_tree_destroy(crypto->llm36); |
| 229 | crypto->llm36 = NULL; |
| 230 | } |
| 231 | if (crypto->llm64) { |
| 232 | q_tree_destroy(crypto->llm64); |
| 233 | crypto->llm64 = NULL; |
| 234 | } |
| 235 | } |
| 236 | |
| 237 | static void mips_cpu_reset_hold(Object *obj, ResetType type) |
| 238 | { |
| 239 | CPUState *cs = CPU(obj); |
| 240 | MIPSCPU *cpu = MIPS_CPU(cs); |
| 241 | MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(obj); |
| 242 | CPUMIPSState *env = &cpu->env; |
| 243 | |
| 244 | if (mcc->parent_phases.hold) { |
| 245 | mcc->parent_phases.hold(obj, type); |
| 246 | } |
| 247 | |
| 248 | mips_octeon_destroy_llm_state(&env->octeon_crypto); |
| 249 | memset(env, 0, offsetof(CPUMIPSState, end_reset_fields)); |
| 250 | |
| 251 | /* Reset registers to their default values */ |
| 252 | env->CP0_PRid = env->cpu_model->CP0_PRid; |
| 253 | env->CP0_Config0 = deposit32(env->cpu_model->CP0_Config0, |
| 254 | CP0C0_BE, 1, cpu->is_big_endian); |
| 255 | env->CP0_Config1 = env->cpu_model->CP0_Config1; |
| 256 | env->CP0_Config2 = env->cpu_model->CP0_Config2; |
| 257 | env->CP0_Config3 = env->cpu_model->CP0_Config3; |
| 258 | env->CP0_Config4 = env->cpu_model->CP0_Config4; |
| 259 | env->CP0_Config4_rw_bitmask = env->cpu_model->CP0_Config4_rw_bitmask; |
| 260 | env->CP0_Config5 = env->cpu_model->CP0_Config5; |
| 261 | env->CP0_Config5_rw_bitmask = env->cpu_model->CP0_Config5_rw_bitmask; |
| 262 | env->CP0_Config6 = env->cpu_model->CP0_Config6; |
| 263 | env->CP0_Config6_rw_bitmask = env->cpu_model->CP0_Config6_rw_bitmask; |
| 264 | env->CP0_Config7 = env->cpu_model->CP0_Config7; |
| 265 | env->CP0_Config7_rw_bitmask = env->cpu_model->CP0_Config7_rw_bitmask; |
| 266 | env->CP0_LLAddr_rw_bitmask = env->cpu_model->CP0_LLAddr_rw_bitmask |
| 267 | << env->cpu_model->CP0_LLAddr_shift; |
| 268 | env->CP0_LLAddr_shift = env->cpu_model->CP0_LLAddr_shift; |
| 269 | env->SYNCI_Step = env->cpu_model->SYNCI_Step; |
| 270 | env->CCRes = env->cpu_model->CCRes; |
| 271 | env->CP0_Status_rw_bitmask = env->cpu_model->CP0_Status_rw_bitmask; |
| 272 | env->CP0_TCStatus_rw_bitmask = env->cpu_model->CP0_TCStatus_rw_bitmask; |
| 273 | env->CP0_SRSCtl = env->cpu_model->CP0_SRSCtl; |
| 274 | env->current_tc = 0; |
| 275 | env->SEGBITS = env->cpu_model->SEGBITS; |
| 276 | env->SEGMask = (target_ulong)((1ULL << env->cpu_model->SEGBITS) - 1); |
| 277 | #if defined(TARGET_MIPS64) |
| 278 | if (env->cpu_model->insn_flags & ISA_MIPS3) { |
| 279 | env->SEGMask |= 3ULL << 62; |
| 280 | } |
| 281 | #endif |
| 282 | env->PABITS = env->cpu_model->PABITS; |
| 283 | env->CP0_SRSConf0_rw_bitmask = env->cpu_model->CP0_SRSConf0_rw_bitmask; |
| 284 | env->CP0_SRSConf0 = env->cpu_model->CP0_SRSConf0; |
| 285 | env->CP0_SRSConf1_rw_bitmask = env->cpu_model->CP0_SRSConf1_rw_bitmask; |
| 286 | env->CP0_SRSConf1 = env->cpu_model->CP0_SRSConf1; |
| 287 | env->CP0_SRSConf2_rw_bitmask = env->cpu_model->CP0_SRSConf2_rw_bitmask; |
| 288 | env->CP0_SRSConf2 = env->cpu_model->CP0_SRSConf2; |
| 289 | env->CP0_SRSConf3_rw_bitmask = env->cpu_model->CP0_SRSConf3_rw_bitmask; |
| 290 | env->CP0_SRSConf3 = env->cpu_model->CP0_SRSConf3; |
| 291 | env->CP0_SRSConf4_rw_bitmask = env->cpu_model->CP0_SRSConf4_rw_bitmask; |
| 292 | env->CP0_SRSConf4 = env->cpu_model->CP0_SRSConf4; |
| 293 | env->CP0_PageGrain_rw_bitmask = env->cpu_model->CP0_PageGrain_rw_bitmask; |
| 294 | env->CP0_PageGrain = env->cpu_model->CP0_PageGrain; |
| 295 | env->CP0_EBaseWG_rw_bitmask = env->cpu_model->CP0_EBaseWG_rw_bitmask; |
| 296 | env->lcsr_cpucfg1 = env->cpu_model->lcsr_cpucfg1; |
| 297 | env->lcsr_cpucfg2 = env->cpu_model->lcsr_cpucfg2; |
| 298 | env->active_fpu.fcr0 = env->cpu_model->CP1_fcr0; |
| 299 | env->active_fpu.fcr31_rw_bitmask = env->cpu_model->CP1_fcr31_rw_bitmask; |
| 300 | env->active_fpu.fcr31 = env->cpu_model->CP1_fcr31; |
| 301 | env->msair = env->cpu_model->MSAIR; |
| 302 | env->insn_flags = env->cpu_model->insn_flags; |
| 303 | if (env->insn_flags & INSN_OCTEON) { |
| 304 | env->octeon_crypto.chord = 1; |
| 305 | } |
| 306 | |
| 307 | #if defined(CONFIG_USER_ONLY) |
| 308 | env->CP0_Status = (MIPS_HFLAG_UM << CP0St_KSU); |
| 309 | # ifdef TARGET_MIPS64 |
| 310 | /* Enable 64-bit register mode. */ |
| 311 | env->CP0_Status |= (1 << CP0St_PX); |
| 312 | # endif |
| 313 | # ifdef TARGET_ABI_MIPSN64 |
| 314 | /* Enable 64-bit address mode. */ |
| 315 | env->CP0_Status |= (1 << CP0St_UX); |
| 316 | # endif |
| 317 | /* |
| 318 | * Enable access to the CPUNum, SYNCI_Step, CC, and CCRes RDHWR |
| 319 | * hardware registers. |
| 320 | */ |
| 321 | env->CP0_HWREna |= 0x0000000F; |
| 322 | if (env->insn_flags & INSN_OCTEON) { |
| 323 | env->CP0_HWREna |= 0x40000000u; |
| 324 | env->CP0_HWREna |= 0x80000000u; |
| 325 | } |
| 326 | if (env->CP0_Config1 & (1 << CP0C1_FP)) { |
| 327 | env->CP0_Status |= (1 << CP0St_CU1); |
| 328 | } |
| 329 | if (env->CP0_Config3 & (1 << CP0C3_DSPP)) { |
| 330 | env->CP0_Status |= (1 << CP0St_MX); |
| 331 | } |
| 332 | # if defined(TARGET_MIPS64) |
| 333 | /* For MIPS64, init FR bit to 1 if FPU unit is there and bit is writable. */ |
| 334 | if ((env->CP0_Config1 & (1 << CP0C1_FP)) && |
| 335 | (env->CP0_Status_rw_bitmask & (1 << CP0St_FR))) { |
| 336 | env->CP0_Status |= (1 << CP0St_FR); |
| 337 | } |
| 338 | # endif |
| 339 | #else /* !CONFIG_USER_ONLY */ |
| 340 | if (env->hflags & MIPS_HFLAG_BMASK) { |
| 341 | /* |
| 342 | * If the exception was raised from a delay slot, |
| 343 | * come back to the jump. |
| 344 | */ |
| 345 | env->CP0_ErrorEPC = (env->active_tc.PC |
| 346 | - (env->hflags & MIPS_HFLAG_B16 ? 2 : 4)); |
| 347 | } else { |
| 348 | env->CP0_ErrorEPC = env->active_tc.PC; |
| 349 | } |
| 350 | env->active_tc.PC = env->exception_base; |
| 351 | env->CP0_Random = env->tlb->nb_tlb - 1; |
| 352 | env->tlb->tlb_in_use = env->tlb->nb_tlb; |
| 353 | env->CP0_Wired = 0; |
| 354 | env->CP0_GlobalNumber = (cs->cpu_index & 0xFF) << CP0GN_VPId; |
| 355 | env->CP0_EBase = KSEG0_BASE | (cs->cpu_index & 0x3FF); |
| 356 | if (env->CP0_Config3 & (1 << CP0C3_CMGCR)) { |
| 357 | env->CP0_CMGCRBase = 0x1fbf8000 >> 4; |
| 358 | } |
| 359 | env->CP0_EntryHi_ASID_mask = (env->CP0_Config5 & (1 << CP0C5_MI)) ? |
| 360 | 0x0 : (env->CP0_Config4 & (1 << CP0C4_AE)) ? 0x3ff : 0xff; |
| 361 | env->CP0_Status = (1 << CP0St_BEV) | (1 << CP0St_ERL); |
| 362 | if (env->insn_flags & INSN_LOONGSON2F) { |
| 363 | /* Loongson-2F has those bits hardcoded to 1 */ |
| 364 | env->CP0_Status |= (1 << CP0St_KX) | (1 << CP0St_SX) | |
| 365 | (1 << CP0St_UX); |
| 366 | } |
| 367 | |
| 368 | /* |
| 369 | * Vectored interrupts not implemented, timer on int 7, |
| 370 | * no performance counters. |
| 371 | */ |
| 372 | env->CP0_IntCtl = 0xe0000000; |
| 373 | { |
| 374 | int i; |
| 375 | |
| 376 | for (i = 0; i < 7; i++) { |
| 377 | env->CP0_WatchLo[i] = 0; |
| 378 | env->CP0_WatchHi[i] = 1 << CP0WH_M; |
| 379 | } |
| 380 | env->CP0_WatchLo[7] = 0; |
| 381 | env->CP0_WatchHi[7] = 0; |
| 382 | } |
| 383 | /* Count register increments in debug mode, EJTAG version 1 */ |
| 384 | env->CP0_Debug = (1 << CP0DB_CNT) | (0x1 << CP0DB_VER); |
| 385 | |
| 386 | cpu_mips_store_count(env, 1); |
| 387 | |
| 388 | if (ase_mt_available(env)) { |
| 389 | int i; |
| 390 | |
| 391 | /* Only TC0 on VPE 0 starts as active. */ |
| 392 | for (i = 0; i < ARRAY_SIZE(env->tcs); i++) { |
| 393 | env->tcs[i].CP0_TCBind = cs->cpu_index << CP0TCBd_CurVPE; |
| 394 | env->tcs[i].CP0_TCHalt = 1; |
| 395 | } |
| 396 | env->active_tc.CP0_TCHalt = 1; |
| 397 | cs->halted = 1; |
| 398 | |
| 399 | if (cs->cpu_index == 0) { |
| 400 | /* VPE0 starts up enabled. */ |
| 401 | cpu->mvp->CP0_MVPControl |= (1 << CP0MVPCo_EVP); |
| 402 | env->CP0_VPEConf0 |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA); |
| 403 | |
| 404 | /* TC0 starts up unhalted. */ |
| 405 | cs->halted = 0; |
| 406 | env->active_tc.CP0_TCHalt = 0; |
| 407 | env->tcs[0].CP0_TCHalt = 0; |
| 408 | /* With thread 0 active. */ |
| 409 | env->active_tc.CP0_TCStatus = (1 << CP0TCSt_A); |
| 410 | env->tcs[0].CP0_TCStatus = (1 << CP0TCSt_A); |
| 411 | } |
| 412 | } |
| 413 | |
| 414 | /* |
| 415 | * Configure default legacy segmentation control. We use this regardless of |
| 416 | * whether segmentation control is presented to the guest. |
| 417 | */ |
| 418 | /* KSeg3 (seg0 0xE0000000..0xFFFFFFFF) */ |
| 419 | env->CP0_SegCtl0 = (CP0SC_AM_MK << CP0SC_AM); |
| 420 | /* KSeg2 (seg1 0xC0000000..0xDFFFFFFF) */ |
| 421 | env->CP0_SegCtl0 |= ((CP0SC_AM_MSK << CP0SC_AM)) << 16; |
| 422 | /* KSeg1 (seg2 0xA0000000..0x9FFFFFFF) */ |
| 423 | env->CP0_SegCtl1 = (0 << CP0SC_PA) | (CP0SC_AM_UK << CP0SC_AM) | |
| 424 | (2 << CP0SC_C); |
| 425 | /* KSeg0 (seg3 0x80000000..0x9FFFFFFF) */ |
| 426 | env->CP0_SegCtl1 |= ((0 << CP0SC_PA) | (CP0SC_AM_UK << CP0SC_AM) | |
| 427 | (3 << CP0SC_C)) << 16; |
| 428 | /* USeg (seg4 0x40000000..0x7FFFFFFF) */ |
| 429 | env->CP0_SegCtl2 = (2 << CP0SC_PA) | (CP0SC_AM_MUSK << CP0SC_AM) | |
| 430 | (1 << CP0SC_EU) | (2 << CP0SC_C); |
| 431 | /* USeg (seg5 0x00000000..0x3FFFFFFF) */ |
| 432 | env->CP0_SegCtl2 |= ((0 << CP0SC_PA) | (CP0SC_AM_MUSK << CP0SC_AM) | |
| 433 | (1 << CP0SC_EU) | (2 << CP0SC_C)) << 16; |
| 434 | /* XKPhys (note, SegCtl2.XR = 0, so XAM won't be used) */ |
| 435 | env->CP0_SegCtl1 |= (CP0SC_AM_UK << CP0SC1_XAM); |
| 436 | #endif /* !CONFIG_USER_ONLY */ |
| 437 | if ((env->insn_flags & ISA_MIPS_R6) && |
| 438 | (env->active_fpu.fcr0 & (1 << FCR0_F64))) { |
| 439 | /* Status.FR = 0 mode in 64-bit FPU not allowed in R6 */ |
| 440 | env->CP0_Status |= (1 << CP0St_FR); |
| 441 | } |
| 442 | |
| 443 | if (env->insn_flags & ISA_MIPS_R6) { |
| 444 | /* PTW = 1 */ |
| 445 | env->CP0_PWSize = 0x40; |
| 446 | /* GDI = 12 */ |
| 447 | /* UDI = 12 */ |
| 448 | /* MDI = 12 */ |
| 449 | /* PRI = 12 */ |
| 450 | /* PTEI = 2 */ |
| 451 | env->CP0_PWField = 0x0C30C302; |
| 452 | } else { |
| 453 | /* GDI = 0 */ |
| 454 | /* UDI = 0 */ |
| 455 | /* MDI = 0 */ |
| 456 | /* PRI = 0 */ |
| 457 | /* PTEI = 2 */ |
| 458 | env->CP0_PWField = 0x02; |
| 459 | } |
| 460 | |
| 461 | if (env->CP0_Config3 & (1 << CP0C3_ISA) & (1 << (CP0C3_ISA + 1))) { |
| 462 | /* microMIPS on reset when Config3.ISA is 3 */ |
| 463 | env->hflags |= MIPS_HFLAG_M16; |
| 464 | } |
| 465 | |
| 466 | msa_reset(env); |
| 467 | fp_reset(env); |
| 468 | |
| 469 | compute_hflags(env); |
| 470 | restore_pamask(env); |
| 471 | cs->exception_index = EXCP_NONE; |
| 472 | |
| 473 | #ifndef CONFIG_USER_ONLY |
| 474 | if (semihosting_get_argc()) { |
| 475 | /* UHI interface can be used to obtain argc and argv */ |
| 476 | env->active_tc.gpr[4] = -1; |
| 477 | } |
| 478 | #endif |
| 479 | } |
| 480 | |
| 481 | static void mips_cpu_finalize(Object *obj) |
| 482 | { |
| 483 | MIPSCPU *cpu = MIPS_CPU(obj); |
| 484 | |
| 485 | mips_octeon_destroy_llm_state(&cpu->env.octeon_crypto); |
| 486 | } |
| 487 | |
| 488 | static void mips_cpu_disas_set_info(const CPUState *cs, disassemble_info *info) |
| 489 | { |
| 490 | const MIPSCPU *cpu = MIPS_CPU(cs); |
| 491 | const CPUMIPSState *env = &cpu->env; |
| 492 | bool is64 = env->hflags & MIPS_HFLAG_64; |
| 493 | int cap_mode = 0; |
| 494 | |
| 495 | if (env->insn_flags & ISA_NANOMIPS32) { |
| 496 | info->print_insn = print_insn_nanomips; |
| 497 | info->endian = BFD_ENDIAN_LITTLE; |
| 498 | /* nanomips has 16, 32 and 48-bit insns */ |
| 499 | info->cap_insn_unit = 2; |
| 500 | info->cap_insn_split = 6; |
| 501 | cap_mode = CS_MODE_NANOMIPS; |
| 502 | } else { |
| 503 | info->endian = TARGET_BIG_ENDIAN ? BFD_ENDIAN_BIG |
| 504 | : BFD_ENDIAN_LITTLE; |
| 505 | info->print_insn = TARGET_BIG_ENDIAN ? print_insn_big_mips |
| 506 | : print_insn_little_mips; |
| 507 | |
| 508 | if (env->hflags & MIPS_HFLAG_M16) { |
| 509 | cap_mode = (env->insn_flags & ASE_MICROMIPS |
| 510 | ? CS_MODE_MICRO : CS_MODE_MIPS16); |
| 511 | /* Beware unsupported capstone mode */ |
| 512 | if (cap_mode == 0) { |
| 513 | return; |
| 514 | } |
| 515 | info->cap_insn_unit = 2; |
| 516 | } else { |
| 517 | info->cap_insn_unit = 4; |
| 518 | } |
| 519 | info->cap_insn_split = 4; |
| 520 | |
| 521 | cap_mode |= is64 ? CS_MODE_MIPS64 : CS_MODE_MIPS32; |
| 522 | if (env->insn_flags & ISA_MIPS_R6) { |
| 523 | cap_mode |= is64 ? CS_MODE_MIPS64R6 : CS_MODE_MIPS32R6; |
| 524 | } else if (env->insn_flags & ISA_MIPS_R5) { |
| 525 | cap_mode |= is64 ? CS_MODE_MIPS64R5 : CS_MODE_MIPS32R5; |
| 526 | } else if (env->insn_flags & ISA_MIPS_R3) { |
| 527 | cap_mode |= is64 ? CS_MODE_MIPS64R3 : CS_MODE_MIPS32R3; |
| 528 | } else if (env->insn_flags & ISA_MIPS_R2) { |
| 529 | cap_mode |= is64 ? CS_MODE_MIPS64R2 : CS_MODE_MIPS32R2; |
| 530 | } else if (env->insn_flags & ISA_MIPS5) { |
| 531 | cap_mode |= CS_MODE_MIPS5; |
| 532 | } else if (env->insn_flags & ISA_MIPS4) { |
| 533 | cap_mode |= CS_MODE_MIPS4; |
| 534 | } else if (env->insn_flags & ISA_MIPS3) { |
| 535 | cap_mode |= CS_MODE_MIPS3; |
| 536 | } else if (env->insn_flags & ISA_MIPS2) { |
| 537 | cap_mode |= CS_MODE_MIPS2; |
| 538 | } else if (env->insn_flags & ISA_MIPS1) { |
| 539 | cap_mode |= CS_MODE_MIPS1; |
| 540 | } |
| 541 | if (env->insn_flags & INSN_OCTEON) { |
| 542 | cap_mode |= CS_MODE_OCTEON | CS_MODE_OCTEONP; |
| 543 | } |
| 544 | if (is64 && !(env->hflags & MIPS_HFLAG_AWRAP)) { |
| 545 | cap_mode |= CS_MODE_MIPS_PTR64; |
| 546 | } |
| 547 | } |
| 548 | /* Beware unsupported capstone mode */ |
| 549 | if (cap_mode) { |
| 550 | info->cap_arch = CS_ARCH_MIPS; |
| 551 | info->cap_mode = cap_mode; |
| 552 | } |
| 553 | } |
| 554 | |
| 555 | /* |
| 556 | * Since commit 6af0bf9c7c3 this model assumes a CPU clocked at 200MHz. |
| 557 | */ |
| 558 | #define CPU_FREQ_HZ_DEFAULT 200000000 |
| 559 | |
| 560 | static void mips_cp0_period_set(MIPSCPU *cpu) |
| 561 | { |
| 562 | CPUMIPSState *env = &cpu->env; |
| 563 | |
| 564 | clock_set_mul_div(cpu->count_div, env->cpu_model->CCRes, 1); |
| 565 | clock_set_source(cpu->count_div, cpu->clock); |
| 566 | clock_set_source(cpu->count_clock, cpu->count_div); |
| 567 | } |
| 568 | |
| 569 | static void mips_cpu_realizefn(DeviceState *dev, Error **errp) |
| 570 | { |
| 571 | CPUState *cs = CPU(dev); |
| 572 | MIPSCPU *cpu = MIPS_CPU(dev); |
| 573 | CPUMIPSState *env = &cpu->env; |
| 574 | MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(dev); |
| 575 | Error *local_err = NULL; |
| 576 | |
| 577 | #ifndef CONFIG_USER_ONLY |
| 578 | if (mcc->cpu_def->lcsr_cpucfg2 & (1 << CPUCFG2_LCSRP)) { |
| 579 | memory_region_init_io(&env->iocsr.mr, OBJECT(cpu), NULL, |
| 580 | env, "iocsr", UINT64_MAX); |
| 581 | address_space_init(&env->iocsr.as, &env->iocsr.mr, "IOCSR"); |
| 582 | } |
| 583 | #endif |
| 584 | |
| 585 | if (!clock_get(cpu->clock)) { |
| 586 | #ifndef CONFIG_USER_ONLY |
| 587 | if (!qtest_enabled()) { |
| 588 | g_autofree char *cpu_freq_str = freq_to_str(CPU_FREQ_HZ_DEFAULT); |
| 589 | |
| 590 | warn_report("CPU input clock is not connected to any output clock, " |
| 591 | "using default frequency of %s.", cpu_freq_str); |
| 592 | } |
| 593 | #endif |
| 594 | /* Initialize the frequency in case the clock remains unconnected. */ |
| 595 | clock_set_hz(cpu->clock, CPU_FREQ_HZ_DEFAULT); |
| 596 | } |
| 597 | mips_cp0_period_set(cpu); |
| 598 | |
| 599 | cpu_common_realize(cs, &local_err); |
| 600 | if (local_err != NULL) { |
| 601 | error_propagate(errp, local_err); |
| 602 | return; |
| 603 | } |
| 604 | |
| 605 | env->exception_base = (int32_t)0xBFC00000; |
| 606 | |
| 607 | #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) |
| 608 | mmu_init(env, env->cpu_model); |
| 609 | #endif |
| 610 | fpu_init(env, env->cpu_model); |
| 611 | mvp_init(env); |
| 612 | |
| 613 | cpu_reset(cs); |
| 614 | qemu_init_vcpu(cs); |
| 615 | |
| 616 | mcc->parent_realize(dev, errp); |
| 617 | } |
| 618 | |
| 619 | static void mips_cpu_unrealizefn(DeviceState *dev) |
| 620 | { |
| 621 | MIPSCPU *cpu = MIPS_CPU(dev); |
| 622 | MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(dev); |
| 623 | |
| 624 | g_free(cpu->mvp); |
| 625 | |
| 626 | mcc->parent_unrealize(dev); |
| 627 | } |
| 628 | |
| 629 | static void mips_cpu_initfn(Object *obj) |
| 630 | { |
| 631 | MIPSCPU *cpu = MIPS_CPU(obj); |
| 632 | CPUMIPSState *env = &cpu->env; |
| 633 | MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(obj); |
| 634 | |
| 635 | cpu->clock = qdev_init_clock_in(DEVICE(obj), "clk-in", NULL, cpu, 0); |
| 636 | cpu->count_div = clock_new(OBJECT(obj), "clk-div-count"); |
| 637 | cpu->count_clock = clock_new(OBJECT(obj), "clk-count"); |
| 638 | env->cpu_model = mcc->cpu_def; |
| 639 | } |
| 640 | |
| 641 | static char *mips_cpu_type_name(const char *cpu_model) |
| 642 | { |
| 643 | return g_strdup_printf(MIPS_CPU_TYPE_NAME("%s"), cpu_model); |
| 644 | } |
| 645 | |
| 646 | static ObjectClass *mips_cpu_class_by_name(const char *cpu_model) |
| 647 | { |
| 648 | ObjectClass *oc; |
| 649 | char *typename; |
| 650 | |
| 651 | typename = mips_cpu_type_name(cpu_model); |
| 652 | oc = object_class_by_name(typename); |
| 653 | g_free(typename); |
| 654 | return oc; |
| 655 | } |
| 656 | |
| 657 | #ifndef CONFIG_USER_ONLY |
| 658 | #include "hw/core/sysemu-cpu-ops.h" |
| 659 | |
| 660 | static const struct SysemuCPUOps mips_sysemu_ops = { |
| 661 | .has_work = mips_cpu_has_work, |
| 662 | .get_phys_addr_debug = mips_cpu_get_phys_addr_debug, |
| 663 | .legacy_vmsd = &vmstate_mips_cpu, |
| 664 | }; |
| 665 | #endif |
| 666 | |
| 667 | static const Property mips_cpu_properties[] = { |
| 668 | DEFINE_PROP_BOOL("big-endian", MIPSCPU, is_big_endian, TARGET_BIG_ENDIAN), |
| 669 | }; |
| 670 | |
| 671 | #ifdef CONFIG_TCG |
| 672 | #include "accel/tcg/cpu-ops.h" |
| 673 | |
| 674 | static int mips_cpu_mmu_index(CPUState *cs, bool ifunc) |
| 675 | { |
| 676 | return mips_env_mmu_index(cpu_env(cs)); |
| 677 | } |
| 678 | |
| 679 | static TCGTBCPUState mips_get_tb_cpu_state(CPUState *cs) |
| 680 | { |
| 681 | CPUMIPSState *env = cpu_env(cs); |
| 682 | uint32_t flags = env->hflags & MIPS_HFLAG_TB_MASK; |
| 683 | |
| 684 | #ifdef CONFIG_USER_ONLY |
| 685 | if (!cs->prctl_unalign_sigbus) { |
| 686 | flags |= TB_FLAG_MIPS_FIXADE; |
| 687 | } |
| 688 | #endif |
| 689 | |
| 690 | return (TCGTBCPUState){ |
| 691 | .pc = env->active_tc.PC, |
| 692 | .flags = flags, |
| 693 | }; |
| 694 | } |
| 695 | |
| 696 | #ifndef CONFIG_USER_ONLY |
| 697 | static vaddr mips_pointer_wrap(CPUState *cs, int mmu_idx, |
| 698 | vaddr result, vaddr base) |
| 699 | { |
| 700 | return cpu_env(cs)->hflags & MIPS_HFLAG_AWRAP ? (int32_t)result : result; |
| 701 | } |
| 702 | #endif |
| 703 | |
| 704 | static const TCGCPUOps mips_tcg_ops = { |
| 705 | .mttcg_supported = TARGET_LONG_BITS == 32, |
| 706 | .guest_default_memory_order = 0, |
| 707 | |
| 708 | .initialize = mips_tcg_init, |
| 709 | .translate_code = mips_translate_code, |
| 710 | .get_tb_cpu_state = mips_get_tb_cpu_state, |
| 711 | .synchronize_from_tb = mips_cpu_synchronize_from_tb, |
| 712 | .restore_state_to_opc = mips_restore_state_to_opc, |
| 713 | .mmu_index = mips_cpu_mmu_index, |
| 714 | |
| 715 | #if !defined(CONFIG_USER_ONLY) |
| 716 | .tlb_fill = mips_cpu_tlb_fill, |
| 717 | .pointer_wrap = mips_pointer_wrap, |
| 718 | .cpu_exec_interrupt = mips_cpu_exec_interrupt, |
| 719 | .cpu_exec_halt = mips_cpu_has_work, |
| 720 | .cpu_exec_reset = cpu_reset, |
| 721 | .do_interrupt = mips_cpu_do_interrupt, |
| 722 | .do_transaction_failed = mips_cpu_do_transaction_failed, |
| 723 | .do_unaligned_access = mips_cpu_do_unaligned_access, |
| 724 | .io_recompile_replay_branch = mips_io_recompile_replay_branch, |
| 725 | #endif /* !CONFIG_USER_ONLY */ |
| 726 | }; |
| 727 | #endif /* CONFIG_TCG */ |
| 728 | |
| 729 | static void mips_cpu_class_init(ObjectClass *c, const void *data) |
| 730 | { |
| 731 | MIPSCPUClass *mcc = MIPS_CPU_CLASS(c); |
| 732 | CPUClass *cc = CPU_CLASS(c); |
| 733 | DeviceClass *dc = DEVICE_CLASS(c); |
| 734 | ResettableClass *rc = RESETTABLE_CLASS(c); |
| 735 | |
| 736 | device_class_set_props(dc, mips_cpu_properties); |
| 737 | device_class_set_parent_realize(dc, mips_cpu_realizefn, |
| 738 | &mcc->parent_realize); |
| 739 | device_class_set_parent_unrealize(dc, mips_cpu_unrealizefn, |
| 740 | &mcc->parent_unrealize); |
| 741 | resettable_class_set_parent_phases(rc, NULL, mips_cpu_reset_hold, NULL, |
| 742 | &mcc->parent_phases); |
| 743 | |
| 744 | cc->class_by_name = mips_cpu_class_by_name; |
| 745 | cc->dump_state = mips_cpu_dump_state; |
| 746 | cc->set_pc = mips_cpu_set_pc; |
| 747 | cc->get_pc = mips_cpu_get_pc; |
| 748 | cc->gdb_read_register = mips_cpu_gdb_read_register; |
| 749 | cc->gdb_write_register = mips_cpu_gdb_write_register; |
| 750 | #ifndef CONFIG_USER_ONLY |
| 751 | cc->sysemu_ops = &mips_sysemu_ops; |
| 752 | #endif |
| 753 | cc->disas_set_info = mips_cpu_disas_set_info; |
| 754 | cc->gdb_num_core_regs = 73; |
| 755 | cc->gdb_stop_before_watchpoint = true; |
| 756 | #ifdef CONFIG_TCG |
| 757 | cc->tcg_ops = &mips_tcg_ops; |
| 758 | #endif /* CONFIG_TCG */ |
| 759 | } |
| 760 | |
| 761 | static const TypeInfo mips_cpu_type_info = { |
| 762 | .name = TYPE_MIPS_CPU, |
| 763 | .parent = TYPE_CPU, |
| 764 | .instance_size = sizeof(MIPSCPU), |
| 765 | .instance_align = __alignof(MIPSCPU), |
| 766 | .instance_init = mips_cpu_initfn, |
| 767 | .instance_finalize = mips_cpu_finalize, |
| 768 | .abstract = true, |
| 769 | .class_size = sizeof(MIPSCPUClass), |
| 770 | .class_init = mips_cpu_class_init, |
| 771 | }; |
| 772 | |
| 773 | static void mips_cpu_cpudef_class_init(ObjectClass *oc, const void *data) |
| 774 | { |
| 775 | MIPSCPUClass *mcc = MIPS_CPU_CLASS(oc); |
| 776 | mcc->cpu_def = data; |
| 777 | } |
| 778 | |
| 779 | static void mips_register_cpudef_type(const struct mips_def_t *def) |
| 780 | { |
| 781 | char *typename = mips_cpu_type_name(def->name); |
| 782 | TypeInfo ti = { |
| 783 | .name = typename, |
| 784 | .parent = TYPE_MIPS_CPU, |
| 785 | .class_init = mips_cpu_cpudef_class_init, |
| 786 | .class_data = def, |
| 787 | }; |
| 788 | |
| 789 | type_register_static(&ti); |
| 790 | g_free(typename); |
| 791 | } |
| 792 | |
| 793 | static void mips_cpu_register_types(void) |
| 794 | { |
| 795 | int i; |
| 796 | |
| 797 | type_register_static(&mips_cpu_type_info); |
| 798 | for (i = 0; i < mips_defs_number; i++) { |
| 799 | mips_register_cpudef_type(&mips_defs[i]); |
| 800 | } |
| 801 | } |
| 802 | |
| 803 | type_init(mips_cpu_register_types) |
| 804 | |
| 805 | /* Could be used by generic CPU object */ |
| 806 | MIPSCPU *mips_cpu_create_with_clock(const char *cpu_type, Clock *cpu_refclk, |
| 807 | bool is_big_endian) |
| 808 | { |
| 809 | DeviceState *cpu; |
| 810 | |
| 811 | cpu = qdev_new(cpu_type); |
| 812 | qdev_connect_clock_in(cpu, "clk-in", cpu_refclk); |
| 813 | object_property_set_bool(OBJECT(cpu), "big-endian", is_big_endian, |
| 814 | &error_abort); |
| 815 | qdev_realize(cpu, NULL, &error_abort); |
| 816 | |
| 817 | return MIPS_CPU(cpu); |
| 818 | } |
| 819 | |
| 820 | bool cpu_supports_isa(const CPUMIPSState *env, uint64_t isa_mask) |
| 821 | { |
| 822 | return (env->cpu_model->insn_flags & isa_mask) != 0; |
| 823 | } |
| 824 | |
| 825 | bool cpu_type_supports_isa(const char *cpu_type, uint64_t isa) |
| 826 | { |
| 827 | const MIPSCPUClass *mcc = MIPS_CPU_CLASS(object_class_by_name(cpu_type)); |
| 828 | return (mcc->cpu_def->insn_flags & isa) != 0; |
| 829 | } |
| 830 | |
| 831 | bool cpu_type_supports_cps_smp(const char *cpu_type) |
| 832 | { |
| 833 | const MIPSCPUClass *mcc = MIPS_CPU_CLASS(object_class_by_name(cpu_type)); |
| 834 | return (mcc->cpu_def->CP0_Config3 & (1 << CP0C3_CMGCR)) != 0; |
| 835 | } |