| 1 | #ifndef MIPS_CPU_H |
| 2 | #define MIPS_CPU_H |
| 3 | |
| 4 | #include "cpu-qom.h" |
| 5 | #include "exec/cpu-common.h" |
| 6 | #include "exec/cpu-interrupt.h" |
| 7 | #include "exec/target_long.h" |
| 8 | #ifndef CONFIG_USER_ONLY |
| 9 | #include "system/memory.h" |
| 10 | #endif |
| 11 | #include "fpu/softfloat-types.h" |
| 12 | #include "hw/core/clock.h" |
| 13 | #include "mips-defs.h" |
| 14 | #include "qemu/qtree.h" |
| 15 | |
| 16 | typedef struct CPUMIPSTLBContext CPUMIPSTLBContext; |
| 17 | |
| 18 | /* MSA Context */ |
| 19 | #define MSA_WRLEN (128) |
| 20 | |
| 21 | typedef union wr_t wr_t; |
| 22 | union wr_t { |
| 23 | int8_t b[MSA_WRLEN / 8]; |
| 24 | int16_t h[MSA_WRLEN / 16]; |
| 25 | int32_t w[MSA_WRLEN / 32]; |
| 26 | int64_t d[MSA_WRLEN / 64]; |
| 27 | }; |
| 28 | |
| 29 | typedef union fpr_t fpr_t; |
| 30 | union fpr_t { |
| 31 | float64 fd; /* ieee double precision */ |
| 32 | float32 fs[2];/* ieee single precision */ |
| 33 | uint64_t d; /* binary double fixed-point */ |
| 34 | uint32_t w[2]; /* binary single fixed-point */ |
| 35 | /* FPU/MSA register mapping is not tested on big-endian hosts. */ |
| 36 | wr_t wr; /* vector data */ |
| 37 | }; |
| 38 | /* |
| 39 | *define FP_ENDIAN_IDX to access the same location |
| 40 | * in the fpr_t union regardless of the host endianness |
| 41 | */ |
| 42 | #if HOST_BIG_ENDIAN |
| 43 | # define FP_ENDIAN_IDX 1 |
| 44 | #else |
| 45 | # define FP_ENDIAN_IDX 0 |
| 46 | #endif |
| 47 | |
| 48 | typedef struct CPUMIPSFPUContext CPUMIPSFPUContext; |
| 49 | struct CPUMIPSFPUContext { |
| 50 | /* Floating point registers */ |
| 51 | fpr_t fpr[32]; |
| 52 | float_status fp_status; |
| 53 | /* fpu implementation/revision register (fir) */ |
| 54 | uint32_t fcr0; |
| 55 | #define FCR0_FREP 29 |
| 56 | #define FCR0_UFRP 28 |
| 57 | #define FCR0_HAS2008 23 |
| 58 | #define FCR0_F64 22 |
| 59 | #define FCR0_L 21 |
| 60 | #define FCR0_W 20 |
| 61 | #define FCR0_3D 19 |
| 62 | #define FCR0_PS 18 |
| 63 | #define FCR0_D 17 |
| 64 | #define FCR0_S 16 |
| 65 | #define FCR0_PRID 8 |
| 66 | #define FCR0_REV 0 |
| 67 | /* fcsr */ |
| 68 | uint32_t fcr31_rw_bitmask; |
| 69 | uint32_t fcr31; |
| 70 | #define FCR31_FS 24 |
| 71 | #define FCR31_ABS2008 19 |
| 72 | #define FCR31_NAN2008 18 |
| 73 | #define SET_FP_COND(num, env) do { ((env).fcr31) |= \ |
| 74 | ((num) ? (1 << ((num) + 24)) : \ |
| 75 | (1 << 23)); \ |
| 76 | } while (0) |
| 77 | #define CLEAR_FP_COND(num, env) do { ((env).fcr31) &= \ |
| 78 | ~((num) ? (1 << ((num) + 24)) : \ |
| 79 | (1 << 23)); \ |
| 80 | } while (0) |
| 81 | #define GET_FP_COND(env) ((((env).fcr31 >> 24) & 0xfe) | \ |
| 82 | (((env).fcr31 >> 23) & 0x1)) |
| 83 | #define GET_FP_CAUSE(reg) (((reg) >> 12) & 0x3f) |
| 84 | #define GET_FP_ENABLE(reg) (((reg) >> 7) & 0x1f) |
| 85 | #define GET_FP_FLAGS(reg) (((reg) >> 2) & 0x1f) |
| 86 | #define SET_FP_CAUSE(reg, v) do { (reg) = ((reg) & ~(0x3f << 12)) | \ |
| 87 | ((v & 0x3f) << 12); \ |
| 88 | } while (0) |
| 89 | #define SET_FP_ENABLE(reg, v) do { (reg) = ((reg) & ~(0x1f << 7)) | \ |
| 90 | ((v & 0x1f) << 7); \ |
| 91 | } while (0) |
| 92 | #define SET_FP_FLAGS(reg, v) do { (reg) = ((reg) & ~(0x1f << 2)) | \ |
| 93 | ((v & 0x1f) << 2); \ |
| 94 | } while (0) |
| 95 | #define UPDATE_FP_FLAGS(reg, v) do { (reg) |= ((v & 0x1f) << 2); } while (0) |
| 96 | #define FP_INEXACT 1 |
| 97 | #define FP_UNDERFLOW 2 |
| 98 | #define FP_OVERFLOW 4 |
| 99 | #define FP_DIV0 8 |
| 100 | #define FP_INVALID 16 |
| 101 | #define FP_UNIMPLEMENTED 32 |
| 102 | }; |
| 103 | |
| 104 | typedef struct CPUMIPSMVPContext CPUMIPSMVPContext; |
| 105 | struct CPUMIPSMVPContext { |
| 106 | int32_t CP0_MVPControl; |
| 107 | #define CP0MVPCo_CPA 3 |
| 108 | #define CP0MVPCo_STLB 2 |
| 109 | #define CP0MVPCo_VPC 1 |
| 110 | #define CP0MVPCo_EVP 0 |
| 111 | int32_t CP0_MVPConf0; |
| 112 | #define CP0MVPC0_M 31 |
| 113 | #define CP0MVPC0_TLBS 29 |
| 114 | #define CP0MVPC0_GS 28 |
| 115 | #define CP0MVPC0_PCP 27 |
| 116 | #define CP0MVPC0_PTLBE 16 |
| 117 | #define CP0MVPC0_TCA 15 |
| 118 | #define CP0MVPC0_PVPE 10 |
| 119 | #define CP0MVPC0_PTC 0 |
| 120 | int32_t CP0_MVPConf1; |
| 121 | #define CP0MVPC1_CIM 31 |
| 122 | #define CP0MVPC1_CIF 30 |
| 123 | #define CP0MVPC1_PCX 20 |
| 124 | #define CP0MVPC1_PCP2 10 |
| 125 | #define CP0MVPC1_PCP1 0 |
| 126 | }; |
| 127 | |
| 128 | typedef struct mips_def_t mips_def_t; |
| 129 | |
| 130 | #define MIPS_SHADOW_SET_MAX 16 |
| 131 | #define MIPS_TC_MAX 5 |
| 132 | #define MIPS_FPU_MAX 1 |
| 133 | #define MIPS_DSP_ACC 4 |
| 134 | #define MIPS_KSCRATCH_NUM 6 |
| 135 | #define MIPS_MAAR_MAX 16 /* Must be an even number. */ |
| 136 | |
| 137 | |
| 138 | /* |
| 139 | * Summary of CP0 registers |
| 140 | * ======================== |
| 141 | * |
| 142 | * |
| 143 | * Register 0 Register 1 Register 2 Register 3 |
| 144 | * ---------- ---------- ---------- ---------- |
| 145 | * |
| 146 | * 0 Index Random EntryLo0 EntryLo1 |
| 147 | * 1 MVPControl VPEControl TCStatus GlobalNumber |
| 148 | * 2 MVPConf0 VPEConf0 TCBind |
| 149 | * 3 MVPConf1 VPEConf1 TCRestart |
| 150 | * 4 VPControl YQMask TCHalt |
| 151 | * 5 VPESchedule TCContext |
| 152 | * 6 VPEScheFBack TCSchedule |
| 153 | * 7 VPEOpt TCScheFBack TCOpt |
| 154 | * |
| 155 | * |
| 156 | * Register 4 Register 5 Register 6 Register 7 |
| 157 | * ---------- ---------- ---------- ---------- |
| 158 | * |
| 159 | * 0 Context PageMask Wired HWREna |
| 160 | * 1 ContextConfig PageGrain SRSConf0 |
| 161 | * 2 UserLocal SegCtl0 SRSConf1 |
| 162 | * 3 XContextConfig SegCtl1 SRSConf2 |
| 163 | * 4 DebugContextID SegCtl2 SRSConf3 |
| 164 | * 5 MemoryMapID PWBase SRSConf4 |
| 165 | * 6 PWField PWCtl |
| 166 | * 7 PWSize |
| 167 | * |
| 168 | * |
| 169 | * Register 8 Register 9 Register 10 Register 11 |
| 170 | * ---------- ---------- ----------- ----------- |
| 171 | * |
| 172 | * 0 BadVAddr Count EntryHi Compare |
| 173 | * 1 BadInstr |
| 174 | * 2 BadInstrP |
| 175 | * 3 BadInstrX |
| 176 | * 4 GuestCtl1 GuestCtl0Ext |
| 177 | * 5 GuestCtl2 |
| 178 | * 6 SAARI GuestCtl3 |
| 179 | * 7 SAAR |
| 180 | * |
| 181 | * |
| 182 | * Register 12 Register 13 Register 14 Register 15 |
| 183 | * ----------- ----------- ----------- ----------- |
| 184 | * |
| 185 | * 0 Status Cause EPC PRId |
| 186 | * 1 IntCtl EBase |
| 187 | * 2 SRSCtl NestedEPC CDMMBase |
| 188 | * 3 SRSMap CMGCRBase |
| 189 | * 4 View_IPL View_RIPL BEVVA |
| 190 | * 5 SRSMap2 NestedExc |
| 191 | * 6 GuestCtl0 |
| 192 | * 7 GTOffset |
| 193 | * |
| 194 | * |
| 195 | * Register 16 Register 17 Register 18 Register 19 |
| 196 | * ----------- ----------- ----------- ----------- |
| 197 | * |
| 198 | * 0 Config LLAddr WatchLo0 WatchHi |
| 199 | * 1 Config1 MAAR WatchLo1 WatchHi |
| 200 | * 2 Config2 MAARI WatchLo2 WatchHi |
| 201 | * 3 Config3 WatchLo3 WatchHi |
| 202 | * 4 Config4 WatchLo4 WatchHi |
| 203 | * 5 Config5 WatchLo5 WatchHi |
| 204 | * 6 Config6 WatchLo6 WatchHi |
| 205 | * 7 Config7 WatchLo7 WatchHi |
| 206 | * |
| 207 | * |
| 208 | * Register 20 Register 21 Register 22 Register 23 |
| 209 | * ----------- ----------- ----------- ----------- |
| 210 | * |
| 211 | * 0 XContext Debug |
| 212 | * 1 TraceControl |
| 213 | * 2 TraceControl2 |
| 214 | * 3 UserTraceData1 |
| 215 | * 4 TraceIBPC |
| 216 | * 5 TraceDBPC |
| 217 | * 6 Debug2 |
| 218 | * 7 |
| 219 | * |
| 220 | * |
| 221 | * Register 24 Register 25 Register 26 Register 27 |
| 222 | * ----------- ----------- ----------- ----------- |
| 223 | * |
| 224 | * 0 DEPC PerfCnt ErrCtl CacheErr |
| 225 | * 1 PerfCnt |
| 226 | * 2 TraceControl3 PerfCnt |
| 227 | * 3 UserTraceData2 PerfCnt |
| 228 | * 4 PerfCnt |
| 229 | * 5 PerfCnt |
| 230 | * 6 PerfCnt |
| 231 | * 7 PerfCnt |
| 232 | * |
| 233 | * |
| 234 | * Register 28 Register 29 Register 30 Register 31 |
| 235 | * ----------- ----------- ----------- ----------- |
| 236 | * |
| 237 | * 0 DataLo DataHi ErrorEPC DESAVE |
| 238 | * 1 TagLo TagHi |
| 239 | * 2 DataLo1 DataHi1 KScratch<n> |
| 240 | * 3 TagLo1 TagHi1 KScratch<n> |
| 241 | * 4 DataLo2 DataHi2 KScratch<n> |
| 242 | * 5 TagLo2 TagHi2 KScratch<n> |
| 243 | * 6 DataLo3 DataHi3 KScratch<n> |
| 244 | * 7 TagLo3 TagHi3 KScratch<n> |
| 245 | * |
| 246 | */ |
| 247 | #define CP0_REGISTER_00 0 |
| 248 | #define CP0_REGISTER_01 1 |
| 249 | #define CP0_REGISTER_02 2 |
| 250 | #define CP0_REGISTER_03 3 |
| 251 | #define CP0_REGISTER_04 4 |
| 252 | #define CP0_REGISTER_05 5 |
| 253 | #define CP0_REGISTER_06 6 |
| 254 | #define CP0_REGISTER_07 7 |
| 255 | #define CP0_REGISTER_08 8 |
| 256 | #define CP0_REGISTER_09 9 |
| 257 | #define CP0_REGISTER_10 10 |
| 258 | #define CP0_REGISTER_11 11 |
| 259 | #define CP0_REGISTER_12 12 |
| 260 | #define CP0_REGISTER_13 13 |
| 261 | #define CP0_REGISTER_14 14 |
| 262 | #define CP0_REGISTER_15 15 |
| 263 | #define CP0_REGISTER_16 16 |
| 264 | #define CP0_REGISTER_17 17 |
| 265 | #define CP0_REGISTER_18 18 |
| 266 | #define CP0_REGISTER_19 19 |
| 267 | #define CP0_REGISTER_20 20 |
| 268 | #define CP0_REGISTER_21 21 |
| 269 | #define CP0_REGISTER_22 22 |
| 270 | #define CP0_REGISTER_23 23 |
| 271 | #define CP0_REGISTER_24 24 |
| 272 | #define CP0_REGISTER_25 25 |
| 273 | #define CP0_REGISTER_26 26 |
| 274 | #define CP0_REGISTER_27 27 |
| 275 | #define CP0_REGISTER_28 28 |
| 276 | #define CP0_REGISTER_29 29 |
| 277 | #define CP0_REGISTER_30 30 |
| 278 | #define CP0_REGISTER_31 31 |
| 279 | |
| 280 | |
| 281 | /* CP0 Register 00 */ |
| 282 | #define CP0_REG00__INDEX 0 |
| 283 | #define CP0_REG00__MVPCONTROL 1 |
| 284 | #define CP0_REG00__MVPCONF0 2 |
| 285 | #define CP0_REG00__MVPCONF1 3 |
| 286 | #define CP0_REG00__VPCONTROL 4 |
| 287 | /* CP0 Register 01 */ |
| 288 | #define CP0_REG01__RANDOM 0 |
| 289 | #define CP0_REG01__VPECONTROL 1 |
| 290 | #define CP0_REG01__VPECONF0 2 |
| 291 | #define CP0_REG01__VPECONF1 3 |
| 292 | #define CP0_REG01__YQMASK 4 |
| 293 | #define CP0_REG01__VPESCHEDULE 5 |
| 294 | #define CP0_REG01__VPESCHEFBACK 6 |
| 295 | #define CP0_REG01__VPEOPT 7 |
| 296 | /* CP0 Register 02 */ |
| 297 | #define CP0_REG02__ENTRYLO0 0 |
| 298 | #define CP0_REG02__TCSTATUS 1 |
| 299 | #define CP0_REG02__TCBIND 2 |
| 300 | #define CP0_REG02__TCRESTART 3 |
| 301 | #define CP0_REG02__TCHALT 4 |
| 302 | #define CP0_REG02__TCCONTEXT 5 |
| 303 | #define CP0_REG02__TCSCHEDULE 6 |
| 304 | #define CP0_REG02__TCSCHEFBACK 7 |
| 305 | /* CP0 Register 03 */ |
| 306 | #define CP0_REG03__ENTRYLO1 0 |
| 307 | #define CP0_REG03__GLOBALNUM 1 |
| 308 | #define CP0_REG03__TCOPT 7 |
| 309 | /* CP0 Register 04 */ |
| 310 | #define CP0_REG04__CONTEXT 0 |
| 311 | #define CP0_REG04__CONTEXTCONFIG 1 |
| 312 | #define CP0_REG04__USERLOCAL 2 |
| 313 | #define CP0_REG04__XCONTEXTCONFIG 3 |
| 314 | #define CP0_REG04__DBGCONTEXTID 4 |
| 315 | #define CP0_REG04__MMID 5 |
| 316 | /* CP0 Register 05 */ |
| 317 | #define CP0_REG05__PAGEMASK 0 |
| 318 | #define CP0_REG05__PAGEGRAIN 1 |
| 319 | #define CP0_REG05__SEGCTL0 2 |
| 320 | #define CP0_REG05__SEGCTL1 3 |
| 321 | #define CP0_REG05__SEGCTL2 4 |
| 322 | #define CP0_REG05__PWBASE 5 |
| 323 | #define CP0_REG05__PWFIELD 6 |
| 324 | #define CP0_REG05__PWSIZE 7 |
| 325 | /* CP0 Register 06 */ |
| 326 | #define CP0_REG06__WIRED 0 |
| 327 | #define CP0_REG06__SRSCONF0 1 |
| 328 | #define CP0_REG06__SRSCONF1 2 |
| 329 | #define CP0_REG06__SRSCONF2 3 |
| 330 | #define CP0_REG06__SRSCONF3 4 |
| 331 | #define CP0_REG06__SRSCONF4 5 |
| 332 | #define CP0_REG06__PWCTL 6 |
| 333 | /* CP0 Register 07 */ |
| 334 | #define CP0_REG07__HWRENA 0 |
| 335 | /* CP0 Register 08 */ |
| 336 | #define CP0_REG08__BADVADDR 0 |
| 337 | #define CP0_REG08__BADINSTR 1 |
| 338 | #define CP0_REG08__BADINSTRP 2 |
| 339 | #define CP0_REG08__BADINSTRX 3 |
| 340 | /* CP0 Register 09 */ |
| 341 | #define CP0_REG09__COUNT 0 |
| 342 | #define CP0_REG09__SAARI 6 |
| 343 | #define CP0_REG09__SAAR 7 |
| 344 | /* CP0 Register 10 */ |
| 345 | #define CP0_REG10__ENTRYHI 0 |
| 346 | #define CP0_REG10__GUESTCTL1 4 |
| 347 | #define CP0_REG10__GUESTCTL2 5 |
| 348 | #define CP0_REG10__GUESTCTL3 6 |
| 349 | /* CP0 Register 11 */ |
| 350 | #define CP0_REG11__COMPARE 0 |
| 351 | #define CP0_REG11__GUESTCTL0EXT 4 |
| 352 | /* CP0 Register 12 */ |
| 353 | #define CP0_REG12__STATUS 0 |
| 354 | #define CP0_REG12__INTCTL 1 |
| 355 | #define CP0_REG12__SRSCTL 2 |
| 356 | #define CP0_REG12__SRSMAP 3 |
| 357 | #define CP0_REG12__VIEW_IPL 4 |
| 358 | #define CP0_REG12__SRSMAP2 5 |
| 359 | #define CP0_REG12__GUESTCTL0 6 |
| 360 | #define CP0_REG12__GTOFFSET 7 |
| 361 | /* CP0 Register 13 */ |
| 362 | #define CP0_REG13__CAUSE 0 |
| 363 | #define CP0_REG13__VIEW_RIPL 4 |
| 364 | #define CP0_REG13__NESTEDEXC 5 |
| 365 | /* CP0 Register 14 */ |
| 366 | #define CP0_REG14__EPC 0 |
| 367 | #define CP0_REG14__NESTEDEPC 2 |
| 368 | /* CP0 Register 15 */ |
| 369 | #define CP0_REG15__PRID 0 |
| 370 | #define CP0_REG15__EBASE 1 |
| 371 | #define CP0_REG15__CDMMBASE 2 |
| 372 | #define CP0_REG15__CMGCRBASE 3 |
| 373 | #define CP0_REG15__BEVVA 4 |
| 374 | /* CP0 Register 16 */ |
| 375 | #define CP0_REG16__CONFIG 0 |
| 376 | #define CP0_REG16__CONFIG1 1 |
| 377 | #define CP0_REG16__CONFIG2 2 |
| 378 | #define CP0_REG16__CONFIG3 3 |
| 379 | #define CP0_REG16__CONFIG4 4 |
| 380 | #define CP0_REG16__CONFIG5 5 |
| 381 | #define CP0_REG16__CONFIG6 6 |
| 382 | #define CP0_REG16__CONFIG7 7 |
| 383 | /* CP0 Register 17 */ |
| 384 | #define CP0_REG17__LLADDR 0 |
| 385 | #define CP0_REG17__MAAR 1 |
| 386 | #define CP0_REG17__MAARI 2 |
| 387 | /* CP0 Register 18 */ |
| 388 | #define CP0_REG18__WATCHLO0 0 |
| 389 | #define CP0_REG18__WATCHLO1 1 |
| 390 | #define CP0_REG18__WATCHLO2 2 |
| 391 | #define CP0_REG18__WATCHLO3 3 |
| 392 | #define CP0_REG18__WATCHLO4 4 |
| 393 | #define CP0_REG18__WATCHLO5 5 |
| 394 | #define CP0_REG18__WATCHLO6 6 |
| 395 | #define CP0_REG18__WATCHLO7 7 |
| 396 | /* CP0 Register 19 */ |
| 397 | #define CP0_REG19__WATCHHI0 0 |
| 398 | #define CP0_REG19__WATCHHI1 1 |
| 399 | #define CP0_REG19__WATCHHI2 2 |
| 400 | #define CP0_REG19__WATCHHI3 3 |
| 401 | #define CP0_REG19__WATCHHI4 4 |
| 402 | #define CP0_REG19__WATCHHI5 5 |
| 403 | #define CP0_REG19__WATCHHI6 6 |
| 404 | #define CP0_REG19__WATCHHI7 7 |
| 405 | /* CP0 Register 20 */ |
| 406 | #define CP0_REG20__XCONTEXT 0 |
| 407 | /* CP0 Register 21 */ |
| 408 | /* CP0 Register 22 */ |
| 409 | /* CP0 Register 23 */ |
| 410 | #define CP0_REG23__DEBUG 0 |
| 411 | #define CP0_REG23__TRACECONTROL 1 |
| 412 | #define CP0_REG23__TRACECONTROL2 2 |
| 413 | #define CP0_REG23__USERTRACEDATA1 3 |
| 414 | #define CP0_REG23__TRACEIBPC 4 |
| 415 | #define CP0_REG23__TRACEDBPC 5 |
| 416 | #define CP0_REG23__DEBUG2 6 |
| 417 | /* CP0 Register 24 */ |
| 418 | #define CP0_REG24__DEPC 0 |
| 419 | /* CP0 Register 25 */ |
| 420 | #define CP0_REG25__PERFCTL0 0 |
| 421 | #define CP0_REG25__PERFCNT0 1 |
| 422 | #define CP0_REG25__PERFCTL1 2 |
| 423 | #define CP0_REG25__PERFCNT1 3 |
| 424 | #define CP0_REG25__PERFCTL2 4 |
| 425 | #define CP0_REG25__PERFCNT2 5 |
| 426 | #define CP0_REG25__PERFCTL3 6 |
| 427 | #define CP0_REG25__PERFCNT3 7 |
| 428 | /* CP0 Register 26 */ |
| 429 | #define CP0_REG26__ERRCTL 0 |
| 430 | /* CP0 Register 27 */ |
| 431 | #define CP0_REG27__CACHERR 0 |
| 432 | /* CP0 Register 28 */ |
| 433 | #define CP0_REG28__TAGLO 0 |
| 434 | #define CP0_REG28__DATALO 1 |
| 435 | #define CP0_REG28__TAGLO1 2 |
| 436 | #define CP0_REG28__DATALO1 3 |
| 437 | #define CP0_REG28__TAGLO2 4 |
| 438 | #define CP0_REG28__DATALO2 5 |
| 439 | #define CP0_REG28__TAGLO3 6 |
| 440 | #define CP0_REG28__DATALO3 7 |
| 441 | /* CP0 Register 29 */ |
| 442 | #define CP0_REG29__TAGHI 0 |
| 443 | #define CP0_REG29__DATAHI 1 |
| 444 | #define CP0_REG29__TAGHI1 2 |
| 445 | #define CP0_REG29__DATAHI1 3 |
| 446 | #define CP0_REG29__TAGHI2 4 |
| 447 | #define CP0_REG29__DATAHI2 5 |
| 448 | #define CP0_REG29__TAGHI3 6 |
| 449 | #define CP0_REG29__DATAHI3 7 |
| 450 | /* CP0 Register 30 */ |
| 451 | #define CP0_REG30__ERROREPC 0 |
| 452 | /* CP0 Register 31 */ |
| 453 | #define CP0_REG31__DESAVE 0 |
| 454 | #define CP0_REG31__KSCRATCH1 2 |
| 455 | #define CP0_REG31__KSCRATCH2 3 |
| 456 | #define CP0_REG31__KSCRATCH3 4 |
| 457 | #define CP0_REG31__KSCRATCH4 5 |
| 458 | #define CP0_REG31__KSCRATCH5 6 |
| 459 | #define CP0_REG31__KSCRATCH6 7 |
| 460 | |
| 461 | |
| 462 | typedef struct TCState TCState; |
| 463 | |
| 464 | /* |
| 465 | * Octeon3 adds a second bank of multiplier/product limbs used by the |
| 466 | * two-source MTM/MTP forms: MPL0..2/P0..2 from rs and MPL3..5/P3..5 from rt. |
| 467 | */ |
| 468 | #define OCTEON_MULTIPLIER_LANES 3 |
| 469 | #define OCTEON_MULTIPLIER_REGS (2 * OCTEON_MULTIPLIER_LANES) |
| 470 | |
| 471 | struct TCState { |
| 472 | target_ulong gpr[32]; |
| 473 | #if defined(TARGET_MIPS64) |
| 474 | /* |
| 475 | * For CPUs using 128-bit GPR registers, we put the lower halves in gpr[]) |
| 476 | * and the upper halves in gpr_hi[]. |
| 477 | */ |
| 478 | uint64_t gpr_hi[32]; |
| 479 | #endif /* TARGET_MIPS64 */ |
| 480 | target_ulong PC; |
| 481 | target_ulong HI[MIPS_DSP_ACC]; |
| 482 | target_ulong LO[MIPS_DSP_ACC]; |
| 483 | target_ulong ACX[MIPS_DSP_ACC]; |
| 484 | target_ulong DSPControl; |
| 485 | int32_t CP0_TCStatus; |
| 486 | #define CP0TCSt_TCU3 31 |
| 487 | #define CP0TCSt_TCU2 30 |
| 488 | #define CP0TCSt_TCU1 29 |
| 489 | #define CP0TCSt_TCU0 28 |
| 490 | #define CP0TCSt_TMX 27 |
| 491 | #define CP0TCSt_RNST 23 |
| 492 | #define CP0TCSt_TDS 21 |
| 493 | #define CP0TCSt_DT 20 |
| 494 | #define CP0TCSt_DA 15 |
| 495 | #define CP0TCSt_A 13 |
| 496 | #define CP0TCSt_TKSU 11 |
| 497 | #define CP0TCSt_IXMT 10 |
| 498 | #define CP0TCSt_TASID 0 |
| 499 | int32_t CP0_TCBind; |
| 500 | #define CP0TCBd_CurTC 21 |
| 501 | #define CP0TCBd_TBE 17 |
| 502 | #define CP0TCBd_CurVPE 0 |
| 503 | target_ulong CP0_TCHalt; |
| 504 | target_ulong CP0_TCContext; |
| 505 | target_ulong CP0_TCSchedule; |
| 506 | target_ulong CP0_TCScheFBack; |
| 507 | int32_t CP0_Debug_tcstatus; |
| 508 | target_ulong CP0_UserLocal; |
| 509 | struct { |
| 510 | uint64_t MPL[OCTEON_MULTIPLIER_REGS]; |
| 511 | uint64_t P[OCTEON_MULTIPLIER_REGS]; |
| 512 | } octeon; |
| 513 | |
| 514 | int32_t msacsr; |
| 515 | |
| 516 | #define MSACSR_FS 24 |
| 517 | #define MSACSR_FS_MASK (1 << MSACSR_FS) |
| 518 | #define MSACSR_NX 18 |
| 519 | #define MSACSR_NX_MASK (1 << MSACSR_NX) |
| 520 | #define MSACSR_CEF 2 |
| 521 | #define MSACSR_CEF_MASK (0xffff << MSACSR_CEF) |
| 522 | #define MSACSR_RM 0 |
| 523 | #define MSACSR_RM_MASK (0x3 << MSACSR_RM) |
| 524 | #define MSACSR_MASK (MSACSR_RM_MASK | MSACSR_CEF_MASK | MSACSR_NX_MASK | \ |
| 525 | MSACSR_FS_MASK) |
| 526 | |
| 527 | float_status msa_fp_status; |
| 528 | |
| 529 | #define NUMBER_OF_MXU_REGISTERS 16 |
| 530 | target_ulong mxu_gpr[NUMBER_OF_MXU_REGISTERS - 1]; |
| 531 | target_ulong mxu_cr; |
| 532 | #define MXU_CR_LC 31 |
| 533 | #define MXU_CR_RC 30 |
| 534 | #define MXU_CR_BIAS 2 |
| 535 | #define MXU_CR_RD_EN 1 |
| 536 | #define MXU_CR_MXU_EN 0 |
| 537 | |
| 538 | }; |
| 539 | |
| 540 | struct MIPSITUState; |
| 541 | typedef struct MIPSOcteonCryptoState { |
| 542 | union { |
| 543 | struct { |
| 544 | uint64_t hsh_dat[16]; |
| 545 | uint64_t hsh_iv[8]; |
| 546 | uint64_t sha3_dat24; |
| 547 | }; |
| 548 | uint64_t sha3_dat[25]; |
| 549 | }; |
| 550 | uint64_t des3_key[3]; |
| 551 | uint64_t des3_iv; |
| 552 | uint64_t des3_result; |
| 553 | uint64_t aes_resinp[2]; |
| 554 | uint64_t aes_iv[2]; |
| 555 | uint64_t aes_key[4]; |
| 556 | uint32_t crc_poly; |
| 557 | uint32_t crc_iv; |
| 558 | uint64_t gfm_mul[2]; |
| 559 | uint64_t gfm_resinp[2]; |
| 560 | uint16_t gfm_poly; |
| 561 | uint8_t aes_keylen; |
| 562 | uint8_t crc_len; |
| 563 | uint64_t chord; |
| 564 | uint64_t llm_data[2]; |
| 565 | QTree *llm36; |
| 566 | QTree *llm64; |
| 567 | } MIPSOcteonCryptoState; |
| 568 | |
| 569 | typedef struct CPUArchState { |
| 570 | TCState active_tc; |
| 571 | CPUMIPSFPUContext active_fpu; |
| 572 | |
| 573 | uint32_t current_tc; |
| 574 | |
| 575 | uint32_t SEGBITS; |
| 576 | uint32_t PABITS; |
| 577 | #if defined(TARGET_MIPS64) |
| 578 | # define PABITS_BASE 36 |
| 579 | #else |
| 580 | # define PABITS_BASE 32 |
| 581 | #endif |
| 582 | target_ulong SEGMask; |
| 583 | uint64_t PAMask; |
| 584 | #define PAMASK_BASE ((1ULL << PABITS_BASE) - 1) |
| 585 | |
| 586 | int32_t msair; |
| 587 | #define MSAIR_ProcID 8 |
| 588 | #define MSAIR_Rev 0 |
| 589 | |
| 590 | MIPSOcteonCryptoState octeon_crypto; |
| 591 | |
| 592 | /* |
| 593 | * CP0 Register 0 |
| 594 | */ |
| 595 | int32_t CP0_Index; |
| 596 | /* CP0_MVP* are per MVP registers. */ |
| 597 | int32_t CP0_VPControl; |
| 598 | #define CP0VPCtl_DIS 0 |
| 599 | /* |
| 600 | * CP0 Register 1 |
| 601 | */ |
| 602 | int32_t CP0_Random; |
| 603 | int32_t CP0_VPEControl; |
| 604 | #define CP0VPECo_YSI 21 |
| 605 | #define CP0VPECo_GSI 20 |
| 606 | #define CP0VPECo_EXCPT 16 |
| 607 | #define CP0VPECo_TE 15 |
| 608 | #define CP0VPECo_TargTC 0 |
| 609 | int32_t CP0_VPEConf0; |
| 610 | #define CP0VPEC0_M 31 |
| 611 | #define CP0VPEC0_XTC 21 |
| 612 | #define CP0VPEC0_TCS 19 |
| 613 | #define CP0VPEC0_SCS 18 |
| 614 | #define CP0VPEC0_DSC 17 |
| 615 | #define CP0VPEC0_ICS 16 |
| 616 | #define CP0VPEC0_MVP 1 |
| 617 | #define CP0VPEC0_VPA 0 |
| 618 | int32_t CP0_VPEConf1; |
| 619 | #define CP0VPEC1_NCX 20 |
| 620 | #define CP0VPEC1_NCP2 10 |
| 621 | #define CP0VPEC1_NCP1 0 |
| 622 | target_ulong CP0_YQMask; |
| 623 | target_ulong CP0_VPESchedule; |
| 624 | target_ulong CP0_VPEScheFBack; |
| 625 | int32_t CP0_VPEOpt; |
| 626 | #define CP0VPEOpt_IWX7 15 |
| 627 | #define CP0VPEOpt_IWX6 14 |
| 628 | #define CP0VPEOpt_IWX5 13 |
| 629 | #define CP0VPEOpt_IWX4 12 |
| 630 | #define CP0VPEOpt_IWX3 11 |
| 631 | #define CP0VPEOpt_IWX2 10 |
| 632 | #define CP0VPEOpt_IWX1 9 |
| 633 | #define CP0VPEOpt_IWX0 8 |
| 634 | #define CP0VPEOpt_DWX7 7 |
| 635 | #define CP0VPEOpt_DWX6 6 |
| 636 | #define CP0VPEOpt_DWX5 5 |
| 637 | #define CP0VPEOpt_DWX4 4 |
| 638 | #define CP0VPEOpt_DWX3 3 |
| 639 | #define CP0VPEOpt_DWX2 2 |
| 640 | #define CP0VPEOpt_DWX1 1 |
| 641 | #define CP0VPEOpt_DWX0 0 |
| 642 | /* |
| 643 | * CP0 Register 2 |
| 644 | */ |
| 645 | uint64_t CP0_EntryLo0; |
| 646 | /* |
| 647 | * CP0 Register 3 |
| 648 | */ |
| 649 | uint64_t CP0_EntryLo1; |
| 650 | #if defined(TARGET_MIPS64) |
| 651 | # define CP0EnLo_RI 63 |
| 652 | # define CP0EnLo_XI 62 |
| 653 | #else |
| 654 | # define CP0EnLo_RI 31 |
| 655 | # define CP0EnLo_XI 30 |
| 656 | #endif |
| 657 | int32_t CP0_GlobalNumber; |
| 658 | #define CP0GN_VPId 0 |
| 659 | /* |
| 660 | * CP0 Register 4 |
| 661 | */ |
| 662 | target_ulong CP0_Context; |
| 663 | int32_t CP0_MemoryMapID; |
| 664 | /* |
| 665 | * CP0 Register 5 |
| 666 | */ |
| 667 | int32_t CP0_PageMask; |
| 668 | #define CP0PM_MASK 13 |
| 669 | int32_t CP0_PageGrain_rw_bitmask; |
| 670 | int32_t CP0_PageGrain; |
| 671 | #define CP0PG_RIE 31 |
| 672 | #define CP0PG_XIE 30 |
| 673 | #define CP0PG_ELPA 29 |
| 674 | #define CP0PG_IEC 27 |
| 675 | target_ulong CP0_SegCtl0; |
| 676 | target_ulong CP0_SegCtl1; |
| 677 | target_ulong CP0_SegCtl2; |
| 678 | #define CP0SC_PA 9 |
| 679 | #define CP0SC_PA_MASK (0x7FULL << CP0SC_PA) |
| 680 | #define CP0SC_PA_1GMASK (0x7EULL << CP0SC_PA) |
| 681 | #define CP0SC_AM 4 |
| 682 | #define CP0SC_AM_MASK (0x7ULL << CP0SC_AM) |
| 683 | #define CP0SC_AM_UK 0ULL |
| 684 | #define CP0SC_AM_MK 1ULL |
| 685 | #define CP0SC_AM_MSK 2ULL |
| 686 | #define CP0SC_AM_MUSK 3ULL |
| 687 | #define CP0SC_AM_MUSUK 4ULL |
| 688 | #define CP0SC_AM_USK 5ULL |
| 689 | #define CP0SC_AM_UUSK 7ULL |
| 690 | #define CP0SC_EU 3 |
| 691 | #define CP0SC_EU_MASK (1ULL << CP0SC_EU) |
| 692 | #define CP0SC_C 0 |
| 693 | #define CP0SC_C_MASK (0x7ULL << CP0SC_C) |
| 694 | #define CP0SC_MASK (CP0SC_C_MASK | CP0SC_EU_MASK | CP0SC_AM_MASK | \ |
| 695 | CP0SC_PA_MASK) |
| 696 | #define CP0SC_1GMASK (CP0SC_C_MASK | CP0SC_EU_MASK | CP0SC_AM_MASK | \ |
| 697 | CP0SC_PA_1GMASK) |
| 698 | #define CP0SC0_MASK (CP0SC_MASK | (CP0SC_MASK << 16)) |
| 699 | #define CP0SC1_XAM 59 |
| 700 | #define CP0SC1_XAM_MASK (0x7ULL << CP0SC1_XAM) |
| 701 | #define CP0SC1_MASK (CP0SC_MASK | (CP0SC_MASK << 16) | CP0SC1_XAM_MASK) |
| 702 | #define CP0SC2_XR 56 |
| 703 | #define CP0SC2_XR_MASK (0xFFULL << CP0SC2_XR) |
| 704 | #define CP0SC2_MASK (CP0SC_1GMASK | (CP0SC_1GMASK << 16) | CP0SC2_XR_MASK) |
| 705 | target_ulong CP0_PWBase; |
| 706 | target_ulong CP0_PWField; |
| 707 | #if defined(TARGET_MIPS64) |
| 708 | #define CP0PF_BDI 32 /* 37..32 */ |
| 709 | #define CP0PF_GDI 24 /* 29..24 */ |
| 710 | #define CP0PF_UDI 18 /* 23..18 */ |
| 711 | #define CP0PF_MDI 12 /* 17..12 */ |
| 712 | #define CP0PF_PTI 6 /* 11..6 */ |
| 713 | #define CP0PF_PTEI 0 /* 5..0 */ |
| 714 | #else |
| 715 | #define CP0PF_GDW 24 /* 29..24 */ |
| 716 | #define CP0PF_UDW 18 /* 23..18 */ |
| 717 | #define CP0PF_MDW 12 /* 17..12 */ |
| 718 | #define CP0PF_PTW 6 /* 11..6 */ |
| 719 | #define CP0PF_PTEW 0 /* 5..0 */ |
| 720 | #endif |
| 721 | target_ulong CP0_PWSize; |
| 722 | #if defined(TARGET_MIPS64) |
| 723 | #define CP0PS_BDW 32 /* 37..32 */ |
| 724 | #endif |
| 725 | #define CP0PS_PS 30 |
| 726 | #define CP0PS_GDW 24 /* 29..24 */ |
| 727 | #define CP0PS_UDW 18 /* 23..18 */ |
| 728 | #define CP0PS_MDW 12 /* 17..12 */ |
| 729 | #define CP0PS_PTW 6 /* 11..6 */ |
| 730 | #define CP0PS_PTEW 0 /* 5..0 */ |
| 731 | /* |
| 732 | * CP0 Register 6 |
| 733 | */ |
| 734 | int32_t CP0_Wired; |
| 735 | int32_t CP0_PWCtl; |
| 736 | #define CP0PC_PWEN 31 |
| 737 | #if defined(TARGET_MIPS64) |
| 738 | #define CP0PC_PWDIREXT 30 |
| 739 | #define CP0PC_XK 28 |
| 740 | #define CP0PC_XS 27 |
| 741 | #define CP0PC_XU 26 |
| 742 | #endif |
| 743 | #define CP0PC_DPH 7 |
| 744 | #define CP0PC_HUGEPG 6 |
| 745 | #define CP0PC_PSN 0 /* 5..0 */ |
| 746 | int32_t CP0_SRSConf0_rw_bitmask; |
| 747 | int32_t CP0_SRSConf0; |
| 748 | #define CP0SRSC0_M 31 |
| 749 | #define CP0SRSC0_SRS3 20 |
| 750 | #define CP0SRSC0_SRS2 10 |
| 751 | #define CP0SRSC0_SRS1 0 |
| 752 | int32_t CP0_SRSConf1_rw_bitmask; |
| 753 | int32_t CP0_SRSConf1; |
| 754 | #define CP0SRSC1_M 31 |
| 755 | #define CP0SRSC1_SRS6 20 |
| 756 | #define CP0SRSC1_SRS5 10 |
| 757 | #define CP0SRSC1_SRS4 0 |
| 758 | int32_t CP0_SRSConf2_rw_bitmask; |
| 759 | int32_t CP0_SRSConf2; |
| 760 | #define CP0SRSC2_M 31 |
| 761 | #define CP0SRSC2_SRS9 20 |
| 762 | #define CP0SRSC2_SRS8 10 |
| 763 | #define CP0SRSC2_SRS7 0 |
| 764 | int32_t CP0_SRSConf3_rw_bitmask; |
| 765 | int32_t CP0_SRSConf3; |
| 766 | #define CP0SRSC3_M 31 |
| 767 | #define CP0SRSC3_SRS12 20 |
| 768 | #define CP0SRSC3_SRS11 10 |
| 769 | #define CP0SRSC3_SRS10 0 |
| 770 | int32_t CP0_SRSConf4_rw_bitmask; |
| 771 | int32_t CP0_SRSConf4; |
| 772 | #define CP0SRSC4_SRS15 20 |
| 773 | #define CP0SRSC4_SRS14 10 |
| 774 | #define CP0SRSC4_SRS13 0 |
| 775 | /* |
| 776 | * CP0 Register 7 |
| 777 | */ |
| 778 | int32_t CP0_HWREna; |
| 779 | /* |
| 780 | * CP0 Register 8 |
| 781 | */ |
| 782 | target_ulong CP0_BadVAddr; |
| 783 | uint32_t CP0_BadInstr; |
| 784 | uint32_t CP0_BadInstrP; |
| 785 | uint32_t CP0_BadInstrX; |
| 786 | /* |
| 787 | * CP0 Register 9 |
| 788 | */ |
| 789 | int32_t CP0_Count; |
| 790 | #define CP0SAARI_TARGET 0 /* 5..0 */ |
| 791 | #define CP0SAAR_BASE 12 /* 43..12 */ |
| 792 | #define CP0SAAR_SIZE 1 /* 5..1 */ |
| 793 | #define CP0SAAR_EN 0 |
| 794 | /* |
| 795 | * CP0 Register 10 |
| 796 | */ |
| 797 | target_ulong CP0_EntryHi; |
| 798 | #define CP0EnHi_EHINV 10 |
| 799 | target_ulong CP0_EntryHi_ASID_mask; |
| 800 | /* |
| 801 | * CP0 Register 11 |
| 802 | */ |
| 803 | int32_t CP0_Compare; |
| 804 | /* |
| 805 | * CP0 Register 12 |
| 806 | */ |
| 807 | int32_t CP0_Status; |
| 808 | #define CP0St_CU3 31 |
| 809 | #define CP0St_CU2 30 |
| 810 | #define CP0St_CU1 29 |
| 811 | #define CP0St_CU0 28 |
| 812 | #define CP0St_RP 27 |
| 813 | #define CP0St_FR 26 |
| 814 | #define CP0St_RE 25 |
| 815 | #define CP0St_MX 24 |
| 816 | #define CP0St_PX 23 |
| 817 | #define CP0St_BEV 22 |
| 818 | #define CP0St_TS 21 |
| 819 | #define CP0St_SR 20 |
| 820 | #define CP0St_NMI 19 |
| 821 | #define CP0St_IM 8 |
| 822 | #define CP0St_KX 7 |
| 823 | #define CP0St_SX 6 |
| 824 | #define CP0St_UX 5 |
| 825 | #define CP0St_KSU 3 |
| 826 | #define CP0St_ERL 2 |
| 827 | #define CP0St_EXL 1 |
| 828 | #define CP0St_IE 0 |
| 829 | int32_t CP0_IntCtl; |
| 830 | #define CP0IntCtl_IPTI 29 |
| 831 | #define CP0IntCtl_IPPCI 26 |
| 832 | #define CP0IntCtl_VS 5 |
| 833 | int32_t CP0_SRSCtl; |
| 834 | #define CP0SRSCtl_HSS 26 |
| 835 | #define CP0SRSCtl_EICSS 18 |
| 836 | #define CP0SRSCtl_ESS 12 |
| 837 | #define CP0SRSCtl_PSS 6 |
| 838 | #define CP0SRSCtl_CSS 0 |
| 839 | int32_t CP0_SRSMap; |
| 840 | #define CP0SRSMap_SSV7 28 |
| 841 | #define CP0SRSMap_SSV6 24 |
| 842 | #define CP0SRSMap_SSV5 20 |
| 843 | #define CP0SRSMap_SSV4 16 |
| 844 | #define CP0SRSMap_SSV3 12 |
| 845 | #define CP0SRSMap_SSV2 8 |
| 846 | #define CP0SRSMap_SSV1 4 |
| 847 | #define CP0SRSMap_SSV0 0 |
| 848 | /* |
| 849 | * CP0 Register 13 |
| 850 | */ |
| 851 | int32_t CP0_Cause; |
| 852 | #define CP0Ca_BD 31 |
| 853 | #define CP0Ca_TI 30 |
| 854 | #define CP0Ca_CE 28 |
| 855 | #define CP0Ca_DC 27 |
| 856 | #define CP0Ca_PCI 26 |
| 857 | #define CP0Ca_IV 23 |
| 858 | #define CP0Ca_WP 22 |
| 859 | #define CP0Ca_IP 8 |
| 860 | #define CP0Ca_IP_mask 0x0000FF00 |
| 861 | #define CP0Ca_EC 2 |
| 862 | /* |
| 863 | * CP0 Register 14 |
| 864 | */ |
| 865 | target_ulong CP0_EPC; |
| 866 | /* |
| 867 | * CP0 Register 15 |
| 868 | */ |
| 869 | int32_t CP0_PRid; |
| 870 | target_ulong CP0_EBase; |
| 871 | target_ulong CP0_EBaseWG_rw_bitmask; |
| 872 | #define CP0EBase_WG 11 |
| 873 | target_ulong CP0_CMGCRBase; |
| 874 | /* |
| 875 | * CP0 Register 16 (after Release 1) |
| 876 | */ |
| 877 | int32_t CP0_Config0; |
| 878 | #define CP0C0_M 31 |
| 879 | #define CP0C0_K23 28 /* 30..28 */ |
| 880 | #define CP0C0_KU 25 /* 27..25 */ |
| 881 | #define CP0C0_MDU 20 |
| 882 | #define CP0C0_MM 18 |
| 883 | #define CP0C0_BM 16 |
| 884 | #define CP0C0_Impl 16 /* 24..16 */ |
| 885 | #define CP0C0_BE 15 |
| 886 | #define CP0C0_AT 13 /* 14..13 */ |
| 887 | #define CP0C0_AR 10 /* 12..10 */ |
| 888 | #define CP0C0_MT 7 /* 9..7 */ |
| 889 | #define CP0C0_VI 3 |
| 890 | #define CP0C0_K0 0 /* 2..0 */ |
| 891 | #define CP0C0_AR_LENGTH 3 |
| 892 | /* |
| 893 | * CP0 Register 16 (before Release 1) |
| 894 | */ |
| 895 | #define CP0C0_Impl 16 /* 24..16 */ |
| 896 | #define CP0C0_IC 9 /* 11..9 */ |
| 897 | #define CP0C0_DC 6 /* 8..6 */ |
| 898 | #define CP0C0_IB 5 |
| 899 | #define CP0C0_DB 4 |
| 900 | int32_t CP0_Config1; |
| 901 | #define CP0C1_M 31 |
| 902 | #define CP0C1_MMU 25 /* 30..25 */ |
| 903 | #define CP0C1_IS 22 /* 24..22 */ |
| 904 | #define CP0C1_IL 19 /* 21..19 */ |
| 905 | #define CP0C1_IA 16 /* 18..16 */ |
| 906 | #define CP0C1_DS 13 /* 15..13 */ |
| 907 | #define CP0C1_DL 10 /* 12..10 */ |
| 908 | #define CP0C1_DA 7 /* 9..7 */ |
| 909 | #define CP0C1_C2 6 |
| 910 | #define CP0C1_MD 5 |
| 911 | #define CP0C1_PC 4 |
| 912 | #define CP0C1_WR 3 |
| 913 | #define CP0C1_CA 2 |
| 914 | #define CP0C1_EP 1 |
| 915 | #define CP0C1_FP 0 |
| 916 | int32_t CP0_Config2; |
| 917 | #define CP0C2_M 31 |
| 918 | #define CP0C2_TU 28 /* 30..28 */ |
| 919 | #define CP0C2_TS 24 /* 27..24 */ |
| 920 | #define CP0C2_TL 20 /* 23..20 */ |
| 921 | #define CP0C2_TA 16 /* 19..16 */ |
| 922 | #define CP0C2_SU 12 /* 15..12 */ |
| 923 | #define CP0C2_SS 8 /* 11..8 */ |
| 924 | #define CP0C2_SL 4 /* 7..4 */ |
| 925 | #define CP0C2_SA 0 /* 3..0 */ |
| 926 | int32_t CP0_Config3; |
| 927 | #define CP0C3_M 31 |
| 928 | #define CP0C3_BPG 30 |
| 929 | #define CP0C3_CMGCR 29 |
| 930 | #define CP0C3_MSAP 28 |
| 931 | #define CP0C3_BP 27 |
| 932 | #define CP0C3_BI 26 |
| 933 | #define CP0C3_SC 25 |
| 934 | #define CP0C3_PW 24 |
| 935 | #define CP0C3_VZ 23 |
| 936 | #define CP0C3_IPLV 21 /* 22..21 */ |
| 937 | #define CP0C3_MMAR 18 /* 20..18 */ |
| 938 | #define CP0C3_MCU 17 |
| 939 | #define CP0C3_ISA_ON_EXC 16 |
| 940 | #define CP0C3_ISA 14 /* 15..14 */ |
| 941 | #define CP0C3_ULRI 13 |
| 942 | #define CP0C3_RXI 12 |
| 943 | #define CP0C3_DSP2P 11 |
| 944 | #define CP0C3_DSPP 10 |
| 945 | #define CP0C3_CTXTC 9 |
| 946 | #define CP0C3_ITL 8 |
| 947 | #define CP0C3_LPA 7 |
| 948 | #define CP0C3_VEIC 6 |
| 949 | #define CP0C3_VInt 5 |
| 950 | #define CP0C3_SP 4 |
| 951 | #define CP0C3_CDMM 3 |
| 952 | #define CP0C3_MT 2 |
| 953 | #define CP0C3_SM 1 |
| 954 | #define CP0C3_TL 0 |
| 955 | int32_t CP0_Config4; |
| 956 | int32_t CP0_Config4_rw_bitmask; |
| 957 | #define CP0C4_M 31 |
| 958 | #define CP0C4_IE 29 /* 30..29 */ |
| 959 | #define CP0C4_AE 28 |
| 960 | #define CP0C4_VTLBSizeExt 24 /* 27..24 */ |
| 961 | #define CP0C4_KScrExist 16 |
| 962 | #define CP0C4_MMUExtDef 14 |
| 963 | #define CP0C4_FTLBPageSize 8 /* 12..8 */ |
| 964 | /* bit layout if MMUExtDef=1 */ |
| 965 | #define CP0C4_MMUSizeExt 0 /* 7..0 */ |
| 966 | /* bit layout if MMUExtDef=2 */ |
| 967 | #define CP0C4_FTLBWays 4 /* 7..4 */ |
| 968 | #define CP0C4_FTLBSets 0 /* 3..0 */ |
| 969 | int32_t CP0_Config5; |
| 970 | int32_t CP0_Config5_rw_bitmask; |
| 971 | #define CP0C5_M 31 |
| 972 | #define CP0C5_K 30 |
| 973 | #define CP0C5_CV 29 |
| 974 | #define CP0C5_EVA 28 |
| 975 | #define CP0C5_MSAEn 27 |
| 976 | #define CP0C5_PMJ 23 /* 25..23 */ |
| 977 | #define CP0C5_WR2 22 |
| 978 | #define CP0C5_NMS 21 |
| 979 | #define CP0C5_ULS 20 |
| 980 | #define CP0C5_XPA 19 |
| 981 | #define CP0C5_CRCP 18 |
| 982 | #define CP0C5_MI 17 |
| 983 | #define CP0C5_GI 15 /* 16..15 */ |
| 984 | #define CP0C5_CA2 14 |
| 985 | #define CP0C5_XNP 13 |
| 986 | #define CP0C5_DEC 11 |
| 987 | #define CP0C5_L2C 10 |
| 988 | #define CP0C5_UFE 9 |
| 989 | #define CP0C5_FRE 8 |
| 990 | #define CP0C5_VP 7 |
| 991 | #define CP0C5_SBRI 6 |
| 992 | #define CP0C5_MVH 5 |
| 993 | #define CP0C5_LLB 4 |
| 994 | #define CP0C5_MRP 3 |
| 995 | #define CP0C5_UFR 2 |
| 996 | #define CP0C5_NFExists 0 |
| 997 | int32_t CP0_Config6; |
| 998 | int32_t CP0_Config6_rw_bitmask; |
| 999 | #define CP0C6_BPPASS 31 |
| 1000 | #define CP0C6_KPOS 24 |
| 1001 | #define CP0C6_KE 23 |
| 1002 | #define CP0C6_VTLBONLY 22 |
| 1003 | #define CP0C6_LASX 21 |
| 1004 | #define CP0C6_SSEN 20 |
| 1005 | #define CP0C6_DISDRTIME 19 |
| 1006 | #define CP0C6_PIXNUEN 18 |
| 1007 | #define CP0C6_SCRAND 17 |
| 1008 | #define CP0C6_LLEXCEN 16 |
| 1009 | #define CP0C6_DISVC 15 |
| 1010 | #define CP0C6_VCLRU 14 |
| 1011 | #define CP0C6_DCLRU 13 |
| 1012 | #define CP0C6_PIXUEN 12 |
| 1013 | #define CP0C6_DISBLKLYEN 11 |
| 1014 | #define CP0C6_UMEMUALEN 10 |
| 1015 | #define CP0C6_SFBEN 8 |
| 1016 | #define CP0C6_FLTINT 7 |
| 1017 | #define CP0C6_VLTINT 6 |
| 1018 | #define CP0C6_DISBTB 5 |
| 1019 | #define CP0C6_STPREFCTL 2 |
| 1020 | #define CP0C6_INSTPREF 1 |
| 1021 | #define CP0C6_DATAPREF 0 |
| 1022 | int32_t CP0_Config7; |
| 1023 | int64_t CP0_Config7_rw_bitmask; |
| 1024 | #define CP0C7_WII 31 |
| 1025 | #define CP0C7_NAPCGEN 2 |
| 1026 | #define CP0C7_UNIMUEN 1 |
| 1027 | #define CP0C7_VFPUCGEN 0 |
| 1028 | uint64_t CP0_LLAddr; |
| 1029 | uint64_t CP0_MAAR[MIPS_MAAR_MAX]; |
| 1030 | int32_t CP0_MAARI; |
| 1031 | /* XXX: Maybe make LLAddr per-TC? */ |
| 1032 | /* |
| 1033 | * CP0 Register 17 |
| 1034 | */ |
| 1035 | target_ulong lladdr; /* LL virtual address compared against SC */ |
| 1036 | target_ulong llval; |
| 1037 | uint64_t llval_wp; |
| 1038 | uint32_t llnewval_wp; |
| 1039 | uint64_t CP0_LLAddr_rw_bitmask; |
| 1040 | int CP0_LLAddr_shift; |
| 1041 | /* |
| 1042 | * CP0 Register 18 |
| 1043 | */ |
| 1044 | target_ulong CP0_WatchLo[8]; |
| 1045 | /* |
| 1046 | * CP0 Register 19 |
| 1047 | */ |
| 1048 | uint64_t CP0_WatchHi[8]; |
| 1049 | #define CP0WH_ASID 16 |
| 1050 | #define CP0WH_M 31 |
| 1051 | /* |
| 1052 | * CP0 Register 20 |
| 1053 | */ |
| 1054 | target_ulong CP0_XContext; |
| 1055 | int32_t CP0_Framemask; |
| 1056 | /* |
| 1057 | * CP0 Register 23 |
| 1058 | */ |
| 1059 | int32_t CP0_Debug; |
| 1060 | #define CP0DB_DBD 31 |
| 1061 | #define CP0DB_DM 30 |
| 1062 | #define CP0DB_LSNM 28 |
| 1063 | #define CP0DB_Doze 27 |
| 1064 | #define CP0DB_Halt 26 |
| 1065 | #define CP0DB_CNT 25 |
| 1066 | #define CP0DB_IBEP 24 |
| 1067 | #define CP0DB_DBEP 21 |
| 1068 | #define CP0DB_IEXI 20 |
| 1069 | #define CP0DB_VER 15 |
| 1070 | #define CP0DB_DEC 10 |
| 1071 | #define CP0DB_SSt 8 |
| 1072 | #define CP0DB_DINT 5 |
| 1073 | #define CP0DB_DIB 4 |
| 1074 | #define CP0DB_DDBS 3 |
| 1075 | #define CP0DB_DDBL 2 |
| 1076 | #define CP0DB_DBp 1 |
| 1077 | #define CP0DB_DSS 0 |
| 1078 | /* |
| 1079 | * CP0 Register 24 |
| 1080 | */ |
| 1081 | target_ulong CP0_DEPC; |
| 1082 | /* |
| 1083 | * CP0 Register 25 |
| 1084 | */ |
| 1085 | int32_t CP0_Performance0; |
| 1086 | /* |
| 1087 | * CP0 Register 26 |
| 1088 | */ |
| 1089 | int32_t CP0_ErrCtl; |
| 1090 | #define CP0EC_WST 29 |
| 1091 | #define CP0EC_SPR 28 |
| 1092 | #define CP0EC_ITC 26 |
| 1093 | /* |
| 1094 | * CP0 Register 28 |
| 1095 | */ |
| 1096 | uint64_t CP0_TagLo; |
| 1097 | int32_t CP0_DataLo; |
| 1098 | /* |
| 1099 | * CP0 Register 29 |
| 1100 | */ |
| 1101 | int32_t CP0_TagHi; |
| 1102 | int32_t CP0_DataHi; |
| 1103 | /* |
| 1104 | * CP0 Register 30 |
| 1105 | */ |
| 1106 | target_ulong CP0_ErrorEPC; |
| 1107 | /* |
| 1108 | * CP0 Register 31 |
| 1109 | */ |
| 1110 | int32_t CP0_DESAVE; |
| 1111 | target_ulong CP0_KScratch[MIPS_KSCRATCH_NUM]; |
| 1112 | /* |
| 1113 | * Loongson CSR CPUCFG registers |
| 1114 | */ |
| 1115 | uint32_t lcsr_cpucfg1; |
| 1116 | #define CPUCFG1_FP 0 |
| 1117 | #define CPUCFG1_FPREV 1 |
| 1118 | #define CPUCFG1_MMI 4 |
| 1119 | #define CPUCFG1_MSA1 5 |
| 1120 | #define CPUCFG1_MSA2 6 |
| 1121 | #define CPUCFG1_LSLDR0 16 |
| 1122 | #define CPUCFG1_LSPERF 17 |
| 1123 | #define CPUCFG1_LSPERFX 18 |
| 1124 | #define CPUCFG1_LSSYNCI 19 |
| 1125 | #define CPUCFG1_LLEXC 20 |
| 1126 | #define CPUCFG1_SCRAND 21 |
| 1127 | #define CPUCFG1_MUALP 25 |
| 1128 | #define CPUCFG1_KMUALEN 26 |
| 1129 | #define CPUCFG1_ITLBT 27 |
| 1130 | #define CPUCFG1_SFBP 29 |
| 1131 | #define CPUCFG1_CDMAP 30 |
| 1132 | uint32_t lcsr_cpucfg2; |
| 1133 | #define CPUCFG2_LEXT1 0 |
| 1134 | #define CPUCFG2_LEXT2 1 |
| 1135 | #define CPUCFG2_LEXT3 2 |
| 1136 | #define CPUCFG2_LSPW 3 |
| 1137 | #define CPUCFG2_LCSRP 27 |
| 1138 | #define CPUCFG2_LDISBLIKELY 28 |
| 1139 | |
| 1140 | /* We waste some space so we can handle shadow registers like TCs. */ |
| 1141 | TCState tcs[MIPS_SHADOW_SET_MAX]; |
| 1142 | CPUMIPSFPUContext fpus[MIPS_FPU_MAX]; |
| 1143 | /* QEMU */ |
| 1144 | int error_code; |
| 1145 | #define EXCP_TLB_NOMATCH 0x1 |
| 1146 | #define EXCP_INST_NOTAVAIL 0x2 /* No valid instruction word for BadInstr */ |
| 1147 | uint32_t hflags; /* CPU State */ |
| 1148 | /* TMASK defines different execution modes */ |
| 1149 | #define MIPS_HFLAG_TMASK 0x3F5807FF |
| 1150 | #define MIPS_HFLAG_MODE 0x00007 /* execution modes */ |
| 1151 | /* |
| 1152 | * The KSU flags must be the lowest bits in hflags. The flag order |
| 1153 | * must be the same as defined for CP0 Status. This allows to use |
| 1154 | * the bits as the value of mmu_idx. |
| 1155 | */ |
| 1156 | #define MIPS_HFLAG_KSU 0x00003 /* kernel/supervisor/user mode mask */ |
| 1157 | #define MIPS_HFLAG_UM 0x00002 /* user mode flag */ |
| 1158 | #define MIPS_HFLAG_SM 0x00001 /* supervisor mode flag */ |
| 1159 | #define MIPS_HFLAG_KM 0x00000 /* kernel mode flag */ |
| 1160 | #define MIPS_HFLAG_DM 0x00004 /* Debug mode */ |
| 1161 | #define MIPS_HFLAG_64 0x00008 /* 64-bit instructions enabled */ |
| 1162 | #define MIPS_HFLAG_CP0 0x00010 /* CP0 enabled */ |
| 1163 | #define MIPS_HFLAG_FPU 0x00020 /* FPU enabled */ |
| 1164 | #define MIPS_HFLAG_F64 0x00040 /* 64-bit FPU enabled */ |
| 1165 | /* |
| 1166 | * True if the MIPS IV COP1X instructions can be used. This also |
| 1167 | * controls the non-COP1X instructions RECIP.S, RECIP.D, RSQRT.S |
| 1168 | * and RSQRT.D. |
| 1169 | */ |
| 1170 | #define MIPS_HFLAG_COP1X 0x00080 /* COP1X instructions enabled */ |
| 1171 | #define MIPS_HFLAG_RE 0x00100 /* Reversed endianness */ |
| 1172 | #define MIPS_HFLAG_AWRAP 0x00200 /* 32-bit compatibility address wrapping */ |
| 1173 | #define MIPS_HFLAG_M16 0x00400 /* MIPS16 mode flag */ |
| 1174 | #define MIPS_HFLAG_M16_SHIFT 10 |
| 1175 | /* |
| 1176 | * If translation is interrupted between the branch instruction and |
| 1177 | * the delay slot, record what type of branch it is so that we can |
| 1178 | * resume translation properly. It might be possible to reduce |
| 1179 | * this from three bits to two. |
| 1180 | */ |
| 1181 | #define MIPS_HFLAG_BMASK_BASE 0x803800 |
| 1182 | #define MIPS_HFLAG_B 0x00800 /* Unconditional branch */ |
| 1183 | #define MIPS_HFLAG_BC 0x01000 /* Conditional branch */ |
| 1184 | #define MIPS_HFLAG_BL 0x01800 /* Likely branch */ |
| 1185 | #define MIPS_HFLAG_BR 0x02000 /* branch to register (can't link TB) */ |
| 1186 | /* Extra flags about the current pending branch. */ |
| 1187 | #define MIPS_HFLAG_BMASK_EXT 0x7C000 |
| 1188 | #define MIPS_HFLAG_B16 0x04000 /* branch instruction was 16 bits */ |
| 1189 | #define MIPS_HFLAG_BDS16 0x08000 /* branch requires 16-bit delay slot */ |
| 1190 | #define MIPS_HFLAG_BDS32 0x10000 /* branch requires 32-bit delay slot */ |
| 1191 | #define MIPS_HFLAG_BDS_STRICT 0x20000 /* Strict delay slot size */ |
| 1192 | #define MIPS_HFLAG_BX 0x40000 /* branch exchanges execution mode */ |
| 1193 | #define MIPS_HFLAG_BMASK (MIPS_HFLAG_BMASK_BASE | MIPS_HFLAG_BMASK_EXT) |
| 1194 | /* MIPS DSP resources access. */ |
| 1195 | #define MIPS_HFLAG_DSP 0x080000 /* Enable access to DSP resources. */ |
| 1196 | #define MIPS_HFLAG_DSP_R2 0x100000 /* Enable access to DSP R2 resources. */ |
| 1197 | #define MIPS_HFLAG_DSP_R3 0x20000000 /* Enable access to DSP R3 resources. */ |
| 1198 | /* Extra flag about HWREna register. */ |
| 1199 | #define MIPS_HFLAG_HWRENA_ULR 0x200000 /* ULR bit from HWREna is set. */ |
| 1200 | #define MIPS_HFLAG_SBRI 0x400000 /* R6 SDBBP causes RI excpt. in user mode */ |
| 1201 | #define MIPS_HFLAG_FBNSLOT 0x800000 /* Forbidden slot */ |
| 1202 | #define MIPS_HFLAG_MSA 0x1000000 |
| 1203 | #define MIPS_HFLAG_FRE 0x2000000 /* FRE enabled */ |
| 1204 | #define MIPS_HFLAG_ELPA 0x4000000 |
| 1205 | #define MIPS_HFLAG_ITC_CACHE 0x8000000 /* CACHE instr. operates on ITC tag */ |
| 1206 | #define MIPS_HFLAG_ERL 0x10000000 /* error level flag */ |
| 1207 | #define MIPS_HFLAG_TB_MASK (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK | \ |
| 1208 | MIPS_HFLAG_HWRENA_ULR) |
| 1209 | |
| 1210 | #define TB_FLAG_MIPS_FIXADE 0x40000000 |
| 1211 | target_ulong btarget; /* Jump / branch target */ |
| 1212 | target_ulong bcond; /* Branch condition (if needed) */ |
| 1213 | |
| 1214 | int SYNCI_Step; /* Address step size for SYNCI */ |
| 1215 | int CCRes; /* Cycle count resolution/divisor */ |
| 1216 | uint32_t CP0_Status_rw_bitmask; /* Read/write bits in CP0_Status */ |
| 1217 | uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */ |
| 1218 | uint64_t insn_flags; /* Supported instruction set */ |
| 1219 | |
| 1220 | /* Fields up to this point are cleared by a CPU reset */ |
| 1221 | struct {} end_reset_fields; |
| 1222 | |
| 1223 | /* Fields from here on are preserved across CPU reset. */ |
| 1224 | #if !defined(CONFIG_USER_ONLY) |
| 1225 | CPUMIPSTLBContext *tlb; |
| 1226 | qemu_irq irq[8]; |
| 1227 | MemoryRegion *itc_tag; /* ITC Configuration Tags */ |
| 1228 | |
| 1229 | /* Loongson IOCSR memory */ |
| 1230 | struct { |
| 1231 | AddressSpace as; |
| 1232 | MemoryRegion mr; |
| 1233 | } iocsr; |
| 1234 | #endif |
| 1235 | |
| 1236 | const mips_def_t *cpu_model; |
| 1237 | QEMUTimer *timer; /* Internal timer */ |
| 1238 | target_ulong exception_base; /* ExceptionBase input to the core */ |
| 1239 | } CPUMIPSState; |
| 1240 | |
| 1241 | /** |
| 1242 | * MIPSCPU: |
| 1243 | * @env: #CPUMIPSState |
| 1244 | * @clock: this CPU input clock (may be connected |
| 1245 | * to an output clock from another device). |
| 1246 | * |
| 1247 | * A MIPS CPU. |
| 1248 | */ |
| 1249 | struct ArchCPU { |
| 1250 | CPUState parent_obj; |
| 1251 | |
| 1252 | CPUMIPSState env; |
| 1253 | |
| 1254 | Clock *clock; |
| 1255 | Clock *count_clock; /* CP0_Count clock */ |
| 1256 | Clock *count_div; /* Divider for CP0_Count clock */ |
| 1257 | |
| 1258 | CPUMIPSMVPContext *mvp; |
| 1259 | |
| 1260 | /* Properties */ |
| 1261 | bool is_big_endian; |
| 1262 | }; |
| 1263 | |
| 1264 | /** |
| 1265 | * MIPSCPUClass: |
| 1266 | * @parent_realize: The parent class' realize handler. |
| 1267 | * @parent_phases: The parent class' reset phase handlers. |
| 1268 | * |
| 1269 | * A MIPS CPU model. |
| 1270 | */ |
| 1271 | struct MIPSCPUClass { |
| 1272 | CPUClass parent_class; |
| 1273 | |
| 1274 | DeviceRealize parent_realize; |
| 1275 | DeviceUnrealize parent_unrealize; |
| 1276 | ResettablePhases parent_phases; |
| 1277 | const struct mips_def_t *cpu_def; |
| 1278 | |
| 1279 | /* Used for the jazz board to modify mips_cpu_do_transaction_failed. */ |
| 1280 | bool no_data_aborts; |
| 1281 | }; |
| 1282 | |
| 1283 | void cpu_wrdsp(uint32_t rs, uint32_t mask_num, CPUMIPSState *env); |
| 1284 | uint32_t cpu_rddsp(uint32_t mask_num, CPUMIPSState *env); |
| 1285 | |
| 1286 | /* |
| 1287 | * MMU modes definitions. We carefully match the indices with our |
| 1288 | * hflags layout. |
| 1289 | */ |
| 1290 | #define MMU_KERNEL_IDX 0 |
| 1291 | #define MMU_USER_IDX 2 |
| 1292 | #define MMU_ERL_IDX 3 |
| 1293 | |
| 1294 | static inline int hflags_mmu_index(uint32_t hflags) |
| 1295 | { |
| 1296 | if (hflags & MIPS_HFLAG_ERL) { |
| 1297 | return MMU_ERL_IDX; |
| 1298 | } else { |
| 1299 | return hflags & MIPS_HFLAG_KSU; |
| 1300 | } |
| 1301 | } |
| 1302 | |
| 1303 | static inline int mips_env_mmu_index(CPUMIPSState *env) |
| 1304 | { |
| 1305 | return hflags_mmu_index(env->hflags); |
| 1306 | } |
| 1307 | |
| 1308 | /* Exceptions */ |
| 1309 | enum { |
| 1310 | EXCP_NONE = -1, |
| 1311 | EXCP_RESET = 0, |
| 1312 | EXCP_SRESET, |
| 1313 | EXCP_DSS, |
| 1314 | EXCP_DINT, |
| 1315 | EXCP_DDBL, |
| 1316 | EXCP_DDBS, |
| 1317 | EXCP_NMI, |
| 1318 | EXCP_MCHECK, |
| 1319 | EXCP_EXT_INTERRUPT, /* 8 */ |
| 1320 | EXCP_DFWATCH, |
| 1321 | EXCP_DIB, |
| 1322 | EXCP_IWATCH, |
| 1323 | EXCP_AdEL, |
| 1324 | EXCP_AdES, |
| 1325 | EXCP_TLBF, |
| 1326 | EXCP_IBE, |
| 1327 | EXCP_DBp, /* 16 */ |
| 1328 | EXCP_SYSCALL, |
| 1329 | EXCP_BREAK, |
| 1330 | EXCP_CpU, |
| 1331 | EXCP_RI, |
| 1332 | EXCP_OVERFLOW, |
| 1333 | EXCP_TRAP, |
| 1334 | EXCP_FPE, |
| 1335 | EXCP_DWATCH, /* 24 */ |
| 1336 | EXCP_LTLBL, |
| 1337 | EXCP_TLBL, |
| 1338 | EXCP_TLBS, |
| 1339 | EXCP_DBE, |
| 1340 | EXCP_THREAD, |
| 1341 | EXCP_MDMX, |
| 1342 | EXCP_C2E, |
| 1343 | EXCP_CACHE, /* 32 */ |
| 1344 | EXCP_DSPDIS, |
| 1345 | EXCP_MSADIS, |
| 1346 | EXCP_MSAFPE, |
| 1347 | EXCP_TLBXI, |
| 1348 | EXCP_TLBRI, |
| 1349 | EXCP_SEMIHOST, |
| 1350 | |
| 1351 | EXCP_LAST = EXCP_SEMIHOST, |
| 1352 | }; |
| 1353 | |
| 1354 | /* |
| 1355 | * This is an internally generated WAKE request line. |
| 1356 | * It is driven by the CPU itself. Raised when the MT |
| 1357 | * block wants to wake a VPE from an inactive state and |
| 1358 | * cleared when VPE goes from active to inactive. |
| 1359 | */ |
| 1360 | #define CPU_INTERRUPT_WAKE CPU_INTERRUPT_TGT_INT_0 |
| 1361 | |
| 1362 | #define CPU_RESOLVING_TYPE TYPE_MIPS_CPU |
| 1363 | |
| 1364 | bool cpu_type_supports_cps_smp(const char *cpu_type); |
| 1365 | bool cpu_supports_isa(const CPUMIPSState *env, uint64_t isa_mask); |
| 1366 | bool cpu_type_supports_isa(const char *cpu_type, uint64_t isa); |
| 1367 | |
| 1368 | /* Check presence of MIPS-3D ASE */ |
| 1369 | static inline bool ase_3d_available(const CPUMIPSState *env) |
| 1370 | { |
| 1371 | return env->active_fpu.fcr0 & (1 << FCR0_3D); |
| 1372 | } |
| 1373 | |
| 1374 | /* Check presence of MSA implementation */ |
| 1375 | static inline bool ase_msa_available(CPUMIPSState *env) |
| 1376 | { |
| 1377 | return env->CP0_Config3 & (1 << CP0C3_MSAP); |
| 1378 | } |
| 1379 | |
| 1380 | /* Check presence of Loongson CSR instructions */ |
| 1381 | static inline bool ase_lcsr_available(CPUMIPSState *env) |
| 1382 | { |
| 1383 | return env->lcsr_cpucfg2 & (1 << CPUCFG2_LCSRP); |
| 1384 | } |
| 1385 | |
| 1386 | /* Check presence of multi-threading ASE implementation */ |
| 1387 | static inline bool ase_mt_available(CPUMIPSState *env) |
| 1388 | { |
| 1389 | return env->CP0_Config3 & (1 << CP0C3_MT); |
| 1390 | } |
| 1391 | |
| 1392 | static inline bool cpu_type_is_64bit(const char *cpu_type) |
| 1393 | { |
| 1394 | return cpu_type_supports_isa(cpu_type, CPU_MIPS64); |
| 1395 | } |
| 1396 | |
| 1397 | void cpu_set_exception_base(int vp_index, target_ulong address); |
| 1398 | |
| 1399 | /* addr.c */ |
| 1400 | uint64_t cpu_mips_kseg0_to_phys(void *opaque, uint64_t addr); |
| 1401 | uint64_t cpu_mips_phys_to_kseg0(void *opaque, uint64_t addr); |
| 1402 | |
| 1403 | uint64_t cpu_mips_kseg1_to_phys(void *opaque, uint64_t addr); |
| 1404 | uint64_t cpu_mips_phys_to_kseg1(void *opaque, uint64_t addr); |
| 1405 | |
| 1406 | #if !defined(CONFIG_USER_ONLY) |
| 1407 | |
| 1408 | /* HW declaration specific to the MIPS target */ |
| 1409 | void cpu_mips_soft_irq(CPUMIPSState *env, int irq, int level); |
| 1410 | void cpu_mips_irq_init_cpu(MIPSCPU *cpu); |
| 1411 | void cpu_mips_clock_init(MIPSCPU *cpu); |
| 1412 | |
| 1413 | #endif /* !CONFIG_USER_ONLY */ |
| 1414 | |
| 1415 | /* helper.c */ |
| 1416 | target_ulong exception_resume_pc(CPUMIPSState *env); |
| 1417 | |
| 1418 | /* fpu.c */ |
| 1419 | void cpu_mips_restore_fp_status(CPUMIPSState *env); |
| 1420 | |
| 1421 | /** |
| 1422 | * mips_cpu_create_with_clock: |
| 1423 | * @typename: a MIPS CPU type. |
| 1424 | * @cpu_refclk: this cpu input clock (an output clock of another device) |
| 1425 | * @is_big_endian: whether this CPU is configured in big endianness |
| 1426 | * |
| 1427 | * Instantiates a MIPS CPU, set the input clock of the CPU to @cpu_refclk, |
| 1428 | * then realizes the CPU. |
| 1429 | * |
| 1430 | * Returns: A #CPUState or %NULL if an error occurred. |
| 1431 | */ |
| 1432 | MIPSCPU *mips_cpu_create_with_clock(const char *cpu_type, Clock *cpu_refclk, |
| 1433 | bool is_big_endian); |
| 1434 | |
| 1435 | #endif /* MIPS_CPU_H */ |