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1 /*
2 * Helpers for emulation of FPU-related MIPS instructions.
3 *
4 * Copyright (C) 2004-2005 Jocelyn Mayer
5 *
6 * SPDX-License-Identifier: LGPL-2.1-or-later
7 */
8 #include "fpu/softfloat-helpers.h"
9 #include "cpu.h"
10
11 extern const FloatRoundMode ieee_rm[4];
12
13 uint32_t float_class_s(uint32_t arg, float_status *fst);
14 uint64_t float_class_d(uint64_t arg, float_status *fst);
15
16 static inline void restore_rounding_mode(CPUMIPSState *env)
17 {
18 set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3],
19 &env->active_fpu.fp_status);
20 }
21
22 static inline void restore_flush_mode(CPUMIPSState *env)
23 {
24 set_flush_to_zero((env->active_fpu.fcr31 & (1 << FCR31_FS)) != 0,
25 &env->active_fpu.fp_status);
26 }
27
28 static inline void restore_snan_bit_mode(CPUMIPSState *env)
29 {
30 bool nan2008 = env->active_fpu.fcr31 & (1 << FCR31_NAN2008);
31 FloatInfZeroNaNRule izn_rule;
32 Float3NaNPropRule nan3_rule;
33
34 /*
35 * With nan2008, SNaNs are silenced in the usual way.
36 * Before that, SNaNs are not silenced; default nans are produced.
37 */
38 set_snan_rule(nan2008 ? float_snan_bit_is_zero : float_snan_bit_is_one,
39 &env->active_fpu.fp_status);
40 set_default_nan_mode(!nan2008, &env->active_fpu.fp_status);
41 /*
42 * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan)
43 * case sets InvalidOp and returns the default NaN.
44 * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan)
45 * case sets InvalidOp and returns the input value 'c'.
46 */
47 izn_rule = nan2008 ? float_infzeronan_dnan_never : float_infzeronan_dnan_always;
48 set_float_infzeronan_rule(izn_rule, &env->active_fpu.fp_status);
49 nan3_rule = nan2008 ? float_3nan_prop_s_cab : float_3nan_prop_s_abc;
50 set_float_3nan_prop_rule(nan3_rule, &env->active_fpu.fp_status);
51 /*
52 * With nan2008, the default NaN value has the sign bit clear and the
53 * frac msb set; with the older mode, the sign bit is clear, and all
54 * frac bits except the msb are set.
55 */
56 set_float_default_nan_pattern(nan2008 ? 0b01000000 : 0b00111111,
57 &env->active_fpu.fp_status);
58
59 }
60
61 static inline void restore_fp_status(CPUMIPSState *env)
62 {
63 restore_rounding_mode(env);
64 restore_flush_mode(env);
65 restore_snan_bit_mode(env);
66 }
67
68 static inline void fp_reset(CPUMIPSState *env)
69 {
70 restore_fp_status(env);
71
72 /*
73 * According to MIPS specifications, if one of the two operands is
74 * a sNaN, a new qNaN has to be generated. This is done in
75 * floatXX_silence_nan(). For qNaN inputs the specifications
76 * says: "When possible, this QNaN result is one of the operand QNaN
77 * values." In practice it seems that most implementations choose
78 * the first operand if both operands are qNaN. In short this gives
79 * the following rules:
80 * 1. A if it is signaling
81 * 2. B if it is signaling
82 * 3. A (quiet)
83 * 4. B (quiet)
84 * A signaling NaN is always silenced before returning it.
85 */
86 set_float_2nan_prop_rule(float_2nan_prop_s_ab,
87 &env->active_fpu.fp_status);
88 /*
89 * TODO: the spec does't say clearly whether FTZ happens before
90 * or after rounding for normal FPU operations.
91 */
92 set_float_ftz_detection(float_ftz_before_rounding,
93 &env->active_fpu.fp_status);
94 }
95
96 /* MSA */
97
98 enum CPUMIPSMSADataFormat {
99 DF_BYTE = 0,
100 DF_HALF,
101 DF_WORD,
102 DF_DOUBLE
103 };
104
105 static inline void restore_msa_fp_status(CPUMIPSState *env)
106 {
107 float_status *status = &env->active_tc.msa_fp_status;
108 int rounding_mode = (env->active_tc.msacsr & MSACSR_RM_MASK) >> MSACSR_RM;
109 bool flush_to_zero = (env->active_tc.msacsr & MSACSR_FS_MASK) != 0;
110
111 set_float_rounding_mode(ieee_rm[rounding_mode], status);
112 set_flush_to_zero(flush_to_zero, status);
113 set_flush_inputs_to_zero(flush_to_zero, status);
114 }