| 1 | /* |
| 2 | * MIPS internal definitions and helpers |
| 3 | * |
| 4 | * This work is licensed under the terms of the GNU GPL, version 2 or later. |
| 5 | * See the COPYING file in the top-level directory. |
| 6 | */ |
| 7 | |
| 8 | #ifndef MIPS_INTERNAL_H |
| 9 | #define MIPS_INTERNAL_H |
| 10 | |
| 11 | #include "exec/memattrs.h" |
| 12 | #ifdef CONFIG_TCG |
| 13 | #include "tcg/tcg-internal.h" |
| 14 | #endif |
| 15 | #include "cpu.h" |
| 16 | |
| 17 | /* |
| 18 | * MMU types, the first four entries have the same layout as the |
| 19 | * CP0C0_MT field. |
| 20 | */ |
| 21 | enum mips_mmu_types { |
| 22 | MMU_TYPE_NONE = 0, |
| 23 | MMU_TYPE_R4000 = 1, /* Standard TLB */ |
| 24 | MMU_TYPE_BAT = 2, /* Block Address Translation */ |
| 25 | MMU_TYPE_FMT = 3, /* Fixed Mapping */ |
| 26 | MMU_TYPE_DVF = 4, /* Dual VTLB and FTLB */ |
| 27 | MMU_TYPE_R3000, |
| 28 | MMU_TYPE_R6000, |
| 29 | MMU_TYPE_R8000 |
| 30 | }; |
| 31 | |
| 32 | struct mips_def_t { |
| 33 | const char *name; |
| 34 | int32_t CP0_PRid; |
| 35 | int32_t CP0_Config0; |
| 36 | int32_t CP0_Config1; |
| 37 | int32_t CP0_Config2; |
| 38 | int32_t CP0_Config3; |
| 39 | int32_t CP0_Config4; |
| 40 | int32_t CP0_Config4_rw_bitmask; |
| 41 | int32_t CP0_Config5; |
| 42 | int32_t CP0_Config5_rw_bitmask; |
| 43 | int32_t CP0_Config6; |
| 44 | int32_t CP0_Config6_rw_bitmask; |
| 45 | int32_t CP0_Config7; |
| 46 | int32_t CP0_Config7_rw_bitmask; |
| 47 | target_ulong CP0_LLAddr_rw_bitmask; |
| 48 | int CP0_LLAddr_shift; |
| 49 | int32_t SYNCI_Step; |
| 50 | /* |
| 51 | * @CCRes: rate at which the coprocessor 0 counter increments |
| 52 | * |
| 53 | * The Count register acts as a timer, incrementing at a constant rate, |
| 54 | * whether or not an instruction is executed, retired, or any forward |
| 55 | * progress is made through the pipeline. The rate at which the counter |
| 56 | * increments is implementation dependent, and is a function of the |
| 57 | * pipeline clock of the processor, not the issue width of the processor. |
| 58 | */ |
| 59 | int32_t CCRes; |
| 60 | int32_t CP0_Status_rw_bitmask; |
| 61 | int32_t CP0_TCStatus_rw_bitmask; |
| 62 | int32_t CP0_SRSCtl; |
| 63 | int32_t CP1_fcr0; |
| 64 | int32_t CP1_fcr31_rw_bitmask; |
| 65 | int32_t CP1_fcr31; |
| 66 | int32_t MSAIR; |
| 67 | int32_t SEGBITS; |
| 68 | int32_t PABITS; |
| 69 | int32_t CP0_SRSConf0_rw_bitmask; |
| 70 | int32_t CP0_SRSConf0; |
| 71 | int32_t CP0_SRSConf1_rw_bitmask; |
| 72 | int32_t CP0_SRSConf1; |
| 73 | int32_t CP0_SRSConf2_rw_bitmask; |
| 74 | int32_t CP0_SRSConf2; |
| 75 | int32_t CP0_SRSConf3_rw_bitmask; |
| 76 | int32_t CP0_SRSConf3; |
| 77 | int32_t CP0_SRSConf4_rw_bitmask; |
| 78 | int32_t CP0_SRSConf4; |
| 79 | int32_t CP0_PageGrain_rw_bitmask; |
| 80 | int32_t CP0_PageGrain; |
| 81 | target_ulong CP0_EBaseWG_rw_bitmask; |
| 82 | uint32_t lcsr_cpucfg1; |
| 83 | uint32_t lcsr_cpucfg2; |
| 84 | uint64_t insn_flags; |
| 85 | enum mips_mmu_types mmu_type; |
| 86 | }; |
| 87 | |
| 88 | extern const char regnames[32][3]; |
| 89 | extern const char fregnames[32][4]; |
| 90 | |
| 91 | extern const struct mips_def_t mips_defs[]; |
| 92 | extern const int mips_defs_number; |
| 93 | |
| 94 | int mips_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); |
| 95 | int mips_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); |
| 96 | QTree *mips_octeon_llm_tree_new(void); |
| 97 | uint64_t mips_octeon_llm_load(QTree *tree, uint64_t addr); |
| 98 | void mips_octeon_llm_store(QTree **treep, uint64_t addr, uint64_t value); |
| 99 | |
| 100 | #define USEG_LIMIT ((target_ulong)(int32_t)0x7FFFFFFFUL) |
| 101 | #define KSEG0_BASE ((target_ulong)(int32_t)0x80000000UL) |
| 102 | #define KSEG1_BASE ((target_ulong)(int32_t)0xA0000000UL) |
| 103 | #define KSEG2_BASE ((target_ulong)(int32_t)0xC0000000UL) |
| 104 | #define KSEG3_BASE ((target_ulong)(int32_t)0xE0000000UL) |
| 105 | |
| 106 | #if !defined(CONFIG_USER_ONLY) |
| 107 | |
| 108 | enum { |
| 109 | TLBRET_XI = -6, |
| 110 | TLBRET_RI = -5, |
| 111 | TLBRET_DIRTY = -4, |
| 112 | TLBRET_INVALID = -3, |
| 113 | TLBRET_NOMATCH = -2, |
| 114 | TLBRET_BADADDR = -1, |
| 115 | TLBRET_MATCH = 0 |
| 116 | }; |
| 117 | |
| 118 | int get_physical_address(CPUMIPSState *env, hwaddr *physical, |
| 119 | int *prot, target_ulong real_address, |
| 120 | MMUAccessType access_type, int mmu_idx); |
| 121 | hwaddr mips_cpu_get_phys_addr_debug(CPUState *cpu, vaddr addr); |
| 122 | |
| 123 | typedef struct r4k_tlb_t r4k_tlb_t; |
| 124 | struct r4k_tlb_t { |
| 125 | target_ulong VPN; |
| 126 | uint32_t PageMask; |
| 127 | uint16_t ASID; |
| 128 | uint32_t MMID; |
| 129 | unsigned int G:1; |
| 130 | unsigned int C0:3; |
| 131 | unsigned int C1:3; |
| 132 | unsigned int V0:1; |
| 133 | unsigned int V1:1; |
| 134 | unsigned int D0:1; |
| 135 | unsigned int D1:1; |
| 136 | unsigned int XI0:1; |
| 137 | unsigned int XI1:1; |
| 138 | unsigned int RI0:1; |
| 139 | unsigned int RI1:1; |
| 140 | unsigned int EHINV:1; |
| 141 | uint64_t PFN[2]; |
| 142 | }; |
| 143 | |
| 144 | struct CPUMIPSTLBContext { |
| 145 | uint32_t nb_tlb; |
| 146 | uint32_t tlb_in_use; |
| 147 | int (*map_address)(CPUMIPSState *env, hwaddr *physical, int *prot, |
| 148 | target_ulong address, MMUAccessType access_type); |
| 149 | void (*helper_tlbwi)(CPUMIPSState *env); |
| 150 | void (*helper_tlbwr)(CPUMIPSState *env); |
| 151 | void (*helper_tlbp)(CPUMIPSState *env); |
| 152 | void (*helper_tlbr)(CPUMIPSState *env); |
| 153 | void (*helper_tlbinv)(CPUMIPSState *env); |
| 154 | void (*helper_tlbinvf)(CPUMIPSState *env); |
| 155 | union { |
| 156 | struct { |
| 157 | r4k_tlb_t tlb[MIPS_TLB_MAX]; |
| 158 | } r4k; |
| 159 | } mmu; |
| 160 | }; |
| 161 | |
| 162 | void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc); |
| 163 | void cpu_mips_store_status(CPUMIPSState *env, target_ulong val); |
| 164 | void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val); |
| 165 | |
| 166 | extern const VMStateDescription vmstate_mips_cpu; |
| 167 | |
| 168 | static inline bool cpu_mips_hw_interrupts_enabled(CPUMIPSState *env) |
| 169 | { |
| 170 | return (env->CP0_Status & (1 << CP0St_IE)) && |
| 171 | !(env->CP0_Status & (1 << CP0St_EXL)) && |
| 172 | !(env->CP0_Status & (1 << CP0St_ERL)) && |
| 173 | !(env->hflags & MIPS_HFLAG_DM) && |
| 174 | /* |
| 175 | * Note that the TCStatus IXMT field is initialized to zero, |
| 176 | * and only MT capable cores can set it to one. So we don't |
| 177 | * need to check for MT capabilities here. |
| 178 | */ |
| 179 | !(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_IXMT)); |
| 180 | } |
| 181 | |
| 182 | /* Check if there is pending and not masked out interrupt */ |
| 183 | static inline bool cpu_mips_hw_interrupts_pending(CPUMIPSState *env) |
| 184 | { |
| 185 | int32_t pending; |
| 186 | int32_t status; |
| 187 | bool r; |
| 188 | |
| 189 | pending = env->CP0_Cause & CP0Ca_IP_mask; |
| 190 | status = env->CP0_Status & CP0Ca_IP_mask; |
| 191 | |
| 192 | if (env->CP0_Config3 & (1 << CP0C3_VEIC)) { |
| 193 | /* |
| 194 | * A MIPS configured with a vectorizing external interrupt controller |
| 195 | * will feed a vector into the Cause pending lines. The core treats |
| 196 | * the status lines as a vector level, not as individual masks. |
| 197 | */ |
| 198 | r = pending > status; |
| 199 | } else { |
| 200 | /* |
| 201 | * A MIPS configured with compatibility or VInt (Vectored Interrupts) |
| 202 | * treats the pending lines as individual interrupt lines, the status |
| 203 | * lines are individual masks. |
| 204 | */ |
| 205 | r = (pending & status) != 0; |
| 206 | } |
| 207 | return r; |
| 208 | } |
| 209 | |
| 210 | #endif /* !CONFIG_USER_ONLY */ |
| 211 | |
| 212 | void msa_reset(CPUMIPSState *env); |
| 213 | |
| 214 | /* cp0_timer.c */ |
| 215 | uint32_t cpu_mips_get_count(CPUMIPSState *env); |
| 216 | void cpu_mips_store_count(CPUMIPSState *env, uint32_t value); |
| 217 | void cpu_mips_store_compare(CPUMIPSState *env, uint32_t value); |
| 218 | void cpu_mips_start_count(CPUMIPSState *env); |
| 219 | void cpu_mips_stop_count(CPUMIPSState *env); |
| 220 | |
| 221 | static inline void mips_env_set_pc(CPUMIPSState *env, target_ulong value) |
| 222 | { |
| 223 | env->active_tc.PC = value & ~(target_ulong)1; |
| 224 | if (value & 1) { |
| 225 | env->hflags |= MIPS_HFLAG_M16; |
| 226 | } else { |
| 227 | env->hflags &= ~(MIPS_HFLAG_M16); |
| 228 | } |
| 229 | } |
| 230 | |
| 231 | static inline bool mips_env_is_bigendian(CPUMIPSState *env) |
| 232 | { |
| 233 | return extract32(env->CP0_Config0, CP0C0_BE, 1); |
| 234 | } |
| 235 | |
| 236 | static inline MemOp mo_endian_env(CPUMIPSState *env) |
| 237 | { |
| 238 | return mips_env_is_bigendian(env) ? MO_BE : MO_LE; |
| 239 | } |
| 240 | |
| 241 | static inline void restore_pamask(CPUMIPSState *env) |
| 242 | { |
| 243 | if (env->hflags & MIPS_HFLAG_ELPA) { |
| 244 | env->PAMask = (1ULL << env->PABITS) - 1; |
| 245 | } else { |
| 246 | env->PAMask = PAMASK_BASE; |
| 247 | } |
| 248 | } |
| 249 | |
| 250 | static inline int mips_vpe_active(CPUMIPSState *env) |
| 251 | { |
| 252 | MIPSCPU *cpu = env_archcpu(env); |
| 253 | int active = 1; |
| 254 | |
| 255 | /* Check that the VPE is enabled. */ |
| 256 | if (!(cpu->mvp->CP0_MVPControl & (1 << CP0MVPCo_EVP))) { |
| 257 | active = 0; |
| 258 | } |
| 259 | /* Check that the VPE is activated. */ |
| 260 | if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))) { |
| 261 | active = 0; |
| 262 | } |
| 263 | |
| 264 | /* |
| 265 | * Now verify that there are active thread contexts in the VPE. |
| 266 | * |
| 267 | * This assumes the CPU model will internally reschedule threads |
| 268 | * if the active one goes to sleep. If there are no threads available |
| 269 | * the active one will be in a sleeping state, and we can turn off |
| 270 | * the entire VPE. |
| 271 | */ |
| 272 | if (!(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_A))) { |
| 273 | /* TC is not activated. */ |
| 274 | active = 0; |
| 275 | } |
| 276 | if (env->active_tc.CP0_TCHalt & 1) { |
| 277 | /* TC is in halt state. */ |
| 278 | active = 0; |
| 279 | } |
| 280 | |
| 281 | return active; |
| 282 | } |
| 283 | |
| 284 | static inline int mips_vp_active(CPUMIPSState *env) |
| 285 | { |
| 286 | CPUState *cs; |
| 287 | |
| 288 | /* Check if the VP disabled other VPs (which means the VP is enabled) */ |
| 289 | if ((env->CP0_VPControl >> CP0VPCtl_DIS) & 1) { |
| 290 | return 1; |
| 291 | } |
| 292 | |
| 293 | /* Check if the virtual processor is disabled due to a DVP */ |
| 294 | CPU_FOREACH(cs) { |
| 295 | CPUMIPSState *other_env = cpu_env(cs); |
| 296 | |
| 297 | if ((other_env != env) && |
| 298 | ((other_env->CP0_VPControl >> CP0VPCtl_DIS) & 1)) { |
| 299 | return 0; |
| 300 | } |
| 301 | } |
| 302 | return 1; |
| 303 | } |
| 304 | |
| 305 | static inline void compute_hflags(CPUMIPSState *env) |
| 306 | { |
| 307 | env->hflags &= ~(MIPS_HFLAG_COP1X | MIPS_HFLAG_64 | MIPS_HFLAG_CP0 | |
| 308 | MIPS_HFLAG_F64 | MIPS_HFLAG_FPU | MIPS_HFLAG_KSU | |
| 309 | MIPS_HFLAG_AWRAP | MIPS_HFLAG_DSP | MIPS_HFLAG_DSP_R2 | |
| 310 | MIPS_HFLAG_DSP_R3 | MIPS_HFLAG_SBRI | MIPS_HFLAG_MSA | |
| 311 | MIPS_HFLAG_FRE | MIPS_HFLAG_ELPA | MIPS_HFLAG_ERL); |
| 312 | if (env->CP0_Status & (1 << CP0St_ERL)) { |
| 313 | env->hflags |= MIPS_HFLAG_ERL; |
| 314 | } |
| 315 | if (!(env->CP0_Status & (1 << CP0St_EXL)) && |
| 316 | !(env->CP0_Status & (1 << CP0St_ERL)) && |
| 317 | !(env->hflags & MIPS_HFLAG_DM)) { |
| 318 | env->hflags |= (env->CP0_Status >> CP0St_KSU) & |
| 319 | MIPS_HFLAG_KSU; |
| 320 | } |
| 321 | #if defined(TARGET_MIPS64) |
| 322 | if ((env->insn_flags & ISA_MIPS3) && |
| 323 | (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_UM) || |
| 324 | (env->CP0_Status & (1 << CP0St_PX)) || |
| 325 | (env->CP0_Status & (1 << CP0St_UX)))) { |
| 326 | env->hflags |= MIPS_HFLAG_64; |
| 327 | } |
| 328 | |
| 329 | if (!(env->insn_flags & ISA_MIPS3)) { |
| 330 | env->hflags |= MIPS_HFLAG_AWRAP; |
| 331 | } else if (((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_UM) && |
| 332 | !(env->CP0_Status & (1 << CP0St_UX))) { |
| 333 | env->hflags |= MIPS_HFLAG_AWRAP; |
| 334 | } else if (env->insn_flags & ISA_MIPS_R6) { |
| 335 | /* Address wrapping for Supervisor and Kernel is specified in R6 */ |
| 336 | if ((((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_SM) && |
| 337 | !(env->CP0_Status & (1 << CP0St_SX))) || |
| 338 | (((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_KM) && |
| 339 | !(env->CP0_Status & (1 << CP0St_KX)))) { |
| 340 | env->hflags |= MIPS_HFLAG_AWRAP; |
| 341 | } |
| 342 | } |
| 343 | #endif |
| 344 | if (((env->CP0_Status & (1 << CP0St_CU0)) && |
| 345 | !(env->insn_flags & ISA_MIPS_R6)) || |
| 346 | !(env->hflags & MIPS_HFLAG_KSU)) { |
| 347 | env->hflags |= MIPS_HFLAG_CP0; |
| 348 | } |
| 349 | if (env->CP0_Status & (1 << CP0St_CU1)) { |
| 350 | env->hflags |= MIPS_HFLAG_FPU; |
| 351 | } |
| 352 | if (env->CP0_Status & (1 << CP0St_FR)) { |
| 353 | env->hflags |= MIPS_HFLAG_F64; |
| 354 | } |
| 355 | if (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_KM) && |
| 356 | (env->CP0_Config5 & (1 << CP0C5_SBRI))) { |
| 357 | env->hflags |= MIPS_HFLAG_SBRI; |
| 358 | } |
| 359 | if (env->insn_flags & ASE_DSP_R3) { |
| 360 | /* |
| 361 | * Our cpu supports DSP R3 ASE, so enable |
| 362 | * access to DSP R3 resources. |
| 363 | */ |
| 364 | if (env->CP0_Status & (1 << CP0St_MX)) { |
| 365 | env->hflags |= MIPS_HFLAG_DSP | MIPS_HFLAG_DSP_R2 | |
| 366 | MIPS_HFLAG_DSP_R3; |
| 367 | } |
| 368 | } else if (env->insn_flags & ASE_DSP_R2) { |
| 369 | /* |
| 370 | * Our cpu supports DSP R2 ASE, so enable |
| 371 | * access to DSP R2 resources. |
| 372 | */ |
| 373 | if (env->CP0_Status & (1 << CP0St_MX)) { |
| 374 | env->hflags |= MIPS_HFLAG_DSP | MIPS_HFLAG_DSP_R2; |
| 375 | } |
| 376 | |
| 377 | } else if (env->insn_flags & ASE_DSP) { |
| 378 | /* |
| 379 | * Our cpu supports DSP ASE, so enable |
| 380 | * access to DSP resources. |
| 381 | */ |
| 382 | if (env->CP0_Status & (1 << CP0St_MX)) { |
| 383 | env->hflags |= MIPS_HFLAG_DSP; |
| 384 | } |
| 385 | |
| 386 | } |
| 387 | if (env->insn_flags & ISA_MIPS_R2) { |
| 388 | if (env->active_fpu.fcr0 & (1 << FCR0_F64)) { |
| 389 | env->hflags |= MIPS_HFLAG_COP1X; |
| 390 | } |
| 391 | } else if (env->insn_flags & ISA_MIPS_R1) { |
| 392 | if (env->hflags & MIPS_HFLAG_64) { |
| 393 | env->hflags |= MIPS_HFLAG_COP1X; |
| 394 | } |
| 395 | } else if (env->insn_flags & ISA_MIPS4) { |
| 396 | /* |
| 397 | * All supported MIPS IV CPUs use the XX (CU3) to enable |
| 398 | * and disable the MIPS IV extensions to the MIPS III ISA. |
| 399 | * Some other MIPS IV CPUs ignore the bit, so the check here |
| 400 | * would be too restrictive for them. |
| 401 | */ |
| 402 | if (env->CP0_Status & (1U << CP0St_CU3)) { |
| 403 | env->hflags |= MIPS_HFLAG_COP1X; |
| 404 | } |
| 405 | } |
| 406 | if (ase_msa_available(env)) { |
| 407 | if (env->CP0_Config5 & (1 << CP0C5_MSAEn)) { |
| 408 | env->hflags |= MIPS_HFLAG_MSA; |
| 409 | } |
| 410 | } |
| 411 | if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) { |
| 412 | if (env->CP0_Config5 & (1 << CP0C5_FRE)) { |
| 413 | env->hflags |= MIPS_HFLAG_FRE; |
| 414 | } |
| 415 | } |
| 416 | if (env->CP0_Config3 & (1 << CP0C3_LPA)) { |
| 417 | if (env->CP0_PageGrain & (1 << CP0PG_ELPA)) { |
| 418 | env->hflags |= MIPS_HFLAG_ELPA; |
| 419 | } |
| 420 | } |
| 421 | } |
| 422 | |
| 423 | #endif |