| 1 | #include "qemu/osdep.h" |
| 2 | #include "qemu/target-info.h" |
| 3 | #include "cpu.h" |
| 4 | #include "internal.h" |
| 5 | #include "migration/cpu.h" |
| 6 | #include "migration/qemu-file-types.h" |
| 7 | #include "fpu_helper.h" |
| 8 | #include "qemu/timer.h" |
| 9 | |
| 10 | static int cpu_post_load(void *opaque, int version_id) |
| 11 | { |
| 12 | MIPSCPU *cpu = opaque; |
| 13 | CPUMIPSState *env = &cpu->env; |
| 14 | |
| 15 | restore_fp_status(env); |
| 16 | restore_msa_fp_status(env); |
| 17 | compute_hflags(env); |
| 18 | restore_pamask(env); |
| 19 | |
| 20 | return 0; |
| 21 | } |
| 22 | |
| 23 | /* FPU state */ |
| 24 | |
| 25 | static int get_fpr(QEMUFile *f, void *pv, size_t size, |
| 26 | const VMStateField *field) |
| 27 | { |
| 28 | int i; |
| 29 | fpr_t *v = pv; |
| 30 | /* Restore entire MSA vector register */ |
| 31 | for (i = 0; i < MSA_WRLEN / 64; i++) { |
| 32 | qemu_get_sbe64s(f, &v->wr.d[i]); |
| 33 | } |
| 34 | return 0; |
| 35 | } |
| 36 | |
| 37 | static int put_fpr(QEMUFile *f, void *pv, size_t size, |
| 38 | const VMStateField *field, JSONWriter *vmdesc) |
| 39 | { |
| 40 | int i; |
| 41 | fpr_t *v = pv; |
| 42 | /* Save entire MSA vector register */ |
| 43 | for (i = 0; i < MSA_WRLEN / 64; i++) { |
| 44 | qemu_put_sbe64s(f, &v->wr.d[i]); |
| 45 | } |
| 46 | |
| 47 | return 0; |
| 48 | } |
| 49 | |
| 50 | static const VMStateInfo vmstate_info_fpr = { |
| 51 | .name = "fpr", |
| 52 | .get = get_fpr, |
| 53 | .put = put_fpr, |
| 54 | }; |
| 55 | |
| 56 | #define VMSTATE_FPR_ARRAY_V(_f, _s, _n, _v) \ |
| 57 | VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_fpr, fpr_t) |
| 58 | |
| 59 | #define VMSTATE_FPR_ARRAY(_f, _s, _n) \ |
| 60 | VMSTATE_FPR_ARRAY_V(_f, _s, _n, 0) |
| 61 | |
| 62 | static const VMStateField vmstate_fpu_fields[] = { |
| 63 | VMSTATE_FPR_ARRAY(fpr, CPUMIPSFPUContext, 32), |
| 64 | VMSTATE_UINT32(fcr0, CPUMIPSFPUContext), |
| 65 | VMSTATE_UINT32(fcr31, CPUMIPSFPUContext), |
| 66 | VMSTATE_END_OF_LIST() |
| 67 | }; |
| 68 | |
| 69 | static const VMStateDescription vmstate_fpu = { |
| 70 | .name = "cpu/fpu", |
| 71 | .version_id = 1, |
| 72 | .minimum_version_id = 1, |
| 73 | .fields = vmstate_fpu_fields |
| 74 | }; |
| 75 | |
| 76 | static const VMStateDescription vmstate_inactive_fpu = { |
| 77 | .name = "cpu/inactive_fpu", |
| 78 | .version_id = 1, |
| 79 | .minimum_version_id = 1, |
| 80 | .fields = vmstate_fpu_fields |
| 81 | }; |
| 82 | |
| 83 | /* TC state */ |
| 84 | |
| 85 | static const VMStateField vmstate_tc_fields[] = { |
| 86 | VMSTATE_UINTTL_ARRAY(gpr, TCState, 32), |
| 87 | #if defined(TARGET_MIPS64) |
| 88 | VMSTATE_UINT64_ARRAY(gpr_hi, TCState, 32), |
| 89 | #endif /* TARGET_MIPS64 */ |
| 90 | VMSTATE_UINTTL(PC, TCState), |
| 91 | VMSTATE_UINTTL_ARRAY(HI, TCState, MIPS_DSP_ACC), |
| 92 | VMSTATE_UINTTL_ARRAY(LO, TCState, MIPS_DSP_ACC), |
| 93 | VMSTATE_UINTTL_ARRAY(ACX, TCState, MIPS_DSP_ACC), |
| 94 | VMSTATE_UINTTL(DSPControl, TCState), |
| 95 | VMSTATE_INT32(CP0_TCStatus, TCState), |
| 96 | VMSTATE_INT32(CP0_TCBind, TCState), |
| 97 | VMSTATE_UINTTL(CP0_TCHalt, TCState), |
| 98 | VMSTATE_UINTTL(CP0_TCContext, TCState), |
| 99 | VMSTATE_UINTTL(CP0_TCSchedule, TCState), |
| 100 | VMSTATE_UINTTL(CP0_TCScheFBack, TCState), |
| 101 | VMSTATE_INT32(CP0_Debug_tcstatus, TCState), |
| 102 | VMSTATE_UINTTL(CP0_UserLocal, TCState), |
| 103 | VMSTATE_INT32(msacsr, TCState), |
| 104 | VMSTATE_UINTTL_ARRAY(mxu_gpr, TCState, NUMBER_OF_MXU_REGISTERS - 1), |
| 105 | VMSTATE_UINTTL(mxu_cr, TCState), |
| 106 | VMSTATE_END_OF_LIST() |
| 107 | }; |
| 108 | |
| 109 | static const VMStateDescription vmstate_tc = { |
| 110 | .name = "cpu/tc", |
| 111 | .version_id = 2, |
| 112 | .minimum_version_id = 2, |
| 113 | .fields = vmstate_tc_fields |
| 114 | }; |
| 115 | |
| 116 | static const VMStateDescription vmstate_inactive_tc = { |
| 117 | .name = "cpu/inactive_tc", |
| 118 | .version_id = 2, |
| 119 | .minimum_version_id = 2, |
| 120 | .fields = vmstate_tc_fields |
| 121 | }; |
| 122 | |
| 123 | static const VMStateDescription vmstate_octeon_multiplier_tc = { |
| 124 | .name = "cpu/tc/octeon_multiplier", |
| 125 | .version_id = 1, |
| 126 | .minimum_version_id = 1, |
| 127 | .fields = (const VMStateField[]) { |
| 128 | VMSTATE_UINT64_ARRAY(octeon.MPL, TCState, OCTEON_MULTIPLIER_REGS), |
| 129 | VMSTATE_UINT64_ARRAY(octeon.P, TCState, OCTEON_MULTIPLIER_REGS), |
| 130 | VMSTATE_END_OF_LIST() |
| 131 | } |
| 132 | }; |
| 133 | |
| 134 | typedef struct OcteonLLMTreePutData { |
| 135 | QEMUFile *f; |
| 136 | } OcteonLLMTreePutData; |
| 137 | |
| 138 | static gboolean put_octeon_llm_tree_entry(gpointer key, gpointer value, |
| 139 | gpointer user_data) |
| 140 | { |
| 141 | OcteonLLMTreePutData *data = user_data; |
| 142 | |
| 143 | qemu_put_be64(data->f, *(uint64_t *)key); |
| 144 | qemu_put_be64(data->f, *(uint64_t *)value); |
| 145 | return false; |
| 146 | } |
| 147 | |
| 148 | static int put_octeon_llm_tree(QEMUFile *f, void *pv, size_t size, |
| 149 | const VMStateField *field, JSONWriter *vmdesc) |
| 150 | { |
| 151 | QTree *tree = *(QTree **)pv; |
| 152 | OcteonLLMTreePutData data = { .f = f }; |
| 153 | uint32_t nnodes = tree ? q_tree_nnodes(tree) : 0; |
| 154 | |
| 155 | qemu_put_be32(f, nnodes); |
| 156 | if (tree) { |
| 157 | q_tree_foreach(tree, put_octeon_llm_tree_entry, &data); |
| 158 | } |
| 159 | |
| 160 | return 0; |
| 161 | } |
| 162 | |
| 163 | static int get_octeon_llm_tree(QEMUFile *f, void *pv, size_t size, |
| 164 | const VMStateField *field) |
| 165 | { |
| 166 | QTree **treep = pv; |
| 167 | uint32_t nnodes = qemu_get_be32(f); |
| 168 | |
| 169 | if (*treep) { |
| 170 | q_tree_destroy(*treep); |
| 171 | } |
| 172 | *treep = mips_octeon_llm_tree_new(); |
| 173 | |
| 174 | for (uint32_t i = 0; i < nnodes; i++) { |
| 175 | uint64_t addr = qemu_get_be64(f); |
| 176 | uint64_t value = qemu_get_be64(f); |
| 177 | |
| 178 | mips_octeon_llm_store(treep, addr, value); |
| 179 | } |
| 180 | |
| 181 | return 0; |
| 182 | } |
| 183 | |
| 184 | static const VMStateInfo vmstate_info_octeon_llm_tree = { |
| 185 | .name = "octeon_llm_tree", |
| 186 | .get = get_octeon_llm_tree, |
| 187 | .put = put_octeon_llm_tree, |
| 188 | }; |
| 189 | |
| 190 | #define VMSTATE_OCTEON_LLM_TREE(_f, _s) { \ |
| 191 | .name = stringify(_f), \ |
| 192 | .version_id = 1, \ |
| 193 | .info = &vmstate_info_octeon_llm_tree, \ |
| 194 | .offset = vmstate_offset_pointer(_s, _f, QTree), \ |
| 195 | } |
| 196 | |
| 197 | /* MVP state */ |
| 198 | |
| 199 | static const VMStateDescription vmstate_mvp = { |
| 200 | .name = "cpu/mvp", |
| 201 | .version_id = 1, |
| 202 | .minimum_version_id = 1, |
| 203 | .fields = (const VMStateField[]) { |
| 204 | VMSTATE_INT32(CP0_MVPControl, CPUMIPSMVPContext), |
| 205 | VMSTATE_INT32(CP0_MVPConf0, CPUMIPSMVPContext), |
| 206 | VMSTATE_INT32(CP0_MVPConf1, CPUMIPSMVPContext), |
| 207 | VMSTATE_END_OF_LIST() |
| 208 | } |
| 209 | }; |
| 210 | |
| 211 | /* TLB state */ |
| 212 | |
| 213 | static int get_tlb(QEMUFile *f, void *pv, size_t size, |
| 214 | const VMStateField *field) |
| 215 | { |
| 216 | r4k_tlb_t *v = pv; |
| 217 | uint16_t flags; |
| 218 | |
| 219 | if (target_long_bits() == 64) { |
| 220 | v->VPN = qemu_get_be64(f); |
| 221 | } else { |
| 222 | v->VPN = qemu_get_be32(f); |
| 223 | } |
| 224 | qemu_get_be32s(f, &v->PageMask); |
| 225 | qemu_get_be16s(f, &v->ASID); |
| 226 | qemu_get_be32s(f, &v->MMID); |
| 227 | qemu_get_be16s(f, &flags); |
| 228 | v->G = (flags >> 10) & 1; |
| 229 | v->C0 = (flags >> 7) & 3; |
| 230 | v->C1 = (flags >> 4) & 3; |
| 231 | v->V0 = (flags >> 3) & 1; |
| 232 | v->V1 = (flags >> 2) & 1; |
| 233 | v->D0 = (flags >> 1) & 1; |
| 234 | v->D1 = (flags >> 0) & 1; |
| 235 | v->EHINV = (flags >> 15) & 1; |
| 236 | v->RI1 = (flags >> 14) & 1; |
| 237 | v->RI0 = (flags >> 13) & 1; |
| 238 | v->XI1 = (flags >> 12) & 1; |
| 239 | v->XI0 = (flags >> 11) & 1; |
| 240 | qemu_get_be64s(f, &v->PFN[0]); |
| 241 | qemu_get_be64s(f, &v->PFN[1]); |
| 242 | |
| 243 | return 0; |
| 244 | } |
| 245 | |
| 246 | static int put_tlb(QEMUFile *f, void *pv, size_t size, |
| 247 | const VMStateField *field, JSONWriter *vmdesc) |
| 248 | { |
| 249 | r4k_tlb_t *v = pv; |
| 250 | |
| 251 | uint16_t asid = v->ASID; |
| 252 | uint32_t mmid = v->MMID; |
| 253 | uint16_t flags = ((v->EHINV << 15) | |
| 254 | (v->RI1 << 14) | |
| 255 | (v->RI0 << 13) | |
| 256 | (v->XI1 << 12) | |
| 257 | (v->XI0 << 11) | |
| 258 | (v->G << 10) | |
| 259 | (v->C0 << 7) | |
| 260 | (v->C1 << 4) | |
| 261 | (v->V0 << 3) | |
| 262 | (v->V1 << 2) | |
| 263 | (v->D0 << 1) | |
| 264 | (v->D1 << 0)); |
| 265 | |
| 266 | if (target_long_bits() == 64) { |
| 267 | qemu_put_be64(f, v->VPN); |
| 268 | } else { |
| 269 | qemu_put_be32(f, v->VPN); |
| 270 | } |
| 271 | qemu_put_be32s(f, &v->PageMask); |
| 272 | qemu_put_be16s(f, &asid); |
| 273 | qemu_put_be32s(f, &mmid); |
| 274 | qemu_put_be16s(f, &flags); |
| 275 | qemu_put_be64s(f, &v->PFN[0]); |
| 276 | qemu_put_be64s(f, &v->PFN[1]); |
| 277 | |
| 278 | return 0; |
| 279 | } |
| 280 | |
| 281 | static const VMStateInfo vmstate_info_tlb = { |
| 282 | .name = "tlb_entry", |
| 283 | .get = get_tlb, |
| 284 | .put = put_tlb, |
| 285 | }; |
| 286 | |
| 287 | #define VMSTATE_TLB_ARRAY_V(_f, _s, _n, _v) \ |
| 288 | VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_tlb, r4k_tlb_t) |
| 289 | |
| 290 | #define VMSTATE_TLB_ARRAY(_f, _s, _n) \ |
| 291 | VMSTATE_TLB_ARRAY_V(_f, _s, _n, 0) |
| 292 | |
| 293 | static const VMStateDescription vmstate_tlb = { |
| 294 | .name = "cpu/tlb", |
| 295 | .version_id = 3, |
| 296 | .minimum_version_id = 3, |
| 297 | .fields = (const VMStateField[]) { |
| 298 | VMSTATE_UINT32(nb_tlb, CPUMIPSTLBContext), |
| 299 | VMSTATE_UINT32(tlb_in_use, CPUMIPSTLBContext), |
| 300 | VMSTATE_TLB_ARRAY(mmu.r4k.tlb, CPUMIPSTLBContext, MIPS_TLB_MAX), |
| 301 | VMSTATE_END_OF_LIST() |
| 302 | } |
| 303 | }; |
| 304 | |
| 305 | /* MIPS CPU state */ |
| 306 | |
| 307 | static bool mips_timer_needed(void *opaque) |
| 308 | { |
| 309 | MIPSCPU *cpu = opaque; |
| 310 | return cpu->env.timer != NULL; |
| 311 | } |
| 312 | |
| 313 | static const VMStateDescription mips_vmstate_timer = { |
| 314 | .name = "cpu/timer", |
| 315 | .version_id = 1, |
| 316 | .minimum_version_id = 1, |
| 317 | .needed = mips_timer_needed, |
| 318 | .fields = (const VMStateField[]) { |
| 319 | VMSTATE_TIMER_PTR(env.timer, MIPSCPU), |
| 320 | VMSTATE_END_OF_LIST() |
| 321 | } |
| 322 | }; |
| 323 | |
| 324 | static bool mips_octeon_needed(void *opaque) |
| 325 | { |
| 326 | MIPSCPU *cpu = opaque; |
| 327 | |
| 328 | return cpu->env.insn_flags & INSN_OCTEON; |
| 329 | } |
| 330 | |
| 331 | static const VMStateDescription mips_vmstate_octeon_multiplier = { |
| 332 | .name = "cpu/octeon_multiplier", |
| 333 | .version_id = 1, |
| 334 | .minimum_version_id = 1, |
| 335 | .needed = mips_octeon_needed, |
| 336 | .fields = (const VMStateField[]) { |
| 337 | VMSTATE_STRUCT(env.active_tc, MIPSCPU, 1, |
| 338 | vmstate_octeon_multiplier_tc, TCState), |
| 339 | VMSTATE_STRUCT_ARRAY(env.tcs, MIPSCPU, MIPS_SHADOW_SET_MAX, 1, |
| 340 | vmstate_octeon_multiplier_tc, TCState), |
| 341 | VMSTATE_END_OF_LIST() |
| 342 | } |
| 343 | }; |
| 344 | |
| 345 | static const VMStateDescription mips_vmstate_octeon_crypto = { |
| 346 | .name = "cpu/octeon_crypto", |
| 347 | .version_id = 1, |
| 348 | .minimum_version_id = 1, |
| 349 | .needed = mips_octeon_needed, |
| 350 | .fields = (const VMStateField[]) { |
| 351 | VMSTATE_UINT64_ARRAY(env.octeon_crypto.hsh_dat, MIPSCPU, 16), |
| 352 | VMSTATE_UINT64_ARRAY(env.octeon_crypto.hsh_iv, MIPSCPU, 8), |
| 353 | VMSTATE_UINT64(env.octeon_crypto.sha3_dat24, MIPSCPU), |
| 354 | VMSTATE_UINT64_ARRAY(env.octeon_crypto.des3_key, MIPSCPU, 3), |
| 355 | VMSTATE_UINT64(env.octeon_crypto.des3_iv, MIPSCPU), |
| 356 | VMSTATE_UINT64(env.octeon_crypto.des3_result, MIPSCPU), |
| 357 | VMSTATE_UINT64_ARRAY(env.octeon_crypto.aes_resinp, MIPSCPU, 2), |
| 358 | VMSTATE_UINT64_ARRAY(env.octeon_crypto.aes_iv, MIPSCPU, 2), |
| 359 | VMSTATE_UINT64_ARRAY(env.octeon_crypto.aes_key, MIPSCPU, 4), |
| 360 | VMSTATE_UINT32(env.octeon_crypto.crc_poly, MIPSCPU), |
| 361 | VMSTATE_UINT32(env.octeon_crypto.crc_iv, MIPSCPU), |
| 362 | VMSTATE_UINT64_ARRAY(env.octeon_crypto.gfm_mul, MIPSCPU, 2), |
| 363 | VMSTATE_UINT64_ARRAY(env.octeon_crypto.gfm_resinp, MIPSCPU, 2), |
| 364 | VMSTATE_UINT16(env.octeon_crypto.gfm_poly, MIPSCPU), |
| 365 | VMSTATE_UINT8(env.octeon_crypto.aes_keylen, MIPSCPU), |
| 366 | VMSTATE_UINT8(env.octeon_crypto.crc_len, MIPSCPU), |
| 367 | VMSTATE_UINT64(env.octeon_crypto.chord, MIPSCPU), |
| 368 | VMSTATE_UINT64_ARRAY(env.octeon_crypto.llm_data, MIPSCPU, 2), |
| 369 | VMSTATE_OCTEON_LLM_TREE(env.octeon_crypto.llm36, MIPSCPU), |
| 370 | VMSTATE_OCTEON_LLM_TREE(env.octeon_crypto.llm64, MIPSCPU), |
| 371 | VMSTATE_END_OF_LIST() |
| 372 | } |
| 373 | }; |
| 374 | |
| 375 | const VMStateDescription vmstate_mips_cpu = { |
| 376 | .name = "cpu", |
| 377 | .version_id = 21, |
| 378 | .minimum_version_id = 21, |
| 379 | .post_load = cpu_post_load, |
| 380 | .fields = (const VMStateField[]) { |
| 381 | /* Active TC */ |
| 382 | VMSTATE_STRUCT(env.active_tc, MIPSCPU, 1, vmstate_tc, TCState), |
| 383 | |
| 384 | /* Active FPU */ |
| 385 | VMSTATE_STRUCT(env.active_fpu, MIPSCPU, 1, vmstate_fpu, |
| 386 | CPUMIPSFPUContext), |
| 387 | |
| 388 | /* MVP */ |
| 389 | VMSTATE_STRUCT_POINTER(mvp, MIPSCPU, vmstate_mvp, |
| 390 | CPUMIPSMVPContext), |
| 391 | |
| 392 | /* TLB */ |
| 393 | VMSTATE_STRUCT_POINTER(env.tlb, MIPSCPU, vmstate_tlb, |
| 394 | CPUMIPSTLBContext), |
| 395 | |
| 396 | /* CPU metastate */ |
| 397 | VMSTATE_UINT32(env.current_tc, MIPSCPU), |
| 398 | VMSTATE_UNUSED(sizeof(uint32_t)), /* was current_fpu */ |
| 399 | VMSTATE_INT32(env.error_code, MIPSCPU), |
| 400 | VMSTATE_UINTTL(env.btarget, MIPSCPU), |
| 401 | VMSTATE_UINTTL(env.bcond, MIPSCPU), |
| 402 | |
| 403 | /* Remaining CP0 registers */ |
| 404 | VMSTATE_INT32(env.CP0_Index, MIPSCPU), |
| 405 | VMSTATE_INT32(env.CP0_VPControl, MIPSCPU), |
| 406 | VMSTATE_INT32(env.CP0_Random, MIPSCPU), |
| 407 | VMSTATE_INT32(env.CP0_VPEControl, MIPSCPU), |
| 408 | VMSTATE_INT32(env.CP0_VPEConf0, MIPSCPU), |
| 409 | VMSTATE_INT32(env.CP0_VPEConf1, MIPSCPU), |
| 410 | VMSTATE_UINTTL(env.CP0_YQMask, MIPSCPU), |
| 411 | VMSTATE_UINTTL(env.CP0_VPESchedule, MIPSCPU), |
| 412 | VMSTATE_UINTTL(env.CP0_VPEScheFBack, MIPSCPU), |
| 413 | VMSTATE_INT32(env.CP0_VPEOpt, MIPSCPU), |
| 414 | VMSTATE_UINT64(env.CP0_EntryLo0, MIPSCPU), |
| 415 | VMSTATE_UINT64(env.CP0_EntryLo1, MIPSCPU), |
| 416 | VMSTATE_INT32(env.CP0_GlobalNumber, MIPSCPU), |
| 417 | VMSTATE_UINTTL(env.CP0_Context, MIPSCPU), |
| 418 | VMSTATE_INT32(env.CP0_MemoryMapID, MIPSCPU), |
| 419 | VMSTATE_INT32(env.CP0_PageMask, MIPSCPU), |
| 420 | VMSTATE_INT32(env.CP0_PageGrain, MIPSCPU), |
| 421 | VMSTATE_UINTTL(env.CP0_SegCtl0, MIPSCPU), |
| 422 | VMSTATE_UINTTL(env.CP0_SegCtl1, MIPSCPU), |
| 423 | VMSTATE_UINTTL(env.CP0_SegCtl2, MIPSCPU), |
| 424 | VMSTATE_UINTTL(env.CP0_PWBase, MIPSCPU), |
| 425 | VMSTATE_UINTTL(env.CP0_PWField, MIPSCPU), |
| 426 | VMSTATE_UINTTL(env.CP0_PWSize, MIPSCPU), |
| 427 | VMSTATE_INT32(env.CP0_Wired, MIPSCPU), |
| 428 | VMSTATE_INT32(env.CP0_PWCtl, MIPSCPU), |
| 429 | VMSTATE_INT32(env.CP0_SRSConf0, MIPSCPU), |
| 430 | VMSTATE_INT32(env.CP0_SRSConf1, MIPSCPU), |
| 431 | VMSTATE_INT32(env.CP0_SRSConf2, MIPSCPU), |
| 432 | VMSTATE_INT32(env.CP0_SRSConf3, MIPSCPU), |
| 433 | VMSTATE_INT32(env.CP0_SRSConf4, MIPSCPU), |
| 434 | VMSTATE_INT32(env.CP0_HWREna, MIPSCPU), |
| 435 | VMSTATE_UINTTL(env.CP0_BadVAddr, MIPSCPU), |
| 436 | VMSTATE_UINT32(env.CP0_BadInstr, MIPSCPU), |
| 437 | VMSTATE_UINT32(env.CP0_BadInstrP, MIPSCPU), |
| 438 | VMSTATE_UINT32(env.CP0_BadInstrX, MIPSCPU), |
| 439 | VMSTATE_INT32(env.CP0_Count, MIPSCPU), |
| 440 | VMSTATE_UNUSED(sizeof(uint32_t)), /* was CP0_SAARI */ |
| 441 | VMSTATE_UNUSED(2 * sizeof(uint64_t)), /* was CP0_SAAR[2] */ |
| 442 | VMSTATE_UINTTL(env.CP0_EntryHi, MIPSCPU), |
| 443 | VMSTATE_INT32(env.CP0_Compare, MIPSCPU), |
| 444 | VMSTATE_INT32(env.CP0_Status, MIPSCPU), |
| 445 | VMSTATE_INT32(env.CP0_IntCtl, MIPSCPU), |
| 446 | VMSTATE_INT32(env.CP0_SRSCtl, MIPSCPU), |
| 447 | VMSTATE_INT32(env.CP0_SRSMap, MIPSCPU), |
| 448 | VMSTATE_INT32(env.CP0_Cause, MIPSCPU), |
| 449 | VMSTATE_UINTTL(env.CP0_EPC, MIPSCPU), |
| 450 | VMSTATE_INT32(env.CP0_PRid, MIPSCPU), |
| 451 | VMSTATE_UINTTL(env.CP0_EBase, MIPSCPU), |
| 452 | VMSTATE_UINTTL(env.CP0_CMGCRBase, MIPSCPU), |
| 453 | VMSTATE_INT32(env.CP0_Config0, MIPSCPU), |
| 454 | VMSTATE_INT32(env.CP0_Config1, MIPSCPU), |
| 455 | VMSTATE_INT32(env.CP0_Config2, MIPSCPU), |
| 456 | VMSTATE_INT32(env.CP0_Config3, MIPSCPU), |
| 457 | VMSTATE_INT32(env.CP0_Config4, MIPSCPU), |
| 458 | VMSTATE_INT32(env.CP0_Config5, MIPSCPU), |
| 459 | VMSTATE_INT32(env.CP0_Config6, MIPSCPU), |
| 460 | VMSTATE_INT32(env.CP0_Config7, MIPSCPU), |
| 461 | VMSTATE_UINT64(env.CP0_LLAddr, MIPSCPU), |
| 462 | VMSTATE_UINT64_ARRAY(env.CP0_MAAR, MIPSCPU, MIPS_MAAR_MAX), |
| 463 | VMSTATE_INT32(env.CP0_MAARI, MIPSCPU), |
| 464 | VMSTATE_UINTTL(env.lladdr, MIPSCPU), |
| 465 | VMSTATE_UINTTL_ARRAY(env.CP0_WatchLo, MIPSCPU, 8), |
| 466 | VMSTATE_UINT64_ARRAY(env.CP0_WatchHi, MIPSCPU, 8), |
| 467 | VMSTATE_UINTTL(env.CP0_XContext, MIPSCPU), |
| 468 | VMSTATE_INT32(env.CP0_Framemask, MIPSCPU), |
| 469 | VMSTATE_INT32(env.CP0_Debug, MIPSCPU), |
| 470 | VMSTATE_UINTTL(env.CP0_DEPC, MIPSCPU), |
| 471 | VMSTATE_INT32(env.CP0_Performance0, MIPSCPU), |
| 472 | VMSTATE_INT32(env.CP0_ErrCtl, MIPSCPU), |
| 473 | VMSTATE_UINT64(env.CP0_TagLo, MIPSCPU), |
| 474 | VMSTATE_INT32(env.CP0_DataLo, MIPSCPU), |
| 475 | VMSTATE_INT32(env.CP0_TagHi, MIPSCPU), |
| 476 | VMSTATE_INT32(env.CP0_DataHi, MIPSCPU), |
| 477 | VMSTATE_UINTTL(env.CP0_ErrorEPC, MIPSCPU), |
| 478 | VMSTATE_INT32(env.CP0_DESAVE, MIPSCPU), |
| 479 | VMSTATE_UINTTL_ARRAY(env.CP0_KScratch, MIPSCPU, MIPS_KSCRATCH_NUM), |
| 480 | |
| 481 | /* Inactive TC */ |
| 482 | VMSTATE_STRUCT_ARRAY(env.tcs, MIPSCPU, MIPS_SHADOW_SET_MAX, 1, |
| 483 | vmstate_inactive_tc, TCState), |
| 484 | VMSTATE_STRUCT_ARRAY(env.fpus, MIPSCPU, MIPS_FPU_MAX, 1, |
| 485 | vmstate_inactive_fpu, CPUMIPSFPUContext), |
| 486 | |
| 487 | VMSTATE_END_OF_LIST() |
| 488 | }, |
| 489 | .subsections = (const VMStateDescription * const []) { |
| 490 | &mips_vmstate_timer, |
| 491 | &mips_vmstate_octeon_multiplier, |
| 492 | &mips_vmstate_octeon_crypto, |
| 493 | NULL |
| 494 | } |
| 495 | }; |