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1 /*
2 * Helpers for emulation of CP0-related MIPS instructions.
3 *
4 * Copyright (C) 2004-2005 Jocelyn Mayer
5 * Copyright (C) 2020 Wave Computing, Inc.
6 * Copyright (C) 2020 Aleksandar Markovic <amarkovic@wavecomp.com>
7 *
8 * This library is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2.1 of the License, or (at your option) any later version.
12 *
13 * This library is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
17 *
18 * You should have received a copy of the GNU Lesser General Public
19 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 *
21 */
22
23 #include "qemu/osdep.h"
24 #include "qemu/log.h"
25 #include "qemu/main-loop.h"
26 #include "cpu.h"
27 #include "internal.h"
28 #include "qemu/host-utils.h"
29 #include "exec/helper-proto.h"
30 #include "exec/cputlb.h"
31 #include "exec/target_page.h"
32
33
34 /* SMP helpers. */
35 static bool mips_vpe_is_wfi(MIPSCPU *c)
36 {
37 CPUState *cpu = CPU(c);
38 CPUMIPSState *env = &c->env;
39
40 /*
41 * If the VPE is halted but otherwise active, it means it's waiting for
42 * an interrupt.\
43 */
44 return cpu->halted && mips_vpe_active(env);
45 }
46
47 static bool mips_vp_is_wfi(MIPSCPU *c)
48 {
49 CPUState *cpu = CPU(c);
50 CPUMIPSState *env = &c->env;
51
52 return cpu->halted && mips_vp_active(env);
53 }
54
55 static inline void mips_vpe_wake(MIPSCPU *c)
56 {
57 /*
58 * Don't set ->halted = 0 directly, let it be done via cpu_has_work
59 * because there might be other conditions that state that c should
60 * be sleeping.
61 */
62 bql_lock();
63 cpu_interrupt(CPU(c), CPU_INTERRUPT_WAKE);
64 bql_unlock();
65 }
66
67 static inline void mips_vpe_sleep(MIPSCPU *cpu)
68 {
69 CPUState *cs = CPU(cpu);
70
71 /*
72 * The VPE was shut off, really go to bed.
73 * Reset any old _WAKE requests.
74 */
75 cs->halted = 1;
76 cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE);
77 }
78
79 static inline void mips_tc_wake(MIPSCPU *cpu, int tc)
80 {
81 CPUMIPSState *c = &cpu->env;
82
83 /* FIXME: TC reschedule. */
84 if (mips_vpe_active(c) && !mips_vpe_is_wfi(cpu)) {
85 mips_vpe_wake(cpu);
86 }
87 }
88
89 static inline void mips_tc_sleep(MIPSCPU *cpu, int tc)
90 {
91 CPUMIPSState *c = &cpu->env;
92
93 /* FIXME: TC reschedule. */
94 if (!mips_vpe_active(c)) {
95 mips_vpe_sleep(cpu);
96 }
97 }
98
99 /**
100 * mips_cpu_map_tc:
101 * @env: CPU from which mapping is performed.
102 * @tc: Should point to an int with the value of the global TC index.
103 *
104 * This function will transform @tc into a local index within the
105 * returned #CPUMIPSState.
106 */
107
108 /*
109 * FIXME: This code assumes that all VPEs have the same number of TCs,
110 * which depends on runtime setup. Can probably be fixed by
111 * walking the list of CPUMIPSStates.
112 */
113 static CPUMIPSState *mips_cpu_map_tc(CPUMIPSState *env, int *tc)
114 {
115 MIPSCPU *cpu;
116 CPUState *cs;
117 CPUState *other_cs;
118 int vpe_idx;
119 int tc_idx = *tc;
120
121 if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))) {
122 /* Not allowed to address other CPUs. */
123 *tc = env->current_tc;
124 return env;
125 }
126
127 cs = env_cpu(env);
128 vpe_idx = tc_idx / cs->nr_threads;
129 *tc = tc_idx % cs->nr_threads;
130 other_cs = qemu_get_cpu(vpe_idx);
131 if (other_cs == NULL) {
132 return env;
133 }
134 cpu = MIPS_CPU(other_cs);
135 return &cpu->env;
136 }
137
138 /*
139 * The per VPE CP0_Status register shares some fields with the per TC
140 * CP0_TCStatus registers. These fields are wired to the same registers,
141 * so changes to either of them should be reflected on both registers.
142 *
143 * Also, EntryHi shares the bottom 8 bit ASID with TCStauts.
144 *
145 * These helper call synchronizes the regs for a given cpu.
146 */
147
148 /*
149 * Called for updates to CP0_Status. Defined in "cpu.h" for gdbstub.c.
150 * static inline void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu,
151 * int tc);
152 */
153
154 /* Called for updates to CP0_TCStatus. */
155 static void sync_c0_tcstatus(CPUMIPSState *cpu, int tc,
156 target_ulong v)
157 {
158 uint32_t status;
159 uint32_t tcu, tmx, tasid, tksu;
160 uint32_t mask = ((1U << CP0St_CU3)
161 | (1 << CP0St_CU2)
162 | (1 << CP0St_CU1)
163 | (1 << CP0St_CU0)
164 | (1 << CP0St_MX)
165 | (3 << CP0St_KSU));
166
167 tcu = (v >> CP0TCSt_TCU0) & 0xf;
168 tmx = (v >> CP0TCSt_TMX) & 0x1;
169 tasid = v & cpu->CP0_EntryHi_ASID_mask;
170 tksu = (v >> CP0TCSt_TKSU) & 0x3;
171
172 status = tcu << CP0St_CU0;
173 status |= tmx << CP0St_MX;
174 status |= tksu << CP0St_KSU;
175
176 cpu->CP0_Status &= ~mask;
177 cpu->CP0_Status |= status;
178
179 /* Sync the TASID with EntryHi. */
180 cpu->CP0_EntryHi &= ~cpu->CP0_EntryHi_ASID_mask;
181 cpu->CP0_EntryHi |= tasid;
182
183 compute_hflags(cpu);
184 }
185
186 /* Called for updates to CP0_EntryHi. */
187 static void sync_c0_entryhi(CPUMIPSState *cpu, int tc)
188 {
189 int32_t *tcst;
190 uint32_t asid, v = cpu->CP0_EntryHi;
191
192 asid = v & cpu->CP0_EntryHi_ASID_mask;
193
194 if (tc == cpu->current_tc) {
195 tcst = &cpu->active_tc.CP0_TCStatus;
196 } else {
197 tcst = &cpu->tcs[tc].CP0_TCStatus;
198 }
199
200 *tcst &= ~cpu->CP0_EntryHi_ASID_mask;
201 *tcst |= asid;
202 }
203
204 /* XXX: do not use a global */
205 uint32_t cpu_mips_get_random(CPUMIPSState *env)
206 {
207 static uint32_t seed = 1;
208 static uint32_t prev_idx;
209 uint32_t idx;
210 uint32_t nb_rand_tlb = env->tlb->nb_tlb - env->CP0_Wired;
211
212 if (nb_rand_tlb == 1) {
213 return env->tlb->nb_tlb - 1;
214 }
215
216 /* Don't return same value twice, so get another value */
217 do {
218 /*
219 * Use a simple algorithm of Linear Congruential Generator
220 * from ISO/IEC 9899 standard.
221 */
222 seed = 1103515245 * seed + 12345;
223 idx = (seed >> 16) % nb_rand_tlb + env->CP0_Wired;
224 } while (idx == prev_idx);
225 prev_idx = idx;
226 return idx;
227 }
228
229 /* CP0 helpers */
230 target_ulong helper_mfc0_mvpcontrol(CPUMIPSState *env)
231 {
232 MIPSCPU *cpu = env_archcpu(env);
233 return cpu->mvp->CP0_MVPControl;
234 }
235
236 target_ulong helper_mfc0_mvpconf0(CPUMIPSState *env)
237 {
238 MIPSCPU *cpu = env_archcpu(env);
239 return cpu->mvp->CP0_MVPConf0;
240 }
241
242 target_ulong helper_mfc0_mvpconf1(CPUMIPSState *env)
243 {
244 MIPSCPU *cpu = env_archcpu(env);
245 return cpu->mvp->CP0_MVPConf1;
246 }
247
248 target_ulong helper_mfc0_random(CPUMIPSState *env)
249 {
250 return (int32_t)cpu_mips_get_random(env);
251 }
252
253 target_ulong helper_mfc0_tcstatus(CPUMIPSState *env)
254 {
255 return env->active_tc.CP0_TCStatus;
256 }
257
258 target_ulong helper_mftc0_tcstatus(CPUMIPSState *env)
259 {
260 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
261 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
262
263 if (other_tc == other->current_tc) {
264 return other->active_tc.CP0_TCStatus;
265 } else {
266 return other->tcs[other_tc].CP0_TCStatus;
267 }
268 }
269
270 target_ulong helper_mfc0_tcbind(CPUMIPSState *env)
271 {
272 return env->active_tc.CP0_TCBind;
273 }
274
275 target_ulong helper_mftc0_tcbind(CPUMIPSState *env)
276 {
277 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
278 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
279
280 if (other_tc == other->current_tc) {
281 return other->active_tc.CP0_TCBind;
282 } else {
283 return other->tcs[other_tc].CP0_TCBind;
284 }
285 }
286
287 target_ulong helper_mfc0_tcrestart(CPUMIPSState *env)
288 {
289 return env->active_tc.PC;
290 }
291
292 target_ulong helper_mftc0_tcrestart(CPUMIPSState *env)
293 {
294 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
295 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
296
297 if (other_tc == other->current_tc) {
298 return other->active_tc.PC;
299 } else {
300 return other->tcs[other_tc].PC;
301 }
302 }
303
304 target_ulong helper_mfc0_tchalt(CPUMIPSState *env)
305 {
306 return env->active_tc.CP0_TCHalt;
307 }
308
309 target_ulong helper_mftc0_tchalt(CPUMIPSState *env)
310 {
311 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
312 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
313
314 if (other_tc == other->current_tc) {
315 return other->active_tc.CP0_TCHalt;
316 } else {
317 return other->tcs[other_tc].CP0_TCHalt;
318 }
319 }
320
321 target_ulong helper_mfc0_tccontext(CPUMIPSState *env)
322 {
323 return env->active_tc.CP0_TCContext;
324 }
325
326 target_ulong helper_mftc0_tccontext(CPUMIPSState *env)
327 {
328 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
329 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
330
331 if (other_tc == other->current_tc) {
332 return other->active_tc.CP0_TCContext;
333 } else {
334 return other->tcs[other_tc].CP0_TCContext;
335 }
336 }
337
338 target_ulong helper_mfc0_tcschedule(CPUMIPSState *env)
339 {
340 return env->active_tc.CP0_TCSchedule;
341 }
342
343 target_ulong helper_mftc0_tcschedule(CPUMIPSState *env)
344 {
345 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
346 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
347
348 if (other_tc == other->current_tc) {
349 return other->active_tc.CP0_TCSchedule;
350 } else {
351 return other->tcs[other_tc].CP0_TCSchedule;
352 }
353 }
354
355 target_ulong helper_mfc0_tcschefback(CPUMIPSState *env)
356 {
357 return env->active_tc.CP0_TCScheFBack;
358 }
359
360 target_ulong helper_mftc0_tcschefback(CPUMIPSState *env)
361 {
362 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
363 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
364
365 if (other_tc == other->current_tc) {
366 return other->active_tc.CP0_TCScheFBack;
367 } else {
368 return other->tcs[other_tc].CP0_TCScheFBack;
369 }
370 }
371
372 target_ulong helper_mfc0_count(CPUMIPSState *env)
373 {
374 return (int32_t)cpu_mips_get_count(env);
375 }
376
377 target_ulong helper_mftc0_entryhi(CPUMIPSState *env)
378 {
379 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
380 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
381
382 return other->CP0_EntryHi;
383 }
384
385 target_ulong helper_mftc0_cause(CPUMIPSState *env)
386 {
387 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
388 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
389
390 return other->CP0_Cause;
391 }
392
393 target_ulong helper_mftc0_status(CPUMIPSState *env)
394 {
395 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
396 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
397
398 return other->CP0_Status;
399 }
400
401 target_ulong helper_mfc0_lladdr(CPUMIPSState *env)
402 {
403 return (int32_t)(env->CP0_LLAddr >> env->CP0_LLAddr_shift);
404 }
405
406 target_ulong helper_mfc0_maar(CPUMIPSState *env)
407 {
408 return (int32_t) env->CP0_MAAR[env->CP0_MAARI];
409 }
410
411 target_ulong helper_mfhc0_maar(CPUMIPSState *env)
412 {
413 return env->CP0_MAAR[env->CP0_MAARI] >> 32;
414 }
415
416 target_ulong helper_mfc0_watchlo(CPUMIPSState *env, uint32_t sel)
417 {
418 return (int32_t)env->CP0_WatchLo[sel];
419 }
420
421 target_ulong helper_mfc0_watchhi(CPUMIPSState *env, uint32_t sel)
422 {
423 return (int32_t) env->CP0_WatchHi[sel];
424 }
425
426 target_ulong helper_mfhc0_watchhi(CPUMIPSState *env, uint32_t sel)
427 {
428 return env->CP0_WatchHi[sel] >> 32;
429 }
430
431 target_ulong helper_mfc0_debug(CPUMIPSState *env)
432 {
433 target_ulong t0 = env->CP0_Debug;
434 if (env->hflags & MIPS_HFLAG_DM) {
435 t0 |= 1 << CP0DB_DM;
436 }
437
438 return t0;
439 }
440
441 target_ulong helper_mftc0_debug(CPUMIPSState *env)
442 {
443 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
444 int32_t tcstatus;
445 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
446
447 if (other_tc == other->current_tc) {
448 tcstatus = other->active_tc.CP0_Debug_tcstatus;
449 } else {
450 tcstatus = other->tcs[other_tc].CP0_Debug_tcstatus;
451 }
452
453 /* XXX: Might be wrong, check with EJTAG spec. */
454 return (other->CP0_Debug & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
455 (tcstatus & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
456 }
457
458 #if defined(TARGET_MIPS64)
459 target_ulong helper_dmfc0_tcrestart(CPUMIPSState *env)
460 {
461 return env->active_tc.PC;
462 }
463
464 target_ulong helper_dmfc0_tchalt(CPUMIPSState *env)
465 {
466 return env->active_tc.CP0_TCHalt;
467 }
468
469 target_ulong helper_dmfc0_tccontext(CPUMIPSState *env)
470 {
471 return env->active_tc.CP0_TCContext;
472 }
473
474 target_ulong helper_dmfc0_tcschedule(CPUMIPSState *env)
475 {
476 return env->active_tc.CP0_TCSchedule;
477 }
478
479 target_ulong helper_dmfc0_tcschefback(CPUMIPSState *env)
480 {
481 return env->active_tc.CP0_TCScheFBack;
482 }
483
484 target_ulong helper_dmfc0_lladdr(CPUMIPSState *env)
485 {
486 return env->CP0_LLAddr >> env->CP0_LLAddr_shift;
487 }
488
489 target_ulong helper_dmfc0_maar(CPUMIPSState *env)
490 {
491 return env->CP0_MAAR[env->CP0_MAARI];
492 }
493
494 target_ulong helper_dmfc0_watchlo(CPUMIPSState *env, uint32_t sel)
495 {
496 return env->CP0_WatchLo[sel];
497 }
498
499 target_ulong helper_dmfc0_watchhi(CPUMIPSState *env, uint32_t sel)
500 {
501 return env->CP0_WatchHi[sel];
502 }
503
504 #endif /* TARGET_MIPS64 */
505
506 void helper_mtc0_index(CPUMIPSState *env, target_ulong arg1)
507 {
508 uint32_t index_p = env->CP0_Index & 0x80000000;
509 uint32_t tlb_index = arg1 & 0x7fffffff;
510 if (tlb_index < env->tlb->nb_tlb) {
511 if (env->insn_flags & ISA_MIPS_R6) {
512 index_p |= arg1 & 0x80000000;
513 }
514 env->CP0_Index = index_p | tlb_index;
515 }
516 }
517
518 void helper_mtc0_mvpcontrol(CPUMIPSState *env, target_ulong arg1)
519 {
520 MIPSCPU *cpu = env_archcpu(env);
521 uint32_t mask = 0;
522 uint32_t newval;
523
524 if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) {
525 mask |= (1 << CP0MVPCo_CPA) | (1 << CP0MVPCo_VPC) |
526 (1 << CP0MVPCo_EVP);
527 }
528 if (cpu->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) {
529 mask |= (1 << CP0MVPCo_STLB);
530 }
531 newval = (cpu->mvp->CP0_MVPControl & ~mask) | (arg1 & mask);
532
533 /* TODO: Enable/disable shared TLB, enable/disable VPEs. */
534
535 cpu->mvp->CP0_MVPControl = newval;
536 }
537
538 void helper_mtc0_vpecontrol(CPUMIPSState *env, target_ulong arg1)
539 {
540 uint32_t mask;
541 uint32_t newval;
542
543 mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) |
544 (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);
545 newval = (env->CP0_VPEControl & ~mask) | (arg1 & mask);
546
547 /*
548 * Yield scheduler intercept not implemented.
549 * Gating storage scheduler intercept not implemented.
550 */
551
552 /* TODO: Enable/disable TCs. */
553
554 env->CP0_VPEControl = newval;
555 }
556
557 void helper_mttc0_vpecontrol(CPUMIPSState *env, target_ulong arg1)
558 {
559 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
560 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
561 uint32_t mask;
562 uint32_t newval;
563
564 mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) |
565 (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);
566 newval = (other->CP0_VPEControl & ~mask) | (arg1 & mask);
567
568 /* TODO: Enable/disable TCs. */
569
570 other->CP0_VPEControl = newval;
571 }
572
573 target_ulong helper_mftc0_vpecontrol(CPUMIPSState *env)
574 {
575 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
576 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
577 /* FIXME: Mask away return zero on read bits. */
578 return other->CP0_VPEControl;
579 }
580
581 target_ulong helper_mftc0_vpeconf0(CPUMIPSState *env)
582 {
583 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
584 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
585
586 return other->CP0_VPEConf0;
587 }
588
589 void helper_mtc0_vpeconf0(CPUMIPSState *env, target_ulong arg1)
590 {
591 uint32_t mask = 0;
592 uint32_t newval;
593
594 if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) {
595 if (env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA)) {
596 mask |= (0xff << CP0VPEC0_XTC);
597 }
598 mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
599 }
600 newval = (env->CP0_VPEConf0 & ~mask) | (arg1 & mask);
601
602 /* TODO: TC exclusive handling due to ERL/EXL. */
603
604 env->CP0_VPEConf0 = newval;
605 }
606
607 void helper_mttc0_vpeconf0(CPUMIPSState *env, target_ulong arg1)
608 {
609 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
610 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
611 uint32_t mask = 0;
612 uint32_t newval;
613
614 mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
615 newval = (other->CP0_VPEConf0 & ~mask) | (arg1 & mask);
616
617 /* TODO: TC exclusive handling due to ERL/EXL. */
618 other->CP0_VPEConf0 = newval;
619 }
620
621 void helper_mtc0_vpeconf1(CPUMIPSState *env, target_ulong arg1)
622 {
623 MIPSCPU *cpu = env_archcpu(env);
624 uint32_t mask = 0;
625 uint32_t newval;
626
627 if (cpu->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
628 mask |= (0xff << CP0VPEC1_NCX) | (0xff << CP0VPEC1_NCP2) |
629 (0xff << CP0VPEC1_NCP1);
630 newval = (env->CP0_VPEConf1 & ~mask) | (arg1 & mask);
631
632 /* UDI not implemented. */
633 /* CP2 not implemented. */
634
635 /* TODO: Handle FPU (CP1) binding. */
636
637 env->CP0_VPEConf1 = newval;
638 }
639
640 void helper_mtc0_yqmask(CPUMIPSState *env, target_ulong arg1)
641 {
642 /* Yield qualifier inputs not implemented. */
643 env->CP0_YQMask = 0x00000000;
644 }
645
646 void helper_mtc0_vpeopt(CPUMIPSState *env, target_ulong arg1)
647 {
648 env->CP0_VPEOpt = arg1 & 0x0000ffff;
649 }
650
651 #define MTC0_ENTRYLO_MASK(env) ((env->PAMask >> 6) & 0x3FFFFFFF)
652
653 void helper_mtc0_entrylo0(CPUMIPSState *env, target_ulong arg1)
654 {
655 /* 1k pages not implemented */
656 target_ulong rxi = arg1 & (env->CP0_PageGrain & (3u << CP0PG_XIE));
657 env->CP0_EntryLo0 = (arg1 & MTC0_ENTRYLO_MASK(env))
658 | (rxi << (CP0EnLo_XI - 30));
659 }
660
661 #if defined(TARGET_MIPS64)
662 #define DMTC0_ENTRYLO_MASK(env) (env->PAMask >> 6)
663
664 void helper_dmtc0_entrylo0(CPUMIPSState *env, uint64_t arg1)
665 {
666 uint64_t rxi = arg1 & ((env->CP0_PageGrain & (3ull << CP0PG_XIE)) << 32);
667 env->CP0_EntryLo0 = (arg1 & DMTC0_ENTRYLO_MASK(env)) | rxi;
668 }
669 #endif
670
671 void helper_mtc0_tcstatus(CPUMIPSState *env, target_ulong arg1)
672 {
673 uint32_t mask = env->CP0_TCStatus_rw_bitmask;
674 uint32_t newval;
675
676 newval = (env->active_tc.CP0_TCStatus & ~mask) | (arg1 & mask);
677
678 env->active_tc.CP0_TCStatus = newval;
679 sync_c0_tcstatus(env, env->current_tc, newval);
680 }
681
682 void helper_mttc0_tcstatus(CPUMIPSState *env, target_ulong arg1)
683 {
684 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
685 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
686
687 if (other_tc == other->current_tc) {
688 other->active_tc.CP0_TCStatus = arg1;
689 } else {
690 other->tcs[other_tc].CP0_TCStatus = arg1;
691 }
692 sync_c0_tcstatus(other, other_tc, arg1);
693 }
694
695 void helper_mtc0_tcbind(CPUMIPSState *env, target_ulong arg1)
696 {
697 MIPSCPU *cpu = env_archcpu(env);
698 uint32_t mask = (1 << CP0TCBd_TBE);
699 uint32_t newval;
700
701 if (cpu->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) {
702 mask |= (1 << CP0TCBd_CurVPE);
703 }
704 newval = (env->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
705 env->active_tc.CP0_TCBind = newval;
706 }
707
708 void helper_mttc0_tcbind(CPUMIPSState *env, target_ulong arg1)
709 {
710 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
711 uint32_t mask = (1 << CP0TCBd_TBE);
712 uint32_t newval;
713 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
714 MIPSCPU *other_cpu = env_archcpu(other);
715
716 if (other_cpu->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) {
717 mask |= (1 << CP0TCBd_CurVPE);
718 }
719 if (other_tc == other->current_tc) {
720 newval = (other->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
721 other->active_tc.CP0_TCBind = newval;
722 } else {
723 newval = (other->tcs[other_tc].CP0_TCBind & ~mask) | (arg1 & mask);
724 other->tcs[other_tc].CP0_TCBind = newval;
725 }
726 }
727
728 void helper_mtc0_tcrestart(CPUMIPSState *env, target_ulong arg1)
729 {
730 env->active_tc.PC = arg1;
731 env->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
732 env->CP0_LLAddr = 0;
733 env->lladdr = 0;
734 /* MIPS16 not implemented. */
735 }
736
737 void helper_mttc0_tcrestart(CPUMIPSState *env, target_ulong arg1)
738 {
739 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
740 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
741
742 if (other_tc == other->current_tc) {
743 other->active_tc.PC = arg1;
744 other->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
745 other->CP0_LLAddr = 0;
746 other->lladdr = 0;
747 /* MIPS16 not implemented. */
748 } else {
749 other->tcs[other_tc].PC = arg1;
750 other->tcs[other_tc].CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
751 other->CP0_LLAddr = 0;
752 other->lladdr = 0;
753 /* MIPS16 not implemented. */
754 }
755 }
756
757 void helper_mtc0_tchalt(CPUMIPSState *env, target_ulong arg1)
758 {
759 MIPSCPU *cpu = env_archcpu(env);
760
761 env->active_tc.CP0_TCHalt = arg1 & 0x1;
762
763 /* TODO: Halt TC / Restart (if allocated+active) TC. */
764 if (env->active_tc.CP0_TCHalt & 1) {
765 mips_tc_sleep(cpu, env->current_tc);
766 } else {
767 mips_tc_wake(cpu, env->current_tc);
768 }
769 }
770
771 void helper_mttc0_tchalt(CPUMIPSState *env, target_ulong arg1)
772 {
773 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
774 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
775 MIPSCPU *other_cpu = env_archcpu(other);
776
777 /* TODO: Halt TC / Restart (if allocated+active) TC. */
778
779 if (other_tc == other->current_tc) {
780 other->active_tc.CP0_TCHalt = arg1;
781 } else {
782 other->tcs[other_tc].CP0_TCHalt = arg1;
783 }
784
785 if (arg1 & 1) {
786 mips_tc_sleep(other_cpu, other_tc);
787 } else {
788 mips_tc_wake(other_cpu, other_tc);
789 }
790 }
791
792 void helper_mtc0_tccontext(CPUMIPSState *env, target_ulong arg1)
793 {
794 env->active_tc.CP0_TCContext = arg1;
795 }
796
797 void helper_mttc0_tccontext(CPUMIPSState *env, target_ulong arg1)
798 {
799 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
800 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
801
802 if (other_tc == other->current_tc) {
803 other->active_tc.CP0_TCContext = arg1;
804 } else {
805 other->tcs[other_tc].CP0_TCContext = arg1;
806 }
807 }
808
809 void helper_mtc0_tcschedule(CPUMIPSState *env, target_ulong arg1)
810 {
811 env->active_tc.CP0_TCSchedule = arg1;
812 }
813
814 void helper_mttc0_tcschedule(CPUMIPSState *env, target_ulong arg1)
815 {
816 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
817 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
818
819 if (other_tc == other->current_tc) {
820 other->active_tc.CP0_TCSchedule = arg1;
821 } else {
822 other->tcs[other_tc].CP0_TCSchedule = arg1;
823 }
824 }
825
826 void helper_mtc0_tcschefback(CPUMIPSState *env, target_ulong arg1)
827 {
828 env->active_tc.CP0_TCScheFBack = arg1;
829 }
830
831 void helper_mttc0_tcschefback(CPUMIPSState *env, target_ulong arg1)
832 {
833 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
834 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
835
836 if (other_tc == other->current_tc) {
837 other->active_tc.CP0_TCScheFBack = arg1;
838 } else {
839 other->tcs[other_tc].CP0_TCScheFBack = arg1;
840 }
841 }
842
843 void helper_mtc0_entrylo1(CPUMIPSState *env, target_ulong arg1)
844 {
845 /* 1k pages not implemented */
846 target_ulong rxi = arg1 & (env->CP0_PageGrain & (3u << CP0PG_XIE));
847 env->CP0_EntryLo1 = (arg1 & MTC0_ENTRYLO_MASK(env))
848 | (rxi << (CP0EnLo_XI - 30));
849 }
850
851 #if defined(TARGET_MIPS64)
852 void helper_dmtc0_entrylo1(CPUMIPSState *env, uint64_t arg1)
853 {
854 uint64_t rxi = arg1 & ((env->CP0_PageGrain & (3ull << CP0PG_XIE)) << 32);
855 env->CP0_EntryLo1 = (arg1 & DMTC0_ENTRYLO_MASK(env)) | rxi;
856 }
857 #endif
858
859 void helper_mtc0_context(CPUMIPSState *env, target_ulong arg1)
860 {
861 env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (arg1 & ~0x007FFFFF);
862 }
863
864 void helper_mtc0_memorymapid(CPUMIPSState *env, target_ulong arg1)
865 {
866 int32_t old;
867 old = env->CP0_MemoryMapID;
868 env->CP0_MemoryMapID = (int32_t) arg1;
869 /* If the MemoryMapID changes, flush qemu's TLB. */
870 if (old != env->CP0_MemoryMapID) {
871 cpu_mips_tlb_flush(env);
872 }
873 }
874
875 uint32_t compute_pagemask(uint32_t val)
876 {
877 /* Don't care MASKX as we don't support 1KB page */
878 uint32_t mask = extract32(val, CP0PM_MASK, 16);
879 int maskbits = cto32(mask);
880
881 /* Ensure no more set bit after first zero, and maskbits even. */
882 if ((mask >> maskbits) == 0 && maskbits % 2 == 0) {
883 return mask << CP0PM_MASK;
884 } else {
885 /* When invalid, set to default target page size. */
886 return 0;
887 }
888 }
889
890 void helper_mtc0_pagemask(CPUMIPSState *env, target_ulong arg1)
891 {
892 env->CP0_PageMask = compute_pagemask(arg1);
893 }
894
895 void helper_mtc0_pagegrain(CPUMIPSState *env, target_ulong arg1)
896 {
897 /* SmartMIPS not implemented */
898 /* 1k pages not implemented */
899 env->CP0_PageGrain = (arg1 & env->CP0_PageGrain_rw_bitmask) |
900 (env->CP0_PageGrain & ~env->CP0_PageGrain_rw_bitmask);
901 compute_hflags(env);
902 restore_pamask(env);
903 }
904
905 void helper_mtc0_segctl0(CPUMIPSState *env, target_ulong arg1)
906 {
907 CPUState *cs = env_cpu(env);
908
909 env->CP0_SegCtl0 = arg1 & CP0SC0_MASK;
910 tlb_flush(cs);
911 }
912
913 void helper_mtc0_segctl1(CPUMIPSState *env, target_ulong arg1)
914 {
915 CPUState *cs = env_cpu(env);
916
917 env->CP0_SegCtl1 = arg1 & CP0SC1_MASK;
918 tlb_flush(cs);
919 }
920
921 void helper_mtc0_segctl2(CPUMIPSState *env, target_ulong arg1)
922 {
923 CPUState *cs = env_cpu(env);
924
925 env->CP0_SegCtl2 = arg1 & CP0SC2_MASK;
926 tlb_flush(cs);
927 }
928
929 void helper_mtc0_pwfield(CPUMIPSState *env, target_ulong arg1)
930 {
931 #if defined(TARGET_MIPS64)
932 uint64_t mask = 0x3F3FFFFFFFULL;
933 uint32_t old_ptei = (env->CP0_PWField >> CP0PF_PTEI) & 0x3FULL;
934 uint32_t new_ptei = (arg1 >> CP0PF_PTEI) & 0x3FULL;
935
936 if ((env->insn_flags & ISA_MIPS_R6)) {
937 if (((arg1 >> CP0PF_BDI) & 0x3FULL) < 12) {
938 mask &= ~(0x3FULL << CP0PF_BDI);
939 }
940 if (((arg1 >> CP0PF_GDI) & 0x3FULL) < 12) {
941 mask &= ~(0x3FULL << CP0PF_GDI);
942 }
943 if (((arg1 >> CP0PF_UDI) & 0x3FULL) < 12) {
944 mask &= ~(0x3FULL << CP0PF_UDI);
945 }
946 if (((arg1 >> CP0PF_MDI) & 0x3FULL) < 12) {
947 mask &= ~(0x3FULL << CP0PF_MDI);
948 }
949 if (((arg1 >> CP0PF_PTI) & 0x3FULL) < 12) {
950 mask &= ~(0x3FULL << CP0PF_PTI);
951 }
952 }
953 env->CP0_PWField = arg1 & mask;
954
955 if ((new_ptei >= 32) ||
956 ((env->insn_flags & ISA_MIPS_R6) &&
957 (new_ptei == 0 || new_ptei == 1))) {
958 env->CP0_PWField = (env->CP0_PWField & ~0x3FULL) |
959 (old_ptei << CP0PF_PTEI);
960 }
961 #else
962 uint32_t mask = 0x3FFFFFFF;
963 uint32_t old_ptew = (env->CP0_PWField >> CP0PF_PTEW) & 0x3F;
964 uint32_t new_ptew = (arg1 >> CP0PF_PTEW) & 0x3F;
965
966 if ((env->insn_flags & ISA_MIPS_R6)) {
967 if (((arg1 >> CP0PF_GDW) & 0x3F) < 12) {
968 mask &= ~(0x3F << CP0PF_GDW);
969 }
970 if (((arg1 >> CP0PF_UDW) & 0x3F) < 12) {
971 mask &= ~(0x3F << CP0PF_UDW);
972 }
973 if (((arg1 >> CP0PF_MDW) & 0x3F) < 12) {
974 mask &= ~(0x3F << CP0PF_MDW);
975 }
976 if (((arg1 >> CP0PF_PTW) & 0x3F) < 12) {
977 mask &= ~(0x3F << CP0PF_PTW);
978 }
979 }
980 env->CP0_PWField = arg1 & mask;
981
982 if ((new_ptew >= 32) ||
983 ((env->insn_flags & ISA_MIPS_R6) &&
984 (new_ptew == 0 || new_ptew == 1))) {
985 env->CP0_PWField = (env->CP0_PWField & ~0x3F) |
986 (old_ptew << CP0PF_PTEW);
987 }
988 #endif
989 }
990
991 void helper_mtc0_pwsize(CPUMIPSState *env, target_ulong arg1)
992 {
993 #if defined(TARGET_MIPS64)
994 env->CP0_PWSize = arg1 & 0x3F7FFFFFFFULL;
995 #else
996 env->CP0_PWSize = arg1 & 0x3FFFFFFF;
997 #endif
998 }
999
1000 void helper_mtc0_wired(CPUMIPSState *env, target_ulong arg1)
1001 {
1002 if (env->insn_flags & ISA_MIPS_R6) {
1003 if (arg1 < env->tlb->nb_tlb) {
1004 env->CP0_Wired = arg1;
1005 }
1006 } else {
1007 env->CP0_Wired = arg1 % env->tlb->nb_tlb;
1008 }
1009 }
1010
1011 void helper_mtc0_pwctl(CPUMIPSState *env, target_ulong arg1)
1012 {
1013 #if defined(TARGET_MIPS64)
1014 /* PWEn = 0. Hardware page table walking is not implemented. */
1015 env->CP0_PWCtl = (env->CP0_PWCtl & 0x000000C0) | (arg1 & 0x5C00003F);
1016 #else
1017 env->CP0_PWCtl = (arg1 & 0x800000FF);
1018 #endif
1019 }
1020
1021 void helper_mtc0_srsconf0(CPUMIPSState *env, target_ulong arg1)
1022 {
1023 env->CP0_SRSConf0 |= arg1 & env->CP0_SRSConf0_rw_bitmask;
1024 }
1025
1026 void helper_mtc0_srsconf1(CPUMIPSState *env, target_ulong arg1)
1027 {
1028 env->CP0_SRSConf1 |= arg1 & env->CP0_SRSConf1_rw_bitmask;
1029 }
1030
1031 void helper_mtc0_srsconf2(CPUMIPSState *env, target_ulong arg1)
1032 {
1033 env->CP0_SRSConf2 |= arg1 & env->CP0_SRSConf2_rw_bitmask;
1034 }
1035
1036 void helper_mtc0_srsconf3(CPUMIPSState *env, target_ulong arg1)
1037 {
1038 env->CP0_SRSConf3 |= arg1 & env->CP0_SRSConf3_rw_bitmask;
1039 }
1040
1041 void helper_mtc0_srsconf4(CPUMIPSState *env, target_ulong arg1)
1042 {
1043 env->CP0_SRSConf4 |= arg1 & env->CP0_SRSConf4_rw_bitmask;
1044 }
1045
1046 void helper_mtc0_hwrena(CPUMIPSState *env, target_ulong arg1)
1047 {
1048 uint32_t mask = 0x0000000F;
1049
1050 if ((env->CP0_Config1 & (1 << CP0C1_PC)) &&
1051 (env->insn_flags & ISA_MIPS_R6)) {
1052 mask |= (1 << 4);
1053 }
1054 if (env->insn_flags & ISA_MIPS_R6) {
1055 mask |= (1 << 5);
1056 }
1057 if (env->CP0_Config3 & (1 << CP0C3_ULRI)) {
1058 mask |= (1 << 29);
1059
1060 if (arg1 & (1 << 29)) {
1061 env->hflags |= MIPS_HFLAG_HWRENA_ULR;
1062 } else {
1063 env->hflags &= ~MIPS_HFLAG_HWRENA_ULR;
1064 }
1065 }
1066
1067 env->CP0_HWREna = arg1 & mask;
1068 }
1069
1070 void helper_mtc0_count(CPUMIPSState *env, target_ulong arg1)
1071 {
1072 cpu_mips_store_count(env, arg1);
1073 }
1074
1075 void helper_mtc0_entryhi(CPUMIPSState *env, target_ulong arg1)
1076 {
1077 target_ulong old, val, mask;
1078 mask = (TARGET_PAGE_MASK << 1) | env->CP0_EntryHi_ASID_mask;
1079 if (((env->CP0_Config4 >> CP0C4_IE) & 0x3) >= 2) {
1080 mask |= 1 << CP0EnHi_EHINV;
1081 }
1082
1083 /* 1k pages not implemented */
1084 #if defined(TARGET_MIPS64)
1085 if (env->insn_flags & ISA_MIPS_R6) {
1086 int entryhi_r = extract64(arg1, 62, 2);
1087 int config0_at = extract32(env->CP0_Config0, 13, 2);
1088 bool no_supervisor = (env->CP0_Status_rw_bitmask & 0x8) == 0;
1089 if ((entryhi_r == 2) ||
1090 (entryhi_r == 1 && (no_supervisor || config0_at == 1))) {
1091 /* skip EntryHi.R field if new value is reserved */
1092 mask &= ~(0x3ull << 62);
1093 }
1094 }
1095 mask &= env->SEGMask;
1096 #endif
1097 old = env->CP0_EntryHi;
1098 val = (arg1 & mask) | (old & ~mask);
1099 env->CP0_EntryHi = val;
1100 if (ase_mt_available(env)) {
1101 sync_c0_entryhi(env, env->current_tc);
1102 }
1103 /* If the ASID changes, flush qemu's TLB. */
1104 if ((old & env->CP0_EntryHi_ASID_mask) !=
1105 (val & env->CP0_EntryHi_ASID_mask)) {
1106 tlb_flush(env_cpu(env));
1107 }
1108 }
1109
1110 void helper_mttc0_entryhi(CPUMIPSState *env, target_ulong arg1)
1111 {
1112 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1113 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1114
1115 other->CP0_EntryHi = arg1;
1116 sync_c0_entryhi(other, other_tc);
1117 }
1118
1119 void helper_mtc0_compare(CPUMIPSState *env, target_ulong arg1)
1120 {
1121 cpu_mips_store_compare(env, arg1);
1122 }
1123
1124 void helper_mtc0_status(CPUMIPSState *env, target_ulong arg1)
1125 {
1126 uint32_t val, old;
1127
1128 old = env->CP0_Status;
1129 cpu_mips_store_status(env, arg1);
1130 val = env->CP0_Status;
1131
1132 if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
1133 qemu_log("Status %08x (%08x) => %08x (%08x) Cause %08x",
1134 old, old & env->CP0_Cause & CP0Ca_IP_mask,
1135 val, val & env->CP0_Cause & CP0Ca_IP_mask,
1136 env->CP0_Cause);
1137 switch (mips_env_mmu_index(env)) {
1138 case 3:
1139 qemu_log(", ERL\n");
1140 break;
1141 case MIPS_HFLAG_UM:
1142 qemu_log(", UM\n");
1143 break;
1144 case MIPS_HFLAG_SM:
1145 qemu_log(", SM\n");
1146 break;
1147 case MIPS_HFLAG_KM:
1148 qemu_log("\n");
1149 break;
1150 default:
1151 cpu_abort(env_cpu(env), "Invalid MMU mode!\n");
1152 break;
1153 }
1154 }
1155 }
1156
1157 void helper_mttc0_status(CPUMIPSState *env, target_ulong arg1)
1158 {
1159 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1160 uint32_t mask = env->CP0_Status_rw_bitmask & ~0xf1000018;
1161 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1162
1163 other->CP0_Status = (other->CP0_Status & ~mask) | (arg1 & mask);
1164 sync_c0_status(env, other, other_tc);
1165 }
1166
1167 void helper_mtc0_intctl(CPUMIPSState *env, target_ulong arg1)
1168 {
1169 env->CP0_IntCtl = (env->CP0_IntCtl & ~0x000003e0) | (arg1 & 0x000003e0);
1170 }
1171
1172 void helper_mtc0_srsctl(CPUMIPSState *env, target_ulong arg1)
1173 {
1174 uint32_t mask = (0xf << CP0SRSCtl_ESS) | (0xf << CP0SRSCtl_PSS);
1175 env->CP0_SRSCtl = (env->CP0_SRSCtl & ~mask) | (arg1 & mask);
1176 }
1177
1178 void helper_mtc0_cause(CPUMIPSState *env, target_ulong arg1)
1179 {
1180 cpu_mips_store_cause(env, arg1);
1181 }
1182
1183 void helper_mttc0_cause(CPUMIPSState *env, target_ulong arg1)
1184 {
1185 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1186 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1187
1188 cpu_mips_store_cause(other, arg1);
1189 }
1190
1191 target_ulong helper_mftc0_epc(CPUMIPSState *env)
1192 {
1193 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1194 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1195
1196 return other->CP0_EPC;
1197 }
1198
1199 target_ulong helper_mftc0_ebase(CPUMIPSState *env)
1200 {
1201 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1202 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1203
1204 return other->CP0_EBase;
1205 }
1206
1207 void helper_mtc0_ebase(CPUMIPSState *env, target_ulong arg1)
1208 {
1209 target_ulong mask = 0x3FFFF000 | env->CP0_EBaseWG_rw_bitmask;
1210 if (arg1 & env->CP0_EBaseWG_rw_bitmask) {
1211 mask |= ~0x3FFFFFFF;
1212 }
1213 env->CP0_EBase = (env->CP0_EBase & ~mask) | (arg1 & mask);
1214 }
1215
1216 void helper_mttc0_ebase(CPUMIPSState *env, target_ulong arg1)
1217 {
1218 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1219 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1220 target_ulong mask = 0x3FFFF000 | env->CP0_EBaseWG_rw_bitmask;
1221 if (arg1 & env->CP0_EBaseWG_rw_bitmask) {
1222 mask |= ~0x3FFFFFFF;
1223 }
1224 other->CP0_EBase = (other->CP0_EBase & ~mask) | (arg1 & mask);
1225 }
1226
1227 target_ulong helper_mftc0_configx(CPUMIPSState *env, target_ulong idx)
1228 {
1229 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1230 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1231
1232 switch (idx) {
1233 case 0: return other->CP0_Config0;
1234 case 1: return other->CP0_Config1;
1235 case 2: return other->CP0_Config2;
1236 case 3: return other->CP0_Config3;
1237 /* 4 and 5 are reserved. */
1238 case 6: return other->CP0_Config6;
1239 case 7: return other->CP0_Config7;
1240 default:
1241 break;
1242 }
1243 return 0;
1244 }
1245
1246 void helper_mtc0_config0(CPUMIPSState *env, target_ulong arg1)
1247 {
1248 env->CP0_Config0 = (env->CP0_Config0 & 0x81FFFFF8) | (arg1 & 0x00000007);
1249 }
1250
1251 void helper_mtc0_config2(CPUMIPSState *env, target_ulong arg1)
1252 {
1253 /* tertiary/secondary caches not implemented */
1254 env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF);
1255 }
1256
1257 void helper_mtc0_config3(CPUMIPSState *env, target_ulong arg1)
1258 {
1259 if (env->insn_flags & ASE_MICROMIPS) {
1260 env->CP0_Config3 = (env->CP0_Config3 & ~(1 << CP0C3_ISA_ON_EXC)) |
1261 (arg1 & (1 << CP0C3_ISA_ON_EXC));
1262 }
1263 }
1264
1265 void helper_mtc0_config4(CPUMIPSState *env, target_ulong arg1)
1266 {
1267 env->CP0_Config4 = (env->CP0_Config4 & (~env->CP0_Config4_rw_bitmask)) |
1268 (arg1 & env->CP0_Config4_rw_bitmask);
1269 }
1270
1271 void helper_mtc0_config5(CPUMIPSState *env, target_ulong arg1)
1272 {
1273 env->CP0_Config5 = (env->CP0_Config5 & (~env->CP0_Config5_rw_bitmask)) |
1274 (arg1 & env->CP0_Config5_rw_bitmask);
1275 env->CP0_EntryHi_ASID_mask = (env->CP0_Config5 & (1 << CP0C5_MI)) ?
1276 0x0 : (env->CP0_Config4 & (1 << CP0C4_AE)) ? 0x3ff : 0xff;
1277 compute_hflags(env);
1278 }
1279
1280 void helper_mtc0_lladdr(CPUMIPSState *env, target_ulong arg1)
1281 {
1282 target_long mask = env->CP0_LLAddr_rw_bitmask;
1283 arg1 = arg1 << env->CP0_LLAddr_shift;
1284 env->CP0_LLAddr = (env->CP0_LLAddr & ~mask) | (arg1 & mask);
1285 }
1286
1287 #define MTC0_MAAR_MASK(env) \
1288 ((0x1ULL << 63) | ((env->PAMask >> 4) & ~0xFFFull) | 0x3)
1289
1290 void helper_mtc0_maar(CPUMIPSState *env, target_ulong arg1)
1291 {
1292 env->CP0_MAAR[env->CP0_MAARI] = arg1 & MTC0_MAAR_MASK(env);
1293 }
1294
1295 void helper_mthc0_maar(CPUMIPSState *env, target_ulong arg1)
1296 {
1297 env->CP0_MAAR[env->CP0_MAARI] =
1298 (((uint64_t) arg1 << 32) & MTC0_MAAR_MASK(env)) |
1299 (env->CP0_MAAR[env->CP0_MAARI] & 0x00000000ffffffffULL);
1300 }
1301
1302 void helper_mtc0_maari(CPUMIPSState *env, target_ulong arg1)
1303 {
1304 int index = arg1 & 0x3f;
1305 if (index == 0x3f) {
1306 /*
1307 * Software may write all ones to INDEX to determine the
1308 * maximum value supported.
1309 */
1310 env->CP0_MAARI = MIPS_MAAR_MAX - 1;
1311 } else if (index < MIPS_MAAR_MAX) {
1312 env->CP0_MAARI = index;
1313 }
1314 /*
1315 * Other than the all ones, if the value written is not supported,
1316 * then INDEX is unchanged from its previous value.
1317 */
1318 }
1319
1320 void helper_mtc0_watchlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1321 {
1322 /*
1323 * Watch exceptions for instructions, data loads, data stores
1324 * not implemented.
1325 */
1326 env->CP0_WatchLo[sel] = (arg1 & ~0x7);
1327 }
1328
1329 void helper_mtc0_watchhi(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1330 {
1331 uint64_t mask = 0x40000FF8 | (env->CP0_EntryHi_ASID_mask << CP0WH_ASID);
1332 uint64_t m_bit = env->CP0_WatchHi[sel] & (1 << CP0WH_M); /* read-only */
1333 if ((env->CP0_Config5 >> CP0C5_MI) & 1) {
1334 mask |= 0xFFFFFFFF00000000ULL; /* MMID */
1335 }
1336 env->CP0_WatchHi[sel] = m_bit | (arg1 & mask);
1337 env->CP0_WatchHi[sel] &= ~(env->CP0_WatchHi[sel] & arg1 & 0x7);
1338 }
1339
1340 void helper_mthc0_watchhi(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1341 {
1342 env->CP0_WatchHi[sel] = ((uint64_t) (arg1) << 32) |
1343 (env->CP0_WatchHi[sel] & 0x00000000ffffffffULL);
1344 }
1345
1346 void helper_mtc0_xcontext(CPUMIPSState *env, target_ulong arg1)
1347 {
1348 target_ulong mask = (1ULL << (env->SEGBITS - 7)) - 1;
1349 env->CP0_XContext = (env->CP0_XContext & mask) | (arg1 & ~mask);
1350 }
1351
1352 void helper_mtc0_framemask(CPUMIPSState *env, target_ulong arg1)
1353 {
1354 env->CP0_Framemask = arg1; /* XXX */
1355 }
1356
1357 void helper_mtc0_debug(CPUMIPSState *env, target_ulong arg1)
1358 {
1359 env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (arg1 & 0x13300120);
1360 if (arg1 & (1 << CP0DB_DM)) {
1361 env->hflags |= MIPS_HFLAG_DM;
1362 } else {
1363 env->hflags &= ~MIPS_HFLAG_DM;
1364 }
1365 }
1366
1367 void helper_mttc0_debug(CPUMIPSState *env, target_ulong arg1)
1368 {
1369 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1370 uint32_t val = arg1 & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt));
1371 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1372
1373 /* XXX: Might be wrong, check with EJTAG spec. */
1374 if (other_tc == other->current_tc) {
1375 other->active_tc.CP0_Debug_tcstatus = val;
1376 } else {
1377 other->tcs[other_tc].CP0_Debug_tcstatus = val;
1378 }
1379 other->CP0_Debug = (other->CP0_Debug &
1380 ((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
1381 (arg1 & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
1382 }
1383
1384 void helper_mtc0_performance0(CPUMIPSState *env, target_ulong arg1)
1385 {
1386 env->CP0_Performance0 = arg1 & 0x000007ff;
1387 }
1388
1389 void helper_mtc0_errctl(CPUMIPSState *env, target_ulong arg1)
1390 {
1391 int32_t wst = arg1 & (1 << CP0EC_WST);
1392 int32_t spr = arg1 & (1 << CP0EC_SPR);
1393 int32_t itc = env->itc_tag ? (arg1 & (1 << CP0EC_ITC)) : 0;
1394
1395 env->CP0_ErrCtl = wst | spr | itc;
1396
1397 if (itc && !wst && !spr) {
1398 env->hflags |= MIPS_HFLAG_ITC_CACHE;
1399 } else {
1400 env->hflags &= ~MIPS_HFLAG_ITC_CACHE;
1401 }
1402 }
1403
1404 void helper_mtc0_taglo(CPUMIPSState *env, target_ulong arg1)
1405 {
1406 if (env->hflags & MIPS_HFLAG_ITC_CACHE) {
1407 /*
1408 * If CACHE instruction is configured for ITC tags then make all
1409 * CP0.TagLo bits writable. The actual write to ITC Configuration
1410 * Tag will take care of the read-only bits.
1411 */
1412 env->CP0_TagLo = arg1;
1413 } else {
1414 env->CP0_TagLo = arg1 & 0xFFFFFCF6;
1415 }
1416 }
1417
1418 void helper_mtc0_datalo(CPUMIPSState *env, target_ulong arg1)
1419 {
1420 env->CP0_DataLo = arg1; /* XXX */
1421 }
1422
1423 void helper_mtc0_taghi(CPUMIPSState *env, target_ulong arg1)
1424 {
1425 env->CP0_TagHi = arg1; /* XXX */
1426 }
1427
1428 void helper_mtc0_datahi(CPUMIPSState *env, target_ulong arg1)
1429 {
1430 env->CP0_DataHi = arg1; /* XXX */
1431 }
1432
1433 /* MIPS MT functions */
1434 target_ulong helper_mftgpr(CPUMIPSState *env, uint32_t sel)
1435 {
1436 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1437 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1438
1439 if (other_tc == other->current_tc) {
1440 return other->active_tc.gpr[sel];
1441 } else {
1442 return other->tcs[other_tc].gpr[sel];
1443 }
1444 }
1445
1446 target_ulong helper_mftlo(CPUMIPSState *env, uint32_t sel)
1447 {
1448 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1449 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1450
1451 if (other_tc == other->current_tc) {
1452 return other->active_tc.LO[sel];
1453 } else {
1454 return other->tcs[other_tc].LO[sel];
1455 }
1456 }
1457
1458 target_ulong helper_mfthi(CPUMIPSState *env, uint32_t sel)
1459 {
1460 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1461 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1462
1463 if (other_tc == other->current_tc) {
1464 return other->active_tc.HI[sel];
1465 } else {
1466 return other->tcs[other_tc].HI[sel];
1467 }
1468 }
1469
1470 target_ulong helper_mftacx(CPUMIPSState *env, uint32_t sel)
1471 {
1472 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1473 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1474
1475 if (other_tc == other->current_tc) {
1476 return other->active_tc.ACX[sel];
1477 } else {
1478 return other->tcs[other_tc].ACX[sel];
1479 }
1480 }
1481
1482 target_ulong helper_mftdsp(CPUMIPSState *env)
1483 {
1484 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1485 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1486
1487 if (other_tc == other->current_tc) {
1488 return other->active_tc.DSPControl;
1489 } else {
1490 return other->tcs[other_tc].DSPControl;
1491 }
1492 }
1493
1494 void helper_mttgpr(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1495 {
1496 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1497 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1498
1499 if (other_tc == other->current_tc) {
1500 other->active_tc.gpr[sel] = arg1;
1501 } else {
1502 other->tcs[other_tc].gpr[sel] = arg1;
1503 }
1504 }
1505
1506 void helper_mttlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1507 {
1508 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1509 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1510
1511 if (other_tc == other->current_tc) {
1512 other->active_tc.LO[sel] = arg1;
1513 } else {
1514 other->tcs[other_tc].LO[sel] = arg1;
1515 }
1516 }
1517
1518 void helper_mtthi(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1519 {
1520 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1521 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1522
1523 if (other_tc == other->current_tc) {
1524 other->active_tc.HI[sel] = arg1;
1525 } else {
1526 other->tcs[other_tc].HI[sel] = arg1;
1527 }
1528 }
1529
1530 void helper_mttacx(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1531 {
1532 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1533 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1534
1535 if (other_tc == other->current_tc) {
1536 other->active_tc.ACX[sel] = arg1;
1537 } else {
1538 other->tcs[other_tc].ACX[sel] = arg1;
1539 }
1540 }
1541
1542 void helper_mttdsp(CPUMIPSState *env, target_ulong arg1)
1543 {
1544 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1545 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1546
1547 if (other_tc == other->current_tc) {
1548 other->active_tc.DSPControl = arg1;
1549 } else {
1550 other->tcs[other_tc].DSPControl = arg1;
1551 }
1552 }
1553
1554 /* MIPS MT functions */
1555 target_ulong helper_dmt(void)
1556 {
1557 /* TODO */
1558 return 0;
1559 }
1560
1561 target_ulong helper_emt(void)
1562 {
1563 /* TODO */
1564 return 0;
1565 }
1566
1567 target_ulong helper_dvpe(CPUMIPSState *env)
1568 {
1569 MIPSCPU *cpu = env_archcpu(env);
1570 target_ulong prev = cpu->mvp->CP0_MVPControl;
1571
1572 if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) {
1573 CPUState *cs;
1574
1575 CPU_FOREACH(cs) {
1576 MIPSCPU *other_cpu = MIPS_CPU(cs);
1577 /* Turn off all VPEs except the one executing the dvpe. */
1578 if (&other_cpu->env != env) {
1579 other_cpu->mvp->CP0_MVPControl &= ~(1 << CP0MVPCo_EVP);
1580 mips_vpe_sleep(other_cpu);
1581 }
1582 }
1583 }
1584 return prev;
1585 }
1586
1587 target_ulong helper_evpe(CPUMIPSState *env)
1588 {
1589 MIPSCPU *cpu = env_archcpu(env);
1590 target_ulong prev = cpu->mvp->CP0_MVPControl;
1591
1592 if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) {
1593 CPUState *cs;
1594
1595 CPU_FOREACH(cs) {
1596 MIPSCPU *other_cpu = MIPS_CPU(cs);
1597
1598 if (&other_cpu->env != env
1599 /* If the VPE is WFI, don't disturb its sleep. */
1600 && !mips_vpe_is_wfi(other_cpu)) {
1601 /* Enable the VPE. */
1602 other_cpu->mvp->CP0_MVPControl |= (1 << CP0MVPCo_EVP);
1603 mips_vpe_wake(other_cpu); /* And wake it up. */
1604 }
1605 }
1606 }
1607 return prev;
1608 }
1609
1610 /* R6 Multi-threading */
1611 target_ulong helper_dvp(CPUMIPSState *env)
1612 {
1613 target_ulong prev = env->CP0_VPControl;
1614
1615 if (!((env->CP0_VPControl >> CP0VPCtl_DIS) & 1)) {
1616 CPUState *cpu;
1617
1618 CPU_FOREACH(cpu) {
1619 MIPSCPU *other_cpu = MIPS_CPU(cpu);
1620 /* Turn off all VPs except the one executing the dvp. */
1621 if (&other_cpu->env != env) {
1622 mips_vpe_sleep(other_cpu);
1623 }
1624 }
1625 env->CP0_VPControl |= (1 << CP0VPCtl_DIS);
1626 }
1627 return prev;
1628 }
1629
1630 target_ulong helper_evp(CPUMIPSState *env)
1631 {
1632 target_ulong prev = env->CP0_VPControl;
1633
1634 if ((env->CP0_VPControl >> CP0VPCtl_DIS) & 1) {
1635 CPUState *cpu;
1636
1637 CPU_FOREACH(cpu) {
1638 MIPSCPU *other_cpu = MIPS_CPU(cpu);
1639 if ((&other_cpu->env != env) && !mips_vp_is_wfi(other_cpu)) {
1640 /*
1641 * If the VP is WFI, don't disturb its sleep.
1642 * Otherwise, wake it up.
1643 */
1644 mips_vpe_wake(other_cpu);
1645 }
1646 }
1647 env->CP0_VPControl &= ~(1 << CP0VPCtl_DIS);
1648 }
1649 return prev;
1650 }