| 1 | /* |
| 2 | * MIPS TLB (Translation lookaside buffer) helpers. |
| 3 | * |
| 4 | * Copyright (c) 2004-2005 Jocelyn Mayer |
| 5 | * |
| 6 | * This library is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU Lesser General Public |
| 8 | * License as published by the Free Software Foundation; either |
| 9 | * version 2.1 of the License, or (at your option) any later version. |
| 10 | * |
| 11 | * This library is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 14 | * Lesser General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU Lesser General Public |
| 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
| 18 | */ |
| 19 | #include "qemu/osdep.h" |
| 20 | #include "qemu/bitops.h" |
| 21 | #include "qemu/plugin.h" |
| 22 | |
| 23 | #include "cpu.h" |
| 24 | #include "internal.h" |
| 25 | #include "exec/cputlb.h" |
| 26 | #include "exec/page-protection.h" |
| 27 | #include "exec/target_page.h" |
| 28 | #include "accel/tcg/cpu-ldst.h" |
| 29 | #include "accel/tcg/cpu-loop.h" |
| 30 | #include "exec/log.h" |
| 31 | #include "exec/helper-proto.h" |
| 32 | |
| 33 | /* TLB management */ |
| 34 | static void r4k_mips_tlb_flush_extra(CPUMIPSState *env, int first) |
| 35 | { |
| 36 | /* Discard entries from env->tlb[first] onwards. */ |
| 37 | while (env->tlb->tlb_in_use > first) { |
| 38 | r4k_invalidate_tlb(env, --env->tlb->tlb_in_use, 0); |
| 39 | } |
| 40 | } |
| 41 | |
| 42 | static inline uint64_t get_tlb_pfn_from_entrylo(uint64_t entrylo) |
| 43 | { |
| 44 | #if defined(TARGET_MIPS64) |
| 45 | return extract64(entrylo, 6, 54); |
| 46 | #else |
| 47 | return extract64(entrylo, 6, 24) | /* PFN */ |
| 48 | (extract64(entrylo, 32, 32) << 24); /* PFNX */ |
| 49 | #endif |
| 50 | } |
| 51 | |
| 52 | static void r4k_fill_tlb(CPUMIPSState *env, int idx) |
| 53 | { |
| 54 | r4k_tlb_t *tlb; |
| 55 | uint64_t mask = env->CP0_PageMask >> (TARGET_PAGE_BITS + 1); |
| 56 | |
| 57 | /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */ |
| 58 | tlb = &env->tlb->mmu.r4k.tlb[idx]; |
| 59 | if (env->CP0_EntryHi & (1 << CP0EnHi_EHINV)) { |
| 60 | tlb->EHINV = 1; |
| 61 | return; |
| 62 | } |
| 63 | tlb->EHINV = 0; |
| 64 | tlb->VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1); |
| 65 | #if defined(TARGET_MIPS64) |
| 66 | tlb->VPN &= env->SEGMask; |
| 67 | #endif |
| 68 | tlb->ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; |
| 69 | tlb->MMID = env->CP0_MemoryMapID; |
| 70 | tlb->PageMask = env->CP0_PageMask; |
| 71 | tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1; |
| 72 | tlb->V0 = (env->CP0_EntryLo0 & 2) != 0; |
| 73 | tlb->D0 = (env->CP0_EntryLo0 & 4) != 0; |
| 74 | tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7; |
| 75 | tlb->XI0 = (env->CP0_EntryLo0 >> CP0EnLo_XI) & 1; |
| 76 | tlb->RI0 = (env->CP0_EntryLo0 >> CP0EnLo_RI) & 1; |
| 77 | tlb->PFN[0] = (get_tlb_pfn_from_entrylo(env->CP0_EntryLo0) & ~mask) << 12; |
| 78 | tlb->V1 = (env->CP0_EntryLo1 & 2) != 0; |
| 79 | tlb->D1 = (env->CP0_EntryLo1 & 4) != 0; |
| 80 | tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7; |
| 81 | tlb->XI1 = (env->CP0_EntryLo1 >> CP0EnLo_XI) & 1; |
| 82 | tlb->RI1 = (env->CP0_EntryLo1 >> CP0EnLo_RI) & 1; |
| 83 | tlb->PFN[1] = (get_tlb_pfn_from_entrylo(env->CP0_EntryLo1) & ~mask) << 12; |
| 84 | } |
| 85 | |
| 86 | static void r4k_helper_tlbinv(CPUMIPSState *env) |
| 87 | { |
| 88 | bool mi = !!((env->CP0_Config5 >> CP0C5_MI) & 1); |
| 89 | uint16_t ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; |
| 90 | uint32_t MMID = env->CP0_MemoryMapID; |
| 91 | uint32_t tlb_mmid; |
| 92 | r4k_tlb_t *tlb; |
| 93 | int idx; |
| 94 | |
| 95 | MMID = mi ? MMID : (uint32_t) ASID; |
| 96 | for (idx = 0; idx < env->tlb->nb_tlb; idx++) { |
| 97 | tlb = &env->tlb->mmu.r4k.tlb[idx]; |
| 98 | tlb_mmid = mi ? tlb->MMID : (uint32_t) tlb->ASID; |
| 99 | if (!tlb->G && tlb_mmid == MMID) { |
| 100 | tlb->EHINV = 1; |
| 101 | } |
| 102 | } |
| 103 | cpu_mips_tlb_flush(env); |
| 104 | } |
| 105 | |
| 106 | static void r4k_helper_tlbinvf(CPUMIPSState *env) |
| 107 | { |
| 108 | int idx; |
| 109 | |
| 110 | for (idx = 0; idx < env->tlb->nb_tlb; idx++) { |
| 111 | env->tlb->mmu.r4k.tlb[idx].EHINV = 1; |
| 112 | } |
| 113 | cpu_mips_tlb_flush(env); |
| 114 | } |
| 115 | |
| 116 | static void r4k_helper_tlbwi(CPUMIPSState *env) |
| 117 | { |
| 118 | bool mi = !!((env->CP0_Config5 >> CP0C5_MI) & 1); |
| 119 | target_ulong VPN; |
| 120 | uint16_t ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; |
| 121 | uint32_t MMID = env->CP0_MemoryMapID; |
| 122 | uint32_t tlb_mmid; |
| 123 | bool EHINV, G, V0, D0, V1, D1, XI0, XI1, RI0, RI1; |
| 124 | r4k_tlb_t *tlb; |
| 125 | int idx; |
| 126 | |
| 127 | MMID = mi ? MMID : (uint32_t) ASID; |
| 128 | |
| 129 | idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb; |
| 130 | tlb = &env->tlb->mmu.r4k.tlb[idx]; |
| 131 | VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1); |
| 132 | #if defined(TARGET_MIPS64) |
| 133 | VPN &= env->SEGMask; |
| 134 | #endif |
| 135 | EHINV = (env->CP0_EntryHi & (1 << CP0EnHi_EHINV)) != 0; |
| 136 | G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1; |
| 137 | V0 = (env->CP0_EntryLo0 & 2) != 0; |
| 138 | D0 = (env->CP0_EntryLo0 & 4) != 0; |
| 139 | XI0 = (env->CP0_EntryLo0 >> CP0EnLo_XI) &1; |
| 140 | RI0 = (env->CP0_EntryLo0 >> CP0EnLo_RI) &1; |
| 141 | V1 = (env->CP0_EntryLo1 & 2) != 0; |
| 142 | D1 = (env->CP0_EntryLo1 & 4) != 0; |
| 143 | XI1 = (env->CP0_EntryLo1 >> CP0EnLo_XI) &1; |
| 144 | RI1 = (env->CP0_EntryLo1 >> CP0EnLo_RI) &1; |
| 145 | |
| 146 | tlb_mmid = mi ? tlb->MMID : (uint32_t) tlb->ASID; |
| 147 | /* |
| 148 | * Discard cached TLB entries, unless tlbwi is just upgrading access |
| 149 | * permissions on the current entry. |
| 150 | */ |
| 151 | if (tlb->VPN != VPN || tlb_mmid != MMID || tlb->G != G || |
| 152 | (!tlb->EHINV && EHINV) || |
| 153 | (tlb->V0 && !V0) || (tlb->D0 && !D0) || |
| 154 | (!tlb->XI0 && XI0) || (!tlb->RI0 && RI0) || |
| 155 | (tlb->V1 && !V1) || (tlb->D1 && !D1) || |
| 156 | (!tlb->XI1 && XI1) || (!tlb->RI1 && RI1)) { |
| 157 | r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb); |
| 158 | } |
| 159 | |
| 160 | r4k_invalidate_tlb(env, idx, 0); |
| 161 | r4k_fill_tlb(env, idx); |
| 162 | } |
| 163 | |
| 164 | static void r4k_helper_tlbwr(CPUMIPSState *env) |
| 165 | { |
| 166 | int r = cpu_mips_get_random(env); |
| 167 | |
| 168 | r4k_invalidate_tlb(env, r, 1); |
| 169 | r4k_fill_tlb(env, r); |
| 170 | } |
| 171 | |
| 172 | static void r4k_helper_tlbp(CPUMIPSState *env) |
| 173 | { |
| 174 | bool mi = !!((env->CP0_Config5 >> CP0C5_MI) & 1); |
| 175 | r4k_tlb_t *tlb; |
| 176 | target_ulong mask; |
| 177 | target_ulong tag; |
| 178 | target_ulong VPN; |
| 179 | uint16_t ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; |
| 180 | uint32_t MMID = env->CP0_MemoryMapID; |
| 181 | uint32_t tlb_mmid; |
| 182 | int i; |
| 183 | |
| 184 | MMID = mi ? MMID : (uint32_t) ASID; |
| 185 | for (i = 0; i < env->tlb->nb_tlb; i++) { |
| 186 | tlb = &env->tlb->mmu.r4k.tlb[i]; |
| 187 | /* 1k pages are not supported. */ |
| 188 | mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1); |
| 189 | tag = env->CP0_EntryHi & ~mask; |
| 190 | VPN = tlb->VPN & ~mask; |
| 191 | #if defined(TARGET_MIPS64) |
| 192 | tag &= env->SEGMask; |
| 193 | #endif |
| 194 | tlb_mmid = mi ? tlb->MMID : (uint32_t) tlb->ASID; |
| 195 | /* Check ASID/MMID, virtual page number & size */ |
| 196 | if ((tlb->G == 1 || tlb_mmid == MMID) && VPN == tag && !tlb->EHINV) { |
| 197 | /* TLB match */ |
| 198 | env->CP0_Index = i; |
| 199 | break; |
| 200 | } |
| 201 | } |
| 202 | if (i == env->tlb->nb_tlb) { |
| 203 | /* No match. Discard any shadow entries, if any of them match. */ |
| 204 | for (i = env->tlb->nb_tlb; i < env->tlb->tlb_in_use; i++) { |
| 205 | tlb = &env->tlb->mmu.r4k.tlb[i]; |
| 206 | /* 1k pages are not supported. */ |
| 207 | mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1); |
| 208 | tag = env->CP0_EntryHi & ~mask; |
| 209 | VPN = tlb->VPN & ~mask; |
| 210 | #if defined(TARGET_MIPS64) |
| 211 | tag &= env->SEGMask; |
| 212 | #endif |
| 213 | tlb_mmid = mi ? tlb->MMID : (uint32_t) tlb->ASID; |
| 214 | /* Check ASID/MMID, virtual page number & size */ |
| 215 | if ((tlb->G == 1 || tlb_mmid == MMID) && VPN == tag) { |
| 216 | r4k_mips_tlb_flush_extra(env, i); |
| 217 | break; |
| 218 | } |
| 219 | } |
| 220 | |
| 221 | env->CP0_Index |= 0x80000000; |
| 222 | } |
| 223 | } |
| 224 | |
| 225 | static inline uint64_t get_entrylo_pfn_from_tlb(uint64_t tlb_pfn) |
| 226 | { |
| 227 | #if defined(TARGET_MIPS64) |
| 228 | return tlb_pfn << 6; |
| 229 | #else |
| 230 | return (extract64(tlb_pfn, 0, 24) << 6) | /* PFN */ |
| 231 | (extract64(tlb_pfn, 24, 32) << 32); /* PFNX */ |
| 232 | #endif |
| 233 | } |
| 234 | |
| 235 | static void r4k_helper_tlbr(CPUMIPSState *env) |
| 236 | { |
| 237 | bool mi = !!((env->CP0_Config5 >> CP0C5_MI) & 1); |
| 238 | uint16_t ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; |
| 239 | uint32_t MMID = env->CP0_MemoryMapID; |
| 240 | uint32_t tlb_mmid; |
| 241 | r4k_tlb_t *tlb; |
| 242 | int idx; |
| 243 | |
| 244 | MMID = mi ? MMID : (uint32_t) ASID; |
| 245 | idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb; |
| 246 | tlb = &env->tlb->mmu.r4k.tlb[idx]; |
| 247 | |
| 248 | tlb_mmid = mi ? tlb->MMID : (uint32_t) tlb->ASID; |
| 249 | /* If this will change the current ASID/MMID, flush qemu's TLB. */ |
| 250 | if (MMID != tlb_mmid) { |
| 251 | cpu_mips_tlb_flush(env); |
| 252 | } |
| 253 | |
| 254 | r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb); |
| 255 | |
| 256 | if (tlb->EHINV) { |
| 257 | env->CP0_EntryHi = 1 << CP0EnHi_EHINV; |
| 258 | env->CP0_PageMask = 0; |
| 259 | env->CP0_EntryLo0 = 0; |
| 260 | env->CP0_EntryLo1 = 0; |
| 261 | } else { |
| 262 | env->CP0_EntryHi = mi ? tlb->VPN : tlb->VPN | tlb->ASID; |
| 263 | env->CP0_MemoryMapID = tlb->MMID; |
| 264 | env->CP0_PageMask = tlb->PageMask; |
| 265 | env->CP0_EntryLo0 = tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2) | |
| 266 | ((uint64_t)tlb->RI0 << CP0EnLo_RI) | |
| 267 | ((uint64_t)tlb->XI0 << CP0EnLo_XI) | (tlb->C0 << 3) | |
| 268 | get_entrylo_pfn_from_tlb(tlb->PFN[0] >> 12); |
| 269 | env->CP0_EntryLo1 = tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) | |
| 270 | ((uint64_t)tlb->RI1 << CP0EnLo_RI) | |
| 271 | ((uint64_t)tlb->XI1 << CP0EnLo_XI) | (tlb->C1 << 3) | |
| 272 | get_entrylo_pfn_from_tlb(tlb->PFN[1] >> 12); |
| 273 | } |
| 274 | } |
| 275 | |
| 276 | void helper_tlbwi(CPUMIPSState *env) |
| 277 | { |
| 278 | env->tlb->helper_tlbwi(env); |
| 279 | } |
| 280 | |
| 281 | void helper_tlbwr(CPUMIPSState *env) |
| 282 | { |
| 283 | env->tlb->helper_tlbwr(env); |
| 284 | } |
| 285 | |
| 286 | void helper_tlbp(CPUMIPSState *env) |
| 287 | { |
| 288 | env->tlb->helper_tlbp(env); |
| 289 | } |
| 290 | |
| 291 | void helper_tlbr(CPUMIPSState *env) |
| 292 | { |
| 293 | env->tlb->helper_tlbr(env); |
| 294 | } |
| 295 | |
| 296 | void helper_tlbinv(CPUMIPSState *env) |
| 297 | { |
| 298 | env->tlb->helper_tlbinv(env); |
| 299 | } |
| 300 | |
| 301 | void helper_tlbinvf(CPUMIPSState *env) |
| 302 | { |
| 303 | env->tlb->helper_tlbinvf(env); |
| 304 | } |
| 305 | |
| 306 | static void global_invalidate_tlb(CPUMIPSState *env, |
| 307 | uint32_t invMsgVPN2, |
| 308 | uint8_t invMsgR, |
| 309 | uint32_t invMsgMMid, |
| 310 | bool invAll, |
| 311 | bool invVAMMid, |
| 312 | bool invMMid, |
| 313 | bool invVA) |
| 314 | { |
| 315 | |
| 316 | int idx; |
| 317 | r4k_tlb_t *tlb; |
| 318 | bool VAMatch; |
| 319 | bool MMidMatch; |
| 320 | |
| 321 | for (idx = 0; idx < env->tlb->nb_tlb; idx++) { |
| 322 | tlb = &env->tlb->mmu.r4k.tlb[idx]; |
| 323 | VAMatch = |
| 324 | (((tlb->VPN & ~tlb->PageMask) == (invMsgVPN2 & ~tlb->PageMask)) |
| 325 | #ifdef TARGET_MIPS64 |
| 326 | && |
| 327 | (extract64(env->CP0_EntryHi, 62, 2) == invMsgR) |
| 328 | #endif |
| 329 | ); |
| 330 | MMidMatch = tlb->MMID == invMsgMMid; |
| 331 | if ((invAll && (idx > env->CP0_Wired)) || |
| 332 | (VAMatch && invVAMMid && (tlb->G || MMidMatch)) || |
| 333 | (VAMatch && invVA) || |
| 334 | (MMidMatch && !(tlb->G) && invMMid)) { |
| 335 | tlb->EHINV = 1; |
| 336 | } |
| 337 | } |
| 338 | cpu_mips_tlb_flush(env); |
| 339 | } |
| 340 | |
| 341 | void helper_ginvt(CPUMIPSState *env, target_ulong arg, uint32_t type) |
| 342 | { |
| 343 | bool invAll = type == 0; |
| 344 | bool invVA = type == 1; |
| 345 | bool invMMid = type == 2; |
| 346 | bool invVAMMid = type == 3; |
| 347 | uint32_t invMsgVPN2 = arg & (TARGET_PAGE_MASK << 1); |
| 348 | uint8_t invMsgR = 0; |
| 349 | uint32_t invMsgMMid = env->CP0_MemoryMapID; |
| 350 | CPUState *cpu; |
| 351 | |
| 352 | #ifdef TARGET_MIPS64 |
| 353 | invMsgR = extract64(arg, 62, 2); |
| 354 | #endif |
| 355 | |
| 356 | CPU_FOREACH(cpu) { |
| 357 | global_invalidate_tlb(cpu_env(cpu), invMsgVPN2, invMsgR, invMsgMMid, |
| 358 | invAll, invVAMMid, invMMid, invVA); |
| 359 | } |
| 360 | } |
| 361 | |
| 362 | /* no MMU emulation */ |
| 363 | static int no_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot, |
| 364 | target_ulong address, MMUAccessType access_type) |
| 365 | { |
| 366 | *physical = address; |
| 367 | *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
| 368 | return TLBRET_MATCH; |
| 369 | } |
| 370 | |
| 371 | /* fixed mapping MMU emulation */ |
| 372 | static int fixed_mmu_map_address(CPUMIPSState *env, hwaddr *physical, |
| 373 | int *prot, target_ulong address, |
| 374 | MMUAccessType access_type) |
| 375 | { |
| 376 | if (address <= (int32_t)0x7FFFFFFFUL) { |
| 377 | if (!(env->CP0_Status & (1 << CP0St_ERL))) { |
| 378 | *physical = address + 0x40000000UL; |
| 379 | } else { |
| 380 | *physical = address; |
| 381 | } |
| 382 | } else if (address <= (int32_t)0xBFFFFFFFUL) { |
| 383 | *physical = address & 0x1FFFFFFF; |
| 384 | } else { |
| 385 | *physical = address; |
| 386 | } |
| 387 | |
| 388 | *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
| 389 | return TLBRET_MATCH; |
| 390 | } |
| 391 | |
| 392 | /* MIPS32/MIPS64 R4000-style MMU emulation */ |
| 393 | static int r4k_map_address(CPUMIPSState *env, hwaddr *physical, int *prot, |
| 394 | target_ulong address, MMUAccessType access_type) |
| 395 | { |
| 396 | uint16_t ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; |
| 397 | uint32_t MMID = env->CP0_MemoryMapID; |
| 398 | bool mi = !!((env->CP0_Config5 >> CP0C5_MI) & 1); |
| 399 | uint32_t tlb_mmid; |
| 400 | int i; |
| 401 | |
| 402 | MMID = mi ? MMID : (uint32_t) ASID; |
| 403 | |
| 404 | for (i = 0; i < env->tlb->tlb_in_use; i++) { |
| 405 | r4k_tlb_t *tlb = &env->tlb->mmu.r4k.tlb[i]; |
| 406 | /* 1k pages are not supported. */ |
| 407 | target_ulong mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1); |
| 408 | target_ulong tag = address & ~mask; |
| 409 | target_ulong VPN = tlb->VPN & ~mask; |
| 410 | #if defined(TARGET_MIPS64) |
| 411 | tag &= env->SEGMask; |
| 412 | #endif |
| 413 | |
| 414 | /* Check ASID/MMID, virtual page number & size */ |
| 415 | tlb_mmid = mi ? tlb->MMID : (uint32_t) tlb->ASID; |
| 416 | if ((tlb->G == 1 || tlb_mmid == MMID) && VPN == tag && !tlb->EHINV) { |
| 417 | /* TLB match */ |
| 418 | int n = !!(address & mask & ~(mask >> 1)); |
| 419 | /* Check access rights */ |
| 420 | if (!(n ? tlb->V1 : tlb->V0)) { |
| 421 | return TLBRET_INVALID; |
| 422 | } |
| 423 | if (access_type == MMU_INST_FETCH && (n ? tlb->XI1 : tlb->XI0)) { |
| 424 | return TLBRET_XI; |
| 425 | } |
| 426 | if (access_type == MMU_DATA_LOAD && (n ? tlb->RI1 : tlb->RI0)) { |
| 427 | return TLBRET_RI; |
| 428 | } |
| 429 | if (access_type != MMU_DATA_STORE || (n ? tlb->D1 : tlb->D0)) { |
| 430 | *physical = tlb->PFN[n] | (address & (mask >> 1)); |
| 431 | *prot = PAGE_READ; |
| 432 | if (n ? tlb->D1 : tlb->D0) { |
| 433 | *prot |= PAGE_WRITE; |
| 434 | } |
| 435 | if (!(n ? tlb->XI1 : tlb->XI0)) { |
| 436 | *prot |= PAGE_EXEC; |
| 437 | } |
| 438 | return TLBRET_MATCH; |
| 439 | } |
| 440 | return TLBRET_DIRTY; |
| 441 | } |
| 442 | } |
| 443 | return TLBRET_NOMATCH; |
| 444 | } |
| 445 | |
| 446 | static void no_mmu_init(CPUMIPSState *env, const mips_def_t *def) |
| 447 | { |
| 448 | env->tlb->nb_tlb = 1; |
| 449 | env->tlb->map_address = &no_mmu_map_address; |
| 450 | } |
| 451 | |
| 452 | static void fixed_mmu_init(CPUMIPSState *env, const mips_def_t *def) |
| 453 | { |
| 454 | env->tlb->nb_tlb = 1; |
| 455 | env->tlb->map_address = &fixed_mmu_map_address; |
| 456 | } |
| 457 | |
| 458 | static void r4k_mmu_init(CPUMIPSState *env, const mips_def_t *def) |
| 459 | { |
| 460 | env->tlb->nb_tlb = 1 + ((def->CP0_Config1 >> CP0C1_MMU) & 63); |
| 461 | env->tlb->map_address = &r4k_map_address; |
| 462 | env->tlb->helper_tlbwi = r4k_helper_tlbwi; |
| 463 | env->tlb->helper_tlbwr = r4k_helper_tlbwr; |
| 464 | env->tlb->helper_tlbp = r4k_helper_tlbp; |
| 465 | env->tlb->helper_tlbr = r4k_helper_tlbr; |
| 466 | env->tlb->helper_tlbinv = r4k_helper_tlbinv; |
| 467 | env->tlb->helper_tlbinvf = r4k_helper_tlbinvf; |
| 468 | } |
| 469 | |
| 470 | void mmu_init(CPUMIPSState *env, const mips_def_t *def) |
| 471 | { |
| 472 | env->tlb = g_malloc0(sizeof(CPUMIPSTLBContext)); |
| 473 | |
| 474 | switch (def->mmu_type) { |
| 475 | case MMU_TYPE_NONE: |
| 476 | no_mmu_init(env, def); |
| 477 | break; |
| 478 | case MMU_TYPE_R4000: |
| 479 | r4k_mmu_init(env, def); |
| 480 | break; |
| 481 | case MMU_TYPE_FMT: |
| 482 | fixed_mmu_init(env, def); |
| 483 | break; |
| 484 | case MMU_TYPE_R3000: |
| 485 | case MMU_TYPE_R6000: |
| 486 | case MMU_TYPE_R8000: |
| 487 | default: |
| 488 | cpu_abort(env_cpu(env), "MMU type not supported\n"); |
| 489 | } |
| 490 | } |
| 491 | |
| 492 | void cpu_mips_tlb_flush(CPUMIPSState *env) |
| 493 | { |
| 494 | /* Flush qemu's TLB and discard all shadowed entries. */ |
| 495 | tlb_flush(env_cpu(env)); |
| 496 | env->tlb->tlb_in_use = env->tlb->nb_tlb; |
| 497 | } |
| 498 | |
| 499 | static void raise_mmu_exception(CPUMIPSState *env, target_ulong address, |
| 500 | MMUAccessType access_type, int tlb_error) |
| 501 | { |
| 502 | CPUState *cs = env_cpu(env); |
| 503 | int exception = 0, error_code = 0; |
| 504 | |
| 505 | if (access_type == MMU_INST_FETCH) { |
| 506 | error_code |= EXCP_INST_NOTAVAIL; |
| 507 | } |
| 508 | |
| 509 | switch (tlb_error) { |
| 510 | default: |
| 511 | case TLBRET_BADADDR: |
| 512 | /* Reference to kernel address from user mode or supervisor mode */ |
| 513 | /* Reference to supervisor address from user mode */ |
| 514 | if (access_type == MMU_DATA_STORE) { |
| 515 | exception = EXCP_AdES; |
| 516 | } else { |
| 517 | exception = EXCP_AdEL; |
| 518 | } |
| 519 | break; |
| 520 | case TLBRET_NOMATCH: |
| 521 | /* No TLB match for a mapped address */ |
| 522 | if (access_type == MMU_DATA_STORE) { |
| 523 | exception = EXCP_TLBS; |
| 524 | } else { |
| 525 | exception = EXCP_TLBL; |
| 526 | } |
| 527 | error_code |= EXCP_TLB_NOMATCH; |
| 528 | break; |
| 529 | case TLBRET_INVALID: |
| 530 | /* TLB match with no valid bit */ |
| 531 | if (access_type == MMU_DATA_STORE) { |
| 532 | exception = EXCP_TLBS; |
| 533 | } else { |
| 534 | exception = EXCP_TLBL; |
| 535 | } |
| 536 | break; |
| 537 | case TLBRET_DIRTY: |
| 538 | /* TLB match but 'D' bit is cleared */ |
| 539 | exception = EXCP_LTLBL; |
| 540 | break; |
| 541 | case TLBRET_XI: |
| 542 | /* Execute-Inhibit Exception */ |
| 543 | if (env->CP0_PageGrain & (1 << CP0PG_IEC)) { |
| 544 | exception = EXCP_TLBXI; |
| 545 | } else { |
| 546 | exception = EXCP_TLBL; |
| 547 | } |
| 548 | break; |
| 549 | case TLBRET_RI: |
| 550 | /* Read-Inhibit Exception */ |
| 551 | if (env->CP0_PageGrain & (1 << CP0PG_IEC)) { |
| 552 | exception = EXCP_TLBRI; |
| 553 | } else { |
| 554 | exception = EXCP_TLBL; |
| 555 | } |
| 556 | break; |
| 557 | } |
| 558 | /* Raise exception */ |
| 559 | if (!(env->hflags & MIPS_HFLAG_DM)) { |
| 560 | env->CP0_BadVAddr = address; |
| 561 | } |
| 562 | env->CP0_Context = (env->CP0_Context & ~0x007fffff) | |
| 563 | ((address >> 9) & 0x007ffff0); |
| 564 | env->CP0_EntryHi = (env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask) | |
| 565 | (env->CP0_EntryHi & (1 << CP0EnHi_EHINV)) | |
| 566 | (address & (TARGET_PAGE_MASK << 1)); |
| 567 | #if defined(TARGET_MIPS64) |
| 568 | env->CP0_EntryHi &= env->SEGMask; |
| 569 | env->CP0_XContext = |
| 570 | (env->CP0_XContext & ((~0ULL) << (env->SEGBITS - 7))) | /* PTEBase */ |
| 571 | (extract64(address, 62, 2) << (env->SEGBITS - 9)) | /* R */ |
| 572 | (extract64(address, 13, env->SEGBITS - 13) << 4); /* BadVPN2 */ |
| 573 | #endif |
| 574 | cs->exception_index = exception; |
| 575 | env->error_code = error_code; |
| 576 | } |
| 577 | |
| 578 | #if !defined(TARGET_MIPS64) |
| 579 | |
| 580 | /* |
| 581 | * Perform hardware page table walk |
| 582 | * |
| 583 | * Memory accesses are performed using the KERNEL privilege level. |
| 584 | * Synchronous exceptions detected on memory accesses cause a silent exit |
| 585 | * from page table walking, resulting in a TLB or XTLB Refill exception. |
| 586 | * |
| 587 | * Implementations are not required to support page table walk memory |
| 588 | * accesses from mapped memory regions. When an unsupported access is |
| 589 | * attempted, a silent exit is taken, resulting in a TLB or XTLB Refill |
| 590 | * exception. |
| 591 | * |
| 592 | * Note that if an exception is caused by AddressTranslation or LoadMemory |
| 593 | * functions, the exception is not taken, a silent exit is taken, |
| 594 | * resulting in a TLB or XTLB Refill exception. |
| 595 | */ |
| 596 | |
| 597 | static bool get_pte(CPUMIPSState *env, uint64_t vaddr, MemOp op, |
| 598 | uint64_t *pte, unsigned ptw_mmu_idx) |
| 599 | { |
| 600 | MemOpIdx oi; |
| 601 | |
| 602 | if ((vaddr & (memop_size(op) - 1)) != 0) { |
| 603 | return false; |
| 604 | } |
| 605 | |
| 606 | oi = make_memop_idx(op | mo_endian_env(env), ptw_mmu_idx); |
| 607 | if (op == MO_64) { |
| 608 | *pte = cpu_ldq_mmu(env, vaddr, oi, 0); |
| 609 | } else { |
| 610 | *pte = cpu_ldl_mmu(env, vaddr, oi, 0); |
| 611 | } |
| 612 | |
| 613 | return true; |
| 614 | } |
| 615 | |
| 616 | static uint64_t get_tlb_entry_layout(CPUMIPSState *env, uint64_t entry, |
| 617 | MemOp op, int ptei) |
| 618 | { |
| 619 | unsigned entry_size = memop_size(op) << 3; |
| 620 | uint64_t result = entry; |
| 621 | uint64_t rixi; |
| 622 | if (ptei > entry_size) { |
| 623 | ptei -= 32; |
| 624 | } |
| 625 | result >>= (ptei - 2); |
| 626 | rixi = result & 3; |
| 627 | result >>= 2; |
| 628 | result |= rixi << CP0EnLo_XI; |
| 629 | return result; |
| 630 | } |
| 631 | |
| 632 | static int walk_directory(CPUMIPSState *env, uint64_t *vaddr, |
| 633 | int directory_index, bool *huge_page, bool *hgpg_directory_hit, |
| 634 | uint64_t *pw_entrylo0, uint64_t *pw_entrylo1, |
| 635 | MemOp directory_mop, MemOp leaf_mop, int ptw_mmu_idx) |
| 636 | { |
| 637 | int dph = (env->CP0_PWCtl >> CP0PC_DPH) & 0x1; |
| 638 | int psn = (env->CP0_PWCtl >> CP0PC_PSN) & 0x3F; |
| 639 | int hugepg = (env->CP0_PWCtl >> CP0PC_HUGEPG) & 0x1; |
| 640 | int pf_ptew = (env->CP0_PWField >> CP0PF_PTEW) & 0x3F; |
| 641 | uint64_t entry; |
| 642 | uint64_t paddr; |
| 643 | int prot; |
| 644 | uint64_t lsb = 0; |
| 645 | uint64_t w = 0; |
| 646 | |
| 647 | if (get_physical_address(env, &paddr, &prot, *vaddr, MMU_DATA_LOAD, |
| 648 | ptw_mmu_idx) != TLBRET_MATCH) { |
| 649 | /* wrong base address */ |
| 650 | return 0; |
| 651 | } |
| 652 | if (!get_pte(env, *vaddr, directory_mop, &entry, ptw_mmu_idx)) { |
| 653 | return 0; |
| 654 | } |
| 655 | |
| 656 | if (extract64(entry, psn, 1) && hugepg) { |
| 657 | *huge_page = true; |
| 658 | *hgpg_directory_hit = true; |
| 659 | entry = get_tlb_entry_layout(env, entry, leaf_mop, pf_ptew); |
| 660 | w = directory_index - 1; |
| 661 | if (directory_index & 0x1) { |
| 662 | /* Generate adjacent page from same PTE for odd TLB page */ |
| 663 | lsb = BIT_ULL(w) >> 6; |
| 664 | *pw_entrylo0 = entry & ~lsb; /* even page */ |
| 665 | *pw_entrylo1 = entry | lsb; /* odd page */ |
| 666 | } else if (dph) { |
| 667 | int oddpagebit = 1 << leaf_mop; |
| 668 | uint64_t vaddr2 = *vaddr ^ oddpagebit; |
| 669 | if (*vaddr & oddpagebit) { |
| 670 | *pw_entrylo1 = entry; |
| 671 | } else { |
| 672 | *pw_entrylo0 = entry; |
| 673 | } |
| 674 | if (get_physical_address(env, &paddr, &prot, vaddr2, MMU_DATA_LOAD, |
| 675 | ptw_mmu_idx) != TLBRET_MATCH) { |
| 676 | return 0; |
| 677 | } |
| 678 | if (!get_pte(env, vaddr2, leaf_mop, &entry, ptw_mmu_idx)) { |
| 679 | return 0; |
| 680 | } |
| 681 | entry = get_tlb_entry_layout(env, entry, leaf_mop, pf_ptew); |
| 682 | if (*vaddr & oddpagebit) { |
| 683 | *pw_entrylo0 = entry; |
| 684 | } else { |
| 685 | *pw_entrylo1 = entry; |
| 686 | } |
| 687 | } else { |
| 688 | return 0; |
| 689 | } |
| 690 | return 1; |
| 691 | } else { |
| 692 | *vaddr = entry; |
| 693 | return 2; |
| 694 | } |
| 695 | } |
| 696 | |
| 697 | static bool page_table_walk_refill(CPUMIPSState *env, vaddr address, |
| 698 | int ptw_mmu_idx) |
| 699 | { |
| 700 | int gdw = (env->CP0_PWSize >> CP0PS_GDW) & 0x3F; |
| 701 | int udw = (env->CP0_PWSize >> CP0PS_UDW) & 0x3F; |
| 702 | int mdw = (env->CP0_PWSize >> CP0PS_MDW) & 0x3F; |
| 703 | int ptw = (env->CP0_PWSize >> CP0PS_PTW) & 0x3F; |
| 704 | int ptew = (env->CP0_PWSize >> CP0PS_PTEW) & 0x3F; |
| 705 | |
| 706 | /* Initial values */ |
| 707 | bool huge_page = false; |
| 708 | bool hgpg_bdhit = false; |
| 709 | bool hgpg_gdhit = false; |
| 710 | bool hgpg_udhit = false; |
| 711 | bool hgpg_mdhit = false; |
| 712 | |
| 713 | int32_t pw_pagemask = 0; |
| 714 | target_ulong pw_entryhi = 0; |
| 715 | uint64_t pw_entrylo0 = 0; |
| 716 | uint64_t pw_entrylo1 = 0; |
| 717 | |
| 718 | /* Native pointer size */ |
| 719 | /*For the 32-bit architectures, this bit is fixed to 0.*/ |
| 720 | MemOp native_op = (((env->CP0_PWSize >> CP0PS_PS) & 1) == 0) ? MO_32 : MO_64; |
| 721 | |
| 722 | /* Indices from PWField */ |
| 723 | int pf_gdw = (env->CP0_PWField >> CP0PF_GDW) & 0x3F; |
| 724 | int pf_udw = (env->CP0_PWField >> CP0PF_UDW) & 0x3F; |
| 725 | int pf_mdw = (env->CP0_PWField >> CP0PF_MDW) & 0x3F; |
| 726 | int pf_ptw = (env->CP0_PWField >> CP0PF_PTW) & 0x3F; |
| 727 | int pf_ptew = (env->CP0_PWField >> CP0PF_PTEW) & 0x3F; |
| 728 | |
| 729 | /* Indices computed from faulting address */ |
| 730 | int gindex = (address >> pf_gdw) & ((1 << gdw) - 1); |
| 731 | int uindex = (address >> pf_udw) & ((1 << udw) - 1); |
| 732 | int mindex = (address >> pf_mdw) & ((1 << mdw) - 1); |
| 733 | int ptindex = (address >> pf_ptw) & ((1 << ptw) - 1); |
| 734 | |
| 735 | /* Other HTW configs */ |
| 736 | int hugepg = (env->CP0_PWCtl >> CP0PC_HUGEPG) & 0x1; |
| 737 | MemOp directory_mop, leaf_mop; |
| 738 | |
| 739 | /* Offsets into tables */ |
| 740 | unsigned goffset, uoffset, moffset, ptoffset0, ptoffset1; |
| 741 | |
| 742 | /* Starting address - Page Table Base */ |
| 743 | uint64_t vaddr = env->CP0_PWBase; |
| 744 | |
| 745 | uint64_t dir_entry; |
| 746 | uint64_t paddr; |
| 747 | int prot; |
| 748 | int m; |
| 749 | |
| 750 | if (!(env->CP0_Config3 & (1 << CP0C3_PW))) { |
| 751 | /* walker is unimplemented */ |
| 752 | return false; |
| 753 | } |
| 754 | if (!(env->CP0_PWCtl & (1 << CP0PC_PWEN))) { |
| 755 | /* walker is disabled */ |
| 756 | return false; |
| 757 | } |
| 758 | if (!(gdw > 0 || udw > 0 || mdw > 0)) { |
| 759 | /* no structure to walk */ |
| 760 | return false; |
| 761 | } |
| 762 | if (ptew > 1) { |
| 763 | return false; |
| 764 | } |
| 765 | |
| 766 | /* HTW Shift values (depend on entry size) */ |
| 767 | directory_mop = (hugepg && (ptew == 1)) ? native_op + 1 : native_op; |
| 768 | leaf_mop = (ptew == 1) ? native_op + 1 : native_op; |
| 769 | |
| 770 | goffset = gindex << directory_mop; |
| 771 | uoffset = uindex << directory_mop; |
| 772 | moffset = mindex << directory_mop; |
| 773 | ptoffset0 = (ptindex >> 1) << (leaf_mop + 1); |
| 774 | ptoffset1 = ptoffset0 | (1 << (leaf_mop)); |
| 775 | |
| 776 | /* Global Directory */ |
| 777 | if (gdw > 0) { |
| 778 | vaddr |= goffset; |
| 779 | switch (walk_directory(env, &vaddr, pf_gdw, &huge_page, &hgpg_gdhit, |
| 780 | &pw_entrylo0, &pw_entrylo1, |
| 781 | directory_mop, leaf_mop, ptw_mmu_idx)) |
| 782 | { |
| 783 | case 0: |
| 784 | return false; |
| 785 | case 1: |
| 786 | goto refill; |
| 787 | case 2: |
| 788 | default: |
| 789 | break; |
| 790 | } |
| 791 | } |
| 792 | |
| 793 | /* Upper directory */ |
| 794 | if (udw > 0) { |
| 795 | vaddr |= uoffset; |
| 796 | switch (walk_directory(env, &vaddr, pf_udw, &huge_page, &hgpg_udhit, |
| 797 | &pw_entrylo0, &pw_entrylo1, |
| 798 | directory_mop, leaf_mop, ptw_mmu_idx)) |
| 799 | { |
| 800 | case 0: |
| 801 | return false; |
| 802 | case 1: |
| 803 | goto refill; |
| 804 | case 2: |
| 805 | default: |
| 806 | break; |
| 807 | } |
| 808 | } |
| 809 | |
| 810 | /* Middle directory */ |
| 811 | if (mdw > 0) { |
| 812 | vaddr |= moffset; |
| 813 | switch (walk_directory(env, &vaddr, pf_mdw, &huge_page, &hgpg_mdhit, |
| 814 | &pw_entrylo0, &pw_entrylo1, |
| 815 | directory_mop, leaf_mop, ptw_mmu_idx)) |
| 816 | { |
| 817 | case 0: |
| 818 | return false; |
| 819 | case 1: |
| 820 | goto refill; |
| 821 | case 2: |
| 822 | default: |
| 823 | break; |
| 824 | } |
| 825 | } |
| 826 | |
| 827 | /* Leaf Level Page Table - First half of PTE pair */ |
| 828 | vaddr |= ptoffset0; |
| 829 | if (get_physical_address(env, &paddr, &prot, vaddr, MMU_DATA_LOAD, |
| 830 | ptw_mmu_idx) != TLBRET_MATCH) { |
| 831 | return false; |
| 832 | } |
| 833 | if (!get_pte(env, vaddr, leaf_mop, &dir_entry, ptw_mmu_idx)) { |
| 834 | return false; |
| 835 | } |
| 836 | dir_entry = get_tlb_entry_layout(env, dir_entry, leaf_mop, pf_ptew); |
| 837 | pw_entrylo0 = dir_entry; |
| 838 | |
| 839 | /* Leaf Level Page Table - Second half of PTE pair */ |
| 840 | vaddr |= ptoffset1; |
| 841 | if (get_physical_address(env, &paddr, &prot, vaddr, MMU_DATA_LOAD, |
| 842 | ptw_mmu_idx) != TLBRET_MATCH) { |
| 843 | return false; |
| 844 | } |
| 845 | if (!get_pte(env, vaddr, leaf_mop, &dir_entry, ptw_mmu_idx)) { |
| 846 | return false; |
| 847 | } |
| 848 | dir_entry = get_tlb_entry_layout(env, dir_entry, leaf_mop, pf_ptew); |
| 849 | pw_entrylo1 = dir_entry; |
| 850 | |
| 851 | refill: |
| 852 | |
| 853 | m = (1 << pf_ptw) - 1; |
| 854 | |
| 855 | if (huge_page) { |
| 856 | switch (hgpg_bdhit << 3 | hgpg_gdhit << 2 | hgpg_udhit << 1 | |
| 857 | hgpg_mdhit) |
| 858 | { |
| 859 | case 4: |
| 860 | m = (1 << pf_gdw) - 1; |
| 861 | if (pf_gdw & 1) { |
| 862 | m >>= 1; |
| 863 | } |
| 864 | break; |
| 865 | case 2: |
| 866 | m = (1 << pf_udw) - 1; |
| 867 | if (pf_udw & 1) { |
| 868 | m >>= 1; |
| 869 | } |
| 870 | break; |
| 871 | case 1: |
| 872 | m = (1 << pf_mdw) - 1; |
| 873 | if (pf_mdw & 1) { |
| 874 | m >>= 1; |
| 875 | } |
| 876 | break; |
| 877 | } |
| 878 | } |
| 879 | pw_pagemask = m >> TARGET_PAGE_BITS; |
| 880 | pw_pagemask = compute_pagemask(pw_pagemask << CP0PM_MASK); |
| 881 | pw_entryhi = (address & ~0x1fff) | (env->CP0_EntryHi & 0xFF); |
| 882 | { |
| 883 | target_ulong tmp_entryhi = env->CP0_EntryHi; |
| 884 | int32_t tmp_pagemask = env->CP0_PageMask; |
| 885 | uint64_t tmp_entrylo0 = env->CP0_EntryLo0; |
| 886 | uint64_t tmp_entrylo1 = env->CP0_EntryLo1; |
| 887 | |
| 888 | env->CP0_EntryHi = pw_entryhi; |
| 889 | env->CP0_PageMask = pw_pagemask; |
| 890 | env->CP0_EntryLo0 = pw_entrylo0; |
| 891 | env->CP0_EntryLo1 = pw_entrylo1; |
| 892 | |
| 893 | /* |
| 894 | * The hardware page walker inserts a page into the TLB in a manner |
| 895 | * identical to a TLBWR instruction as executed by the software refill |
| 896 | * handler. |
| 897 | */ |
| 898 | r4k_helper_tlbwr(env); |
| 899 | |
| 900 | env->CP0_EntryHi = tmp_entryhi; |
| 901 | env->CP0_PageMask = tmp_pagemask; |
| 902 | env->CP0_EntryLo0 = tmp_entrylo0; |
| 903 | env->CP0_EntryLo1 = tmp_entrylo1; |
| 904 | } |
| 905 | return true; |
| 906 | } |
| 907 | #endif |
| 908 | |
| 909 | bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size, |
| 910 | MMUAccessType access_type, int mmu_idx, |
| 911 | bool probe, uintptr_t retaddr) |
| 912 | { |
| 913 | CPUMIPSState *env = cpu_env(cs); |
| 914 | hwaddr physical; |
| 915 | int prot; |
| 916 | int ret = TLBRET_BADADDR; |
| 917 | |
| 918 | /* data access */ |
| 919 | /* XXX: put correct access by using cpu_restore_state() correctly */ |
| 920 | ret = get_physical_address(env, &physical, &prot, address, |
| 921 | access_type, mmu_idx); |
| 922 | switch (ret) { |
| 923 | case TLBRET_MATCH: |
| 924 | qemu_log_mask(CPU_LOG_MMU, |
| 925 | "%s address=%" VADDR_PRIx " physical " HWADDR_FMT_plx |
| 926 | " prot %d\n", __func__, address, physical, prot); |
| 927 | break; |
| 928 | default: |
| 929 | qemu_log_mask(CPU_LOG_MMU, |
| 930 | "%s address=%" VADDR_PRIx " ret %d\n", __func__, address, |
| 931 | ret); |
| 932 | break; |
| 933 | } |
| 934 | if (ret == TLBRET_MATCH) { |
| 935 | tlb_set_page(cs, address & TARGET_PAGE_MASK, |
| 936 | physical & TARGET_PAGE_MASK, prot, |
| 937 | mmu_idx, TARGET_PAGE_SIZE); |
| 938 | return true; |
| 939 | } |
| 940 | #if !defined(TARGET_MIPS64) |
| 941 | if ((ret == TLBRET_NOMATCH) && (env->tlb->nb_tlb > 1)) { |
| 942 | /* |
| 943 | * Memory reads during hardware page table walking are performed |
| 944 | * as if they were kernel-mode load instructions. |
| 945 | */ |
| 946 | int ptw_mmu_idx = (env->hflags & MIPS_HFLAG_ERL ? |
| 947 | MMU_ERL_IDX : MMU_KERNEL_IDX); |
| 948 | |
| 949 | if (page_table_walk_refill(env, address, ptw_mmu_idx)) { |
| 950 | ret = get_physical_address(env, &physical, &prot, address, |
| 951 | access_type, mmu_idx); |
| 952 | if (ret == TLBRET_MATCH) { |
| 953 | tlb_set_page(cs, address & TARGET_PAGE_MASK, |
| 954 | physical & TARGET_PAGE_MASK, prot, |
| 955 | mmu_idx, TARGET_PAGE_SIZE); |
| 956 | return true; |
| 957 | } |
| 958 | } |
| 959 | } |
| 960 | #endif |
| 961 | if (probe) { |
| 962 | return false; |
| 963 | } |
| 964 | |
| 965 | raise_mmu_exception(env, address, access_type, ret); |
| 966 | do_raise_exception_err(env, cs->exception_index, env->error_code, retaddr); |
| 967 | } |
| 968 | |
| 969 | hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address, |
| 970 | MMUAccessType access_type, uintptr_t retaddr) |
| 971 | { |
| 972 | hwaddr physical; |
| 973 | int prot; |
| 974 | int ret = 0; |
| 975 | CPUState *cs = env_cpu(env); |
| 976 | |
| 977 | /* data access */ |
| 978 | ret = get_physical_address(env, &physical, &prot, address, access_type, |
| 979 | mips_env_mmu_index(env)); |
| 980 | if (ret == TLBRET_MATCH) { |
| 981 | return physical; |
| 982 | } |
| 983 | |
| 984 | raise_mmu_exception(env, address, access_type, ret); |
| 985 | cpu_loop_exit_restore(cs, retaddr); |
| 986 | } |
| 987 | |
| 988 | static void set_hflags_for_handler(CPUMIPSState *env) |
| 989 | { |
| 990 | /* Exception handlers are entered in 32-bit mode. */ |
| 991 | env->hflags &= ~(MIPS_HFLAG_M16); |
| 992 | /* ...except that microMIPS lets you choose. */ |
| 993 | if (env->insn_flags & ASE_MICROMIPS) { |
| 994 | env->hflags |= (!!(env->CP0_Config3 & |
| 995 | (1 << CP0C3_ISA_ON_EXC)) |
| 996 | << MIPS_HFLAG_M16_SHIFT); |
| 997 | } |
| 998 | } |
| 999 | |
| 1000 | static inline void set_badinstr_registers(CPUMIPSState *env) |
| 1001 | { |
| 1002 | CPUState *cs = env_cpu(env); |
| 1003 | MemOpIdx oi; |
| 1004 | |
| 1005 | if (env->insn_flags & ISA_NANOMIPS32) { |
| 1006 | if (env->CP0_Config3 & (1 << CP0C3_BI)) { |
| 1007 | uint32_t instr; |
| 1008 | |
| 1009 | oi = make_memop_idx(mo_endian_env(env) | MO_UW, cpu_mmu_index(cs, true)); |
| 1010 | instr = cpu_ldw_code_mmu(env, env->active_tc.PC, oi, 0) << 16; |
| 1011 | if ((instr & 0x10000000) == 0) { |
| 1012 | instr |= cpu_ldw_code_mmu(env, env->active_tc.PC + 2, oi, 0); |
| 1013 | } |
| 1014 | env->CP0_BadInstr = instr; |
| 1015 | |
| 1016 | if ((instr & 0xFC000000) == 0x60000000) { |
| 1017 | instr = cpu_ldw_code_mmu(env, env->active_tc.PC + 4, oi, 0) << 16; |
| 1018 | env->CP0_BadInstrX = instr; |
| 1019 | } |
| 1020 | } |
| 1021 | return; |
| 1022 | } |
| 1023 | |
| 1024 | if (env->hflags & MIPS_HFLAG_M16) { |
| 1025 | /* TODO: add BadInstr support for microMIPS */ |
| 1026 | return; |
| 1027 | } |
| 1028 | |
| 1029 | oi = make_memop_idx(mo_endian_env(env) | MO_UL, cpu_mmu_index(cs, true)); |
| 1030 | if (env->CP0_Config3 & (1 << CP0C3_BI)) { |
| 1031 | env->CP0_BadInstr = cpu_ldl_code_mmu(env, env->active_tc.PC, oi, 0); |
| 1032 | } |
| 1033 | if ((env->CP0_Config3 & (1 << CP0C3_BP)) && |
| 1034 | (env->hflags & MIPS_HFLAG_BMASK)) { |
| 1035 | env->CP0_BadInstrP = cpu_ldl_code_mmu(env, env->active_tc.PC - 4, oi, 0); |
| 1036 | } |
| 1037 | } |
| 1038 | |
| 1039 | void mips_cpu_do_interrupt(CPUState *cs) |
| 1040 | { |
| 1041 | MIPSCPU *cpu = MIPS_CPU(cs); |
| 1042 | CPUMIPSState *env = &cpu->env; |
| 1043 | bool update_badinstr = 0; |
| 1044 | target_ulong offset; |
| 1045 | int cause = -1; |
| 1046 | uint64_t last_pc = env->active_tc.PC; |
| 1047 | |
| 1048 | if (qemu_loglevel_mask(CPU_LOG_INT) |
| 1049 | && cs->exception_index != EXCP_EXT_INTERRUPT) { |
| 1050 | qemu_log("%s enter: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx |
| 1051 | " %s exception\n", |
| 1052 | __func__, env->active_tc.PC, env->CP0_EPC, |
| 1053 | mips_exception_name(cs->exception_index)); |
| 1054 | } |
| 1055 | if (cs->exception_index == EXCP_EXT_INTERRUPT && |
| 1056 | (env->hflags & MIPS_HFLAG_DM)) { |
| 1057 | cs->exception_index = EXCP_DINT; |
| 1058 | } |
| 1059 | offset = 0x180; |
| 1060 | switch (cs->exception_index) { |
| 1061 | case EXCP_SEMIHOST: |
| 1062 | cs->exception_index = EXCP_NONE; |
| 1063 | mips_semihosting(env); |
| 1064 | env->active_tc.PC += env->error_code; |
| 1065 | qemu_plugin_vcpu_hostcall_cb(cs, last_pc); |
| 1066 | return; |
| 1067 | case EXCP_DSS: |
| 1068 | env->CP0_Debug |= 1 << CP0DB_DSS; |
| 1069 | /* |
| 1070 | * Debug single step cannot be raised inside a delay slot and |
| 1071 | * resume will always occur on the next instruction |
| 1072 | * (but we assume the pc has always been updated during |
| 1073 | * code translation). |
| 1074 | */ |
| 1075 | env->CP0_DEPC = env->active_tc.PC | !!(env->hflags & MIPS_HFLAG_M16); |
| 1076 | goto enter_debug_mode; |
| 1077 | case EXCP_DINT: |
| 1078 | env->CP0_Debug |= 1 << CP0DB_DINT; |
| 1079 | goto set_DEPC; |
| 1080 | case EXCP_DIB: |
| 1081 | env->CP0_Debug |= 1 << CP0DB_DIB; |
| 1082 | goto set_DEPC; |
| 1083 | case EXCP_DBp: |
| 1084 | env->CP0_Debug |= 1 << CP0DB_DBp; |
| 1085 | /* Setup DExcCode - SDBBP instruction */ |
| 1086 | env->CP0_Debug = (env->CP0_Debug & ~(0x1fULL << CP0DB_DEC)) | |
| 1087 | (9 << CP0DB_DEC); |
| 1088 | goto set_DEPC; |
| 1089 | case EXCP_DDBS: |
| 1090 | env->CP0_Debug |= 1 << CP0DB_DDBS; |
| 1091 | goto set_DEPC; |
| 1092 | case EXCP_DDBL: |
| 1093 | env->CP0_Debug |= 1 << CP0DB_DDBL; |
| 1094 | set_DEPC: |
| 1095 | env->CP0_DEPC = exception_resume_pc(env); |
| 1096 | env->hflags &= ~MIPS_HFLAG_BMASK; |
| 1097 | enter_debug_mode: |
| 1098 | if (env->insn_flags & ISA_MIPS3) { |
| 1099 | env->hflags |= MIPS_HFLAG_64; |
| 1100 | if (!(env->insn_flags & ISA_MIPS_R6) || |
| 1101 | env->CP0_Status & (1 << CP0St_KX)) { |
| 1102 | env->hflags &= ~MIPS_HFLAG_AWRAP; |
| 1103 | } |
| 1104 | } |
| 1105 | env->hflags |= MIPS_HFLAG_DM | MIPS_HFLAG_CP0; |
| 1106 | env->hflags &= ~(MIPS_HFLAG_KSU); |
| 1107 | /* EJTAG probe trap enable is not implemented... */ |
| 1108 | if (!(env->CP0_Status & (1 << CP0St_EXL))) { |
| 1109 | env->CP0_Cause &= ~(1U << CP0Ca_BD); |
| 1110 | } |
| 1111 | env->active_tc.PC = env->exception_base + 0x480; |
| 1112 | set_hflags_for_handler(env); |
| 1113 | break; |
| 1114 | case EXCP_RESET: |
| 1115 | cpu_reset(CPU(cpu)); |
| 1116 | break; |
| 1117 | case EXCP_SRESET: |
| 1118 | env->CP0_Status |= (1 << CP0St_SR); |
| 1119 | memset(env->CP0_WatchLo, 0, sizeof(env->CP0_WatchLo)); |
| 1120 | goto set_error_EPC; |
| 1121 | case EXCP_NMI: |
| 1122 | env->CP0_Status |= (1 << CP0St_NMI); |
| 1123 | set_error_EPC: |
| 1124 | env->CP0_ErrorEPC = exception_resume_pc(env); |
| 1125 | env->hflags &= ~MIPS_HFLAG_BMASK; |
| 1126 | env->CP0_Status |= (1 << CP0St_ERL) | (1 << CP0St_BEV); |
| 1127 | if (env->insn_flags & ISA_MIPS3) { |
| 1128 | env->hflags |= MIPS_HFLAG_64; |
| 1129 | if (!(env->insn_flags & ISA_MIPS_R6) || |
| 1130 | env->CP0_Status & (1 << CP0St_KX)) { |
| 1131 | env->hflags &= ~MIPS_HFLAG_AWRAP; |
| 1132 | } |
| 1133 | } |
| 1134 | env->hflags |= MIPS_HFLAG_CP0; |
| 1135 | env->hflags &= ~(MIPS_HFLAG_KSU); |
| 1136 | if (!(env->CP0_Status & (1 << CP0St_EXL))) { |
| 1137 | env->CP0_Cause &= ~(1U << CP0Ca_BD); |
| 1138 | } |
| 1139 | env->active_tc.PC = env->exception_base; |
| 1140 | set_hflags_for_handler(env); |
| 1141 | break; |
| 1142 | case EXCP_EXT_INTERRUPT: |
| 1143 | cause = 0; |
| 1144 | if (env->CP0_Cause & (1 << CP0Ca_IV)) { |
| 1145 | uint32_t spacing = (env->CP0_IntCtl >> CP0IntCtl_VS) & 0x1f; |
| 1146 | |
| 1147 | if ((env->CP0_Status & (1 << CP0St_BEV)) || spacing == 0) { |
| 1148 | offset = 0x200; |
| 1149 | } else { |
| 1150 | uint32_t vector = 0; |
| 1151 | uint32_t pending = (env->CP0_Cause & CP0Ca_IP_mask) >> CP0Ca_IP; |
| 1152 | |
| 1153 | if (env->CP0_Config3 & (1 << CP0C3_VEIC)) { |
| 1154 | /* |
| 1155 | * For VEIC mode, the external interrupt controller feeds |
| 1156 | * the vector through the CP0Cause IP lines. |
| 1157 | */ |
| 1158 | vector = pending; |
| 1159 | } else { |
| 1160 | /* |
| 1161 | * Vectored Interrupts |
| 1162 | * Mask with Status.IM7-IM0 to get enabled interrupts. |
| 1163 | */ |
| 1164 | pending &= (env->CP0_Status >> CP0St_IM) & 0xff; |
| 1165 | /* Find the highest-priority interrupt. */ |
| 1166 | while (pending >>= 1) { |
| 1167 | vector++; |
| 1168 | } |
| 1169 | } |
| 1170 | offset = 0x200 + (vector * (spacing << 5)); |
| 1171 | } |
| 1172 | } |
| 1173 | goto set_EPC; |
| 1174 | case EXCP_LTLBL: |
| 1175 | cause = 1; |
| 1176 | update_badinstr = !(env->error_code & EXCP_INST_NOTAVAIL); |
| 1177 | goto set_EPC; |
| 1178 | case EXCP_TLBL: |
| 1179 | cause = 2; |
| 1180 | update_badinstr = !(env->error_code & EXCP_INST_NOTAVAIL); |
| 1181 | if ((env->error_code & EXCP_TLB_NOMATCH) && |
| 1182 | !(env->CP0_Status & (1 << CP0St_EXL))) { |
| 1183 | #if defined(TARGET_MIPS64) |
| 1184 | int R = env->CP0_BadVAddr >> 62; |
| 1185 | int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0; |
| 1186 | int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0; |
| 1187 | |
| 1188 | if ((R != 0 || UX) && (R != 3 || KX) && |
| 1189 | (!(env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F)))) { |
| 1190 | offset = 0x080; |
| 1191 | } else { |
| 1192 | #endif |
| 1193 | offset = 0x000; |
| 1194 | #if defined(TARGET_MIPS64) |
| 1195 | } |
| 1196 | #endif |
| 1197 | } |
| 1198 | goto set_EPC; |
| 1199 | case EXCP_TLBS: |
| 1200 | cause = 3; |
| 1201 | update_badinstr = 1; |
| 1202 | if ((env->error_code & EXCP_TLB_NOMATCH) && |
| 1203 | !(env->CP0_Status & (1 << CP0St_EXL))) { |
| 1204 | #if defined(TARGET_MIPS64) |
| 1205 | int R = env->CP0_BadVAddr >> 62; |
| 1206 | int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0; |
| 1207 | int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0; |
| 1208 | |
| 1209 | if ((R != 0 || UX) && (R != 3 || KX) && |
| 1210 | (!(env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F)))) { |
| 1211 | offset = 0x080; |
| 1212 | } else { |
| 1213 | #endif |
| 1214 | offset = 0x000; |
| 1215 | #if defined(TARGET_MIPS64) |
| 1216 | } |
| 1217 | #endif |
| 1218 | } |
| 1219 | goto set_EPC; |
| 1220 | case EXCP_AdEL: |
| 1221 | cause = 4; |
| 1222 | update_badinstr = !(env->error_code & EXCP_INST_NOTAVAIL); |
| 1223 | goto set_EPC; |
| 1224 | case EXCP_AdES: |
| 1225 | cause = 5; |
| 1226 | update_badinstr = 1; |
| 1227 | goto set_EPC; |
| 1228 | case EXCP_IBE: |
| 1229 | cause = 6; |
| 1230 | goto set_EPC; |
| 1231 | case EXCP_DBE: |
| 1232 | cause = 7; |
| 1233 | goto set_EPC; |
| 1234 | case EXCP_SYSCALL: |
| 1235 | cause = 8; |
| 1236 | update_badinstr = 1; |
| 1237 | goto set_EPC; |
| 1238 | case EXCP_BREAK: |
| 1239 | cause = 9; |
| 1240 | update_badinstr = 1; |
| 1241 | goto set_EPC; |
| 1242 | case EXCP_RI: |
| 1243 | cause = 10; |
| 1244 | update_badinstr = 1; |
| 1245 | goto set_EPC; |
| 1246 | case EXCP_CpU: |
| 1247 | cause = 11; |
| 1248 | update_badinstr = 1; |
| 1249 | env->CP0_Cause = (env->CP0_Cause & ~(0x3 << CP0Ca_CE)) | |
| 1250 | (env->error_code << CP0Ca_CE); |
| 1251 | goto set_EPC; |
| 1252 | case EXCP_OVERFLOW: |
| 1253 | cause = 12; |
| 1254 | update_badinstr = 1; |
| 1255 | goto set_EPC; |
| 1256 | case EXCP_TRAP: |
| 1257 | cause = 13; |
| 1258 | update_badinstr = 1; |
| 1259 | goto set_EPC; |
| 1260 | case EXCP_MSAFPE: |
| 1261 | cause = 14; |
| 1262 | update_badinstr = 1; |
| 1263 | goto set_EPC; |
| 1264 | case EXCP_FPE: |
| 1265 | cause = 15; |
| 1266 | update_badinstr = 1; |
| 1267 | goto set_EPC; |
| 1268 | case EXCP_C2E: |
| 1269 | cause = 18; |
| 1270 | goto set_EPC; |
| 1271 | case EXCP_TLBRI: |
| 1272 | cause = 19; |
| 1273 | update_badinstr = 1; |
| 1274 | goto set_EPC; |
| 1275 | case EXCP_TLBXI: |
| 1276 | cause = 20; |
| 1277 | goto set_EPC; |
| 1278 | case EXCP_MSADIS: |
| 1279 | cause = 21; |
| 1280 | update_badinstr = 1; |
| 1281 | goto set_EPC; |
| 1282 | case EXCP_MDMX: |
| 1283 | cause = 22; |
| 1284 | goto set_EPC; |
| 1285 | case EXCP_DWATCH: |
| 1286 | cause = 23; |
| 1287 | /* XXX: TODO: manage deferred watch exceptions */ |
| 1288 | goto set_EPC; |
| 1289 | case EXCP_MCHECK: |
| 1290 | cause = 24; |
| 1291 | goto set_EPC; |
| 1292 | case EXCP_THREAD: |
| 1293 | cause = 25; |
| 1294 | goto set_EPC; |
| 1295 | case EXCP_DSPDIS: |
| 1296 | cause = 26; |
| 1297 | goto set_EPC; |
| 1298 | case EXCP_CACHE: |
| 1299 | cause = 30; |
| 1300 | offset = 0x100; |
| 1301 | set_EPC: |
| 1302 | if (!(env->CP0_Status & (1 << CP0St_EXL))) { |
| 1303 | env->CP0_EPC = exception_resume_pc(env); |
| 1304 | if (update_badinstr) { |
| 1305 | set_badinstr_registers(env); |
| 1306 | } |
| 1307 | if (env->hflags & MIPS_HFLAG_BMASK) { |
| 1308 | env->CP0_Cause |= (1U << CP0Ca_BD); |
| 1309 | } else { |
| 1310 | env->CP0_Cause &= ~(1U << CP0Ca_BD); |
| 1311 | } |
| 1312 | env->CP0_Status |= (1 << CP0St_EXL); |
| 1313 | if (env->insn_flags & ISA_MIPS3) { |
| 1314 | env->hflags |= MIPS_HFLAG_64; |
| 1315 | if (!(env->insn_flags & ISA_MIPS_R6) || |
| 1316 | env->CP0_Status & (1 << CP0St_KX)) { |
| 1317 | env->hflags &= ~MIPS_HFLAG_AWRAP; |
| 1318 | } |
| 1319 | } |
| 1320 | env->hflags |= MIPS_HFLAG_CP0; |
| 1321 | env->hflags &= ~(MIPS_HFLAG_KSU); |
| 1322 | } |
| 1323 | env->hflags &= ~MIPS_HFLAG_BMASK; |
| 1324 | if (env->CP0_Status & (1 << CP0St_BEV)) { |
| 1325 | env->active_tc.PC = env->exception_base + 0x200; |
| 1326 | } else if (cause == 30 && !(env->CP0_Config3 & (1 << CP0C3_SC) && |
| 1327 | env->CP0_Config5 & (1 << CP0C5_CV))) { |
| 1328 | /* Force KSeg1 for cache errors */ |
| 1329 | env->active_tc.PC = KSEG1_BASE | (env->CP0_EBase & 0x1FFFF000); |
| 1330 | } else { |
| 1331 | env->active_tc.PC = env->CP0_EBase & ~0xfff; |
| 1332 | } |
| 1333 | |
| 1334 | env->active_tc.PC += offset; |
| 1335 | set_hflags_for_handler(env); |
| 1336 | env->CP0_Cause = (env->CP0_Cause & ~(0x1f << CP0Ca_EC)) | |
| 1337 | (cause << CP0Ca_EC); |
| 1338 | break; |
| 1339 | default: |
| 1340 | abort(); |
| 1341 | } |
| 1342 | if (qemu_loglevel_mask(CPU_LOG_INT) |
| 1343 | && cs->exception_index != EXCP_EXT_INTERRUPT) { |
| 1344 | qemu_log("%s: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " cause %d\n" |
| 1345 | " S %08x C %08x A " TARGET_FMT_lx " D " TARGET_FMT_lx "\n", |
| 1346 | __func__, env->active_tc.PC, env->CP0_EPC, cause, |
| 1347 | env->CP0_Status, env->CP0_Cause, env->CP0_BadVAddr, |
| 1348 | env->CP0_DEPC); |
| 1349 | } |
| 1350 | switch (cs->exception_index) { |
| 1351 | case EXCP_NMI: |
| 1352 | case EXCP_EXT_INTERRUPT: |
| 1353 | qemu_plugin_vcpu_interrupt_cb(cs, last_pc); |
| 1354 | break; |
| 1355 | default: |
| 1356 | qemu_plugin_vcpu_exception_cb(cs, last_pc); |
| 1357 | } |
| 1358 | cs->exception_index = EXCP_NONE; |
| 1359 | } |
| 1360 | |
| 1361 | bool mips_cpu_exec_interrupt(CPUState *cs, int interrupt_request) |
| 1362 | { |
| 1363 | if (interrupt_request & CPU_INTERRUPT_HARD) { |
| 1364 | CPUMIPSState *env = cpu_env(cs); |
| 1365 | |
| 1366 | if (cpu_mips_hw_interrupts_enabled(env) && |
| 1367 | cpu_mips_hw_interrupts_pending(env)) { |
| 1368 | /* Raise it */ |
| 1369 | cs->exception_index = EXCP_EXT_INTERRUPT; |
| 1370 | env->error_code = 0; |
| 1371 | mips_cpu_do_interrupt(cs); |
| 1372 | return true; |
| 1373 | } |
| 1374 | } |
| 1375 | return false; |
| 1376 | } |
| 1377 | |
| 1378 | void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra) |
| 1379 | { |
| 1380 | CPUState *cs = env_cpu(env); |
| 1381 | r4k_tlb_t *tlb; |
| 1382 | target_ulong addr; |
| 1383 | target_ulong end; |
| 1384 | uint16_t ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; |
| 1385 | uint32_t MMID = env->CP0_MemoryMapID; |
| 1386 | bool mi = !!((env->CP0_Config5 >> CP0C5_MI) & 1); |
| 1387 | uint32_t tlb_mmid; |
| 1388 | target_ulong mask; |
| 1389 | |
| 1390 | MMID = mi ? MMID : (uint32_t) ASID; |
| 1391 | |
| 1392 | tlb = &env->tlb->mmu.r4k.tlb[idx]; |
| 1393 | /* |
| 1394 | * The qemu TLB is flushed when the ASID/MMID changes, so no need to |
| 1395 | * flush these entries again. |
| 1396 | */ |
| 1397 | tlb_mmid = mi ? tlb->MMID : (uint32_t) tlb->ASID; |
| 1398 | if (tlb->G == 0 && tlb_mmid != MMID) { |
| 1399 | return; |
| 1400 | } |
| 1401 | |
| 1402 | if (use_extra && env->tlb->tlb_in_use < MIPS_TLB_MAX) { |
| 1403 | /* |
| 1404 | * For tlbwr, we can shadow the discarded entry into |
| 1405 | * a new (fake) TLB entry, as long as the guest can not |
| 1406 | * tell that it's there. |
| 1407 | */ |
| 1408 | env->tlb->mmu.r4k.tlb[env->tlb->tlb_in_use] = *tlb; |
| 1409 | env->tlb->tlb_in_use++; |
| 1410 | return; |
| 1411 | } |
| 1412 | |
| 1413 | /* 1k pages are not supported. */ |
| 1414 | mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1); |
| 1415 | if (tlb->V0) { |
| 1416 | addr = tlb->VPN & ~mask; |
| 1417 | #if defined(TARGET_MIPS64) |
| 1418 | if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) { |
| 1419 | addr |= 0x3FFFFF0000000000ULL; |
| 1420 | } |
| 1421 | #endif |
| 1422 | end = addr | (mask >> 1); |
| 1423 | while (addr < end) { |
| 1424 | tlb_flush_page(cs, addr); |
| 1425 | addr += TARGET_PAGE_SIZE; |
| 1426 | } |
| 1427 | } |
| 1428 | if (tlb->V1) { |
| 1429 | addr = (tlb->VPN & ~mask) | ((mask >> 1) + 1); |
| 1430 | #if defined(TARGET_MIPS64) |
| 1431 | if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) { |
| 1432 | addr |= 0x3FFFFF0000000000ULL; |
| 1433 | } |
| 1434 | #endif |
| 1435 | end = addr | mask; |
| 1436 | while (addr - 1 < end) { |
| 1437 | tlb_flush_page(cs, addr); |
| 1438 | addr += TARGET_PAGE_SIZE; |
| 1439 | } |
| 1440 | } |
| 1441 | } |