| 1 | /* |
| 2 | * QEMU OpenRISC CPU |
| 3 | * |
| 4 | * Copyright (c) 2012 Jia Liu <proljc@gmail.com> |
| 5 | * |
| 6 | * This library is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU Lesser General Public |
| 8 | * License as published by the Free Software Foundation; either |
| 9 | * version 2.1 of the License, or (at your option) any later version. |
| 10 | * |
| 11 | * This library is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 14 | * Lesser General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU Lesser General Public |
| 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
| 18 | */ |
| 19 | |
| 20 | #include "qemu/osdep.h" |
| 21 | #include "qapi/error.h" |
| 22 | #include "qemu/qemu-print.h" |
| 23 | #include "cpu.h" |
| 24 | #include "exec/translation-block.h" |
| 25 | #include "fpu/softfloat-helpers.h" |
| 26 | #include "accel/tcg/cpu-ops.h" |
| 27 | #include "tcg/tcg.h" |
| 28 | |
| 29 | static void openrisc_cpu_set_pc(CPUState *cs, vaddr value) |
| 30 | { |
| 31 | OpenRISCCPU *cpu = OPENRISC_CPU(cs); |
| 32 | |
| 33 | cpu->env.pc = value; |
| 34 | cpu->env.dflag = 0; |
| 35 | } |
| 36 | |
| 37 | static vaddr openrisc_cpu_get_pc(CPUState *cs) |
| 38 | { |
| 39 | OpenRISCCPU *cpu = OPENRISC_CPU(cs); |
| 40 | |
| 41 | return cpu->env.pc; |
| 42 | } |
| 43 | |
| 44 | static TCGTBCPUState openrisc_get_tb_cpu_state(CPUState *cs) |
| 45 | { |
| 46 | CPUOpenRISCState *env = cpu_env(cs); |
| 47 | |
| 48 | return (TCGTBCPUState){ |
| 49 | .pc = env->pc, |
| 50 | .flags = ((env->dflag ? TB_FLAGS_DFLAG : 0) |
| 51 | | (cpu_get_gpr(env, 0) ? 0 : TB_FLAGS_R0_0) |
| 52 | | (env->sr & (SR_SM | SR_DME | SR_IME | SR_OVE))), |
| 53 | }; |
| 54 | } |
| 55 | |
| 56 | static void openrisc_cpu_synchronize_from_tb(CPUState *cs, |
| 57 | const TranslationBlock *tb) |
| 58 | { |
| 59 | OpenRISCCPU *cpu = OPENRISC_CPU(cs); |
| 60 | |
| 61 | tcg_debug_assert(!tcg_cflags_has(cs, CF_PCREL)); |
| 62 | cpu->env.pc = tb->pc; |
| 63 | } |
| 64 | |
| 65 | static void openrisc_restore_state_to_opc(CPUState *cs, |
| 66 | const TranslationBlock *tb, |
| 67 | const uint64_t *data) |
| 68 | { |
| 69 | OpenRISCCPU *cpu = OPENRISC_CPU(cs); |
| 70 | |
| 71 | cpu->env.pc = data[0]; |
| 72 | cpu->env.dflag = data[1] & 1; |
| 73 | if (data[1] & 2) { |
| 74 | cpu->env.ppc = cpu->env.pc - 4; |
| 75 | } |
| 76 | } |
| 77 | |
| 78 | #ifndef CONFIG_USER_ONLY |
| 79 | static bool openrisc_cpu_has_work(CPUState *cs) |
| 80 | { |
| 81 | return cpu_test_interrupt(cs, CPU_INTERRUPT_HARD | CPU_INTERRUPT_TIMER); |
| 82 | } |
| 83 | #endif /* !CONFIG_USER_ONLY */ |
| 84 | |
| 85 | static int openrisc_cpu_mmu_index(CPUState *cs, bool ifetch) |
| 86 | { |
| 87 | CPUOpenRISCState *env = cpu_env(cs); |
| 88 | |
| 89 | if (env->sr & (ifetch ? SR_IME : SR_DME)) { |
| 90 | /* The mmu is enabled; test supervisor state. */ |
| 91 | return env->sr & SR_SM ? MMU_SUPERVISOR_IDX : MMU_USER_IDX; |
| 92 | } |
| 93 | |
| 94 | return MMU_NOMMU_IDX; /* mmu is disabled */ |
| 95 | } |
| 96 | |
| 97 | static void openrisc_disas_set_info(const CPUState *cpu, disassemble_info *info) |
| 98 | { |
| 99 | info->endian = BFD_ENDIAN_BIG; |
| 100 | info->print_insn = print_insn_or1k; |
| 101 | } |
| 102 | |
| 103 | static void openrisc_cpu_reset_hold(Object *obj, ResetType type) |
| 104 | { |
| 105 | CPUState *cs = CPU(obj); |
| 106 | OpenRISCCPU *cpu = OPENRISC_CPU(cs); |
| 107 | OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(obj); |
| 108 | |
| 109 | if (occ->parent_phases.hold) { |
| 110 | occ->parent_phases.hold(obj, type); |
| 111 | } |
| 112 | |
| 113 | memset(&cpu->env, 0, offsetof(CPUOpenRISCState, end_reset_fields)); |
| 114 | |
| 115 | cpu->env.pc = 0x100; |
| 116 | cpu->env.sr = SR_FO | SR_SM; |
| 117 | cpu->env.lock_addr = -1; |
| 118 | cs->exception_index = -1; |
| 119 | cpu_set_fpcsr(&cpu->env, 0); |
| 120 | |
| 121 | set_float_detect_tininess(float_tininess_before_rounding, |
| 122 | &cpu->env.fp_status); |
| 123 | /* |
| 124 | * TODO: this is probably not the correct NaN propagation rule for |
| 125 | * this architecture. |
| 126 | */ |
| 127 | set_float_2nan_prop_rule(float_2nan_prop_x87, &cpu->env.fp_status); |
| 128 | |
| 129 | /* Default NaN: sign bit clear, frac msb set */ |
| 130 | set_float_default_nan_pattern(0b01000000, &cpu->env.fp_status); |
| 131 | |
| 132 | #ifndef CONFIG_USER_ONLY |
| 133 | cpu->env.picmr = 0x00000000; |
| 134 | cpu->env.picsr = 0x00000000; |
| 135 | |
| 136 | cpu->env.ttmr = 0x00000000; |
| 137 | #endif |
| 138 | } |
| 139 | |
| 140 | #ifndef CONFIG_USER_ONLY |
| 141 | static void openrisc_cpu_set_irq(void *opaque, int irq, int level) |
| 142 | { |
| 143 | OpenRISCCPU *cpu = (OpenRISCCPU *)opaque; |
| 144 | CPUState *cs = CPU(cpu); |
| 145 | uint32_t irq_bit; |
| 146 | |
| 147 | if (irq > 31 || irq < 0) { |
| 148 | return; |
| 149 | } |
| 150 | |
| 151 | irq_bit = 1U << irq; |
| 152 | |
| 153 | if (level) { |
| 154 | cpu->env.picsr |= irq_bit; |
| 155 | } else { |
| 156 | cpu->env.picsr &= ~irq_bit; |
| 157 | } |
| 158 | |
| 159 | if (cpu->env.picsr & cpu->env.picmr) { |
| 160 | cpu_interrupt(cs, CPU_INTERRUPT_HARD); |
| 161 | } else { |
| 162 | cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); |
| 163 | } |
| 164 | } |
| 165 | #endif |
| 166 | |
| 167 | static void openrisc_cpu_realizefn(DeviceState *dev, Error **errp) |
| 168 | { |
| 169 | CPUState *cs = CPU(dev); |
| 170 | OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(dev); |
| 171 | Error *local_err = NULL; |
| 172 | |
| 173 | cpu_common_realize(cs, &local_err); |
| 174 | if (local_err != NULL) { |
| 175 | error_propagate(errp, local_err); |
| 176 | return; |
| 177 | } |
| 178 | |
| 179 | qemu_init_vcpu(cs); |
| 180 | cpu_reset(cs); |
| 181 | |
| 182 | #ifndef CONFIG_USER_ONLY |
| 183 | cpu_openrisc_clock_init(OPENRISC_CPU(dev)); |
| 184 | #endif |
| 185 | |
| 186 | occ->parent_realize(dev, errp); |
| 187 | } |
| 188 | |
| 189 | static void openrisc_cpu_initfn(Object *obj) |
| 190 | { |
| 191 | #ifndef CONFIG_USER_ONLY |
| 192 | qdev_init_gpio_in_named(DEVICE(obj), openrisc_cpu_set_irq, "IRQ", NR_IRQS); |
| 193 | #endif |
| 194 | } |
| 195 | |
| 196 | /* CPU models */ |
| 197 | |
| 198 | static ObjectClass *openrisc_cpu_class_by_name(const char *cpu_model) |
| 199 | { |
| 200 | ObjectClass *oc; |
| 201 | char *typename; |
| 202 | |
| 203 | typename = g_strdup_printf(OPENRISC_CPU_TYPE_NAME("%s"), cpu_model); |
| 204 | oc = object_class_by_name(typename); |
| 205 | g_free(typename); |
| 206 | |
| 207 | return oc; |
| 208 | } |
| 209 | |
| 210 | static void or1200_initfn(Object *obj) |
| 211 | { |
| 212 | OpenRISCCPU *cpu = OPENRISC_CPU(obj); |
| 213 | |
| 214 | cpu->env.vr = 0x13000008; |
| 215 | cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP | UPR_PMP; |
| 216 | cpu->env.cpucfgr = CPUCFGR_NSGF | CPUCFGR_OB32S | CPUCFGR_OF32S | |
| 217 | CPUCFGR_EVBARP; |
| 218 | |
| 219 | /* 1Way, TLB_SIZE entries. */ |
| 220 | cpu->env.dmmucfgr = (DMMUCFGR_NTW & (0 << 2)) |
| 221 | | (DMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2)); |
| 222 | cpu->env.immucfgr = (IMMUCFGR_NTW & (0 << 2)) |
| 223 | | (IMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2)); |
| 224 | } |
| 225 | |
| 226 | static void openrisc_any_initfn(Object *obj) |
| 227 | { |
| 228 | OpenRISCCPU *cpu = OPENRISC_CPU(obj); |
| 229 | |
| 230 | cpu->env.vr = 0x13000040; /* Obsolete VER + UVRP for new SPRs */ |
| 231 | cpu->env.vr2 = 0; /* No version specific id */ |
| 232 | cpu->env.avr = 0x01030000; /* Architecture v1.3 */ |
| 233 | |
| 234 | cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP | UPR_PMP; |
| 235 | cpu->env.cpucfgr = CPUCFGR_NSGF | CPUCFGR_OB32S | CPUCFGR_OF32S | |
| 236 | CPUCFGR_AVRP | CPUCFGR_EVBARP | CPUCFGR_OF64A32S; |
| 237 | |
| 238 | /* 1Way, TLB_SIZE entries. */ |
| 239 | cpu->env.dmmucfgr = (DMMUCFGR_NTW & (0 << 2)) |
| 240 | | (DMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2)); |
| 241 | cpu->env.immucfgr = (IMMUCFGR_NTW & (0 << 2)) |
| 242 | | (IMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2)); |
| 243 | } |
| 244 | |
| 245 | #ifndef CONFIG_USER_ONLY |
| 246 | #include "hw/core/sysemu-cpu-ops.h" |
| 247 | |
| 248 | static const struct SysemuCPUOps openrisc_sysemu_ops = { |
| 249 | .has_work = openrisc_cpu_has_work, |
| 250 | .get_phys_addr_debug = openrisc_cpu_get_phys_addr_debug, |
| 251 | }; |
| 252 | #endif |
| 253 | |
| 254 | static const TCGCPUOps openrisc_tcg_ops = { |
| 255 | .guest_default_memory_order = 0, |
| 256 | .mttcg_supported = true, |
| 257 | |
| 258 | .initialize = openrisc_translate_init, |
| 259 | .translate_code = openrisc_translate_code, |
| 260 | .get_tb_cpu_state = openrisc_get_tb_cpu_state, |
| 261 | .synchronize_from_tb = openrisc_cpu_synchronize_from_tb, |
| 262 | .restore_state_to_opc = openrisc_restore_state_to_opc, |
| 263 | .mmu_index = openrisc_cpu_mmu_index, |
| 264 | |
| 265 | #ifndef CONFIG_USER_ONLY |
| 266 | .tlb_fill = openrisc_cpu_tlb_fill, |
| 267 | .pointer_wrap = cpu_pointer_wrap_uint32, |
| 268 | .cpu_exec_interrupt = openrisc_cpu_exec_interrupt, |
| 269 | .cpu_exec_halt = openrisc_cpu_has_work, |
| 270 | .cpu_exec_reset = cpu_reset, |
| 271 | .do_interrupt = openrisc_cpu_do_interrupt, |
| 272 | #endif /* !CONFIG_USER_ONLY */ |
| 273 | }; |
| 274 | |
| 275 | static void openrisc_cpu_class_init(ObjectClass *oc, const void *data) |
| 276 | { |
| 277 | OpenRISCCPUClass *occ = OPENRISC_CPU_CLASS(oc); |
| 278 | CPUClass *cc = CPU_CLASS(occ); |
| 279 | DeviceClass *dc = DEVICE_CLASS(oc); |
| 280 | ResettableClass *rc = RESETTABLE_CLASS(oc); |
| 281 | |
| 282 | device_class_set_parent_realize(dc, openrisc_cpu_realizefn, |
| 283 | &occ->parent_realize); |
| 284 | resettable_class_set_parent_phases(rc, NULL, openrisc_cpu_reset_hold, NULL, |
| 285 | &occ->parent_phases); |
| 286 | |
| 287 | cc->class_by_name = openrisc_cpu_class_by_name; |
| 288 | cc->dump_state = openrisc_cpu_dump_state; |
| 289 | cc->set_pc = openrisc_cpu_set_pc; |
| 290 | cc->get_pc = openrisc_cpu_get_pc; |
| 291 | cc->gdb_core_xml_file = "or1k-core.xml"; |
| 292 | cc->gdb_read_register = openrisc_cpu_gdb_read_register; |
| 293 | cc->gdb_write_register = openrisc_cpu_gdb_write_register; |
| 294 | #ifndef CONFIG_USER_ONLY |
| 295 | dc->vmsd = &vmstate_openrisc_cpu; |
| 296 | cc->sysemu_ops = &openrisc_sysemu_ops; |
| 297 | #endif |
| 298 | cc->disas_set_info = openrisc_disas_set_info; |
| 299 | cc->tcg_ops = &openrisc_tcg_ops; |
| 300 | } |
| 301 | |
| 302 | #define DEFINE_OPENRISC_CPU_TYPE(cpu_model, initfn) \ |
| 303 | { \ |
| 304 | .parent = TYPE_OPENRISC_CPU, \ |
| 305 | .instance_init = initfn, \ |
| 306 | .name = OPENRISC_CPU_TYPE_NAME(cpu_model), \ |
| 307 | } |
| 308 | |
| 309 | static const TypeInfo openrisc_cpus_type_infos[] = { |
| 310 | { /* base class should be registered first */ |
| 311 | .name = TYPE_OPENRISC_CPU, |
| 312 | .parent = TYPE_CPU, |
| 313 | .instance_size = sizeof(OpenRISCCPU), |
| 314 | .instance_align = __alignof(OpenRISCCPU), |
| 315 | .instance_init = openrisc_cpu_initfn, |
| 316 | .abstract = true, |
| 317 | .class_size = sizeof(OpenRISCCPUClass), |
| 318 | .class_init = openrisc_cpu_class_init, |
| 319 | }, |
| 320 | DEFINE_OPENRISC_CPU_TYPE("or1200", or1200_initfn), |
| 321 | DEFINE_OPENRISC_CPU_TYPE("any", openrisc_any_initfn), |
| 322 | }; |
| 323 | |
| 324 | DEFINE_TYPES(openrisc_cpus_type_infos) |