| 1 | /* |
| 2 | * OpenRISC virtual CPU header. |
| 3 | * |
| 4 | * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com> |
| 5 | * |
| 6 | * This library is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU Lesser General Public |
| 8 | * License as published by the Free Software Foundation; either |
| 9 | * version 2.1 of the License, or (at your option) any later version. |
| 10 | * |
| 11 | * This library is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 14 | * Lesser General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU Lesser General Public |
| 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
| 18 | */ |
| 19 | |
| 20 | #ifndef OPENRISC_CPU_H |
| 21 | #define OPENRISC_CPU_H |
| 22 | |
| 23 | #include "cpu-qom.h" |
| 24 | #include "exec/cpu-common.h" |
| 25 | #include "exec/cpu-interrupt.h" |
| 26 | #include "fpu/softfloat-types.h" |
| 27 | |
| 28 | /** |
| 29 | * OpenRISCCPUClass: |
| 30 | * @parent_realize: The parent class' realize handler. |
| 31 | * @parent_phases: The parent class' reset phase handlers. |
| 32 | * |
| 33 | * A OpenRISC CPU model. |
| 34 | */ |
| 35 | struct OpenRISCCPUClass { |
| 36 | CPUClass parent_class; |
| 37 | |
| 38 | DeviceRealize parent_realize; |
| 39 | ResettablePhases parent_phases; |
| 40 | }; |
| 41 | |
| 42 | enum { |
| 43 | MMU_NOMMU_IDX = 0, |
| 44 | MMU_SUPERVISOR_IDX = 1, |
| 45 | MMU_USER_IDX = 2, |
| 46 | }; |
| 47 | |
| 48 | #define SET_FP_CAUSE(reg, v) do {\ |
| 49 | (reg) = ((reg) & ~(0x3f << 12)) | \ |
| 50 | ((v & 0x3f) << 12);\ |
| 51 | } while (0) |
| 52 | #define GET_FP_ENABLE(reg) (((reg) >> 7) & 0x1f) |
| 53 | #define UPDATE_FP_FLAGS(reg, v) do {\ |
| 54 | (reg) |= ((v & 0x1f) << 2);\ |
| 55 | } while (0) |
| 56 | |
| 57 | /* Interrupt */ |
| 58 | #define NR_IRQS 32 |
| 59 | |
| 60 | /* Unit presece register */ |
| 61 | enum { |
| 62 | UPR_UP = (1 << 0), |
| 63 | UPR_DCP = (1 << 1), |
| 64 | UPR_ICP = (1 << 2), |
| 65 | UPR_DMP = (1 << 3), |
| 66 | UPR_IMP = (1 << 4), |
| 67 | UPR_MP = (1 << 5), |
| 68 | UPR_DUP = (1 << 6), |
| 69 | UPR_PCUR = (1 << 7), |
| 70 | UPR_PMP = (1 << 8), |
| 71 | UPR_PICP = (1 << 9), |
| 72 | UPR_TTP = (1 << 10), |
| 73 | UPR_CUP = (255 << 24), |
| 74 | }; |
| 75 | |
| 76 | /* CPU configure register */ |
| 77 | enum { |
| 78 | CPUCFGR_NSGF = (15 << 0), |
| 79 | CPUCFGR_CGF = (1 << 4), |
| 80 | CPUCFGR_OB32S = (1 << 5), |
| 81 | CPUCFGR_OB64S = (1 << 6), |
| 82 | CPUCFGR_OF32S = (1 << 7), |
| 83 | CPUCFGR_OF64S = (1 << 8), |
| 84 | CPUCFGR_OV64S = (1 << 9), |
| 85 | CPUCFGR_ND = (1 << 10), |
| 86 | CPUCFGR_AVRP = (1 << 11), |
| 87 | CPUCFGR_EVBARP = (1 << 12), |
| 88 | CPUCFGR_ISRP = (1 << 13), |
| 89 | CPUCFGR_AECSRP = (1 << 14), |
| 90 | CPUCFGR_OF64A32S = (1 << 15), |
| 91 | }; |
| 92 | |
| 93 | /* DMMU configure register */ |
| 94 | enum { |
| 95 | DMMUCFGR_NTW = (3 << 0), |
| 96 | DMMUCFGR_NTS = (7 << 2), |
| 97 | DMMUCFGR_NAE = (7 << 5), |
| 98 | DMMUCFGR_CRI = (1 << 8), |
| 99 | DMMUCFGR_PRI = (1 << 9), |
| 100 | DMMUCFGR_TEIRI = (1 << 10), |
| 101 | DMMUCFGR_HTR = (1 << 11), |
| 102 | }; |
| 103 | |
| 104 | /* IMMU configure register */ |
| 105 | enum { |
| 106 | IMMUCFGR_NTW = (3 << 0), |
| 107 | IMMUCFGR_NTS = (7 << 2), |
| 108 | IMMUCFGR_NAE = (7 << 5), |
| 109 | IMMUCFGR_CRI = (1 << 8), |
| 110 | IMMUCFGR_PRI = (1 << 9), |
| 111 | IMMUCFGR_TEIRI = (1 << 10), |
| 112 | IMMUCFGR_HTR = (1 << 11), |
| 113 | }; |
| 114 | |
| 115 | /* Power management register */ |
| 116 | enum { |
| 117 | PMR_SDF = (15 << 0), |
| 118 | PMR_DME = (1 << 4), |
| 119 | PMR_SME = (1 << 5), |
| 120 | PMR_DCGE = (1 << 6), |
| 121 | PMR_SUME = (1 << 7), |
| 122 | }; |
| 123 | |
| 124 | /* Float point control status register */ |
| 125 | enum { |
| 126 | FPCSR_FPEE = 1, |
| 127 | FPCSR_RM = (3 << 1), |
| 128 | FPCSR_OVF = (1 << 3), |
| 129 | FPCSR_UNF = (1 << 4), |
| 130 | FPCSR_SNF = (1 << 5), |
| 131 | FPCSR_QNF = (1 << 6), |
| 132 | FPCSR_ZF = (1 << 7), |
| 133 | FPCSR_IXF = (1 << 8), |
| 134 | FPCSR_IVF = (1 << 9), |
| 135 | FPCSR_INF = (1 << 10), |
| 136 | FPCSR_DZF = (1 << 11), |
| 137 | }; |
| 138 | |
| 139 | /* Exceptions indices */ |
| 140 | enum { |
| 141 | EXCP_RESET = 0x1, |
| 142 | EXCP_BUSERR = 0x2, |
| 143 | EXCP_DPF = 0x3, |
| 144 | EXCP_IPF = 0x4, |
| 145 | EXCP_TICK = 0x5, |
| 146 | EXCP_ALIGN = 0x6, |
| 147 | EXCP_ILLEGAL = 0x7, |
| 148 | EXCP_INT = 0x8, |
| 149 | EXCP_DTLBMISS = 0x9, |
| 150 | EXCP_ITLBMISS = 0xa, |
| 151 | EXCP_RANGE = 0xb, |
| 152 | EXCP_SYSCALL = 0xc, |
| 153 | EXCP_FPE = 0xd, |
| 154 | EXCP_TRAP = 0xe, |
| 155 | EXCP_NR, |
| 156 | }; |
| 157 | |
| 158 | /* Supervisor register */ |
| 159 | enum { |
| 160 | SR_SM = (1 << 0), |
| 161 | SR_TEE = (1 << 1), |
| 162 | SR_IEE = (1 << 2), |
| 163 | SR_DCE = (1 << 3), |
| 164 | SR_ICE = (1 << 4), |
| 165 | SR_DME = (1 << 5), |
| 166 | SR_IME = (1 << 6), |
| 167 | SR_LEE = (1 << 7), |
| 168 | SR_CE = (1 << 8), |
| 169 | SR_F = (1 << 9), |
| 170 | SR_CY = (1 << 10), |
| 171 | SR_OV = (1 << 11), |
| 172 | SR_OVE = (1 << 12), |
| 173 | SR_DSX = (1 << 13), |
| 174 | SR_EPH = (1 << 14), |
| 175 | SR_FO = (1 << 15), |
| 176 | SR_SUMRA = (1 << 16), |
| 177 | SR_SCE = (1 << 17), |
| 178 | }; |
| 179 | |
| 180 | /* Tick Timer Mode Register */ |
| 181 | enum { |
| 182 | TTMR_TP = (0xfffffff), |
| 183 | TTMR_IP = (1 << 28), |
| 184 | TTMR_IE = (1 << 29), |
| 185 | TTMR_M = (3 << 30), |
| 186 | }; |
| 187 | |
| 188 | /* Timer Mode */ |
| 189 | enum { |
| 190 | TIMER_NONE = (0 << 30), |
| 191 | TIMER_INTR = (1 << 30), |
| 192 | TIMER_SHOT = (2 << 30), |
| 193 | TIMER_CONT = (3 << 30), |
| 194 | }; |
| 195 | |
| 196 | /* TLB size */ |
| 197 | enum { |
| 198 | TLB_SIZE = 128, |
| 199 | TLB_MASK = TLB_SIZE - 1, |
| 200 | }; |
| 201 | |
| 202 | /* TLB prot */ |
| 203 | enum { |
| 204 | URE = (1 << 6), |
| 205 | UWE = (1 << 7), |
| 206 | SRE = (1 << 8), |
| 207 | SWE = (1 << 9), |
| 208 | |
| 209 | SXE = (1 << 6), |
| 210 | UXE = (1 << 7), |
| 211 | }; |
| 212 | |
| 213 | typedef struct OpenRISCTLBEntry { |
| 214 | uint32_t mr; |
| 215 | uint32_t tr; |
| 216 | } OpenRISCTLBEntry; |
| 217 | |
| 218 | #ifndef CONFIG_USER_ONLY |
| 219 | typedef struct CPUOpenRISCTLBContext { |
| 220 | OpenRISCTLBEntry itlb[TLB_SIZE]; |
| 221 | OpenRISCTLBEntry dtlb[TLB_SIZE]; |
| 222 | } CPUOpenRISCTLBContext; |
| 223 | #endif |
| 224 | |
| 225 | typedef struct CPUArchState { |
| 226 | uint32_t shadow_gpr[16][32]; /* Shadow registers */ |
| 227 | |
| 228 | uint32_t pc; /* Program counter */ |
| 229 | uint32_t ppc; /* Prev PC */ |
| 230 | uint32_t jmp_pc; /* Jump PC */ |
| 231 | |
| 232 | uint64_t mac; /* Multiply registers MACHI:MACLO */ |
| 233 | |
| 234 | uint32_t epcr; /* Exception PC register */ |
| 235 | uint32_t eear; /* Exception EA register */ |
| 236 | |
| 237 | uint32_t sr_f; /* the SR_F bit, values 0, 1. */ |
| 238 | uint32_t sr_cy; /* the SR_CY bit, values 0, 1. */ |
| 239 | int32_t sr_ov; /* the SR_OV bit (in the sign bit only) */ |
| 240 | uint32_t sr; /* Supervisor register, without SR_{F,CY,OV} */ |
| 241 | uint32_t esr; /* Exception supervisor register */ |
| 242 | uint32_t evbar; /* Exception vector base address register */ |
| 243 | uint32_t pmr; /* Power Management Register */ |
| 244 | uint32_t fpcsr; /* Float register */ |
| 245 | float_status fp_status; |
| 246 | |
| 247 | uint32_t lock_addr; |
| 248 | uint32_t lock_value; |
| 249 | |
| 250 | uint32_t dflag; /* In delay slot (boolean) */ |
| 251 | |
| 252 | #ifndef CONFIG_USER_ONLY |
| 253 | CPUOpenRISCTLBContext tlb; |
| 254 | #endif |
| 255 | |
| 256 | /* Fields up to this point are cleared by a CPU reset */ |
| 257 | struct {} end_reset_fields; |
| 258 | |
| 259 | /* Fields from here on are preserved across CPU reset. */ |
| 260 | uint32_t vr; /* Version register */ |
| 261 | uint32_t vr2; /* Version register 2 */ |
| 262 | uint32_t avr; /* Architecture version register */ |
| 263 | uint32_t upr; /* Unit presence register */ |
| 264 | uint32_t cpucfgr; /* CPU configure register */ |
| 265 | uint32_t dmmucfgr; /* DMMU configure register */ |
| 266 | uint32_t immucfgr; /* IMMU configure register */ |
| 267 | |
| 268 | #ifndef CONFIG_USER_ONLY |
| 269 | QEMUTimer *timer; |
| 270 | uint32_t ttmr; /* Timer tick mode register */ |
| 271 | int is_counting; |
| 272 | |
| 273 | uint32_t picmr; /* Interrupt mask register */ |
| 274 | uint32_t picsr; /* Interrupt control register */ |
| 275 | #endif |
| 276 | } CPUOpenRISCState; |
| 277 | |
| 278 | /** |
| 279 | * OpenRISCCPU: |
| 280 | * @env: #CPUOpenRISCState |
| 281 | * |
| 282 | * A OpenRISC CPU. |
| 283 | */ |
| 284 | struct ArchCPU { |
| 285 | CPUState parent_obj; |
| 286 | |
| 287 | CPUOpenRISCState env; |
| 288 | }; |
| 289 | |
| 290 | void openrisc_cpu_dump_state(CPUState *cpu, FILE *f, int flags); |
| 291 | int openrisc_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); |
| 292 | int openrisc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); |
| 293 | void openrisc_translate_init(void); |
| 294 | void openrisc_translate_code(CPUState *cs, TranslationBlock *tb, |
| 295 | int *max_insns, vaddr pc, void *host_pc); |
| 296 | int print_insn_or1k(bfd_vma addr, disassemble_info *info); |
| 297 | |
| 298 | #ifndef CONFIG_USER_ONLY |
| 299 | hwaddr openrisc_cpu_get_phys_addr_debug(CPUState *cpu, vaddr addr); |
| 300 | |
| 301 | bool openrisc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, |
| 302 | MMUAccessType access_type, int mmu_idx, |
| 303 | bool probe, uintptr_t retaddr); |
| 304 | |
| 305 | extern const VMStateDescription vmstate_openrisc_cpu; |
| 306 | |
| 307 | void openrisc_cpu_do_interrupt(CPUState *cpu); |
| 308 | bool openrisc_cpu_exec_interrupt(CPUState *cpu, int int_req); |
| 309 | |
| 310 | /* hw/openrisc_pic.c */ |
| 311 | void cpu_openrisc_pic_init(OpenRISCCPU *cpu); |
| 312 | |
| 313 | /* hw/openrisc_timer.c */ |
| 314 | void cpu_openrisc_clock_init(OpenRISCCPU *cpu); |
| 315 | uint32_t cpu_openrisc_count_get(OpenRISCCPU *cpu); |
| 316 | void cpu_openrisc_count_set(OpenRISCCPU *cpu, uint32_t val); |
| 317 | void cpu_openrisc_count_update(OpenRISCCPU *cpu); |
| 318 | void cpu_openrisc_timer_update(OpenRISCCPU *cpu); |
| 319 | void cpu_openrisc_count_start(OpenRISCCPU *cpu); |
| 320 | void cpu_openrisc_count_stop(OpenRISCCPU *cpu); |
| 321 | #endif |
| 322 | |
| 323 | #define CPU_RESOLVING_TYPE TYPE_OPENRISC_CPU |
| 324 | |
| 325 | #define TB_FLAGS_SM SR_SM |
| 326 | #define TB_FLAGS_DME SR_DME |
| 327 | #define TB_FLAGS_IME SR_IME |
| 328 | #define TB_FLAGS_OVE SR_OVE |
| 329 | #define TB_FLAGS_DFLAG 2 /* reuse SR_TEE */ |
| 330 | #define TB_FLAGS_R0_0 4 /* reuse SR_IEE */ |
| 331 | |
| 332 | static inline uint32_t cpu_get_gpr(const CPUOpenRISCState *env, int i) |
| 333 | { |
| 334 | return env->shadow_gpr[0][i]; |
| 335 | } |
| 336 | |
| 337 | static inline void cpu_set_gpr(CPUOpenRISCState *env, int i, uint32_t val) |
| 338 | { |
| 339 | env->shadow_gpr[0][i] = val; |
| 340 | } |
| 341 | |
| 342 | static inline uint32_t cpu_get_sr(const CPUOpenRISCState *env) |
| 343 | { |
| 344 | return (env->sr |
| 345 | + env->sr_f * SR_F |
| 346 | + env->sr_cy * SR_CY |
| 347 | + (env->sr_ov < 0) * SR_OV); |
| 348 | } |
| 349 | |
| 350 | static inline void cpu_set_sr(CPUOpenRISCState *env, uint32_t val) |
| 351 | { |
| 352 | env->sr_f = (val & SR_F) != 0; |
| 353 | env->sr_cy = (val & SR_CY) != 0; |
| 354 | env->sr_ov = (val & SR_OV ? -1 : 0); |
| 355 | env->sr = (val & ~(SR_F | SR_CY | SR_OV)) | SR_FO; |
| 356 | } |
| 357 | |
| 358 | void cpu_set_fpcsr(CPUOpenRISCState *env, uint32_t val); |
| 359 | |
| 360 | #define CPU_INTERRUPT_TIMER CPU_INTERRUPT_TGT_INT_0 |
| 361 | |
| 362 | #endif /* OPENRISC_CPU_H */ |