| 1 | /* |
| 2 | * OpenRISC interrupt. |
| 3 | * |
| 4 | * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com> |
| 5 | * |
| 6 | * This library is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU Lesser General Public |
| 8 | * License as published by the Free Software Foundation; either |
| 9 | * version 2.1 of the License, or (at your option) any later version. |
| 10 | * |
| 11 | * This library is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 14 | * Lesser General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU Lesser General Public |
| 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
| 18 | */ |
| 19 | |
| 20 | #include "qemu/osdep.h" |
| 21 | #include "qemu/log.h" |
| 22 | #include "cpu.h" |
| 23 | #include "qemu/host-utils.h" |
| 24 | #ifndef CONFIG_USER_ONLY |
| 25 | #include "hw/core/loader.h" |
| 26 | #endif |
| 27 | #include "qemu/plugin.h" |
| 28 | |
| 29 | void openrisc_cpu_do_interrupt(CPUState *cs) |
| 30 | { |
| 31 | CPUOpenRISCState *env = cpu_env(cs); |
| 32 | int exception = cs->exception_index; |
| 33 | uint64_t last_pc = env->pc; |
| 34 | |
| 35 | env->epcr = env->pc; |
| 36 | |
| 37 | /* When we have an illegal instruction the error effective address |
| 38 | shall be set to the illegal instruction address. */ |
| 39 | if (exception == EXCP_ILLEGAL) { |
| 40 | env->eear = env->pc; |
| 41 | } |
| 42 | |
| 43 | /* During exceptions esr is populared with the pre-exception sr. */ |
| 44 | env->esr = cpu_get_sr(env); |
| 45 | /* In parallel sr is updated to disable mmu, interrupts, timers and |
| 46 | set the delay slot exception flag. */ |
| 47 | env->sr &= ~SR_DME; |
| 48 | env->sr &= ~SR_IME; |
| 49 | env->sr |= SR_SM; |
| 50 | env->sr &= ~SR_IEE; |
| 51 | env->sr &= ~SR_TEE; |
| 52 | env->pmr &= ~PMR_DME; |
| 53 | env->pmr &= ~PMR_SME; |
| 54 | env->lock_addr = -1; |
| 55 | |
| 56 | /* Set/clear dsx to indicate if we are in a delay slot exception. */ |
| 57 | if (env->dflag) { |
| 58 | env->dflag = 0; |
| 59 | env->sr |= SR_DSX; |
| 60 | env->epcr -= 4; |
| 61 | } else { |
| 62 | env->sr &= ~SR_DSX; |
| 63 | if (exception == EXCP_SYSCALL || exception == EXCP_FPE) { |
| 64 | env->epcr += 4; |
| 65 | } |
| 66 | } |
| 67 | |
| 68 | if (exception > 0 && exception < EXCP_NR) { |
| 69 | static const char * const int_name[EXCP_NR] = { |
| 70 | [EXCP_RESET] = "RESET", |
| 71 | [EXCP_BUSERR] = "BUSERR (bus error)", |
| 72 | [EXCP_DPF] = "DFP (data protection fault)", |
| 73 | [EXCP_IPF] = "IPF (code protection fault)", |
| 74 | [EXCP_TICK] = "TICK (timer interrupt)", |
| 75 | [EXCP_ALIGN] = "ALIGN", |
| 76 | [EXCP_ILLEGAL] = "ILLEGAL", |
| 77 | [EXCP_INT] = "INT (device interrupt)", |
| 78 | [EXCP_DTLBMISS] = "DTLBMISS (data tlb miss)", |
| 79 | [EXCP_ITLBMISS] = "ITLBMISS (code tlb miss)", |
| 80 | [EXCP_RANGE] = "RANGE", |
| 81 | [EXCP_SYSCALL] = "SYSCALL", |
| 82 | [EXCP_FPE] = "FPE", |
| 83 | [EXCP_TRAP] = "TRAP", |
| 84 | }; |
| 85 | |
| 86 | qemu_log_mask(CPU_LOG_INT, "CPU: %d INT: %s\n", |
| 87 | cs->cpu_index, |
| 88 | int_name[exception]); |
| 89 | |
| 90 | hwaddr vect_pc = exception << 8; |
| 91 | if (env->cpucfgr & CPUCFGR_EVBARP) { |
| 92 | vect_pc |= env->evbar; |
| 93 | } |
| 94 | if (env->sr & SR_EPH) { |
| 95 | vect_pc |= 0xf0000000; |
| 96 | } |
| 97 | env->pc = vect_pc; |
| 98 | } else { |
| 99 | cpu_abort(cs, "Unhandled exception 0x%x\n", exception); |
| 100 | } |
| 101 | |
| 102 | switch (exception) { |
| 103 | case EXCP_RESET: |
| 104 | /* Resets are already exposed to plugins through a dedicated callback */ |
| 105 | break; |
| 106 | case EXCP_TICK: |
| 107 | case EXCP_INT: |
| 108 | qemu_plugin_vcpu_interrupt_cb(cs, last_pc); |
| 109 | break; |
| 110 | default: |
| 111 | qemu_plugin_vcpu_exception_cb(cs, last_pc); |
| 112 | break; |
| 113 | } |
| 114 | |
| 115 | cs->exception_index = -1; |
| 116 | } |
| 117 | |
| 118 | bool openrisc_cpu_exec_interrupt(CPUState *cs, int interrupt_request) |
| 119 | { |
| 120 | CPUOpenRISCState *env = cpu_env(cs); |
| 121 | int idx = -1; |
| 122 | |
| 123 | if ((interrupt_request & CPU_INTERRUPT_HARD) && (env->sr & SR_IEE)) { |
| 124 | idx = EXCP_INT; |
| 125 | } |
| 126 | if ((interrupt_request & CPU_INTERRUPT_TIMER) && (env->sr & SR_TEE)) { |
| 127 | idx = EXCP_TICK; |
| 128 | } |
| 129 | if (idx >= 0) { |
| 130 | cs->exception_index = idx; |
| 131 | openrisc_cpu_do_interrupt(cs); |
| 132 | return true; |
| 133 | } |
| 134 | return false; |
| 135 | } |