| 1 | /* |
| 2 | * OpenRISC translation |
| 3 | * |
| 4 | * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com> |
| 5 | * Feng Gao <gf91597@gmail.com> |
| 6 | * |
| 7 | * This library is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU Lesser General Public |
| 9 | * License as published by the Free Software Foundation; either |
| 10 | * version 2.1 of the License, or (at your option) any later version. |
| 11 | * |
| 12 | * This library is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 15 | * Lesser General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU Lesser General Public |
| 18 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
| 19 | */ |
| 20 | |
| 21 | #include "qemu/osdep.h" |
| 22 | #include "cpu.h" |
| 23 | #include "accel/tcg/cpu-mmu-index.h" |
| 24 | #include "tcg/tcg-op.h" |
| 25 | #include "qemu/log.h" |
| 26 | #include "qemu/bitops.h" |
| 27 | #include "qemu/qemu-print.h" |
| 28 | #include "exec/translator.h" |
| 29 | #include "exec/translation-block.h" |
| 30 | #include "exec/target_page.h" |
| 31 | #include "exec/helper-proto.h" |
| 32 | #include "exec/helper-gen.h" |
| 33 | |
| 34 | #include "exec/log.h" |
| 35 | |
| 36 | #define HELPER_H "helper.h" |
| 37 | #include "exec/helper-info.c.inc" |
| 38 | #undef HELPER_H |
| 39 | |
| 40 | |
| 41 | /* is_jmp field values */ |
| 42 | #define DISAS_EXIT DISAS_TARGET_0 /* force exit to main loop */ |
| 43 | #define DISAS_JUMP DISAS_TARGET_1 /* exit via jmp_pc/jmp_pc_imm */ |
| 44 | |
| 45 | typedef struct DisasContext { |
| 46 | DisasContextBase base; |
| 47 | uint32_t mem_idx; |
| 48 | uint32_t tb_flags; |
| 49 | uint32_t delayed_branch; |
| 50 | uint32_t cpucfgr; |
| 51 | uint32_t avr; |
| 52 | |
| 53 | /* If not -1, jmp_pc contains this value and so is a direct jump. */ |
| 54 | vaddr jmp_pc_imm; |
| 55 | |
| 56 | /* The temporary corresponding to register 0 for this compilation. */ |
| 57 | TCGv_i32 R0; |
| 58 | /* The constant zero. */ |
| 59 | TCGv_i32 zero; |
| 60 | } DisasContext; |
| 61 | |
| 62 | static inline MemOp mo_endian(DisasContext *dc) |
| 63 | { |
| 64 | /* The SR_LEE bit sets the (little) endianness, but we don't implement it. */ |
| 65 | return MO_BE; |
| 66 | } |
| 67 | |
| 68 | static inline bool is_user(DisasContext *dc) |
| 69 | { |
| 70 | #ifdef CONFIG_USER_ONLY |
| 71 | return true; |
| 72 | #else |
| 73 | return !(dc->tb_flags & TB_FLAGS_SM); |
| 74 | #endif |
| 75 | } |
| 76 | |
| 77 | /* Include the auto-generated decoder. */ |
| 78 | #include "decode-insns.c.inc" |
| 79 | |
| 80 | static TCGv_i32 cpu_sr; |
| 81 | static TCGv_i32 cpu_regs[32]; |
| 82 | static TCGv_i32 cpu_pc; |
| 83 | static TCGv_i32 jmp_pc; /* l.jr/l.jalr temp pc */ |
| 84 | static TCGv_i32 cpu_ppc; |
| 85 | static TCGv_i32 cpu_sr_f; /* bf/bnf, F flag taken */ |
| 86 | static TCGv_i32 cpu_sr_cy; /* carry (unsigned overflow) */ |
| 87 | static TCGv_i32 cpu_sr_ov; /* signed overflow */ |
| 88 | static TCGv_i32 cpu_lock_addr; |
| 89 | static TCGv_i32 cpu_lock_value; |
| 90 | static TCGv_i32 fpcsr; |
| 91 | static TCGv_i64 cpu_mac; /* MACHI:MACLO */ |
| 92 | static TCGv_i32 cpu_dflag; |
| 93 | |
| 94 | void openrisc_translate_init(void) |
| 95 | { |
| 96 | static const char * const regnames[] = { |
| 97 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
| 98 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", |
| 99 | "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", |
| 100 | "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", |
| 101 | }; |
| 102 | int i; |
| 103 | |
| 104 | cpu_sr = tcg_global_mem_new_i32(tcg_env, |
| 105 | offsetof(CPUOpenRISCState, sr), "sr"); |
| 106 | cpu_dflag = tcg_global_mem_new_i32(tcg_env, |
| 107 | offsetof(CPUOpenRISCState, dflag), |
| 108 | "dflag"); |
| 109 | cpu_pc = tcg_global_mem_new_i32(tcg_env, |
| 110 | offsetof(CPUOpenRISCState, pc), "pc"); |
| 111 | cpu_ppc = tcg_global_mem_new_i32(tcg_env, |
| 112 | offsetof(CPUOpenRISCState, ppc), "ppc"); |
| 113 | jmp_pc = tcg_global_mem_new_i32(tcg_env, |
| 114 | offsetof(CPUOpenRISCState, jmp_pc), "jmp_pc"); |
| 115 | cpu_sr_f = tcg_global_mem_new_i32(tcg_env, |
| 116 | offsetof(CPUOpenRISCState, sr_f), "sr_f"); |
| 117 | cpu_sr_cy = tcg_global_mem_new_i32(tcg_env, |
| 118 | offsetof(CPUOpenRISCState, sr_cy), "sr_cy"); |
| 119 | cpu_sr_ov = tcg_global_mem_new_i32(tcg_env, |
| 120 | offsetof(CPUOpenRISCState, sr_ov), "sr_ov"); |
| 121 | cpu_lock_addr = tcg_global_mem_new_i32(tcg_env, |
| 122 | offsetof(CPUOpenRISCState, lock_addr), |
| 123 | "lock_addr"); |
| 124 | cpu_lock_value = tcg_global_mem_new_i32(tcg_env, |
| 125 | offsetof(CPUOpenRISCState, lock_value), |
| 126 | "lock_value"); |
| 127 | fpcsr = tcg_global_mem_new_i32(tcg_env, |
| 128 | offsetof(CPUOpenRISCState, fpcsr), |
| 129 | "fpcsr"); |
| 130 | cpu_mac = tcg_global_mem_new_i64(tcg_env, |
| 131 | offsetof(CPUOpenRISCState, mac), |
| 132 | "mac"); |
| 133 | for (i = 0; i < 32; i++) { |
| 134 | cpu_regs[i] = tcg_global_mem_new_i32(tcg_env, |
| 135 | offsetof(CPUOpenRISCState, |
| 136 | shadow_gpr[0][i]), |
| 137 | regnames[i]); |
| 138 | } |
| 139 | } |
| 140 | |
| 141 | static void gen_exception(DisasContext *dc, unsigned int excp) |
| 142 | { |
| 143 | gen_helper_exception(tcg_env, tcg_constant_i32(excp)); |
| 144 | } |
| 145 | |
| 146 | static void gen_illegal_exception(DisasContext *dc) |
| 147 | { |
| 148 | tcg_gen_movi_i32(cpu_pc, dc->base.pc_next); |
| 149 | gen_exception(dc, EXCP_ILLEGAL); |
| 150 | dc->base.is_jmp = DISAS_NORETURN; |
| 151 | } |
| 152 | |
| 153 | static bool check_v1_3(DisasContext *dc) |
| 154 | { |
| 155 | return dc->avr >= 0x01030000; |
| 156 | } |
| 157 | |
| 158 | static bool check_of32s(DisasContext *dc) |
| 159 | { |
| 160 | return dc->cpucfgr & CPUCFGR_OF32S; |
| 161 | } |
| 162 | |
| 163 | static bool check_of64a32s(DisasContext *dc) |
| 164 | { |
| 165 | return dc->cpucfgr & CPUCFGR_OF64A32S; |
| 166 | } |
| 167 | |
| 168 | static TCGv_i32 cpu_R(DisasContext *dc, int reg) |
| 169 | { |
| 170 | if (reg == 0) { |
| 171 | return dc->R0; |
| 172 | } else { |
| 173 | return cpu_regs[reg]; |
| 174 | } |
| 175 | } |
| 176 | |
| 177 | /* |
| 178 | * We're about to write to REG. On the off-chance that the user is |
| 179 | * writing to R0, re-instate the architectural register. |
| 180 | */ |
| 181 | static void check_r0_write(DisasContext *dc, int reg) |
| 182 | { |
| 183 | if (unlikely(reg == 0)) { |
| 184 | dc->R0 = cpu_regs[0]; |
| 185 | } |
| 186 | } |
| 187 | |
| 188 | static void gen_ove_cy(DisasContext *dc) |
| 189 | { |
| 190 | if (dc->tb_flags & SR_OVE) { |
| 191 | gen_helper_ove_cy(tcg_env); |
| 192 | } |
| 193 | } |
| 194 | |
| 195 | static void gen_ove_ov(DisasContext *dc) |
| 196 | { |
| 197 | if (dc->tb_flags & SR_OVE) { |
| 198 | gen_helper_ove_ov(tcg_env); |
| 199 | } |
| 200 | } |
| 201 | |
| 202 | static void gen_ove_cyov(DisasContext *dc) |
| 203 | { |
| 204 | if (dc->tb_flags & SR_OVE) { |
| 205 | gen_helper_ove_cyov(tcg_env); |
| 206 | } |
| 207 | } |
| 208 | |
| 209 | static void gen_add(DisasContext *dc, TCGv_i32 dest, |
| 210 | TCGv_i32 srca, TCGv_i32 srcb) |
| 211 | { |
| 212 | TCGv_i32 t0 = tcg_temp_new_i32(); |
| 213 | TCGv_i32 res = tcg_temp_new_i32(); |
| 214 | |
| 215 | tcg_gen_add2_i32(res, cpu_sr_cy, srca, dc->zero, srcb, dc->zero); |
| 216 | tcg_gen_xor_i32(cpu_sr_ov, srca, srcb); |
| 217 | tcg_gen_xor_i32(t0, res, srcb); |
| 218 | tcg_gen_andc_i32(cpu_sr_ov, t0, cpu_sr_ov); |
| 219 | |
| 220 | tcg_gen_mov_i32(dest, res); |
| 221 | |
| 222 | gen_ove_cyov(dc); |
| 223 | } |
| 224 | |
| 225 | static void gen_addc(DisasContext *dc, TCGv_i32 dest, |
| 226 | TCGv_i32 srca, TCGv_i32 srcb) |
| 227 | { |
| 228 | TCGv_i32 t0 = tcg_temp_new_i32(); |
| 229 | TCGv_i32 res = tcg_temp_new_i32(); |
| 230 | |
| 231 | tcg_gen_addcio_i32(res, cpu_sr_cy, srca, srcb, cpu_sr_cy); |
| 232 | tcg_gen_xor_i32(cpu_sr_ov, srca, srcb); |
| 233 | tcg_gen_xor_i32(t0, res, srcb); |
| 234 | tcg_gen_andc_i32(cpu_sr_ov, t0, cpu_sr_ov); |
| 235 | |
| 236 | tcg_gen_mov_i32(dest, res); |
| 237 | |
| 238 | gen_ove_cyov(dc); |
| 239 | } |
| 240 | |
| 241 | static void gen_sub(DisasContext *dc, TCGv_i32 dest, |
| 242 | TCGv_i32 srca, TCGv_i32 srcb) |
| 243 | { |
| 244 | TCGv_i32 res = tcg_temp_new_i32(); |
| 245 | |
| 246 | tcg_gen_sub_i32(res, srca, srcb); |
| 247 | tcg_gen_xor_i32(cpu_sr_cy, srca, srcb); |
| 248 | tcg_gen_xor_i32(cpu_sr_ov, res, srcb); |
| 249 | tcg_gen_and_i32(cpu_sr_ov, cpu_sr_ov, cpu_sr_cy); |
| 250 | tcg_gen_setcond_i32(TCG_COND_LTU, cpu_sr_cy, srca, srcb); |
| 251 | |
| 252 | tcg_gen_mov_i32(dest, res); |
| 253 | |
| 254 | gen_ove_cyov(dc); |
| 255 | } |
| 256 | |
| 257 | static void gen_mul(DisasContext *dc, TCGv_i32 dest, |
| 258 | TCGv_i32 srca, TCGv_i32 srcb) |
| 259 | { |
| 260 | TCGv_i32 t0 = tcg_temp_new_i32(); |
| 261 | |
| 262 | tcg_gen_muls2_i32(dest, cpu_sr_ov, srca, srcb); |
| 263 | tcg_gen_sari_i32(t0, dest, TARGET_LONG_BITS - 1); |
| 264 | tcg_gen_negsetcond_i32(TCG_COND_NE, cpu_sr_ov, cpu_sr_ov, t0); |
| 265 | |
| 266 | gen_ove_ov(dc); |
| 267 | } |
| 268 | |
| 269 | static void gen_mulu(DisasContext *dc, TCGv_i32 dest, |
| 270 | TCGv_i32 srca, TCGv_i32 srcb) |
| 271 | { |
| 272 | tcg_gen_muls2_i32(dest, cpu_sr_cy, srca, srcb); |
| 273 | tcg_gen_setcondi_i32(TCG_COND_NE, cpu_sr_cy, cpu_sr_cy, 0); |
| 274 | |
| 275 | gen_ove_cy(dc); |
| 276 | } |
| 277 | |
| 278 | static void gen_div(DisasContext *dc, TCGv_i32 dest, |
| 279 | TCGv_i32 srca, TCGv_i32 srcb) |
| 280 | { |
| 281 | TCGv_i32 t0 = tcg_temp_new_i32(); |
| 282 | |
| 283 | tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_sr_ov, srcb, 0); |
| 284 | /* The result of divide-by-zero is undefined. |
| 285 | Suppress the host-side exception by dividing by 1. */ |
| 286 | tcg_gen_or_i32(t0, srcb, cpu_sr_ov); |
| 287 | tcg_gen_div_i32(dest, srca, t0); |
| 288 | |
| 289 | tcg_gen_neg_i32(cpu_sr_ov, cpu_sr_ov); |
| 290 | gen_ove_ov(dc); |
| 291 | } |
| 292 | |
| 293 | static void gen_divu(DisasContext *dc, TCGv_i32 dest, |
| 294 | TCGv_i32 srca, TCGv_i32 srcb) |
| 295 | { |
| 296 | TCGv_i32 t0 = tcg_temp_new_i32(); |
| 297 | |
| 298 | tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_sr_cy, srcb, 0); |
| 299 | /* The result of divide-by-zero is undefined. |
| 300 | Suppress the host-side exception by dividing by 1. */ |
| 301 | tcg_gen_or_i32(t0, srcb, cpu_sr_cy); |
| 302 | tcg_gen_divu_i32(dest, srca, t0); |
| 303 | |
| 304 | gen_ove_cy(dc); |
| 305 | } |
| 306 | |
| 307 | static void gen_muld(DisasContext *dc, TCGv_i32 srca, TCGv_i32 srcb) |
| 308 | { |
| 309 | TCGv_i64 t1 = tcg_temp_new_i64(); |
| 310 | TCGv_i64 t2 = tcg_temp_new_i64(); |
| 311 | |
| 312 | tcg_gen_ext_i32_i64(t1, srca); |
| 313 | tcg_gen_ext_i32_i64(t2, srcb); |
| 314 | tcg_gen_mul_i64(cpu_mac, t1, t2); |
| 315 | tcg_gen_movi_i32(cpu_sr_ov, 0); |
| 316 | } |
| 317 | |
| 318 | static void gen_muldu(DisasContext *dc, TCGv_i32 srca, TCGv_i32 srcb) |
| 319 | { |
| 320 | TCGv_i64 t1 = tcg_temp_new_i64(); |
| 321 | TCGv_i64 t2 = tcg_temp_new_i64(); |
| 322 | |
| 323 | tcg_gen_extu_i32_i64(t1, srca); |
| 324 | tcg_gen_extu_i32_i64(t2, srcb); |
| 325 | tcg_gen_mul_i64(cpu_mac, t1, t2); |
| 326 | tcg_gen_movi_i32(cpu_sr_cy, 0); |
| 327 | } |
| 328 | |
| 329 | static void gen_mac(DisasContext *dc, TCGv_i32 srca, TCGv_i32 srcb) |
| 330 | { |
| 331 | TCGv_i64 t1 = tcg_temp_new_i64(); |
| 332 | TCGv_i64 t2 = tcg_temp_new_i64(); |
| 333 | |
| 334 | tcg_gen_ext_i32_i64(t1, srca); |
| 335 | tcg_gen_ext_i32_i64(t2, srcb); |
| 336 | tcg_gen_mul_i64(t1, t1, t2); |
| 337 | |
| 338 | /* Note that overflow is only computed during addition stage. */ |
| 339 | tcg_gen_xor_i64(t2, cpu_mac, t1); |
| 340 | tcg_gen_add_i64(cpu_mac, cpu_mac, t1); |
| 341 | tcg_gen_xor_i64(t1, t1, cpu_mac); |
| 342 | tcg_gen_andc_i64(t1, t1, t2); |
| 343 | |
| 344 | tcg_gen_extrh_i64_i32(cpu_sr_ov, t1); |
| 345 | |
| 346 | gen_ove_ov(dc); |
| 347 | } |
| 348 | |
| 349 | static void gen_macu(DisasContext *dc, TCGv_i32 srca, TCGv_i32 srcb) |
| 350 | { |
| 351 | TCGv_i64 t1 = tcg_temp_new_i64(); |
| 352 | TCGv_i64 t2 = tcg_temp_new_i64(); |
| 353 | |
| 354 | tcg_gen_extu_i32_i64(t1, srca); |
| 355 | tcg_gen_extu_i32_i64(t2, srcb); |
| 356 | tcg_gen_mul_i64(t1, t1, t2); |
| 357 | |
| 358 | /* Note that overflow is only computed during addition stage. */ |
| 359 | tcg_gen_add_i64(cpu_mac, cpu_mac, t1); |
| 360 | tcg_gen_setcond_i64(TCG_COND_LTU, t1, cpu_mac, t1); |
| 361 | tcg_gen_extrl_i64_i32(cpu_sr_cy, t1); |
| 362 | |
| 363 | gen_ove_cy(dc); |
| 364 | } |
| 365 | |
| 366 | static void gen_msb(DisasContext *dc, TCGv_i32 srca, TCGv_i32 srcb) |
| 367 | { |
| 368 | TCGv_i64 t1 = tcg_temp_new_i64(); |
| 369 | TCGv_i64 t2 = tcg_temp_new_i64(); |
| 370 | |
| 371 | tcg_gen_ext_i32_i64(t1, srca); |
| 372 | tcg_gen_ext_i32_i64(t2, srcb); |
| 373 | tcg_gen_mul_i64(t1, t1, t2); |
| 374 | |
| 375 | /* Note that overflow is only computed during subtraction stage. */ |
| 376 | tcg_gen_xor_i64(t2, cpu_mac, t1); |
| 377 | tcg_gen_sub_i64(cpu_mac, cpu_mac, t1); |
| 378 | tcg_gen_xor_i64(t1, t1, cpu_mac); |
| 379 | tcg_gen_and_i64(t1, t1, t2); |
| 380 | |
| 381 | #if TARGET_LONG_BITS == 32 |
| 382 | tcg_gen_extrh_i64_i32(cpu_sr_ov, t1); |
| 383 | #else |
| 384 | tcg_gen_mov_i64(cpu_sr_ov, t1); |
| 385 | #endif |
| 386 | |
| 387 | gen_ove_ov(dc); |
| 388 | } |
| 389 | |
| 390 | static void gen_msbu(DisasContext *dc, TCGv_i32 srca, TCGv_i32 srcb) |
| 391 | { |
| 392 | TCGv_i64 t1 = tcg_temp_new_i64(); |
| 393 | TCGv_i64 t2 = tcg_temp_new_i64(); |
| 394 | |
| 395 | tcg_gen_extu_i32_i64(t1, srca); |
| 396 | tcg_gen_extu_i32_i64(t2, srcb); |
| 397 | tcg_gen_mul_i64(t1, t1, t2); |
| 398 | |
| 399 | /* Note that overflow is only computed during subtraction stage. */ |
| 400 | tcg_gen_setcond_i64(TCG_COND_LTU, t2, cpu_mac, t1); |
| 401 | tcg_gen_sub_i64(cpu_mac, cpu_mac, t1); |
| 402 | tcg_gen_extrl_i64_i32(cpu_sr_cy, t2); |
| 403 | |
| 404 | gen_ove_cy(dc); |
| 405 | } |
| 406 | |
| 407 | static bool trans_l_add(DisasContext *dc, arg_dab *a) |
| 408 | { |
| 409 | check_r0_write(dc, a->d); |
| 410 | gen_add(dc, cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b)); |
| 411 | return true; |
| 412 | } |
| 413 | |
| 414 | static bool trans_l_addc(DisasContext *dc, arg_dab *a) |
| 415 | { |
| 416 | check_r0_write(dc, a->d); |
| 417 | gen_addc(dc, cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b)); |
| 418 | return true; |
| 419 | } |
| 420 | |
| 421 | static bool trans_l_sub(DisasContext *dc, arg_dab *a) |
| 422 | { |
| 423 | check_r0_write(dc, a->d); |
| 424 | gen_sub(dc, cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b)); |
| 425 | return true; |
| 426 | } |
| 427 | |
| 428 | static bool trans_l_and(DisasContext *dc, arg_dab *a) |
| 429 | { |
| 430 | check_r0_write(dc, a->d); |
| 431 | tcg_gen_and_i32(cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b)); |
| 432 | return true; |
| 433 | } |
| 434 | |
| 435 | static bool trans_l_or(DisasContext *dc, arg_dab *a) |
| 436 | { |
| 437 | check_r0_write(dc, a->d); |
| 438 | tcg_gen_or_i32(cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b)); |
| 439 | return true; |
| 440 | } |
| 441 | |
| 442 | static bool trans_l_xor(DisasContext *dc, arg_dab *a) |
| 443 | { |
| 444 | check_r0_write(dc, a->d); |
| 445 | tcg_gen_xor_i32(cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b)); |
| 446 | return true; |
| 447 | } |
| 448 | |
| 449 | static bool trans_l_sll(DisasContext *dc, arg_dab *a) |
| 450 | { |
| 451 | check_r0_write(dc, a->d); |
| 452 | tcg_gen_shl_i32(cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b)); |
| 453 | return true; |
| 454 | } |
| 455 | |
| 456 | static bool trans_l_srl(DisasContext *dc, arg_dab *a) |
| 457 | { |
| 458 | check_r0_write(dc, a->d); |
| 459 | tcg_gen_shr_i32(cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b)); |
| 460 | return true; |
| 461 | } |
| 462 | |
| 463 | static bool trans_l_sra(DisasContext *dc, arg_dab *a) |
| 464 | { |
| 465 | check_r0_write(dc, a->d); |
| 466 | tcg_gen_sar_i32(cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b)); |
| 467 | return true; |
| 468 | } |
| 469 | |
| 470 | static bool trans_l_ror(DisasContext *dc, arg_dab *a) |
| 471 | { |
| 472 | check_r0_write(dc, a->d); |
| 473 | tcg_gen_rotr_i32(cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b)); |
| 474 | return true; |
| 475 | } |
| 476 | |
| 477 | static bool trans_l_exths(DisasContext *dc, arg_da *a) |
| 478 | { |
| 479 | check_r0_write(dc, a->d); |
| 480 | tcg_gen_ext16s_i32(cpu_R(dc, a->d), cpu_R(dc, a->a)); |
| 481 | return true; |
| 482 | } |
| 483 | |
| 484 | static bool trans_l_extbs(DisasContext *dc, arg_da *a) |
| 485 | { |
| 486 | check_r0_write(dc, a->d); |
| 487 | tcg_gen_ext8s_i32(cpu_R(dc, a->d), cpu_R(dc, a->a)); |
| 488 | return true; |
| 489 | } |
| 490 | |
| 491 | static bool trans_l_exthz(DisasContext *dc, arg_da *a) |
| 492 | { |
| 493 | check_r0_write(dc, a->d); |
| 494 | tcg_gen_ext16u_i32(cpu_R(dc, a->d), cpu_R(dc, a->a)); |
| 495 | return true; |
| 496 | } |
| 497 | |
| 498 | static bool trans_l_extbz(DisasContext *dc, arg_da *a) |
| 499 | { |
| 500 | check_r0_write(dc, a->d); |
| 501 | tcg_gen_ext8u_i32(cpu_R(dc, a->d), cpu_R(dc, a->a)); |
| 502 | return true; |
| 503 | } |
| 504 | |
| 505 | static bool trans_l_cmov(DisasContext *dc, arg_dab *a) |
| 506 | { |
| 507 | check_r0_write(dc, a->d); |
| 508 | tcg_gen_movcond_i32(TCG_COND_NE, cpu_R(dc, a->d), cpu_sr_f, dc->zero, |
| 509 | cpu_R(dc, a->a), cpu_R(dc, a->b)); |
| 510 | return true; |
| 511 | } |
| 512 | |
| 513 | static bool trans_l_ff1(DisasContext *dc, arg_da *a) |
| 514 | { |
| 515 | check_r0_write(dc, a->d); |
| 516 | tcg_gen_ctzi_i32(cpu_R(dc, a->d), cpu_R(dc, a->a), -1); |
| 517 | tcg_gen_addi_i32(cpu_R(dc, a->d), cpu_R(dc, a->d), 1); |
| 518 | return true; |
| 519 | } |
| 520 | |
| 521 | static bool trans_l_fl1(DisasContext *dc, arg_da *a) |
| 522 | { |
| 523 | check_r0_write(dc, a->d); |
| 524 | tcg_gen_clzi_i32(cpu_R(dc, a->d), cpu_R(dc, a->a), TARGET_LONG_BITS); |
| 525 | tcg_gen_subfi_i32(cpu_R(dc, a->d), TARGET_LONG_BITS, cpu_R(dc, a->d)); |
| 526 | return true; |
| 527 | } |
| 528 | |
| 529 | static bool trans_l_mul(DisasContext *dc, arg_dab *a) |
| 530 | { |
| 531 | check_r0_write(dc, a->d); |
| 532 | gen_mul(dc, cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b)); |
| 533 | return true; |
| 534 | } |
| 535 | |
| 536 | static bool trans_l_mulu(DisasContext *dc, arg_dab *a) |
| 537 | { |
| 538 | check_r0_write(dc, a->d); |
| 539 | gen_mulu(dc, cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b)); |
| 540 | return true; |
| 541 | } |
| 542 | |
| 543 | static bool trans_l_div(DisasContext *dc, arg_dab *a) |
| 544 | { |
| 545 | check_r0_write(dc, a->d); |
| 546 | gen_div(dc, cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b)); |
| 547 | return true; |
| 548 | } |
| 549 | |
| 550 | static bool trans_l_divu(DisasContext *dc, arg_dab *a) |
| 551 | { |
| 552 | check_r0_write(dc, a->d); |
| 553 | gen_divu(dc, cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b)); |
| 554 | return true; |
| 555 | } |
| 556 | |
| 557 | static bool trans_l_muld(DisasContext *dc, arg_ab *a) |
| 558 | { |
| 559 | gen_muld(dc, cpu_R(dc, a->a), cpu_R(dc, a->b)); |
| 560 | return true; |
| 561 | } |
| 562 | |
| 563 | static bool trans_l_muldu(DisasContext *dc, arg_ab *a) |
| 564 | { |
| 565 | gen_muldu(dc, cpu_R(dc, a->a), cpu_R(dc, a->b)); |
| 566 | return true; |
| 567 | } |
| 568 | |
| 569 | static bool trans_l_j(DisasContext *dc, arg_l_j *a) |
| 570 | { |
| 571 | vaddr tmp_pc = dc->base.pc_next + a->n * 4; |
| 572 | |
| 573 | tcg_gen_movi_i32(jmp_pc, tmp_pc); |
| 574 | dc->jmp_pc_imm = tmp_pc; |
| 575 | dc->delayed_branch = 2; |
| 576 | return true; |
| 577 | } |
| 578 | |
| 579 | static bool trans_l_jal(DisasContext *dc, arg_l_jal *a) |
| 580 | { |
| 581 | vaddr tmp_pc = dc->base.pc_next + a->n * 4; |
| 582 | vaddr ret_pc = dc->base.pc_next + 8; |
| 583 | |
| 584 | tcg_gen_movi_i32(cpu_regs[9], ret_pc); |
| 585 | /* Optimize jal being used to load the PC for PIC. */ |
| 586 | if (tmp_pc != ret_pc) { |
| 587 | tcg_gen_movi_i32(jmp_pc, tmp_pc); |
| 588 | dc->jmp_pc_imm = tmp_pc; |
| 589 | dc->delayed_branch = 2; |
| 590 | } |
| 591 | return true; |
| 592 | } |
| 593 | |
| 594 | static void do_bf(DisasContext *dc, arg_l_bf *a, TCGCond cond) |
| 595 | { |
| 596 | vaddr tmp_pc = dc->base.pc_next + a->n * 4; |
| 597 | TCGv_i32 t_next = tcg_constant_i32(dc->base.pc_next + 8); |
| 598 | TCGv_i32 t_true = tcg_constant_i32(tmp_pc); |
| 599 | |
| 600 | tcg_gen_movcond_i32(cond, jmp_pc, cpu_sr_f, dc->zero, t_true, t_next); |
| 601 | dc->delayed_branch = 2; |
| 602 | } |
| 603 | |
| 604 | static bool trans_l_bf(DisasContext *dc, arg_l_bf *a) |
| 605 | { |
| 606 | do_bf(dc, a, TCG_COND_NE); |
| 607 | return true; |
| 608 | } |
| 609 | |
| 610 | static bool trans_l_bnf(DisasContext *dc, arg_l_bf *a) |
| 611 | { |
| 612 | do_bf(dc, a, TCG_COND_EQ); |
| 613 | return true; |
| 614 | } |
| 615 | |
| 616 | static bool trans_l_jr(DisasContext *dc, arg_l_jr *a) |
| 617 | { |
| 618 | tcg_gen_mov_i32(jmp_pc, cpu_R(dc, a->b)); |
| 619 | dc->delayed_branch = 2; |
| 620 | return true; |
| 621 | } |
| 622 | |
| 623 | static bool trans_l_jalr(DisasContext *dc, arg_l_jalr *a) |
| 624 | { |
| 625 | tcg_gen_mov_i32(jmp_pc, cpu_R(dc, a->b)); |
| 626 | tcg_gen_movi_i32(cpu_regs[9], dc->base.pc_next + 8); |
| 627 | dc->delayed_branch = 2; |
| 628 | return true; |
| 629 | } |
| 630 | |
| 631 | static bool trans_l_lwa(DisasContext *dc, arg_load *a) |
| 632 | { |
| 633 | TCGv_i32 ea; |
| 634 | |
| 635 | check_r0_write(dc, a->d); |
| 636 | ea = tcg_temp_new_i32(); |
| 637 | tcg_gen_addi_i32(ea, cpu_R(dc, a->a), a->i); |
| 638 | tcg_gen_qemu_ld_i32(cpu_R(dc, a->d), ea, dc->mem_idx, |
| 639 | mo_endian(dc) | MO_UL); |
| 640 | tcg_gen_mov_i32(cpu_lock_addr, ea); |
| 641 | tcg_gen_mov_i32(cpu_lock_value, cpu_R(dc, a->d)); |
| 642 | return true; |
| 643 | } |
| 644 | |
| 645 | static void do_load(DisasContext *dc, arg_load *a, MemOp mop) |
| 646 | { |
| 647 | TCGv_i32 ea; |
| 648 | |
| 649 | mop |= mo_endian(dc); |
| 650 | |
| 651 | check_r0_write(dc, a->d); |
| 652 | ea = tcg_temp_new_i32(); |
| 653 | tcg_gen_addi_i32(ea, cpu_R(dc, a->a), a->i); |
| 654 | tcg_gen_qemu_ld_i32(cpu_R(dc, a->d), ea, dc->mem_idx, mop); |
| 655 | } |
| 656 | |
| 657 | static bool trans_l_lwz(DisasContext *dc, arg_load *a) |
| 658 | { |
| 659 | do_load(dc, a, MO_UL); |
| 660 | return true; |
| 661 | } |
| 662 | |
| 663 | static bool trans_l_lws(DisasContext *dc, arg_load *a) |
| 664 | { |
| 665 | do_load(dc, a, MO_SL); |
| 666 | return true; |
| 667 | } |
| 668 | |
| 669 | static bool trans_l_lbz(DisasContext *dc, arg_load *a) |
| 670 | { |
| 671 | do_load(dc, a, MO_UB); |
| 672 | return true; |
| 673 | } |
| 674 | |
| 675 | static bool trans_l_lbs(DisasContext *dc, arg_load *a) |
| 676 | { |
| 677 | do_load(dc, a, MO_SB); |
| 678 | return true; |
| 679 | } |
| 680 | |
| 681 | static bool trans_l_lhz(DisasContext *dc, arg_load *a) |
| 682 | { |
| 683 | do_load(dc, a, MO_UW); |
| 684 | return true; |
| 685 | } |
| 686 | |
| 687 | static bool trans_l_lhs(DisasContext *dc, arg_load *a) |
| 688 | { |
| 689 | do_load(dc, a, MO_SW); |
| 690 | return true; |
| 691 | } |
| 692 | |
| 693 | static bool trans_l_swa(DisasContext *dc, arg_store *a) |
| 694 | { |
| 695 | TCGv_i32 ea, val; |
| 696 | TCGLabel *lab_fail, *lab_done; |
| 697 | |
| 698 | ea = tcg_temp_new_i32(); |
| 699 | tcg_gen_addi_i32(ea, cpu_R(dc, a->a), a->i); |
| 700 | |
| 701 | lab_fail = gen_new_label(); |
| 702 | lab_done = gen_new_label(); |
| 703 | tcg_gen_brcond_i32(TCG_COND_NE, ea, cpu_lock_addr, lab_fail); |
| 704 | |
| 705 | val = tcg_temp_new_i32(); |
| 706 | tcg_gen_atomic_cmpxchg_i32(val, cpu_lock_addr, cpu_lock_value, |
| 707 | cpu_R(dc, a->b), dc->mem_idx, |
| 708 | mo_endian(dc) | MO_UL); |
| 709 | tcg_gen_setcond_i32(TCG_COND_EQ, cpu_sr_f, val, cpu_lock_value); |
| 710 | |
| 711 | tcg_gen_br(lab_done); |
| 712 | |
| 713 | gen_set_label(lab_fail); |
| 714 | tcg_gen_movi_i32(cpu_sr_f, 0); |
| 715 | |
| 716 | gen_set_label(lab_done); |
| 717 | tcg_gen_movi_i32(cpu_lock_addr, -1); |
| 718 | return true; |
| 719 | } |
| 720 | |
| 721 | static void do_store(DisasContext *dc, arg_store *a, MemOp mop) |
| 722 | { |
| 723 | TCGv_i32 t0 = tcg_temp_new_i32(); |
| 724 | |
| 725 | mop |= mo_endian(dc); |
| 726 | |
| 727 | tcg_gen_addi_i32(t0, cpu_R(dc, a->a), a->i); |
| 728 | tcg_gen_qemu_st_i32(cpu_R(dc, a->b), t0, dc->mem_idx, mop); |
| 729 | } |
| 730 | |
| 731 | static bool trans_l_sw(DisasContext *dc, arg_store *a) |
| 732 | { |
| 733 | do_store(dc, a, MO_UL); |
| 734 | return true; |
| 735 | } |
| 736 | |
| 737 | static bool trans_l_sb(DisasContext *dc, arg_store *a) |
| 738 | { |
| 739 | do_store(dc, a, MO_UB); |
| 740 | return true; |
| 741 | } |
| 742 | |
| 743 | static bool trans_l_sh(DisasContext *dc, arg_store *a) |
| 744 | { |
| 745 | do_store(dc, a, MO_UW); |
| 746 | return true; |
| 747 | } |
| 748 | |
| 749 | static bool trans_l_nop(DisasContext *dc, arg_l_nop *a) |
| 750 | { |
| 751 | return true; |
| 752 | } |
| 753 | |
| 754 | static bool trans_l_adrp(DisasContext *dc, arg_l_adrp *a) |
| 755 | { |
| 756 | if (!check_v1_3(dc)) { |
| 757 | return false; |
| 758 | } |
| 759 | check_r0_write(dc, a->d); |
| 760 | |
| 761 | tcg_gen_movi_i32(cpu_R(dc, a->d), |
| 762 | (dc->base.pc_next & TARGET_PAGE_MASK) + |
| 763 | ((target_long)a->i << TARGET_PAGE_BITS)); |
| 764 | return true; |
| 765 | } |
| 766 | |
| 767 | static bool trans_l_addi(DisasContext *dc, arg_rri *a) |
| 768 | { |
| 769 | check_r0_write(dc, a->d); |
| 770 | gen_add(dc, cpu_R(dc, a->d), cpu_R(dc, a->a), tcg_constant_i32(a->i)); |
| 771 | return true; |
| 772 | } |
| 773 | |
| 774 | static bool trans_l_addic(DisasContext *dc, arg_rri *a) |
| 775 | { |
| 776 | check_r0_write(dc, a->d); |
| 777 | gen_addc(dc, cpu_R(dc, a->d), cpu_R(dc, a->a), tcg_constant_i32(a->i)); |
| 778 | return true; |
| 779 | } |
| 780 | |
| 781 | static bool trans_l_muli(DisasContext *dc, arg_rri *a) |
| 782 | { |
| 783 | check_r0_write(dc, a->d); |
| 784 | gen_mul(dc, cpu_R(dc, a->d), cpu_R(dc, a->a), tcg_constant_i32(a->i)); |
| 785 | return true; |
| 786 | } |
| 787 | |
| 788 | static bool trans_l_maci(DisasContext *dc, arg_l_maci *a) |
| 789 | { |
| 790 | gen_mac(dc, cpu_R(dc, a->a), tcg_constant_i32(a->i)); |
| 791 | return true; |
| 792 | } |
| 793 | |
| 794 | static bool trans_l_andi(DisasContext *dc, arg_rrk *a) |
| 795 | { |
| 796 | check_r0_write(dc, a->d); |
| 797 | tcg_gen_andi_i32(cpu_R(dc, a->d), cpu_R(dc, a->a), a->k); |
| 798 | return true; |
| 799 | } |
| 800 | |
| 801 | static bool trans_l_ori(DisasContext *dc, arg_rrk *a) |
| 802 | { |
| 803 | check_r0_write(dc, a->d); |
| 804 | tcg_gen_ori_i32(cpu_R(dc, a->d), cpu_R(dc, a->a), a->k); |
| 805 | return true; |
| 806 | } |
| 807 | |
| 808 | static bool trans_l_xori(DisasContext *dc, arg_rri *a) |
| 809 | { |
| 810 | check_r0_write(dc, a->d); |
| 811 | tcg_gen_xori_i32(cpu_R(dc, a->d), cpu_R(dc, a->a), a->i); |
| 812 | return true; |
| 813 | } |
| 814 | |
| 815 | static bool trans_l_mfspr(DisasContext *dc, arg_l_mfspr *a) |
| 816 | { |
| 817 | TCGv_i32 spr = tcg_temp_new_i32(); |
| 818 | |
| 819 | check_r0_write(dc, a->d); |
| 820 | |
| 821 | if (translator_io_start(&dc->base)) { |
| 822 | if (dc->delayed_branch) { |
| 823 | tcg_gen_mov_i32(cpu_pc, jmp_pc); |
| 824 | tcg_gen_discard_i32(jmp_pc); |
| 825 | } else { |
| 826 | tcg_gen_movi_i32(cpu_pc, dc->base.pc_next + 4); |
| 827 | } |
| 828 | dc->base.is_jmp = DISAS_EXIT; |
| 829 | } |
| 830 | |
| 831 | tcg_gen_ori_i32(spr, cpu_R(dc, a->a), a->k); |
| 832 | gen_helper_mfspr(cpu_R(dc, a->d), tcg_env, cpu_R(dc, a->d), spr); |
| 833 | return true; |
| 834 | } |
| 835 | |
| 836 | static bool trans_l_mtspr(DisasContext *dc, arg_l_mtspr *a) |
| 837 | { |
| 838 | TCGv_i32 spr = tcg_temp_new_i32(); |
| 839 | |
| 840 | translator_io_start(&dc->base); |
| 841 | |
| 842 | /* |
| 843 | * For SR, we will need to exit the TB to recognize the new |
| 844 | * exception state. For NPC, in theory this counts as a branch |
| 845 | * (although the SPR only exists for use by an ICE). Save all |
| 846 | * of the cpu state first, allowing it to be overwritten. |
| 847 | */ |
| 848 | if (dc->delayed_branch) { |
| 849 | tcg_gen_mov_i32(cpu_pc, jmp_pc); |
| 850 | tcg_gen_discard_i32(jmp_pc); |
| 851 | } else { |
| 852 | tcg_gen_movi_i32(cpu_pc, dc->base.pc_next + 4); |
| 853 | } |
| 854 | dc->base.is_jmp = DISAS_EXIT; |
| 855 | |
| 856 | tcg_gen_ori_i32(spr, cpu_R(dc, a->a), a->k); |
| 857 | gen_helper_mtspr(tcg_env, spr, cpu_R(dc, a->b)); |
| 858 | return true; |
| 859 | } |
| 860 | |
| 861 | static bool trans_l_mac(DisasContext *dc, arg_ab *a) |
| 862 | { |
| 863 | gen_mac(dc, cpu_R(dc, a->a), cpu_R(dc, a->b)); |
| 864 | return true; |
| 865 | } |
| 866 | |
| 867 | static bool trans_l_msb(DisasContext *dc, arg_ab *a) |
| 868 | { |
| 869 | gen_msb(dc, cpu_R(dc, a->a), cpu_R(dc, a->b)); |
| 870 | return true; |
| 871 | } |
| 872 | |
| 873 | static bool trans_l_macu(DisasContext *dc, arg_ab *a) |
| 874 | { |
| 875 | gen_macu(dc, cpu_R(dc, a->a), cpu_R(dc, a->b)); |
| 876 | return true; |
| 877 | } |
| 878 | |
| 879 | static bool trans_l_msbu(DisasContext *dc, arg_ab *a) |
| 880 | { |
| 881 | gen_msbu(dc, cpu_R(dc, a->a), cpu_R(dc, a->b)); |
| 882 | return true; |
| 883 | } |
| 884 | |
| 885 | static bool trans_l_slli(DisasContext *dc, arg_dal *a) |
| 886 | { |
| 887 | check_r0_write(dc, a->d); |
| 888 | tcg_gen_shli_i32(cpu_R(dc, a->d), cpu_R(dc, a->a), |
| 889 | a->l & (TARGET_LONG_BITS - 1)); |
| 890 | return true; |
| 891 | } |
| 892 | |
| 893 | static bool trans_l_srli(DisasContext *dc, arg_dal *a) |
| 894 | { |
| 895 | check_r0_write(dc, a->d); |
| 896 | tcg_gen_shri_i32(cpu_R(dc, a->d), cpu_R(dc, a->a), |
| 897 | a->l & (TARGET_LONG_BITS - 1)); |
| 898 | return true; |
| 899 | } |
| 900 | |
| 901 | static bool trans_l_srai(DisasContext *dc, arg_dal *a) |
| 902 | { |
| 903 | check_r0_write(dc, a->d); |
| 904 | tcg_gen_sari_i32(cpu_R(dc, a->d), cpu_R(dc, a->a), |
| 905 | a->l & (TARGET_LONG_BITS - 1)); |
| 906 | return true; |
| 907 | } |
| 908 | |
| 909 | static bool trans_l_rori(DisasContext *dc, arg_dal *a) |
| 910 | { |
| 911 | check_r0_write(dc, a->d); |
| 912 | tcg_gen_rotri_i32(cpu_R(dc, a->d), cpu_R(dc, a->a), |
| 913 | a->l & (TARGET_LONG_BITS - 1)); |
| 914 | return true; |
| 915 | } |
| 916 | |
| 917 | static bool trans_l_movhi(DisasContext *dc, arg_l_movhi *a) |
| 918 | { |
| 919 | check_r0_write(dc, a->d); |
| 920 | tcg_gen_movi_i32(cpu_R(dc, a->d), a->k << 16); |
| 921 | return true; |
| 922 | } |
| 923 | |
| 924 | static bool trans_l_macrc(DisasContext *dc, arg_l_macrc *a) |
| 925 | { |
| 926 | check_r0_write(dc, a->d); |
| 927 | tcg_gen_extrl_i64_i32(cpu_R(dc, a->d), cpu_mac); |
| 928 | tcg_gen_movi_i64(cpu_mac, 0); |
| 929 | return true; |
| 930 | } |
| 931 | |
| 932 | static bool trans_l_sfeq(DisasContext *dc, arg_ab *a) |
| 933 | { |
| 934 | tcg_gen_setcond_i32(TCG_COND_EQ, cpu_sr_f, |
| 935 | cpu_R(dc, a->a), cpu_R(dc, a->b)); |
| 936 | return true; |
| 937 | } |
| 938 | |
| 939 | static bool trans_l_sfne(DisasContext *dc, arg_ab *a) |
| 940 | { |
| 941 | tcg_gen_setcond_i32(TCG_COND_NE, cpu_sr_f, |
| 942 | cpu_R(dc, a->a), cpu_R(dc, a->b)); |
| 943 | return true; |
| 944 | } |
| 945 | |
| 946 | static bool trans_l_sfgtu(DisasContext *dc, arg_ab *a) |
| 947 | { |
| 948 | tcg_gen_setcond_i32(TCG_COND_GTU, cpu_sr_f, |
| 949 | cpu_R(dc, a->a), cpu_R(dc, a->b)); |
| 950 | return true; |
| 951 | } |
| 952 | |
| 953 | static bool trans_l_sfgeu(DisasContext *dc, arg_ab *a) |
| 954 | { |
| 955 | tcg_gen_setcond_i32(TCG_COND_GEU, cpu_sr_f, |
| 956 | cpu_R(dc, a->a), cpu_R(dc, a->b)); |
| 957 | return true; |
| 958 | } |
| 959 | |
| 960 | static bool trans_l_sfltu(DisasContext *dc, arg_ab *a) |
| 961 | { |
| 962 | tcg_gen_setcond_i32(TCG_COND_LTU, cpu_sr_f, |
| 963 | cpu_R(dc, a->a), cpu_R(dc, a->b)); |
| 964 | return true; |
| 965 | } |
| 966 | |
| 967 | static bool trans_l_sfleu(DisasContext *dc, arg_ab *a) |
| 968 | { |
| 969 | tcg_gen_setcond_i32(TCG_COND_LEU, cpu_sr_f, |
| 970 | cpu_R(dc, a->a), cpu_R(dc, a->b)); |
| 971 | return true; |
| 972 | } |
| 973 | |
| 974 | static bool trans_l_sfgts(DisasContext *dc, arg_ab *a) |
| 975 | { |
| 976 | tcg_gen_setcond_i32(TCG_COND_GT, cpu_sr_f, |
| 977 | cpu_R(dc, a->a), cpu_R(dc, a->b)); |
| 978 | return true; |
| 979 | } |
| 980 | |
| 981 | static bool trans_l_sfges(DisasContext *dc, arg_ab *a) |
| 982 | { |
| 983 | tcg_gen_setcond_i32(TCG_COND_GE, cpu_sr_f, |
| 984 | cpu_R(dc, a->a), cpu_R(dc, a->b)); |
| 985 | return true; |
| 986 | } |
| 987 | |
| 988 | static bool trans_l_sflts(DisasContext *dc, arg_ab *a) |
| 989 | { |
| 990 | tcg_gen_setcond_i32(TCG_COND_LT, cpu_sr_f, |
| 991 | cpu_R(dc, a->a), cpu_R(dc, a->b)); |
| 992 | return true; |
| 993 | } |
| 994 | |
| 995 | static bool trans_l_sfles(DisasContext *dc, arg_ab *a) |
| 996 | { |
| 997 | tcg_gen_setcond_i32(TCG_COND_LE, |
| 998 | cpu_sr_f, cpu_R(dc, a->a), cpu_R(dc, a->b)); |
| 999 | return true; |
| 1000 | } |
| 1001 | |
| 1002 | static bool trans_l_sfeqi(DisasContext *dc, arg_ai *a) |
| 1003 | { |
| 1004 | tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_sr_f, cpu_R(dc, a->a), a->i); |
| 1005 | return true; |
| 1006 | } |
| 1007 | |
| 1008 | static bool trans_l_sfnei(DisasContext *dc, arg_ai *a) |
| 1009 | { |
| 1010 | tcg_gen_setcondi_i32(TCG_COND_NE, cpu_sr_f, cpu_R(dc, a->a), a->i); |
| 1011 | return true; |
| 1012 | } |
| 1013 | |
| 1014 | static bool trans_l_sfgtui(DisasContext *dc, arg_ai *a) |
| 1015 | { |
| 1016 | tcg_gen_setcondi_i32(TCG_COND_GTU, cpu_sr_f, cpu_R(dc, a->a), a->i); |
| 1017 | return true; |
| 1018 | } |
| 1019 | |
| 1020 | static bool trans_l_sfgeui(DisasContext *dc, arg_ai *a) |
| 1021 | { |
| 1022 | tcg_gen_setcondi_i32(TCG_COND_GEU, cpu_sr_f, cpu_R(dc, a->a), a->i); |
| 1023 | return true; |
| 1024 | } |
| 1025 | |
| 1026 | static bool trans_l_sfltui(DisasContext *dc, arg_ai *a) |
| 1027 | { |
| 1028 | tcg_gen_setcondi_i32(TCG_COND_LTU, cpu_sr_f, cpu_R(dc, a->a), a->i); |
| 1029 | return true; |
| 1030 | } |
| 1031 | |
| 1032 | static bool trans_l_sfleui(DisasContext *dc, arg_ai *a) |
| 1033 | { |
| 1034 | tcg_gen_setcondi_i32(TCG_COND_LEU, cpu_sr_f, cpu_R(dc, a->a), a->i); |
| 1035 | return true; |
| 1036 | } |
| 1037 | |
| 1038 | static bool trans_l_sfgtsi(DisasContext *dc, arg_ai *a) |
| 1039 | { |
| 1040 | tcg_gen_setcondi_i32(TCG_COND_GT, cpu_sr_f, cpu_R(dc, a->a), a->i); |
| 1041 | return true; |
| 1042 | } |
| 1043 | |
| 1044 | static bool trans_l_sfgesi(DisasContext *dc, arg_ai *a) |
| 1045 | { |
| 1046 | tcg_gen_setcondi_i32(TCG_COND_GE, cpu_sr_f, cpu_R(dc, a->a), a->i); |
| 1047 | return true; |
| 1048 | } |
| 1049 | |
| 1050 | static bool trans_l_sfltsi(DisasContext *dc, arg_ai *a) |
| 1051 | { |
| 1052 | tcg_gen_setcondi_i32(TCG_COND_LT, cpu_sr_f, cpu_R(dc, a->a), a->i); |
| 1053 | return true; |
| 1054 | } |
| 1055 | |
| 1056 | static bool trans_l_sflesi(DisasContext *dc, arg_ai *a) |
| 1057 | { |
| 1058 | tcg_gen_setcondi_i32(TCG_COND_LE, cpu_sr_f, cpu_R(dc, a->a), a->i); |
| 1059 | return true; |
| 1060 | } |
| 1061 | |
| 1062 | static bool trans_l_sys(DisasContext *dc, arg_l_sys *a) |
| 1063 | { |
| 1064 | tcg_gen_movi_i32(cpu_pc, dc->base.pc_next); |
| 1065 | gen_exception(dc, EXCP_SYSCALL); |
| 1066 | dc->base.is_jmp = DISAS_NORETURN; |
| 1067 | return true; |
| 1068 | } |
| 1069 | |
| 1070 | static bool trans_l_trap(DisasContext *dc, arg_l_trap *a) |
| 1071 | { |
| 1072 | tcg_gen_movi_i32(cpu_pc, dc->base.pc_next); |
| 1073 | gen_exception(dc, EXCP_TRAP); |
| 1074 | dc->base.is_jmp = DISAS_NORETURN; |
| 1075 | return true; |
| 1076 | } |
| 1077 | |
| 1078 | static bool trans_l_msync(DisasContext *dc, arg_l_msync *a) |
| 1079 | { |
| 1080 | tcg_gen_mb(TCG_MO_ALL); |
| 1081 | return true; |
| 1082 | } |
| 1083 | |
| 1084 | static bool trans_l_psync(DisasContext *dc, arg_l_psync *a) |
| 1085 | { |
| 1086 | return true; |
| 1087 | } |
| 1088 | |
| 1089 | static bool trans_l_csync(DisasContext *dc, arg_l_csync *a) |
| 1090 | { |
| 1091 | return true; |
| 1092 | } |
| 1093 | |
| 1094 | static bool trans_l_rfe(DisasContext *dc, arg_l_rfe *a) |
| 1095 | { |
| 1096 | if (is_user(dc)) { |
| 1097 | gen_illegal_exception(dc); |
| 1098 | } else { |
| 1099 | gen_helper_rfe(tcg_env); |
| 1100 | dc->base.is_jmp = DISAS_EXIT; |
| 1101 | } |
| 1102 | return true; |
| 1103 | } |
| 1104 | |
| 1105 | static bool do_fp2(DisasContext *dc, arg_da *a, |
| 1106 | void (*fn)(TCGv_i32, TCGv_env, TCGv_i32)) |
| 1107 | { |
| 1108 | if (!check_of32s(dc)) { |
| 1109 | return false; |
| 1110 | } |
| 1111 | check_r0_write(dc, a->d); |
| 1112 | fn(cpu_R(dc, a->d), tcg_env, cpu_R(dc, a->a)); |
| 1113 | gen_helper_update_fpcsr(tcg_env); |
| 1114 | return true; |
| 1115 | } |
| 1116 | |
| 1117 | static bool do_fp3(DisasContext *dc, arg_dab *a, |
| 1118 | void (*fn)(TCGv_i32, TCGv_env, TCGv_i32, TCGv_i32)) |
| 1119 | { |
| 1120 | if (!check_of32s(dc)) { |
| 1121 | return false; |
| 1122 | } |
| 1123 | check_r0_write(dc, a->d); |
| 1124 | fn(cpu_R(dc, a->d), tcg_env, cpu_R(dc, a->a), cpu_R(dc, a->b)); |
| 1125 | gen_helper_update_fpcsr(tcg_env); |
| 1126 | return true; |
| 1127 | } |
| 1128 | |
| 1129 | static bool do_fpcmp(DisasContext *dc, arg_ab *a, |
| 1130 | void (*fn)(TCGv_i32, TCGv_env, TCGv_i32, TCGv_i32), |
| 1131 | bool inv, bool swap) |
| 1132 | { |
| 1133 | if (!check_of32s(dc)) { |
| 1134 | return false; |
| 1135 | } |
| 1136 | if (swap) { |
| 1137 | fn(cpu_sr_f, tcg_env, cpu_R(dc, a->b), cpu_R(dc, a->a)); |
| 1138 | } else { |
| 1139 | fn(cpu_sr_f, tcg_env, cpu_R(dc, a->a), cpu_R(dc, a->b)); |
| 1140 | } |
| 1141 | if (inv) { |
| 1142 | tcg_gen_xori_i32(cpu_sr_f, cpu_sr_f, 1); |
| 1143 | } |
| 1144 | gen_helper_update_fpcsr(tcg_env); |
| 1145 | return true; |
| 1146 | } |
| 1147 | |
| 1148 | static bool trans_lf_add_s(DisasContext *dc, arg_dab *a) |
| 1149 | { |
| 1150 | return do_fp3(dc, a, gen_helper_float_add_s); |
| 1151 | } |
| 1152 | |
| 1153 | static bool trans_lf_sub_s(DisasContext *dc, arg_dab *a) |
| 1154 | { |
| 1155 | return do_fp3(dc, a, gen_helper_float_sub_s); |
| 1156 | } |
| 1157 | |
| 1158 | static bool trans_lf_mul_s(DisasContext *dc, arg_dab *a) |
| 1159 | { |
| 1160 | return do_fp3(dc, a, gen_helper_float_mul_s); |
| 1161 | } |
| 1162 | |
| 1163 | static bool trans_lf_div_s(DisasContext *dc, arg_dab *a) |
| 1164 | { |
| 1165 | return do_fp3(dc, a, gen_helper_float_div_s); |
| 1166 | } |
| 1167 | |
| 1168 | static bool trans_lf_rem_s(DisasContext *dc, arg_dab *a) |
| 1169 | { |
| 1170 | return do_fp3(dc, a, gen_helper_float_rem_s); |
| 1171 | return true; |
| 1172 | } |
| 1173 | |
| 1174 | static bool trans_lf_itof_s(DisasContext *dc, arg_da *a) |
| 1175 | { |
| 1176 | return do_fp2(dc, a, gen_helper_itofs); |
| 1177 | } |
| 1178 | |
| 1179 | static bool trans_lf_ftoi_s(DisasContext *dc, arg_da *a) |
| 1180 | { |
| 1181 | return do_fp2(dc, a, gen_helper_ftois); |
| 1182 | } |
| 1183 | |
| 1184 | static bool trans_lf_madd_s(DisasContext *dc, arg_dab *a) |
| 1185 | { |
| 1186 | if (!check_of32s(dc)) { |
| 1187 | return false; |
| 1188 | } |
| 1189 | check_r0_write(dc, a->d); |
| 1190 | gen_helper_float_madd_s(cpu_R(dc, a->d), tcg_env, cpu_R(dc, a->d), |
| 1191 | cpu_R(dc, a->a), cpu_R(dc, a->b)); |
| 1192 | gen_helper_update_fpcsr(tcg_env); |
| 1193 | return true; |
| 1194 | } |
| 1195 | |
| 1196 | static bool trans_lf_sfeq_s(DisasContext *dc, arg_ab *a) |
| 1197 | { |
| 1198 | return do_fpcmp(dc, a, gen_helper_float_eq_s, false, false); |
| 1199 | } |
| 1200 | |
| 1201 | static bool trans_lf_sfne_s(DisasContext *dc, arg_ab *a) |
| 1202 | { |
| 1203 | return do_fpcmp(dc, a, gen_helper_float_eq_s, true, false); |
| 1204 | } |
| 1205 | |
| 1206 | static bool trans_lf_sfgt_s(DisasContext *dc, arg_ab *a) |
| 1207 | { |
| 1208 | return do_fpcmp(dc, a, gen_helper_float_lt_s, false, true); |
| 1209 | } |
| 1210 | |
| 1211 | static bool trans_lf_sfge_s(DisasContext *dc, arg_ab *a) |
| 1212 | { |
| 1213 | return do_fpcmp(dc, a, gen_helper_float_le_s, false, true); |
| 1214 | } |
| 1215 | |
| 1216 | static bool trans_lf_sflt_s(DisasContext *dc, arg_ab *a) |
| 1217 | { |
| 1218 | return do_fpcmp(dc, a, gen_helper_float_lt_s, false, false); |
| 1219 | } |
| 1220 | |
| 1221 | static bool trans_lf_sfle_s(DisasContext *dc, arg_ab *a) |
| 1222 | { |
| 1223 | return do_fpcmp(dc, a, gen_helper_float_le_s, false, false); |
| 1224 | } |
| 1225 | |
| 1226 | static bool trans_lf_sfueq_s(DisasContext *dc, arg_ab *a) |
| 1227 | { |
| 1228 | if (!check_v1_3(dc)) { |
| 1229 | return false; |
| 1230 | } |
| 1231 | return do_fpcmp(dc, a, gen_helper_float_ueq_s, false, false); |
| 1232 | } |
| 1233 | |
| 1234 | static bool trans_lf_sfult_s(DisasContext *dc, arg_ab *a) |
| 1235 | { |
| 1236 | if (!check_v1_3(dc)) { |
| 1237 | return false; |
| 1238 | } |
| 1239 | return do_fpcmp(dc, a, gen_helper_float_ult_s, false, false); |
| 1240 | } |
| 1241 | |
| 1242 | static bool trans_lf_sfugt_s(DisasContext *dc, arg_ab *a) |
| 1243 | { |
| 1244 | if (!check_v1_3(dc)) { |
| 1245 | return false; |
| 1246 | } |
| 1247 | return do_fpcmp(dc, a, gen_helper_float_ult_s, false, true); |
| 1248 | } |
| 1249 | |
| 1250 | static bool trans_lf_sfule_s(DisasContext *dc, arg_ab *a) |
| 1251 | { |
| 1252 | if (!check_v1_3(dc)) { |
| 1253 | return false; |
| 1254 | } |
| 1255 | return do_fpcmp(dc, a, gen_helper_float_ule_s, false, false); |
| 1256 | } |
| 1257 | |
| 1258 | static bool trans_lf_sfuge_s(DisasContext *dc, arg_ab *a) |
| 1259 | { |
| 1260 | if (!check_v1_3(dc)) { |
| 1261 | return false; |
| 1262 | } |
| 1263 | return do_fpcmp(dc, a, gen_helper_float_ule_s, false, true); |
| 1264 | } |
| 1265 | |
| 1266 | static bool trans_lf_sfun_s(DisasContext *dc, arg_ab *a) |
| 1267 | { |
| 1268 | if (!check_v1_3(dc)) { |
| 1269 | return false; |
| 1270 | } |
| 1271 | return do_fpcmp(dc, a, gen_helper_float_un_s, false, false); |
| 1272 | } |
| 1273 | |
| 1274 | static bool check_pair(DisasContext *dc, int r, int p) |
| 1275 | { |
| 1276 | return r + 1 + p < 32; |
| 1277 | } |
| 1278 | |
| 1279 | static void load_pair(DisasContext *dc, TCGv_i64 t, int r, int p) |
| 1280 | { |
| 1281 | tcg_gen_concat_i32_i64(t, cpu_R(dc, r + 1 + p), cpu_R(dc, r)); |
| 1282 | } |
| 1283 | |
| 1284 | static void save_pair(DisasContext *dc, TCGv_i64 t, int r, int p) |
| 1285 | { |
| 1286 | tcg_gen_extr_i64_i32(cpu_R(dc, r + 1 + p), cpu_R(dc, r), t); |
| 1287 | } |
| 1288 | |
| 1289 | static bool do_dp3(DisasContext *dc, arg_dab_pair *a, |
| 1290 | void (*fn)(TCGv_i64, TCGv_env, TCGv_i64, TCGv_i64)) |
| 1291 | { |
| 1292 | TCGv_i64 t0, t1; |
| 1293 | |
| 1294 | if (!check_of64a32s(dc) || |
| 1295 | !check_pair(dc, a->a, a->ap) || |
| 1296 | !check_pair(dc, a->b, a->bp) || |
| 1297 | !check_pair(dc, a->d, a->dp)) { |
| 1298 | return false; |
| 1299 | } |
| 1300 | check_r0_write(dc, a->d); |
| 1301 | |
| 1302 | t0 = tcg_temp_new_i64(); |
| 1303 | t1 = tcg_temp_new_i64(); |
| 1304 | load_pair(dc, t0, a->a, a->ap); |
| 1305 | load_pair(dc, t1, a->b, a->bp); |
| 1306 | fn(t0, tcg_env, t0, t1); |
| 1307 | save_pair(dc, t0, a->d, a->dp); |
| 1308 | |
| 1309 | gen_helper_update_fpcsr(tcg_env); |
| 1310 | return true; |
| 1311 | } |
| 1312 | |
| 1313 | static bool do_dp2(DisasContext *dc, arg_da_pair *a, |
| 1314 | void (*fn)(TCGv_i64, TCGv_env, TCGv_i64)) |
| 1315 | { |
| 1316 | TCGv_i64 t0; |
| 1317 | |
| 1318 | if (!check_of64a32s(dc) || |
| 1319 | !check_pair(dc, a->a, a->ap) || |
| 1320 | !check_pair(dc, a->d, a->dp)) { |
| 1321 | return false; |
| 1322 | } |
| 1323 | check_r0_write(dc, a->d); |
| 1324 | |
| 1325 | t0 = tcg_temp_new_i64(); |
| 1326 | load_pair(dc, t0, a->a, a->ap); |
| 1327 | fn(t0, tcg_env, t0); |
| 1328 | save_pair(dc, t0, a->d, a->dp); |
| 1329 | |
| 1330 | gen_helper_update_fpcsr(tcg_env); |
| 1331 | return true; |
| 1332 | } |
| 1333 | |
| 1334 | static bool do_dpcmp(DisasContext *dc, arg_ab_pair *a, |
| 1335 | void (*fn)(TCGv_i32, TCGv_env, TCGv_i64, TCGv_i64), |
| 1336 | bool inv, bool swap) |
| 1337 | { |
| 1338 | TCGv_i64 t0, t1; |
| 1339 | |
| 1340 | if (!check_of64a32s(dc) || |
| 1341 | !check_pair(dc, a->a, a->ap) || |
| 1342 | !check_pair(dc, a->b, a->bp)) { |
| 1343 | return false; |
| 1344 | } |
| 1345 | |
| 1346 | t0 = tcg_temp_new_i64(); |
| 1347 | t1 = tcg_temp_new_i64(); |
| 1348 | load_pair(dc, t0, a->a, a->ap); |
| 1349 | load_pair(dc, t1, a->b, a->bp); |
| 1350 | if (swap) { |
| 1351 | fn(cpu_sr_f, tcg_env, t1, t0); |
| 1352 | } else { |
| 1353 | fn(cpu_sr_f, tcg_env, t0, t1); |
| 1354 | } |
| 1355 | |
| 1356 | if (inv) { |
| 1357 | tcg_gen_xori_i32(cpu_sr_f, cpu_sr_f, 1); |
| 1358 | } |
| 1359 | gen_helper_update_fpcsr(tcg_env); |
| 1360 | return true; |
| 1361 | } |
| 1362 | |
| 1363 | static bool trans_lf_add_d(DisasContext *dc, arg_dab_pair *a) |
| 1364 | { |
| 1365 | return do_dp3(dc, a, gen_helper_float_add_d); |
| 1366 | } |
| 1367 | |
| 1368 | static bool trans_lf_sub_d(DisasContext *dc, arg_dab_pair *a) |
| 1369 | { |
| 1370 | return do_dp3(dc, a, gen_helper_float_sub_d); |
| 1371 | } |
| 1372 | |
| 1373 | static bool trans_lf_mul_d(DisasContext *dc, arg_dab_pair *a) |
| 1374 | { |
| 1375 | return do_dp3(dc, a, gen_helper_float_mul_d); |
| 1376 | } |
| 1377 | |
| 1378 | static bool trans_lf_div_d(DisasContext *dc, arg_dab_pair *a) |
| 1379 | { |
| 1380 | return do_dp3(dc, a, gen_helper_float_div_d); |
| 1381 | } |
| 1382 | |
| 1383 | static bool trans_lf_rem_d(DisasContext *dc, arg_dab_pair *a) |
| 1384 | { |
| 1385 | return do_dp3(dc, a, gen_helper_float_rem_d); |
| 1386 | } |
| 1387 | |
| 1388 | static bool trans_lf_itof_d(DisasContext *dc, arg_da_pair *a) |
| 1389 | { |
| 1390 | return do_dp2(dc, a, gen_helper_itofd); |
| 1391 | } |
| 1392 | |
| 1393 | static bool trans_lf_ftoi_d(DisasContext *dc, arg_da_pair *a) |
| 1394 | { |
| 1395 | return do_dp2(dc, a, gen_helper_ftoid); |
| 1396 | } |
| 1397 | |
| 1398 | static bool trans_lf_stod_d(DisasContext *dc, arg_lf_stod_d *a) |
| 1399 | { |
| 1400 | TCGv_i64 t0; |
| 1401 | |
| 1402 | if (!check_of64a32s(dc) || |
| 1403 | !check_pair(dc, a->d, a->dp)) { |
| 1404 | return false; |
| 1405 | } |
| 1406 | check_r0_write(dc, a->d); |
| 1407 | |
| 1408 | t0 = tcg_temp_new_i64(); |
| 1409 | gen_helper_stod(t0, tcg_env, cpu_R(dc, a->a)); |
| 1410 | save_pair(dc, t0, a->d, a->dp); |
| 1411 | |
| 1412 | gen_helper_update_fpcsr(tcg_env); |
| 1413 | return true; |
| 1414 | } |
| 1415 | |
| 1416 | static bool trans_lf_dtos_d(DisasContext *dc, arg_lf_dtos_d *a) |
| 1417 | { |
| 1418 | TCGv_i64 t0; |
| 1419 | |
| 1420 | if (!check_of64a32s(dc) || |
| 1421 | !check_pair(dc, a->a, a->ap)) { |
| 1422 | return false; |
| 1423 | } |
| 1424 | check_r0_write(dc, a->d); |
| 1425 | |
| 1426 | t0 = tcg_temp_new_i64(); |
| 1427 | load_pair(dc, t0, a->a, a->ap); |
| 1428 | gen_helper_dtos(cpu_R(dc, a->d), tcg_env, t0); |
| 1429 | |
| 1430 | gen_helper_update_fpcsr(tcg_env); |
| 1431 | return true; |
| 1432 | } |
| 1433 | |
| 1434 | static bool trans_lf_madd_d(DisasContext *dc, arg_dab_pair *a) |
| 1435 | { |
| 1436 | TCGv_i64 t0, t1, t2; |
| 1437 | |
| 1438 | if (!check_of64a32s(dc) || |
| 1439 | !check_pair(dc, a->a, a->ap) || |
| 1440 | !check_pair(dc, a->b, a->bp) || |
| 1441 | !check_pair(dc, a->d, a->dp)) { |
| 1442 | return false; |
| 1443 | } |
| 1444 | check_r0_write(dc, a->d); |
| 1445 | |
| 1446 | t0 = tcg_temp_new_i64(); |
| 1447 | t1 = tcg_temp_new_i64(); |
| 1448 | t2 = tcg_temp_new_i64(); |
| 1449 | load_pair(dc, t0, a->d, a->dp); |
| 1450 | load_pair(dc, t1, a->a, a->ap); |
| 1451 | load_pair(dc, t2, a->b, a->bp); |
| 1452 | gen_helper_float_madd_d(t0, tcg_env, t0, t1, t2); |
| 1453 | save_pair(dc, t0, a->d, a->dp); |
| 1454 | |
| 1455 | gen_helper_update_fpcsr(tcg_env); |
| 1456 | return true; |
| 1457 | } |
| 1458 | |
| 1459 | static bool trans_lf_sfeq_d(DisasContext *dc, arg_ab_pair *a) |
| 1460 | { |
| 1461 | return do_dpcmp(dc, a, gen_helper_float_eq_d, false, false); |
| 1462 | } |
| 1463 | |
| 1464 | static bool trans_lf_sfne_d(DisasContext *dc, arg_ab_pair *a) |
| 1465 | { |
| 1466 | return do_dpcmp(dc, a, gen_helper_float_eq_d, true, false); |
| 1467 | } |
| 1468 | |
| 1469 | static bool trans_lf_sfgt_d(DisasContext *dc, arg_ab_pair *a) |
| 1470 | { |
| 1471 | return do_dpcmp(dc, a, gen_helper_float_lt_d, false, true); |
| 1472 | } |
| 1473 | |
| 1474 | static bool trans_lf_sfge_d(DisasContext *dc, arg_ab_pair *a) |
| 1475 | { |
| 1476 | return do_dpcmp(dc, a, gen_helper_float_le_d, false, true); |
| 1477 | } |
| 1478 | |
| 1479 | static bool trans_lf_sflt_d(DisasContext *dc, arg_ab_pair *a) |
| 1480 | { |
| 1481 | return do_dpcmp(dc, a, gen_helper_float_lt_d, false, false); |
| 1482 | } |
| 1483 | |
| 1484 | static bool trans_lf_sfle_d(DisasContext *dc, arg_ab_pair *a) |
| 1485 | { |
| 1486 | return do_dpcmp(dc, a, gen_helper_float_le_d, false, false); |
| 1487 | } |
| 1488 | |
| 1489 | static bool trans_lf_sfueq_d(DisasContext *dc, arg_ab_pair *a) |
| 1490 | { |
| 1491 | return do_dpcmp(dc, a, gen_helper_float_ueq_d, false, false); |
| 1492 | } |
| 1493 | |
| 1494 | static bool trans_lf_sfule_d(DisasContext *dc, arg_ab_pair *a) |
| 1495 | { |
| 1496 | return do_dpcmp(dc, a, gen_helper_float_ule_d, false, false); |
| 1497 | } |
| 1498 | |
| 1499 | static bool trans_lf_sfuge_d(DisasContext *dc, arg_ab_pair *a) |
| 1500 | { |
| 1501 | return do_dpcmp(dc, a, gen_helper_float_ule_d, false, true); |
| 1502 | } |
| 1503 | |
| 1504 | static bool trans_lf_sfult_d(DisasContext *dc, arg_ab_pair *a) |
| 1505 | { |
| 1506 | return do_dpcmp(dc, a, gen_helper_float_ult_d, false, false); |
| 1507 | } |
| 1508 | |
| 1509 | static bool trans_lf_sfugt_d(DisasContext *dc, arg_ab_pair *a) |
| 1510 | { |
| 1511 | return do_dpcmp(dc, a, gen_helper_float_ult_d, false, true); |
| 1512 | } |
| 1513 | |
| 1514 | static bool trans_lf_sfun_d(DisasContext *dc, arg_ab_pair *a) |
| 1515 | { |
| 1516 | return do_dpcmp(dc, a, gen_helper_float_un_d, false, false); |
| 1517 | } |
| 1518 | |
| 1519 | static void openrisc_tr_init_disas_context(DisasContextBase *dcb, CPUState *cs) |
| 1520 | { |
| 1521 | DisasContext *dc = container_of(dcb, DisasContext, base); |
| 1522 | CPUOpenRISCState *env = cpu_env(cs); |
| 1523 | int bound; |
| 1524 | |
| 1525 | dc->mem_idx = cpu_mmu_index(cs, false); |
| 1526 | dc->tb_flags = dc->base.tb->flags; |
| 1527 | dc->delayed_branch = (dc->tb_flags & TB_FLAGS_DFLAG) != 0; |
| 1528 | dc->cpucfgr = env->cpucfgr; |
| 1529 | dc->avr = env->avr; |
| 1530 | dc->jmp_pc_imm = -1; |
| 1531 | |
| 1532 | bound = -(dc->base.pc_first | TARGET_PAGE_MASK) / 4; |
| 1533 | dc->base.max_insns = MIN(dc->base.max_insns, bound); |
| 1534 | } |
| 1535 | |
| 1536 | static void openrisc_tr_tb_start(DisasContextBase *db, CPUState *cs) |
| 1537 | { |
| 1538 | DisasContext *dc = container_of(db, DisasContext, base); |
| 1539 | |
| 1540 | /* Allow the TCG optimizer to see that R0 == 0, |
| 1541 | when it's true, which is the common case. */ |
| 1542 | dc->zero = tcg_constant_i32(0); |
| 1543 | if (dc->tb_flags & TB_FLAGS_R0_0) { |
| 1544 | dc->R0 = dc->zero; |
| 1545 | } else { |
| 1546 | dc->R0 = cpu_regs[0]; |
| 1547 | } |
| 1548 | } |
| 1549 | |
| 1550 | static void openrisc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) |
| 1551 | { |
| 1552 | DisasContext *dc = container_of(dcbase, DisasContext, base); |
| 1553 | |
| 1554 | tcg_gen_insn_start(dc->base.pc_next, (dc->delayed_branch ? 1 : 0) |
| 1555 | | (dc->base.num_insns > 1 ? 2 : 0), 0); |
| 1556 | } |
| 1557 | |
| 1558 | static void openrisc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) |
| 1559 | { |
| 1560 | DisasContext *dc = container_of(dcbase, DisasContext, base); |
| 1561 | uint32_t insn = translator_ldl_end(cpu_env(cs), &dc->base, |
| 1562 | dc->base.pc_next, mo_endian(dc)); |
| 1563 | |
| 1564 | if (!decode(dc, insn)) { |
| 1565 | gen_illegal_exception(dc); |
| 1566 | } |
| 1567 | dc->base.pc_next += 4; |
| 1568 | |
| 1569 | /* When exiting the delay slot normally, exit via jmp_pc. |
| 1570 | * For DISAS_NORETURN, we have raised an exception and already exited. |
| 1571 | * For DISAS_EXIT, we found l.rfe in a delay slot. There's nothing |
| 1572 | * in the manual saying this is illegal, but it surely it should. |
| 1573 | * At least or1ksim overrides pcnext and ignores the branch. |
| 1574 | */ |
| 1575 | if (dc->delayed_branch |
| 1576 | && --dc->delayed_branch == 0 |
| 1577 | && dc->base.is_jmp == DISAS_NEXT) { |
| 1578 | dc->base.is_jmp = DISAS_JUMP; |
| 1579 | } |
| 1580 | } |
| 1581 | |
| 1582 | static void openrisc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) |
| 1583 | { |
| 1584 | DisasContext *dc = container_of(dcbase, DisasContext, base); |
| 1585 | vaddr jmp_dest; |
| 1586 | |
| 1587 | /* If we have already exited the TB, nothing following has effect. */ |
| 1588 | if (dc->base.is_jmp == DISAS_NORETURN) { |
| 1589 | return; |
| 1590 | } |
| 1591 | |
| 1592 | /* Adjust the delayed branch state for the next TB. */ |
| 1593 | if ((dc->tb_flags & TB_FLAGS_DFLAG ? 1 : 0) != (dc->delayed_branch != 0)) { |
| 1594 | tcg_gen_movi_i32(cpu_dflag, dc->delayed_branch != 0); |
| 1595 | } |
| 1596 | |
| 1597 | /* For DISAS_TOO_MANY, jump to the next insn. */ |
| 1598 | jmp_dest = dc->base.pc_next; |
| 1599 | tcg_gen_movi_i32(cpu_ppc, jmp_dest - 4); |
| 1600 | |
| 1601 | switch (dc->base.is_jmp) { |
| 1602 | case DISAS_JUMP: |
| 1603 | jmp_dest = dc->jmp_pc_imm; |
| 1604 | if (jmp_dest == -1) { |
| 1605 | /* The jump destination is indirect/computed; use jmp_pc. */ |
| 1606 | tcg_gen_mov_i32(cpu_pc, jmp_pc); |
| 1607 | tcg_gen_discard_i32(jmp_pc); |
| 1608 | tcg_gen_lookup_and_goto_ptr(); |
| 1609 | break; |
| 1610 | } |
| 1611 | /* The jump destination is direct; use jmp_pc_imm. |
| 1612 | However, we will have stored into jmp_pc as well; |
| 1613 | we know now that it wasn't needed. */ |
| 1614 | tcg_gen_discard_i32(jmp_pc); |
| 1615 | /* fallthru */ |
| 1616 | |
| 1617 | case DISAS_TOO_MANY: |
| 1618 | if (translator_use_goto_tb(&dc->base, jmp_dest)) { |
| 1619 | tcg_gen_goto_tb(0); |
| 1620 | tcg_gen_movi_i32(cpu_pc, jmp_dest); |
| 1621 | tcg_gen_exit_tb(dc->base.tb, 0); |
| 1622 | break; |
| 1623 | } |
| 1624 | tcg_gen_movi_i32(cpu_pc, jmp_dest); |
| 1625 | tcg_gen_lookup_and_goto_ptr(); |
| 1626 | break; |
| 1627 | |
| 1628 | case DISAS_EXIT: |
| 1629 | tcg_gen_exit_tb(NULL, 0); |
| 1630 | break; |
| 1631 | default: |
| 1632 | g_assert_not_reached(); |
| 1633 | } |
| 1634 | } |
| 1635 | |
| 1636 | static const TranslatorOps openrisc_tr_ops = { |
| 1637 | .init_disas_context = openrisc_tr_init_disas_context, |
| 1638 | .tb_start = openrisc_tr_tb_start, |
| 1639 | .insn_start = openrisc_tr_insn_start, |
| 1640 | .translate_insn = openrisc_tr_translate_insn, |
| 1641 | .tb_stop = openrisc_tr_tb_stop, |
| 1642 | }; |
| 1643 | |
| 1644 | void openrisc_translate_code(CPUState *cs, TranslationBlock *tb, |
| 1645 | int *max_insns, vaddr pc, void *host_pc) |
| 1646 | { |
| 1647 | DisasContext ctx; |
| 1648 | |
| 1649 | translator_loop(cs, tb, max_insns, pc, host_pc, |
| 1650 | &openrisc_tr_ops, &ctx.base, |
| 1651 | TCG_TYPE_VA); |
| 1652 | } |
| 1653 | |
| 1654 | void openrisc_cpu_dump_state(CPUState *cs, FILE *f, int flags) |
| 1655 | { |
| 1656 | CPUOpenRISCState *env = cpu_env(cs); |
| 1657 | int i; |
| 1658 | |
| 1659 | qemu_fprintf(f, "PC=%08x\n", env->pc); |
| 1660 | for (i = 0; i < 32; ++i) { |
| 1661 | qemu_fprintf(f, "R%02d=%08x%c", i, cpu_get_gpr(env, i), |
| 1662 | (i % 4) == 3 ? '\n' : ' '); |
| 1663 | } |
| 1664 | } |