| 1 | /* |
| 2 | * PowerPC CPU routines for qemu. |
| 3 | * |
| 4 | * Copyright (c) 2017 Nikunj A Dadhania, IBM Corporation. |
| 5 | * |
| 6 | * This library is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU Lesser General Public |
| 8 | * License as published by the Free Software Foundation; either |
| 9 | * version 2.1 of the License, or (at your option) any later version. |
| 10 | * |
| 11 | * This library is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 14 | * Lesser General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU Lesser General Public |
| 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
| 18 | */ |
| 19 | |
| 20 | #include "qemu/osdep.h" |
| 21 | #include "cpu.h" |
| 22 | #include "cpu-models.h" |
| 23 | #include "cpu-qom.h" |
| 24 | #include "exec/log.h" |
| 25 | #include "exec/watchpoint.h" |
| 26 | #include "fpu/softfloat-helpers.h" |
| 27 | #include "mmu-hash64.h" |
| 28 | #include "helper_regs.h" |
| 29 | #include "system/tcg.h" |
| 30 | |
| 31 | target_ulong cpu_read_xer(const CPUPPCState *env) |
| 32 | { |
| 33 | if (is_isa300(env)) { |
| 34 | return env->xer | (env->so << XER_SO) | |
| 35 | (env->ov << XER_OV) | (env->ca << XER_CA) | |
| 36 | (env->ov32 << XER_OV32) | (env->ca32 << XER_CA32); |
| 37 | } |
| 38 | |
| 39 | return env->xer | (env->so << XER_SO) | (env->ov << XER_OV) | |
| 40 | (env->ca << XER_CA); |
| 41 | } |
| 42 | |
| 43 | void cpu_write_xer(CPUPPCState *env, target_ulong xer) |
| 44 | { |
| 45 | env->so = (xer >> XER_SO) & 1; |
| 46 | env->ov = (xer >> XER_OV) & 1; |
| 47 | env->ca = (xer >> XER_CA) & 1; |
| 48 | /* write all the flags, while reading back check of isa300 */ |
| 49 | env->ov32 = (xer >> XER_OV32) & 1; |
| 50 | env->ca32 = (xer >> XER_CA32) & 1; |
| 51 | env->xer = xer & ~((1ul << XER_SO) | |
| 52 | (1ul << XER_OV) | (1ul << XER_CA) | |
| 53 | (1ul << XER_OV32) | (1ul << XER_CA32)); |
| 54 | } |
| 55 | |
| 56 | void ppc_store_vscr(CPUPPCState *env, uint32_t vscr) |
| 57 | { |
| 58 | env->vscr = vscr & ~(1u << VSCR_SAT); |
| 59 | /* Which bit we set is completely arbitrary, but clear the rest. */ |
| 60 | env->vscr_sat.u64[0] = vscr & (1u << VSCR_SAT); |
| 61 | env->vscr_sat.u64[1] = 0; |
| 62 | set_flush_to_zero((vscr >> VSCR_NJ) & 1, &env->vec_status); |
| 63 | set_flush_inputs_to_zero((vscr >> VSCR_NJ) & 1, &env->vec_status); |
| 64 | } |
| 65 | |
| 66 | uint32_t ppc_get_vscr(CPUPPCState *env) |
| 67 | { |
| 68 | uint32_t sat = (env->vscr_sat.u64[0] | env->vscr_sat.u64[1]) != 0; |
| 69 | return env->vscr | (sat << VSCR_SAT); |
| 70 | } |
| 71 | |
| 72 | void ppc_set_cr(CPUPPCState *env, uint64_t cr) |
| 73 | { |
| 74 | for (int i = 7; i >= 0; i--) { |
| 75 | env->crf[i] = cr & 0xf; |
| 76 | cr >>= 4; |
| 77 | } |
| 78 | } |
| 79 | |
| 80 | uint64_t ppc_get_cr(const CPUPPCState *env) |
| 81 | { |
| 82 | uint64_t cr = 0; |
| 83 | for (int i = 0; i < 8; i++) { |
| 84 | cr |= (env->crf[i] & 0xf) << (4 * (7 - i)); |
| 85 | } |
| 86 | return cr; |
| 87 | } |
| 88 | |
| 89 | /* GDBstub can read and write MSR... */ |
| 90 | void ppc_store_msr(CPUPPCState *env, target_ulong value) |
| 91 | { |
| 92 | hreg_store_msr(env, value, 0); |
| 93 | } |
| 94 | |
| 95 | #if !defined(CONFIG_USER_ONLY) |
| 96 | void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong val) |
| 97 | { |
| 98 | PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); |
| 99 | CPUPPCState *env = &cpu->env; |
| 100 | |
| 101 | env->spr[SPR_LPCR] = val & pcc->lpcr_mask; |
| 102 | /* The gtse bit affects hflags */ |
| 103 | hreg_compute_hflags(env); |
| 104 | |
| 105 | ppc_maybe_interrupt(env); |
| 106 | } |
| 107 | |
| 108 | #if defined(TARGET_PPC64) |
| 109 | void ppc_update_ciabr(CPUPPCState *env) |
| 110 | { |
| 111 | CPUState *cs = env_cpu(env); |
| 112 | target_ulong ciabr = env->spr[SPR_CIABR]; |
| 113 | target_ulong ciea, priv; |
| 114 | |
| 115 | ciea = ciabr & PPC_BITMASK(0, 61); |
| 116 | priv = ciabr & PPC_BITMASK(62, 63); |
| 117 | |
| 118 | if (env->ciabr_breakpoint) { |
| 119 | cpu_breakpoint_remove_by_ref(cs, env->ciabr_breakpoint); |
| 120 | env->ciabr_breakpoint = NULL; |
| 121 | } |
| 122 | |
| 123 | if (priv) { |
| 124 | cpu_breakpoint_insert(cs, ciea, BP_CPU, &env->ciabr_breakpoint); |
| 125 | } |
| 126 | } |
| 127 | |
| 128 | void ppc_store_ciabr(CPUPPCState *env, target_ulong val) |
| 129 | { |
| 130 | env->spr[SPR_CIABR] = val; |
| 131 | ppc_update_ciabr(env); |
| 132 | } |
| 133 | |
| 134 | void ppc_update_daw(CPUPPCState *env, int rid) |
| 135 | { |
| 136 | CPUState *cs = env_cpu(env); |
| 137 | int spr_dawr = rid ? SPR_DAWR1 : SPR_DAWR0; |
| 138 | int spr_dawrx = rid ? SPR_DAWRX1 : SPR_DAWRX0; |
| 139 | target_ulong deaw = env->spr[spr_dawr] & PPC_BITMASK(0, 60); |
| 140 | uint32_t dawrx = env->spr[spr_dawrx]; |
| 141 | int mrd = extract32(dawrx, PPC_BIT_NR(48), 54 - 48); |
| 142 | bool dw = extract32(dawrx, PPC_BIT_NR(57), 1); |
| 143 | bool dr = extract32(dawrx, PPC_BIT_NR(58), 1); |
| 144 | bool hv = extract32(dawrx, PPC_BIT_NR(61), 1); |
| 145 | bool sv = extract32(dawrx, PPC_BIT_NR(62), 1); |
| 146 | bool pr = extract32(dawrx, PPC_BIT_NR(62), 1); |
| 147 | vaddr len; |
| 148 | int flags; |
| 149 | |
| 150 | assert(tcg_enabled()); |
| 151 | |
| 152 | if (env->dawr_watchpoint[rid]) { |
| 153 | cpu_watchpoint_remove_by_ref(cs, env->dawr_watchpoint[rid]); |
| 154 | env->dawr_watchpoint[rid] = NULL; |
| 155 | } |
| 156 | |
| 157 | if (!dr && !dw) { |
| 158 | return; |
| 159 | } |
| 160 | |
| 161 | if (!hv && !sv && !pr) { |
| 162 | return; |
| 163 | } |
| 164 | |
| 165 | len = (mrd + 1) * 8; |
| 166 | flags = BP_CPU | BP_STOP_BEFORE_ACCESS; |
| 167 | if (dr) { |
| 168 | flags |= BP_MEM_READ; |
| 169 | } |
| 170 | if (dw) { |
| 171 | flags |= BP_MEM_WRITE; |
| 172 | } |
| 173 | |
| 174 | cpu_watchpoint_insert(cs, deaw, len, flags, &env->dawr_watchpoint[rid]); |
| 175 | } |
| 176 | |
| 177 | void ppc_store_dawr0(CPUPPCState *env, target_ulong val) |
| 178 | { |
| 179 | env->spr[SPR_DAWR0] = val; |
| 180 | ppc_update_daw(env, 0); |
| 181 | } |
| 182 | |
| 183 | static void ppc_store_dawrx(CPUPPCState *env, uint32_t val, int rid) |
| 184 | { |
| 185 | int hrammc = extract32(val, PPC_BIT_NR(56), 1); |
| 186 | |
| 187 | if (hrammc) { |
| 188 | /* This might be done with a second watchpoint at the xor of DEAW[0] */ |
| 189 | qemu_log_mask(LOG_UNIMP, "%s: DAWRX%d[HRAMMC] is unimplemented\n", |
| 190 | __func__, rid); |
| 191 | } |
| 192 | |
| 193 | env->spr[rid ? SPR_DAWRX1 : SPR_DAWRX0] = val; |
| 194 | ppc_update_daw(env, rid); |
| 195 | } |
| 196 | |
| 197 | void ppc_store_dawrx0(CPUPPCState *env, uint32_t val) |
| 198 | { |
| 199 | ppc_store_dawrx(env, val, 0); |
| 200 | } |
| 201 | |
| 202 | void ppc_store_dawr1(CPUPPCState *env, target_ulong val) |
| 203 | { |
| 204 | env->spr[SPR_DAWR1] = val; |
| 205 | ppc_update_daw(env, 1); |
| 206 | } |
| 207 | |
| 208 | void ppc_store_dawrx1(CPUPPCState *env, uint32_t val) |
| 209 | { |
| 210 | ppc_store_dawrx(env, val, 1); |
| 211 | } |
| 212 | |
| 213 | #endif |
| 214 | #endif |
| 215 | |
| 216 | static inline void fpscr_set_rounding_mode(CPUPPCState *env) |
| 217 | { |
| 218 | int rnd_type; |
| 219 | |
| 220 | /* Set rounding mode */ |
| 221 | switch (env->fpscr & FP_RN) { |
| 222 | case 0: |
| 223 | /* Best approximation (round to nearest) */ |
| 224 | rnd_type = float_round_nearest_even; |
| 225 | break; |
| 226 | case 1: |
| 227 | /* Smaller magnitude (round toward zero) */ |
| 228 | rnd_type = float_round_to_zero; |
| 229 | break; |
| 230 | case 2: |
| 231 | /* Round toward +infinite */ |
| 232 | rnd_type = float_round_up; |
| 233 | break; |
| 234 | default: |
| 235 | case 3: |
| 236 | /* Round toward -infinite */ |
| 237 | rnd_type = float_round_down; |
| 238 | break; |
| 239 | } |
| 240 | set_float_rounding_mode(rnd_type, &env->fp_status); |
| 241 | } |
| 242 | |
| 243 | void ppc_store_fpscr(CPUPPCState *env, target_ulong val) |
| 244 | { |
| 245 | val &= FPSCR_MTFS_MASK; |
| 246 | if (val & FPSCR_IX) { |
| 247 | val |= FP_VX; |
| 248 | } |
| 249 | if ((val >> FPSCR_XX) & (val >> FPSCR_XE) & 0x1f) { |
| 250 | val |= FP_FEX; |
| 251 | } |
| 252 | env->fpscr = val; |
| 253 | set_float_rebias_overflow(FP_OE & env->fpscr, &env->fp_status); |
| 254 | set_float_rebias_underflow(FP_UE & env->fpscr, &env->fp_status); |
| 255 | if (tcg_enabled()) { |
| 256 | fpscr_set_rounding_mode(env); |
| 257 | } |
| 258 | } |