cpu.h · samitouri/QOSamiQemu · siGit Code & Deploy

Code Commits Issues Pulls Sessions CI/CD

master

h 3,127 lines 127 KB

Raw

1	/*
2	* PowerPC emulation cpu definitions for qemu.
3	*
4	* Copyright (c) 2003-2007 Jocelyn Mayer
5	*
6	* This library is free software; you can redistribute it and/or
7	* modify it under the terms of the GNU Lesser General Public
8	* License as published by the Free Software Foundation; either
9	* version 2.1 of the License, or (at your option) any later version.
10	*
11	* This library is distributed in the hope that it will be useful,
12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14	* Lesser General Public License for more details.
15	*
16	* You should have received a copy of the GNU Lesser General Public
17	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
18	*/
19
20	#ifndef PPC_CPU_H
21	#define PPC_CPU_H
22
23	#include "qemu/int128.h"
24	#include "qemu/cpu-float.h"
25	#include "exec/cpu-common.h"
26	#include "exec/cpu-interrupt.h"
27	#include "exec/target_long.h"
28	#include "cpu-qom.h"
29	#include "qom/object.h"
30	#include "hw/core/registerfields.h"
31
32	#define CPU_RESOLVING_TYPE TYPE_POWERPC_CPU
33
34	#define TARGET_PAGE_BITS_64K 16
35	#define TARGET_PAGE_BITS_16M 24
36
37	#if defined(TARGET_PPC64)
38	#define PPC_ELF_MACHINE EM_PPC64
39	#else
40	#define PPC_ELF_MACHINE EM_PPC
41	#endif
42
43	#define PPC_BIT_NR(bit) (63 - (bit))
44	#define PPC_BIT(bit) (0x8000000000000000ULL >> (bit))
45	#define PPC_BIT32_NR(bit) (31 - (bit))
46	#define PPC_BIT32(bit) (0x80000000 >> (bit))
47	#define PPC_BIT8(bit) (0x80 >> (bit))
48	#define PPC_BITMASK(bs, be) ((PPC_BIT(bs) - PPC_BIT(be)) \| PPC_BIT(bs))
49	#define PPC_BITMASK32(bs, be) ((PPC_BIT32(bs) - PPC_BIT32(be)) \| \
50	PPC_BIT32(bs))
51	#define PPC_BITMASK8(bs, be) ((PPC_BIT8(bs) - PPC_BIT8(be)) \| PPC_BIT8(bs))
52
53	/*
54	* QEMU version of the GETFIELD/SETFIELD macros from skiboot
55	*
56	* It might be better to use the existing extract64() and
57	* deposit64() but this means that all the register definitions will
58	* change and become incompatible with the ones found in skiboot.
59	*/
60	#define MASK_TO_LSH(m) (__builtin_ffsll(m) - 1)
61	#define GETFIELD(m, v) (((v) & (m)) >> MASK_TO_LSH(m))
62	#define SETFIELD(m, v, val) \
63	(((v) & ~(m)) \| ((((typeof(v))(val)) << MASK_TO_LSH(m)) & (m)))
64
65	/*****************************************************************************/
66	/* Exception vectors definitions */
67	enum {
68	POWERPC_EXCP_NONE = -1,
69	/* The 64 first entries are used by the PowerPC embedded specification */
70	POWERPC_EXCP_CRITICAL = 0, /* Critical input */
71	POWERPC_EXCP_MCHECK = 1, /* Machine check exception */
72	POWERPC_EXCP_DSI = 2, /* Data storage exception */
73	POWERPC_EXCP_ISI = 3, /* Instruction storage exception */
74	POWERPC_EXCP_EXTERNAL = 4, /* External input */
75	POWERPC_EXCP_ALIGN = 5, /* Alignment exception */
76	POWERPC_EXCP_PROGRAM = 6, /* Program exception */
77	POWERPC_EXCP_FPU = 7, /* Floating-point unavailable exception */
78	POWERPC_EXCP_SYSCALL = 8, /* System call exception */
79	POWERPC_EXCP_APU = 9, /* Auxiliary processor unavailable */
80	POWERPC_EXCP_DECR = 10, /* Decrementer exception */
81	POWERPC_EXCP_FIT = 11, /* Fixed-interval timer interrupt */
82	POWERPC_EXCP_WDT = 12, /* Watchdog timer interrupt */
83	POWERPC_EXCP_DTLB = 13, /* Data TLB miss */
84	POWERPC_EXCP_ITLB = 14, /* Instruction TLB miss */
85	POWERPC_EXCP_DEBUG = 15, /* Debug interrupt */
86	/* Vectors 16 to 31 are reserved */
87	POWERPC_EXCP_SPEU = 32, /* SPE/embedded floating-point unavailable */
88	POWERPC_EXCP_EFPDI = 33, /* Embedded floating-point data interrupt */
89	POWERPC_EXCP_EFPRI = 34, /* Embedded floating-point round interrupt */
90	POWERPC_EXCP_EPERFM = 35, /* Embedded performance monitor interrupt */
91	POWERPC_EXCP_DOORI = 36, /* Embedded doorbell interrupt */
92	POWERPC_EXCP_DOORCI = 37, /* Embedded doorbell critical interrupt */
93	POWERPC_EXCP_GDOORI = 38, /* Embedded guest doorbell interrupt */
94	POWERPC_EXCP_GDOORCI = 39, /* Embedded guest doorbell critical interrupt*/
95	POWERPC_EXCP_HYPPRIV = 41, /* Embedded hypervisor priv instruction */
96	/* Vectors 42 to 63 are reserved */
97	/* Exceptions defined in the PowerPC server specification */
98	POWERPC_EXCP_RESET = 64, /* System reset exception */
99	POWERPC_EXCP_DSEG = 65, /* Data segment exception */
100	POWERPC_EXCP_ISEG = 66, /* Instruction segment exception */
101	POWERPC_EXCP_HDECR = 67, /* Hypervisor decrementer exception */
102	POWERPC_EXCP_TRACE = 68, /* Trace exception */
103	POWERPC_EXCP_HDSI = 69, /* Hypervisor data storage exception */
104	POWERPC_EXCP_HISI = 70, /* Hypervisor instruction storage exception */
105	POWERPC_EXCP_HDSEG = 71, /* Hypervisor data segment exception */
106	POWERPC_EXCP_HISEG = 72, /* Hypervisor instruction segment exception */
107	POWERPC_EXCP_VPU = 73, /* Vector unavailable exception */
108	/* 40x specific exceptions */
109	POWERPC_EXCP_PIT = 74, /* Programmable interval timer interrupt */
110	/* Vectors 75-76 are 601 specific exceptions */
111	/* 602 specific exceptions */
112	POWERPC_EXCP_EMUL = 77, /* Emulation trap exception */
113	/* 602/603 specific exceptions */
114	POWERPC_EXCP_IFTLB = 78, /* Instruction fetch TLB miss */
115	POWERPC_EXCP_DLTLB = 79, /* Data load TLB miss */
116	POWERPC_EXCP_DSTLB = 80, /* Data store TLB miss */
117	/* Exceptions available on most PowerPC */
118	POWERPC_EXCP_FPA = 81, /* Floating-point assist exception */
119	POWERPC_EXCP_DABR = 82, /* Data address breakpoint */
120	POWERPC_EXCP_IABR = 83, /* Instruction address breakpoint */
121	POWERPC_EXCP_SMI = 84, /* System management interrupt */
122	POWERPC_EXCP_PERFM = 85, /* Embedded performance monitor interrupt */
123	/* 7xx/74xx specific exceptions */
124	POWERPC_EXCP_THERM = 86, /* Thermal interrupt */
125	/* 74xx specific exceptions */
126	POWERPC_EXCP_VPUA = 87, /* Vector assist exception */
127	/* 970FX specific exceptions */
128	POWERPC_EXCP_SOFTP = 88, /* Soft patch exception */
129	POWERPC_EXCP_MAINT = 89, /* Maintenance exception */
130	/* Freescale embedded cores specific exceptions */
131	POWERPC_EXCP_MEXTBR = 90, /* Maskable external breakpoint */
132	POWERPC_EXCP_NMEXTBR = 91, /* Non maskable external breakpoint */
133	POWERPC_EXCP_ITLBE = 92, /* Instruction TLB error */
134	POWERPC_EXCP_DTLBE = 93, /* Data TLB error */
135	/* VSX Unavailable (Power ISA 2.06 and later) */
136	POWERPC_EXCP_VSXU = 94, /* VSX Unavailable */
137	POWERPC_EXCP_FU = 95, /* Facility Unavailable */
138	/* Additional ISA 2.06 and later server exceptions */
139	POWERPC_EXCP_HV_EMU = 96, /* HV emulation assistance */
140	POWERPC_EXCP_HV_MAINT = 97, /* HMI */
141	POWERPC_EXCP_HV_FU = 98, /* Hypervisor Facility unavailable */
142	/* Server doorbell variants */
143	POWERPC_EXCP_SDOOR = 99,
144	POWERPC_EXCP_SDOOR_HV = 100,
145	/* ISA 3.00 additions */
146	POWERPC_EXCP_HVIRT = 101,
147	POWERPC_EXCP_SYSCALL_VECTORED = 102, /* scv exception */
148	POWERPC_EXCP_PERFM_EBB = 103, /* Performance Monitor EBB Exception */
149	POWERPC_EXCP_EXTERNAL_EBB = 104, /* External EBB Exception */
150	/* EOL */
151	POWERPC_EXCP_NB = 105,
152	/* QEMU exceptions: special cases we want to stop translation */
153	POWERPC_EXCP_SYSCALL_USER = 0x203, /* System call in user mode only */
154	};
155
156	/* Exceptions error codes */
157	enum {
158	/* Exception subtypes for POWERPC_EXCP_ALIGN */
159	POWERPC_EXCP_ALIGN_FP = 0x01, /* FP alignment exception */
160	POWERPC_EXCP_ALIGN_LST = 0x02, /* Unaligned mult/extern load/store */
161	POWERPC_EXCP_ALIGN_LE = 0x03, /* Multiple little-endian access */
162	POWERPC_EXCP_ALIGN_PROT = 0x04, /* Access cross protection boundary */
163	POWERPC_EXCP_ALIGN_BAT = 0x05, /* Access cross a BAT/seg boundary */
164	POWERPC_EXCP_ALIGN_CACHE = 0x06, /* Impossible dcbz access */
165	POWERPC_EXCP_ALIGN_INSN = 0x07, /* Pref. insn x-ing 64-byte boundary */
166	/* Exception subtypes for POWERPC_EXCP_PROGRAM */
167	/* FP exceptions */
168	POWERPC_EXCP_FP = 0x10,
169	POWERPC_EXCP_FP_OX = 0x01, /* FP overflow */
170	POWERPC_EXCP_FP_UX = 0x02, /* FP underflow */
171	POWERPC_EXCP_FP_ZX = 0x03, /* FP divide by zero */
172	POWERPC_EXCP_FP_XX = 0x04, /* FP inexact */
173	POWERPC_EXCP_FP_VXSNAN = 0x05, /* FP invalid SNaN op */
174	POWERPC_EXCP_FP_VXISI = 0x06, /* FP invalid infinite subtraction */
175	POWERPC_EXCP_FP_VXIDI = 0x07, /* FP invalid infinite divide */
176	POWERPC_EXCP_FP_VXZDZ = 0x08, /* FP invalid zero divide */
177	POWERPC_EXCP_FP_VXIMZ = 0x09, /* FP invalid infinite * zero */
178	POWERPC_EXCP_FP_VXVC = 0x0A, /* FP invalid compare */
179	POWERPC_EXCP_FP_VXSOFT = 0x0B, /* FP invalid operation */
180	POWERPC_EXCP_FP_VXSQRT = 0x0C, /* FP invalid square root */
181	POWERPC_EXCP_FP_VXCVI = 0x0D, /* FP invalid integer conversion */
182	/* Invalid instruction */
183	POWERPC_EXCP_INVAL = 0x20,
184	POWERPC_EXCP_INVAL_INVAL = 0x01, /* Invalid instruction */
185	POWERPC_EXCP_INVAL_LSWX = 0x02, /* Invalid lswx instruction */
186	POWERPC_EXCP_INVAL_SPR = 0x03, /* Invalid SPR access */
187	POWERPC_EXCP_INVAL_FP = 0x04, /* Unimplemented mandatory fp instr */
188	/* Privileged instruction */
189	POWERPC_EXCP_PRIV = 0x30,
190	POWERPC_EXCP_PRIV_OPC = 0x01, /* Privileged operation exception */
191	POWERPC_EXCP_PRIV_REG = 0x02, /* Privileged register exception */
192	/* Trap */
193	POWERPC_EXCP_TRAP = 0x40,
194	};
195
196	/* Exception model */
197	typedef enum powerpc_excp_t {
198	POWERPC_EXCP_UNKNOWN = 0,
199	/* Standard PowerPC exception model */
200	POWERPC_EXCP_STD,
201	/* PowerPC 40x exception model */
202	POWERPC_EXCP_40x,
203	/* PowerPC 603/604/G2 exception model */
204	POWERPC_EXCP_6xx,
205	/* PowerPC 7xx exception model */
206	POWERPC_EXCP_7xx,
207	/* PowerPC 74xx exception model */
208	POWERPC_EXCP_74xx,
209	/* BookE exception model */
210	POWERPC_EXCP_BOOKE,
211	/* PowerPC 970 exception model */
212	POWERPC_EXCP_970,
213	/* POWER7 exception model */
214	POWERPC_EXCP_POWER7,
215	/* POWER8 exception model */
216	POWERPC_EXCP_POWER8,
217	/* POWER9 exception model */
218	POWERPC_EXCP_POWER9,
219	/* POWER10 exception model */
220	POWERPC_EXCP_POWER10,
221	/* POWER11 exception model */
222	POWERPC_EXCP_POWER11,
223	/* PPE42 exception model */
224	POWERPC_EXCP_PPE42,
225	} powerpc_excp_t;
226
227	/*****************************************************************************/
228	/* MMU model */
229	typedef enum powerpc_mmu_t {
230	POWERPC_MMU_UNKNOWN = 0x00000000,
231	/* Standard 32 bits PowerPC MMU */
232	POWERPC_MMU_32B = 0x00000001,
233	/* PowerPC 6xx MMU with software TLB */
234	POWERPC_MMU_SOFT_6xx = 0x00000002,
235	/*
236	* PowerPC 74xx MMU with software TLB (this has been
237	* disabled, see git history for more information.
238	* keywords: tlbld tlbli TLBMISS PTEHI PTELO)
239	*/
240	POWERPC_MMU_SOFT_74xx = 0x00000003,
241	/* PowerPC 4xx MMU with software TLB */
242	POWERPC_MMU_SOFT_4xx = 0x00000004,
243	/* PowerPC MMU in real mode only */
244	POWERPC_MMU_REAL = 0x00000006,
245	/* Freescale MPC8xx MMU model */
246	POWERPC_MMU_MPC8xx = 0x00000007,
247	/* BookE MMU model */
248	POWERPC_MMU_BOOKE = 0x00000008,
249	/* BookE 2.06 MMU model */
250	POWERPC_MMU_BOOKE206 = 0x00000009,
251	#define POWERPC_MMU_64 0x00010000
252	/* 64 bits PowerPC MMU */
253	POWERPC_MMU_64B = POWERPC_MMU_64 \| 0x00000001,
254	/* Architecture 2.03 and later (has LPCR) */
255	POWERPC_MMU_2_03 = POWERPC_MMU_64 \| 0x00000002,
256	/* Architecture 2.06 variant */
257	POWERPC_MMU_2_06 = POWERPC_MMU_64 \| 0x00000003,
258	/* Architecture 2.07 variant */
259	POWERPC_MMU_2_07 = POWERPC_MMU_64 \| 0x00000004,
260	/* Architecture 3.00 variant */
261	POWERPC_MMU_3_00 = POWERPC_MMU_64 \| 0x00000005,
262	} powerpc_mmu_t;
263
264	static inline bool mmu_is_64bit(powerpc_mmu_t mmu_model)
265	{
266	return mmu_model & POWERPC_MMU_64;
267	}
268
269	/*****************************************************************************/
270	/* Input pins model */
271	typedef enum powerpc_input_t {
272	PPC_FLAGS_INPUT_UNKNOWN = 0,
273	/* PowerPC 6xx bus */
274	PPC_FLAGS_INPUT_6xx,
275	/* BookE bus */
276	PPC_FLAGS_INPUT_BookE,
277	/* PowerPC 405 bus */
278	PPC_FLAGS_INPUT_405,
279	/* PowerPC 970 bus */
280	PPC_FLAGS_INPUT_970,
281	/* PowerPC POWER7 bus */
282	PPC_FLAGS_INPUT_POWER7,
283	/* PowerPC POWER9 bus */
284	PPC_FLAGS_INPUT_POWER9,
285	/* Freescale RCPU bus */
286	PPC_FLAGS_INPUT_RCPU,
287	/* PPE42 bus */
288	PPC_FLAGS_INPUT_PPE42,
289	} powerpc_input_t;
290
291	#define PPC_INPUT(env) ((env)->bus_model)
292
293	/*****************************************************************************/
294	typedef struct opc_handler_t opc_handler_t;
295
296	/*****************************************************************************/
297	/* Types used to describe some PowerPC registers etc. */
298	typedef struct DisasContext DisasContext;
299	typedef struct ppc_dcr_t ppc_dcr_t;
300	typedef struct ppc_spr_t ppc_spr_t;
301	typedef struct ppc_tb_t ppc_tb_t;
302	typedef union ppc_tlb_t ppc_tlb_t;
303	typedef struct ppc_hash_pte64 ppc_hash_pte64_t;
304	typedef struct PPCHash64Options PPCHash64Options;
305
306	typedef struct CPUArchState CPUPPCState;
307
308	/* SPR access micro-ops generations callbacks */
309	struct ppc_spr_t {
310	const char *name;
311	target_ulong default_value;
312	#ifndef CONFIG_USER_ONLY
313	unsigned int gdb_id;
314	#endif
315	#ifdef CONFIG_TCG
316	void (uea_read)(DisasContext ctx, int gpr_num, int spr_num);
317	void (uea_write)(DisasContext ctx, int spr_num, int gpr_num);
318	# ifndef CONFIG_USER_ONLY
319	void (oea_read)(DisasContext ctx, int gpr_num, int spr_num);
320	void (oea_write)(DisasContext ctx, int spr_num, int gpr_num);
321	void (hea_read)(DisasContext ctx, int gpr_num, int spr_num);
322	void (hea_write)(DisasContext ctx, int spr_num, int gpr_num);
323	# endif
324	#endif
325	#ifdef CONFIG_KVM
326	/*
327	* We (ab)use the fact that all the SPRs will have ids for the
328	* ONE_REG interface will have KVM_REG_PPC to use 0 as meaning,
329	* don't sync this
330	*/
331	uint64_t one_reg_id;
332	#endif
333	};
334
335	/* VSX/Altivec registers (128 bits) */
336	typedef union _ppc_vsr_t {
337	uint8_t u8[16];
338	uint16_t u16[8];
339	uint32_t u32[4];
340	uint64_t u64[2];
341	int8_t s8[16];
342	int16_t s16[8];
343	int32_t s32[4];
344	int64_t s64[2];
345	float16 f16[8];
346	float32 f32[4];
347	float64 f64[2];
348	float128 f128;
349	#ifdef CONFIG_INT128
350	__uint128_t u128;
351	#endif
352	Int128 s128;
353	} ppc_vsr_t;
354
355	typedef ppc_vsr_t ppc_avr_t;
356	typedef ppc_vsr_t ppc_fprp_t;
357	typedef ppc_vsr_t ppc_acc_t;
358
359	#if !defined(CONFIG_USER_ONLY)
360	/* Software TLB cache */
361	typedef struct ppc6xx_tlb_t ppc6xx_tlb_t;
362	struct ppc6xx_tlb_t {
363	target_ulong pte0;
364	target_ulong pte1;
365	target_ulong EPN;
366	};
367
368	typedef struct ppcemb_tlb_t ppcemb_tlb_t;
369	struct ppcemb_tlb_t {
370	uint64_t RPN;
371	target_ulong EPN;
372	target_ulong PID;
373	target_ulong size;
374	uint32_t prot;
375	uint32_t attr; /* Storage attributes */
376	};
377
378	typedef struct ppcmas_tlb_t {
379	uint32_t mas8;
380	uint32_t mas1;
381	uint64_t mas2;
382	uint64_t mas7_3;
383	} ppcmas_tlb_t;
384
385	union ppc_tlb_t {
386	ppc6xx_tlb_t *tlb6;
387	ppcemb_tlb_t *tlbe;
388	ppcmas_tlb_t *tlbm;
389	};
390
391	/* possible TLB variants */
392	#define TLB_NONE 0
393	#define TLB_6XX 1
394	#define TLB_EMB 2
395	#define TLB_MAS 3
396	#endif
397
398	typedef struct PPCHash64SegmentPageSizes PPCHash64SegmentPageSizes;
399
400	typedef struct ppc_slb_t ppc_slb_t;
401	struct ppc_slb_t {
402	uint64_t esid;
403	uint64_t vsid;
404	const PPCHash64SegmentPageSizes *sps;
405	};
406
407	#define MAX_SLB_ENTRIES 64
408	#define SEGMENT_SHIFT_256M 28
409	#define SEGMENT_MASK_256M (~((1ULL << SEGMENT_SHIFT_256M) - 1))
410
411	#define SEGMENT_SHIFT_1T 40
412	#define SEGMENT_MASK_1T (~((1ULL << SEGMENT_SHIFT_1T) - 1))
413
414	typedef struct ppc_v3_pate_t {
415	uint64_t dw0;
416	uint64_t dw1;
417	} ppc_v3_pate_t;
418
419	/* PMU related structs and defines */
420	#define PMU_COUNTERS_NUM 6
421	typedef enum {
422	PMU_EVENT_INVALID = 0,
423	PMU_EVENT_INACTIVE,
424	PMU_EVENT_CYCLES,
425	PMU_EVENT_INSTRUCTIONS,
426	PMU_EVENT_INSN_RUN_LATCH,
427	} PMUEventType;
428
429	/*****************************************************************************/
430	/* Machine state register bits definition */
431	#define MSR_SF PPC_BIT_NR(0) /* Sixty-four-bit mode hflags */
432	#define MSR_TAG PPC_BIT_NR(1) /* Tag-active mode (POWERx ?) */
433	#define MSR_ISF PPC_BIT_NR(2) /* Sixty-four-bit interrupt mode on 630 */
434	#define MSR_HV PPC_BIT_NR(3) /* hypervisor state hflags */
435	#define MSR_TS0 PPC_BIT_NR(29) /* Transactional state, 2 bits (Book3s) */
436	#define MSR_TS1 PPC_BIT_NR(30)
437	#define MSR_TM PPC_BIT_NR(31) /* Transactional Memory Available (Book3s) */
438	#define MSR_CM PPC_BIT_NR(32) /* Computation mode for BookE hflags */
439	#define MSR_ICM PPC_BIT_NR(33) /* Interrupt computation mode for BookE */
440	#define MSR_SEM0 PPC_BIT_NR(33) /* SIB Error Mask Bit 0 (PPE42) */
441	#define MSR_SEM1 PPC_BIT_NR(34) /* SIB Error Mask Bit 1 (PPE42) */
442	#define MSR_SEM2 PPC_BIT_NR(35) /* SIB Error Mask Bit 2 (PPE42) */
443	#define MSR_GS PPC_BIT_NR(35) /* guest state for BookE */
444	#define MSR_SEM3 PPC_BIT_NR(36) /* SIB Error Mask Bit 3 (PPE42) */
445	#define MSR_SEM4 PPC_BIT_NR(37) /* SIB Error Mask Bit 4 (PPE42) */
446	#define MSR_UCLE PPC_BIT_NR(37) /* User-mode cache lock enable for BookE */
447	#define MSR_VR PPC_BIT_NR(38) /* altivec available x hflags */
448	#define MSR_SPE PPC_BIT_NR(38) /* SPE enable for BookE x hflags */
449	#define MSR_SEM5 PPC_BIT_NR(38) /* SIB Error Mask Bit 5 (PPE42) */
450	#define MSR_SEM6 PPC_BIT_NR(39) /* SIB Error Mask Bit 6 (PPE42) */
451	#define MSR_VSX PPC_BIT_NR(40) /* Vector Scalar Extension (>= 2.06)x hflags */
452	#define MSR_IS0 PPC_BIT_NR(40) /* Instance Specific Bit 0 (PPE42) */
453	#define MSR_S PPC_BIT_NR(41) /* Secure state */
454	#define MSR_SIBRC0 PPC_BIT_NR(41) /* Last SIB return code Bit 0 (PPE42) */
455	#define MSR_SIBRC1 PPC_BIT_NR(42) /* Last SIB return code Bit 1 (PPE42) */
456	#define MSR_SIBRC2 PPC_BIT_NR(43) /* Last SIB return code Bit 2 (PPE42) */
457	#define MSR_LP PPC_BIT_NR(44) /* Low Priority (PPE42) */
458	#define MSR_KEY PPC_BIT_NR(44) /* key bit on 603e */
459	#define MSR_POW PPC_BIT_NR(45) /* Power management */
460	#define MSR_WE PPC_BIT_NR(45) /* Wait State Enable on 405 */
461	#define MSR_IS1 PPC_BIT_NR(46) /* Instance Specific Bit 1 (PPE42) */
462	#define MSR_TGPR PPC_BIT_NR(46) /* TGPR usage on 602/603 x */
463	#define MSR_CE PPC_BIT_NR(46) /* Critical int. enable on embedded PPC x */
464	#define MSR_ILE PPC_BIT_NR(47) /* Interrupt little-endian mode */
465	#define MSR_UIE PPC_BIT_NR(47) /* Unmaskable Interrupt Enable (PPE42) */
466	#define MSR_EE PPC_BIT_NR(48) /* External interrupt enable */
467	#define MSR_PR PPC_BIT_NR(49) /* Problem state hflags */
468	#define MSR_FP PPC_BIT_NR(50) /* Floating point available hflags */
469	#define MSR_ME PPC_BIT_NR(51) /* Machine check interrupt enable */
470	#define MSR_FE0 PPC_BIT_NR(52) /* Floating point exception mode 0 */
471	#define MSR_IS2 PPC_BIT_NR(52) /* Instance Specific Bit 2 (PPE42) */
472	#define MSR_IS3 PPC_BIT_NR(53) /* Instance Specific Bit 3 (PPE42) */
473	#define MSR_SE PPC_BIT_NR(53) /* Single-step trace enable x hflags */
474	#define MSR_DWE PPC_BIT_NR(53) /* Debug wait enable on 405 x */
475	#define MSR_UBLE PPC_BIT_NR(53) /* User BTB lock enable on e500 x */
476	#define MSR_BE PPC_BIT_NR(54) /* Branch trace enable x hflags */
477	#define MSR_DE PPC_BIT_NR(54) /* Debug int. enable on embedded PPC x */
478	#define MSR_FE1 PPC_BIT_NR(55) /* Floating point exception mode 1 */
479	#define MSR_IPE PPC_BIT_NR(55) /* Imprecise Mode Enable (PPE42) */
480	#define MSR_AL PPC_BIT_NR(56) /* AL bit on POWER */
481	#define MSR_SIBRCA0 PPC_BIT_NR(56) /* SIB Return Code Accumulator 0 (PPE42) */
482	#define MSR_SIBRCA1 PPC_BIT_NR(57) /* SIB Return Code Accumulator 1 (PPE42) */
483	#define MSR_EP PPC_BIT_NR(57) /* Exception prefix on 601 */
484	#define MSR_IR PPC_BIT_NR(58) /* Instruction relocate */
485	#define MSR_IS PPC_BIT_NR(58) /* Instruction address space (BookE) */
486	#define MSR_SIBRCA2 PPC_BIT_NR(58) /* SIB Return Code Accumulator 2 (PPE42) */
487	#define MSR_SIBRCA3 PPC_BIT_NR(59) /* SIB Return Code Accumulator 3 (PPE42) */
488	#define MSR_DR PPC_BIT_NR(59) /* Data relocate */
489	#define MSR_DS PPC_BIT_NR(59) /* Data address space (BookE) */
490	#define MSR_PE PPC_BIT_NR(60) /* Protection enable on 403 */
491	#define MSR_SIBRCA4 PPC_BIT_NR(60) /* SIB Return Code Accumulator 4 (PPE42) */
492	#define MSR_SIBRCA5 PPC_BIT_NR(61) /* SIB Return Code Accumulator 5 (PPE42) */
493	#define MSR_PX PPC_BIT_NR(61) /* Protection exclusive on 403 x */
494	#define MSR_PMM PPC_BIT_NR(61) /* Performance monitor mark on POWER x */
495	#define MSR_RI PPC_BIT_NR(62) /* Recoverable interrupt 1 */
496	#define MSR_SIBRCA6 PPC_BIT_NR(62) /* SIB Return Code Accumulator 6 (PPE42) */
497	#define MSR_SIBRCA7 PPC_BIT_NR(63) /* SIB Return Code Accumulator 7 (PPE42) */
498	#define MSR_LE PPC_BIT_NR(63) /* Little-endian mode 1 hflags */
499
500	FIELD(MSR, SF, MSR_SF, 1)
501	FIELD(MSR, TAG, MSR_TAG, 1)
502	FIELD(MSR, ISF, MSR_ISF, 1)
503	#if defined(TARGET_PPC64)
504	FIELD(MSR, HV, MSR_HV, 1)
505	#define FIELD_EX64_HV(storage) FIELD_EX64(storage, MSR, HV)
506	#else
507	#define FIELD_EX64_HV(storage) 0
508	#endif
509	FIELD(MSR, TS0, MSR_TS0, 1)
510	FIELD(MSR, TS1, MSR_TS1, 1)
511	FIELD(MSR, TS, MSR_TS0, 2)
512	FIELD(MSR, TM, MSR_TM, 1)
513	FIELD(MSR, CM, MSR_CM, 1)
514	FIELD(MSR, ICM, MSR_ICM, 1)
515	FIELD(MSR, GS, MSR_GS, 1)
516	FIELD(MSR, UCLE, MSR_UCLE, 1)
517	FIELD(MSR, VR, MSR_VR, 1)
518	FIELD(MSR, SPE, MSR_SPE, 1)
519	FIELD(MSR, VSX, MSR_VSX, 1)
520	FIELD(MSR, S, MSR_S, 1)
521	FIELD(MSR, KEY, MSR_KEY, 1)
522	FIELD(MSR, POW, MSR_POW, 1)
523	FIELD(MSR, WE, MSR_WE, 1)
524	FIELD(MSR, TGPR, MSR_TGPR, 1)
525	FIELD(MSR, CE, MSR_CE, 1)
526	FIELD(MSR, ILE, MSR_ILE, 1)
527	FIELD(MSR, EE, MSR_EE, 1)
528	FIELD(MSR, PR, MSR_PR, 1)
529	FIELD(MSR, FP, MSR_FP, 1)
530	FIELD(MSR, ME, MSR_ME, 1)
531	FIELD(MSR, FE0, MSR_FE0, 1)
532	FIELD(MSR, SE, MSR_SE, 1)
533	FIELD(MSR, DWE, MSR_DWE, 1)
534	FIELD(MSR, UBLE, MSR_UBLE, 1)
535	FIELD(MSR, BE, MSR_BE, 1)
536	FIELD(MSR, DE, MSR_DE, 1)
537	FIELD(MSR, FE1, MSR_FE1, 1)
538	FIELD(MSR, AL, MSR_AL, 1)
539	FIELD(MSR, EP, MSR_EP, 1)
540	FIELD(MSR, IR, MSR_IR, 1)
541	FIELD(MSR, DR, MSR_DR, 1)
542	FIELD(MSR, IS, MSR_IS, 1)
543	FIELD(MSR, DS, MSR_DS, 1)
544	FIELD(MSR, PE, MSR_PE, 1)
545	FIELD(MSR, PX, MSR_PX, 1)
546	FIELD(MSR, PMM, MSR_PMM, 1)
547	FIELD(MSR, RI, MSR_RI, 1)
548	FIELD(MSR, LE, MSR_LE, 1)
549	FIELD(MSR, SEM, MSR_SEM6, 7)
550	FIELD(MSR, SIBRC, MSR_SIBRC2, 3)
551	FIELD(MSR, SIBRCA, MSR_SIBRCA7, 8)
552
553	/*
554	* FE0 and FE1 bits are not side-by-side
555	* so we can't combine them using FIELD()
556	*/
557	#define FIELD_EX64_FE(msr) \
558	((FIELD_EX64(msr, MSR, FE0) << 1) \| FIELD_EX64(msr, MSR, FE1))
559
560	/* PMU bits */
561	#define MMCR0_FC PPC_BIT(32) /* Freeze Counters */
562	#define MMCR0_PMAO PPC_BIT(56) /* Perf Monitor Alert Occurred */
563	#define MMCR0_PMAE PPC_BIT(37) /* Perf Monitor Alert Enable */
564	#define MMCR0_EBE PPC_BIT(43) /* Perf Monitor EBB Enable */
565	#define MMCR0_FCECE PPC_BIT(38) /* FC on Enabled Cond or Event */
566	#define MMCR0_PMCC0 PPC_BIT(44) /* PMC Control bit 0 */
567	#define MMCR0_PMCC1 PPC_BIT(45) /* PMC Control bit 1 */
568	#define MMCR0_PMCC PPC_BITMASK(44, 45) /* PMC Control */
569	#define MMCR0_FC14 PPC_BIT(58) /* PMC Freeze Counters 1-4 bit */
570	#define MMCR0_FC56 PPC_BIT(59) /* PMC Freeze Counters 5-6 bit */
571	#define MMCR0_PMC1CE PPC_BIT(48) /* MMCR0 PMC1 Condition Enabled */
572	#define MMCR0_PMCjCE PPC_BIT(49) /* MMCR0 PMCj Condition Enabled */
573	#define MMCR0_FCP PPC_BIT(34) /* Freeze Counters/BHRB if PR=1 */
574	#define MMCR0_FCPC PPC_BIT(51) /* Condition for FCP bit */
575	#define MMCR0_BHRBA_NR PPC_BIT_NR(42) /* BHRB Available */
576	/* MMCR0 userspace r/w mask */
577	#define MMCR0_UREG_MASK (MMCR0_FC \| MMCR0_PMAO \| MMCR0_PMAE)
578	/* MMCR2 userspace r/w mask */
579	#define MMCR2_FC1P0 PPC_BIT(1) /* MMCR2 FCnP0 for PMC1 */
580	#define MMCR2_FC2P0 PPC_BIT(10) /* MMCR2 FCnP0 for PMC2 */
581	#define MMCR2_FC3P0 PPC_BIT(19) /* MMCR2 FCnP0 for PMC3 */
582	#define MMCR2_FC4P0 PPC_BIT(28) /* MMCR2 FCnP0 for PMC4 */
583	#define MMCR2_FC5P0 PPC_BIT(37) /* MMCR2 FCnP0 for PMC5 */
584	#define MMCR2_FC6P0 PPC_BIT(46) /* MMCR2 FCnP0 for PMC6 */
585	#define MMCR2_UREG_MASK (MMCR2_FC1P0 \| MMCR2_FC2P0 \| MMCR2_FC3P0 \| \
586	MMCR2_FC4P0 \| MMCR2_FC5P0 \| MMCR2_FC6P0)
587
588	#define MMCRA_BHRBRD PPC_BIT(26) /* BHRB Recording Disable */
589	#define MMCRA_IFM_MASK PPC_BITMASK(32, 33) /* BHRB Instruction Filtering */
590	#define MMCRA_IFM_SHIFT PPC_BIT_NR(33)
591
592	#define MMCR1_EVT_SIZE 8
593	/* extract64() does a right shift before extracting */
594	#define MMCR1_PMC1SEL_START 32
595	#define MMCR1_PMC1EVT_EXTR (64 - MMCR1_PMC1SEL_START - MMCR1_EVT_SIZE)
596	#define MMCR1_PMC2SEL_START 40
597	#define MMCR1_PMC2EVT_EXTR (64 - MMCR1_PMC2SEL_START - MMCR1_EVT_SIZE)
598	#define MMCR1_PMC3SEL_START 48
599	#define MMCR1_PMC3EVT_EXTR (64 - MMCR1_PMC3SEL_START - MMCR1_EVT_SIZE)
600	#define MMCR1_PMC4SEL_START 56
601	#define MMCR1_PMC4EVT_EXTR (64 - MMCR1_PMC4SEL_START - MMCR1_EVT_SIZE)
602
603	/* PMU uses CTRL_RUN to sample PM_RUN_INST_CMPL */
604	#define CTRL_RUN PPC_BIT(63)
605
606	/* EBB/BESCR bits */
607	/* Global Enable */
608	#define BESCR_GE PPC_BIT(0)
609	/* External Event-based Exception Enable */
610	#define BESCR_EE PPC_BIT(30)
611	/* Performance Monitor Event-based Exception Enable */
612	#define BESCR_PME PPC_BIT(31)
613	/* External Event-based Exception Occurred */
614	#define BESCR_EEO PPC_BIT(62)
615	/* Performance Monitor Event-based Exception Occurred */
616	#define BESCR_PMEO PPC_BIT(63)
617	#define BESCR_INVALID PPC_BITMASK(32, 33)
618
619	/* LPCR bits */
620	#define LPCR_VPM0 PPC_BIT(0)
621	#define LPCR_VPM1 PPC_BIT(1)
622	#define LPCR_ISL PPC_BIT(2)
623	#define LPCR_KBV PPC_BIT(3)
624	#define LPCR_DPFD_SHIFT (63 - 11)
625	#define LPCR_DPFD (0x7ull << LPCR_DPFD_SHIFT)
626	#define LPCR_VRMASD_SHIFT (63 - 16)
627	#define LPCR_VRMASD (0x1full << LPCR_VRMASD_SHIFT)
628	/* P9: Power-saving mode Exit Cause Enable (Upper Section) Mask */
629	#define LPCR_PECE_U_SHIFT (63 - 19)
630	#define LPCR_PECE_U_MASK (0x7ull << LPCR_PECE_U_SHIFT)
631	#define LPCR_HVEE PPC_BIT(17) /* Hypervisor Virt Exit Enable */
632	#define LPCR_RMLS_SHIFT (63 - 37) /* RMLS (removed in ISA v3.0) */
633	#define LPCR_RMLS (0xfull << LPCR_RMLS_SHIFT)
634	#define LPCR_HAIL PPC_BIT(37) /* ISA v3.1 HV AIL=3 equivalent */
635	#define LPCR_ILE PPC_BIT(38)
636	#define LPCR_AIL_SHIFT (63 - 40) /* Alternate interrupt location */
637	#define LPCR_AIL (3ull << LPCR_AIL_SHIFT)
638	#define LPCR_UPRT PPC_BIT(41) /* Use Process Table */
639	#define LPCR_EVIRT PPC_BIT(42) /* Enhanced Virtualisation */
640	#define LPCR_HR PPC_BIT(43) /* Host Radix */
641	#define LPCR_ONL PPC_BIT(45)
642	#define LPCR_LD PPC_BIT(46) /* Large Decrementer */
643	#define LPCR_P7_PECE0 PPC_BIT(49)
644	#define LPCR_P7_PECE1 PPC_BIT(50)
645	#define LPCR_P7_PECE2 PPC_BIT(51)
646	#define LPCR_P8_PECE0 PPC_BIT(47)
647	#define LPCR_P8_PECE1 PPC_BIT(48)
648	#define LPCR_P8_PECE2 PPC_BIT(49)
649	#define LPCR_P8_PECE3 PPC_BIT(50)
650	#define LPCR_P8_PECE4 PPC_BIT(51)
651	/* P9: Power-saving mode Exit Cause Enable (Lower Section) Mask */
652	#define LPCR_PECE_L_SHIFT (63 - 51)
653	#define LPCR_PECE_L_MASK (0x1full << LPCR_PECE_L_SHIFT)
654	#define LPCR_PDEE PPC_BIT(47) /* Privileged Doorbell Exit EN */
655	#define LPCR_HDEE PPC_BIT(48) /* Hyperv Doorbell Exit Enable */
656	#define LPCR_EEE PPC_BIT(49) /* External Exit Enable */
657	#define LPCR_DEE PPC_BIT(50) /* Decrementer Exit Enable */
658	#define LPCR_OEE PPC_BIT(51) /* Other Exit Enable */
659	#define LPCR_MER PPC_BIT(52)
660	#define LPCR_GTSE PPC_BIT(53) /* Guest Translation Shootdown */
661	#define LPCR_TC PPC_BIT(54)
662	#define LPCR_HEIC PPC_BIT(59) /* HV Extern Interrupt Control */
663	#define LPCR_LPES0 PPC_BIT(60)
664	#define LPCR_LPES1 PPC_BIT(61)
665	#define LPCR_RMI PPC_BIT(62)
666	#define LPCR_HVICE PPC_BIT(62) /* HV Virtualisation Int Enable */
667	#define LPCR_HDICE PPC_BIT(63)
668
669	/* PSSCR bits */
670	#define PSSCR_ESL PPC_BIT(42) /* Enable State Loss */
671	#define PSSCR_EC PPC_BIT(43) /* Exit Criterion */
672
673	/* HFSCR bits */
674	#define HFSCR_MSGP PPC_BIT_NR(53) /* Privileged Message Send Facilities */
675	#define HFSCR_BHRB PPC_BIT_NR(59) /* BHRB Instructions */
676	#define HFSCR_IC_MSGP 0xA
677
678	#define DBCR0_ICMP (1 << 27)
679	#define DBCR0_BRT (1 << 26)
680	#define DBSR_ICMP (1 << 27)
681	#define DBSR_BRT (1 << 26)
682
683	/* Hypervisor bit is more specific */
684	#if defined(TARGET_PPC64)
685	#define MSR_HVB (1ULL << MSR_HV)
686	#else
687	#define MSR_HVB (0ULL)
688	#endif
689
690	/* DSISR */
691	#define DSISR_NOPTE 0x40000000
692	/* Not permitted by access authority of encoded access authority */
693	#define DSISR_PROTFAULT 0x08000000
694	#define DSISR_ISSTORE 0x02000000
695	/* Not permitted by virtual page class key protection */
696	#define DSISR_AMR 0x00200000
697	/* Unsupported Radix Tree Configuration */
698	#define DSISR_R_BADCONFIG 0x00080000
699	#define DSISR_ATOMIC_RC 0x00040000
700	/* Unable to translate address of (guest) pde or process/page table entry */
701	#define DSISR_PRTABLE_FAULT 0x00020000
702
703	/* SRR1 error code fields */
704
705	#define SRR1_NOPTE DSISR_NOPTE
706	/* Not permitted due to no-execute or guard bit set */
707	#define SRR1_NOEXEC_GUARD 0x10000000
708	#define SRR1_PROTFAULT DSISR_PROTFAULT
709	#define SRR1_IAMR DSISR_AMR
710
711	/* SRR1[42:45] wakeup fields for System Reset Interrupt */
712
713	#define SRR1_WAKEMASK 0x003c0000 /* reason for wakeup */
714
715	#define SRR1_WAKEHMI 0x00280000 /* Hypervisor maintenance */
716	#define SRR1_WAKEHVI 0x00240000 /* Hypervisor Virt. Interrupt (P9) */
717	#define SRR1_WAKEEE 0x00200000 /* External interrupt */
718	#define SRR1_WAKEDEC 0x00180000 /* Decrementer interrupt */
719	#define SRR1_WAKEDBELL 0x00140000 /* Privileged doorbell */
720	#define SRR1_WAKERESET 0x00100000 /* System reset */
721	#define SRR1_WAKEHDBELL 0x000c0000 /* Hypervisor doorbell */
722	#define SRR1_WAKESCOM 0x00080000 /* SCOM not in power-saving mode */
723
724	/* SRR1[46:47] power-saving exit mode */
725
726	#define SRR1_WAKESTATE 0x00030000 /* Powersave exit mask */
727
728	#define SRR1_WS_HVLOSS 0x00030000 /* HV resources not maintained */
729	#define SRR1_WS_GPRLOSS 0x00020000 /* GPRs not maintained */
730	#define SRR1_WS_NOLOSS 0x00010000 /* All resources maintained */
731
732	/* Facility Status and Control (FSCR) bits */
733	#define FSCR_EBB (63 - 56) /* Event-Based Branch Facility */
734	#define FSCR_TAR (63 - 55) /* Target Address Register */
735	#define FSCR_SCV (63 - 51) /* System call vectored */
736	/* Interrupt cause mask and position in FSCR. HFSCR has the same format */
737	#define FSCR_IC_MASK (0xFFULL)
738	#define FSCR_IC_POS (63 - 7)
739	#define FSCR_IC_DSCR_SPR3 2
740	#define FSCR_IC_PMU 3
741	#define FSCR_IC_BHRB 4
742	#define FSCR_IC_TM 5
743	#define FSCR_IC_EBB 7
744	#define FSCR_IC_TAR 8
745	#define FSCR_IC_SCV 12
746
747	/* Exception state register bits definition */
748	#define ESR_PIL PPC_BIT(36) /* Illegal Instruction */
749	#define ESR_PPR PPC_BIT(37) /* Privileged Instruction */
750	#define ESR_PTR PPC_BIT(38) /* Trap */
751	#define ESR_FP PPC_BIT(39) /* Floating-Point Operation */
752	#define ESR_ST PPC_BIT(40) /* Store Operation */
753	#define ESR_AP PPC_BIT(44) /* Auxiliary Processor Operation */
754	#define ESR_PUO PPC_BIT(45) /* Unimplemented Operation */
755	#define ESR_BO PPC_BIT(46) /* Byte Ordering */
756	#define ESR_PIE PPC_BIT(47) /* Imprecise exception */
757	#define ESR_DATA PPC_BIT(53) /* Data Access (Embedded page table) */
758	#define ESR_TLBI PPC_BIT(54) /* TLB Ineligible (Embedded page table) */
759	#define ESR_PT PPC_BIT(55) /* Page Table (Embedded page table) */
760	#define ESR_SPV PPC_BIT(56) /* SPE/VMX operation */
761	#define ESR_EPID PPC_BIT(57) /* External Process ID operation */
762	#define ESR_VLEMI PPC_BIT(58) /* VLE operation */
763	#define ESR_MIF PPC_BIT(62) /* Misaligned instruction (VLE) */
764
765	/* PPE42 Interrupt Status Register bits */
766	#define PPE42_ISR_SRSMS0 PPC_BIT_NR(48) /* Sys Reset State Machine State 0 */
767	#define PPE42_ISR_SRSMS1 PPC_BIT_NR(49) /* Sys Reset State Machine State 1 */
768	#define PPE42_ISR_SRSMS2 PPC_BIT_NR(50) /* Sys Reset State Machine State 2 */
769	#define PPE42_ISR_SRSMS3 PPC_BIT_NR(51) /* Sys Reset State Machine State 3 */
770	#define PPE42_ISR_EP PPC_BIT_NR(53) /* MSR[EE] Maskable Event Pending */
771	#define PPE42_ISR_PTR PPC_BIT_NR(56) /* Program Interrupt from trap */
772	#define PPE42_ISR_ST PPC_BIT_NR(57) /* Data Interrupt caused by store */
773	#define PPE42_ISR_MFE PPC_BIT_NR(60) /* Multiple Fault Error */
774	#define PPE42_ISR_MCS0 PPC_BIT_NR(61) /* Machine Check Status bit0 */
775	#define PPE42_ISR_MCS1 PPC_BIT_NR(62) /* Machine Check Status bit1 */
776	#define PPE42_ISR_MCS2 PPC_BIT_NR(63) /* Machine Check Status bit2 */
777	FIELD(PPE42_ISR, SRSMS, PPE42_ISR_SRSMS3, 4)
778	FIELD(PPE42_ISR, MCS, PPE42_ISR_MCS2, 3)
779
780	/* PPE42 Machine Check Status field values */
781	#define PPE42_ISR_MCS_INSTRUCTION 0
782	#define PPE42_ISR_MCS_DATA_LOAD 1
783	#define PPE42_ISR_MCS_DATA_PRECISE_STORE 2
784	#define PPE42_ISR_MCS_DATA_IMPRECISE_STORE 3
785	#define PPE42_ISR_MCS_PROGRAM 4
786	#define PPE42_ISR_MCS_ISI 5
787	#define PPE42_ISR_MCS_ALIGNMENT 6
788	#define PPE42_ISR_MCS_DSI 7
789
790	/* Transaction EXception And Summary Register bits */
791	#define TEXASR_FAILURE_PERSISTENT (63 - 7)
792	#define TEXASR_DISALLOWED (63 - 8)
793	#define TEXASR_NESTING_OVERFLOW (63 - 9)
794	#define TEXASR_FOOTPRINT_OVERFLOW (63 - 10)
795	#define TEXASR_SELF_INDUCED_CONFLICT (63 - 11)
796	#define TEXASR_NON_TRANSACTIONAL_CONFLICT (63 - 12)
797	#define TEXASR_TRANSACTION_CONFLICT (63 - 13)
798	#define TEXASR_TRANSLATION_INVALIDATION_CONFLICT (63 - 14)
799	#define TEXASR_IMPLEMENTATION_SPECIFIC (63 - 15)
800	#define TEXASR_INSTRUCTION_FETCH_CONFLICT (63 - 16)
801	#define TEXASR_ABORT (63 - 31)
802	#define TEXASR_SUSPENDED (63 - 32)
803	#define TEXASR_PRIVILEGE_HV (63 - 34)
804	#define TEXASR_PRIVILEGE_PR (63 - 35)
805	#define TEXASR_FAILURE_SUMMARY (63 - 36)
806	#define TEXASR_TFIAR_EXACT (63 - 37)
807	#define TEXASR_ROT (63 - 38)
808	#define TEXASR_TRANSACTION_LEVEL (63 - 52) /* 12 bits */
809
810	enum {
811	POWERPC_FLAG_NONE = 0x00000000,
812	/* Flag for MSR bit 25 signification (VRE/SPE) */
813	POWERPC_FLAG_SPE = 0x00000001,
814	POWERPC_FLAG_VRE = 0x00000002,
815	/* Flag for MSR bit 17 signification (TGPR/CE) */
816	POWERPC_FLAG_TGPR = 0x00000004,
817	POWERPC_FLAG_CE = 0x00000008,
818	/* Flag for MSR bit 10 signification (SE/DWE/UBLE) */
819	POWERPC_FLAG_SE = 0x00000010,
820	POWERPC_FLAG_DWE = 0x00000020,
821	POWERPC_FLAG_UBLE = 0x00000040,
822	/* Flag for MSR bit 9 signification (BE/DE) */
823	POWERPC_FLAG_BE = 0x00000080,
824	POWERPC_FLAG_DE = 0x00000100,
825	/* Flag for MSR bit 2 signification (PX/PMM) */
826	POWERPC_FLAG_PX = 0x00000200,
827	POWERPC_FLAG_PMM = 0x00000400,
828	/* Flag for special features */
829	/* Decrementer clock */
830	POWERPC_FLAG_BUS_CLK = 0x00020000,
831	/* Has CFAR */
832	POWERPC_FLAG_CFAR = 0x00040000,
833	/* Has VSX */
834	POWERPC_FLAG_VSX = 0x00080000,
835	/* Has Transaction Memory (ISA 2.07) */
836	POWERPC_FLAG_TM = 0x00100000,
837	/* Has SCV (ISA 3.00) */
838	POWERPC_FLAG_SCV = 0x00200000,
839	/* Has >1 thread per core */
840	POWERPC_FLAG_SMT = 0x00400000,
841	/* Using "LPAR per core" mode (as opposed to per-thread) */
842	POWERPC_FLAG_SMT_1LPAR = 0x00800000,
843	/* Has BHRB */
844	POWERPC_FLAG_BHRB = 0x01000000,
845	/* Use PPE42-specific behavior */
846	POWERPC_FLAG_PPE42 = 0x02000000,
847	};
848
849	/*
850	* Bits for env->hflags.
851	*
852	* Most of these bits overlap with corresponding bits in MSR,
853	* but some come from other sources. Those that do come from
854	* the MSR are validated in hreg_compute_hflags.
855	*/
856	enum {
857	HFLAGS_LE = 0, /* MSR_LE */
858	HFLAGS_HV = 1, /* computed from MSR_HV and other state */
859	HFLAGS_64 = 2, /* computed from MSR_CE and MSR_SF */
860	HFLAGS_GTSE = 3, /* computed from SPR_LPCR[GTSE] */
861	HFLAGS_DR = 4, /* MSR_DR */
862	HFLAGS_HR = 5, /* computed from SPR_LPCR[HR] */
863	HFLAGS_SPE = 6, /* from MSR_SPE if cpu has SPE; avoid overlap w/ MSR_VR */
864	HFLAGS_TM = 8, /* computed from MSR_TM */
865	HFLAGS_BE = 9, /* MSR_BE -- from elsewhere on embedded ppc */
866	HFLAGS_SE = 10, /* MSR_SE -- from elsewhere on embedded ppc */
867	HFLAGS_FP = 13, /* MSR_FP */
868	HFLAGS_PR = 14, /* MSR_PR */
869	HFLAGS_PMCC0 = 15, /* MMCR0 PMCC bit 0 */
870	HFLAGS_PMCC1 = 16, /* MMCR0 PMCC bit 1 */
871	HFLAGS_PMCJCE = 17, /* MMCR0 PMCjCE bit */
872	HFLAGS_PMC_OTHER = 18, /* PMC other than PMC5-6 is enabled */
873	HFLAGS_INSN_CNT = 19, /* PMU instruction count enabled */
874	HFLAGS_BHRB_ENABLE = 20, /* Summary flag for enabling BHRB */
875	HFLAGS_VSX = 23, /* MSR_VSX if cpu has VSX */
876	HFLAGS_VR = 25, /* MSR_VR if cpu has VRE */
877
878	HFLAGS_IMMU_IDX = 26, /* 26..28 -- the composite immu_idx */
879	HFLAGS_DMMU_IDX = 29, /* 29..31 -- the composite dmmu_idx */
880	};
881
882	/*****************************************************************************/
883	/* Floating point status and control register */
884	#define FPSCR_DRN2 PPC_BIT_NR(29) /* Decimal Floating-Point rounding ctrl. */
885	#define FPSCR_DRN1 PPC_BIT_NR(30) /* Decimal Floating-Point rounding ctrl. */
886	#define FPSCR_DRN0 PPC_BIT_NR(31) /* Decimal Floating-Point rounding ctrl. */
887	#define FPSCR_FX PPC_BIT_NR(32) /* Floating-point exception summary */
888	#define FPSCR_FEX PPC_BIT_NR(33) /* Floating-point enabled exception summ.*/
889	#define FPSCR_VX PPC_BIT_NR(34) /* Floating-point invalid op. excp. summ.*/
890	#define FPSCR_OX PPC_BIT_NR(35) /* Floating-point overflow exception */
891	#define FPSCR_UX PPC_BIT_NR(36) /* Floating-point underflow exception */
892	#define FPSCR_ZX PPC_BIT_NR(37) /* Floating-point zero divide exception */
893	#define FPSCR_XX PPC_BIT_NR(38) /* Floating-point inexact exception */
894	#define FPSCR_VXSNAN PPC_BIT_NR(39) /* Floating-point invalid op. excp (sNan)*/
895	#define FPSCR_VXISI PPC_BIT_NR(40) /* Floating-point invalid op. excp (inf) */
896	#define FPSCR_VXIDI PPC_BIT_NR(41) /* Floating-point invalid op. excp (inf) */
897	#define FPSCR_VXZDZ PPC_BIT_NR(42) /* Floating-point invalid op. excp (zero)*/
898	#define FPSCR_VXIMZ PPC_BIT_NR(43) /* Floating-point invalid op. excp (inf) */
899	#define FPSCR_VXVC PPC_BIT_NR(44) /* Floating-point invalid op. excp (comp)*/
900	#define FPSCR_FR PPC_BIT_NR(45) /* Floating-point fraction rounded */
901	#define FPSCR_FI PPC_BIT_NR(46) /* Floating-point fraction inexact */
902	#define FPSCR_C PPC_BIT_NR(47) /* Floating-point result class descriptor*/
903	#define FPSCR_FL PPC_BIT_NR(48) /* Floating-point less than or negative */
904	#define FPSCR_FG PPC_BIT_NR(49) /* Floating-point greater than or neg. */
905	#define FPSCR_FE PPC_BIT_NR(50) /* Floating-point equal or zero */
906	#define FPSCR_FU PPC_BIT_NR(51) /* Floating-point unordered or NaN */
907	#define FPSCR_FPCC PPC_BIT_NR(51) /* Floating-point condition code */
908	#define FPSCR_FPRF PPC_BIT_NR(51) /* Floating-point result flags */
909	#define FPSCR_VXSOFT PPC_BIT_NR(53) /* Floating-point invalid op. excp (soft)*/
910	#define FPSCR_VXSQRT PPC_BIT_NR(54) /* Floating-point invalid op. excp (sqrt)*/
911	#define FPSCR_VXCVI PPC_BIT_NR(55) /* Floating-point invalid op. excp (int) */
912	#define FPSCR_VE PPC_BIT_NR(56) /* Floating-point invalid op. excp enable*/
913	#define FPSCR_OE PPC_BIT_NR(57) /* Floating-point overflow excp. enable */
914	#define FPSCR_UE PPC_BIT_NR(58) /* Floating-point underflow excp. enable */
915	#define FPSCR_ZE PPC_BIT_NR(59) /* Floating-point zero divide excp enable*/
916	#define FPSCR_XE PPC_BIT_NR(60) /* Floating-point inexact excp. enable */
917	#define FPSCR_NI PPC_BIT_NR(61) /* Floating-point non-IEEE mode */
918	#define FPSCR_RN1 PPC_BIT_NR(62)
919	#define FPSCR_RN0 PPC_BIT_NR(63) /* Floating-point rounding control */
920	/* Invalid operation exception summary */
921	#define FPSCR_IX ((1 << FPSCR_VXSNAN) \| (1 << FPSCR_VXISI) \| \
922	(1 << FPSCR_VXIDI) \| (1 << FPSCR_VXZDZ) \| \
923	(1 << FPSCR_VXIMZ) \| (1 << FPSCR_VXVC) \| \
924	(1 << FPSCR_VXSOFT) \| (1 << FPSCR_VXSQRT) \| \
925	(1 << FPSCR_VXCVI))
926
927	FIELD(FPSCR, FI, FPSCR_FI, 1)
928
929	#define FP_DRN2 (1ull << FPSCR_DRN2)
930	#define FP_DRN1 (1ull << FPSCR_DRN1)
931	#define FP_DRN0 (1ull << FPSCR_DRN0)
932	#define FP_DRN (FP_DRN2 \| FP_DRN1 \| FP_DRN0)
933	#define FP_FX (1ull << FPSCR_FX)
934	#define FP_FEX (1ull << FPSCR_FEX)
935	#define FP_VX (1ull << FPSCR_VX)
936	#define FP_OX (1ull << FPSCR_OX)
937	#define FP_UX (1ull << FPSCR_UX)
938	#define FP_ZX (1ull << FPSCR_ZX)
939	#define FP_XX (1ull << FPSCR_XX)
940	#define FP_VXSNAN (1ull << FPSCR_VXSNAN)
941	#define FP_VXISI (1ull << FPSCR_VXISI)
942	#define FP_VXIDI (1ull << FPSCR_VXIDI)
943	#define FP_VXZDZ (1ull << FPSCR_VXZDZ)
944	#define FP_VXIMZ (1ull << FPSCR_VXIMZ)
945	#define FP_VXVC (1ull << FPSCR_VXVC)
946	#define FP_FR (1ull << FPSCR_FR)
947	#define FP_FI (1ull << FPSCR_FI)
948	#define FP_C (1ull << FPSCR_C)
949	#define FP_FL (1ull << FPSCR_FL)
950	#define FP_FG (1ull << FPSCR_FG)
951	#define FP_FE (1ull << FPSCR_FE)
952	#define FP_FU (1ull << FPSCR_FU)
953	#define FP_FPCC (FP_FL \| FP_FG \| FP_FE \| FP_FU)
954	#define FP_FPRF (FP_C \| FP_FPCC)
955	#define FP_VXSOFT (1ull << FPSCR_VXSOFT)
956	#define FP_VXSQRT (1ull << FPSCR_VXSQRT)
957	#define FP_VXCVI (1ull << FPSCR_VXCVI)
958	#define FP_VE (1ull << FPSCR_VE)
959	#define FP_OE (1ull << FPSCR_OE)
960	#define FP_UE (1ull << FPSCR_UE)
961	#define FP_ZE (1ull << FPSCR_ZE)
962	#define FP_XE (1ull << FPSCR_XE)
963	#define FP_NI (1ull << FPSCR_NI)
964	#define FP_RN1 (1ull << FPSCR_RN1)
965	#define FP_RN0 (1ull << FPSCR_RN0)
966	#define FP_RN (FP_RN1 \| FP_RN0)
967
968	#define FP_ENABLES (FP_VE \| FP_OE \| FP_UE \| FP_ZE \| FP_XE)
969	#define FP_STATUS (FP_FR \| FP_FI \| FP_FPRF)
970
971	/* the exception bits which can be cleared by mcrfs - includes FX */
972	#define FP_EX_CLEAR_BITS (FP_FX \| FP_OX \| FP_UX \| FP_ZX \| \
973	FP_XX \| FP_VXSNAN \| FP_VXISI \| FP_VXIDI \| \
974	FP_VXZDZ \| FP_VXIMZ \| FP_VXVC \| FP_VXSOFT \| \
975	FP_VXSQRT \| FP_VXCVI)
976
977	/* FPSCR bits that can be set by mtfsf, mtfsfi and mtfsb1 */
978	#define FPSCR_MTFS_MASK (~(MAKE_64BIT_MASK(36, 28) \| PPC_BIT(28) \| \
979	FP_FEX \| FP_VX \| PPC_BIT(52)))
980
981	/*****************************************************************************/
982	/* Vector status and control register */
983	#define VSCR_NJ 16 /* Vector non-java */
984	#define VSCR_SAT 0 /* Vector saturation */
985
986	/*****************************************************************************/
987	/* BookE e500 MMU registers */
988
989	#define MAS0_NV_SHIFT 0
990	#define MAS0_NV_MASK (0xfff << MAS0_NV_SHIFT)
991
992	#define MAS0_WQ_SHIFT 12
993	#define MAS0_WQ_MASK (3 << MAS0_WQ_SHIFT)
994	/* Write TLB entry regardless of reservation */
995	#define MAS0_WQ_ALWAYS (0 << MAS0_WQ_SHIFT)
996	/* Write TLB entry only already in use */
997	#define MAS0_WQ_COND (1 << MAS0_WQ_SHIFT)
998	/* Clear TLB entry */
999	#define MAS0_WQ_CLR_RSRV (2 << MAS0_WQ_SHIFT)
1000
1001	#define MAS0_HES_SHIFT 14
1002	#define MAS0_HES (1 << MAS0_HES_SHIFT)
1003
1004	#define MAS0_ESEL_SHIFT 16
1005	#define MAS0_ESEL_MASK (0xfff << MAS0_ESEL_SHIFT)
1006
1007	#define MAS0_TLBSEL_SHIFT 28
1008	#define MAS0_TLBSEL_MASK (3 << MAS0_TLBSEL_SHIFT)
1009	#define MAS0_TLBSEL_TLB0 (0 << MAS0_TLBSEL_SHIFT)
1010	#define MAS0_TLBSEL_TLB1 (1 << MAS0_TLBSEL_SHIFT)
1011	#define MAS0_TLBSEL_TLB2 (2 << MAS0_TLBSEL_SHIFT)
1012	#define MAS0_TLBSEL_TLB3 (3 << MAS0_TLBSEL_SHIFT)
1013
1014	#define MAS0_ATSEL_SHIFT 31
1015	#define MAS0_ATSEL (1 << MAS0_ATSEL_SHIFT)
1016	#define MAS0_ATSEL_TLB 0
1017	#define MAS0_ATSEL_LRAT MAS0_ATSEL
1018
1019	#define MAS1_TSIZE_SHIFT 7
1020	#define MAS1_TSIZE_MASK (0x1f << MAS1_TSIZE_SHIFT)
1021
1022	#define MAS1_TS_SHIFT 12
1023	#define MAS1_TS (1 << MAS1_TS_SHIFT)
1024
1025	#define MAS1_IND_SHIFT 13
1026	#define MAS1_IND (1 << MAS1_IND_SHIFT)
1027
1028	#define MAS1_TID_SHIFT 16
1029	#define MAS1_TID_MASK (0x3fff << MAS1_TID_SHIFT)
1030
1031	#define MAS1_IPROT_SHIFT 30
1032	#define MAS1_IPROT (1 << MAS1_IPROT_SHIFT)
1033
1034	#define MAS1_VALID_SHIFT 31
1035	#define MAS1_VALID 0x80000000
1036
1037	#define MAS2_EPN_SHIFT 12
1038	#define MAS2_EPN_MASK (~0ULL << MAS2_EPN_SHIFT)
1039
1040	#define MAS2_ACM_SHIFT 6
1041	#define MAS2_ACM (1 << MAS2_ACM_SHIFT)
1042
1043	#define MAS2_VLE_SHIFT 5
1044	#define MAS2_VLE (1 << MAS2_VLE_SHIFT)
1045
1046	#define MAS2_W_SHIFT 4
1047	#define MAS2_W (1 << MAS2_W_SHIFT)
1048
1049	#define MAS2_I_SHIFT 3
1050	#define MAS2_I (1 << MAS2_I_SHIFT)
1051
1052	#define MAS2_M_SHIFT 2
1053	#define MAS2_M (1 << MAS2_M_SHIFT)
1054
1055	#define MAS2_G_SHIFT 1
1056	#define MAS2_G (1 << MAS2_G_SHIFT)
1057
1058	#define MAS2_E_SHIFT 0
1059	#define MAS2_E (1 << MAS2_E_SHIFT)
1060
1061	#define MAS3_RPN_SHIFT 12
1062	#define MAS3_RPN_MASK (0xfffff << MAS3_RPN_SHIFT)
1063
1064	#define MAS3_U0 0x00000200
1065	#define MAS3_U1 0x00000100
1066	#define MAS3_U2 0x00000080
1067	#define MAS3_U3 0x00000040
1068	#define MAS3_UX 0x00000020
1069	#define MAS3_SX 0x00000010
1070	#define MAS3_UW 0x00000008
1071	#define MAS3_SW 0x00000004
1072	#define MAS3_UR 0x00000002
1073	#define MAS3_SR 0x00000001
1074	#define MAS3_SPSIZE_SHIFT 1
1075	#define MAS3_SPSIZE_MASK (0x3e << MAS3_SPSIZE_SHIFT)
1076
1077	#define MAS4_TLBSELD_SHIFT MAS0_TLBSEL_SHIFT
1078	#define MAS4_TLBSELD_MASK MAS0_TLBSEL_MASK
1079	#define MAS4_TIDSELD_MASK 0x00030000
1080	#define MAS4_TIDSELD_PID0 0x00000000
1081	#define MAS4_TIDSELD_PID1 0x00010000
1082	#define MAS4_TIDSELD_PID2 0x00020000
1083	#define MAS4_TIDSELD_PIDZ 0x00030000
1084	#define MAS4_INDD 0x00008000 /* Default IND */
1085	#define MAS4_TSIZED_SHIFT MAS1_TSIZE_SHIFT
1086	#define MAS4_TSIZED_MASK MAS1_TSIZE_MASK
1087	#define MAS4_ACMD 0x00000040
1088	#define MAS4_VLED 0x00000020
1089	#define MAS4_WD 0x00000010
1090	#define MAS4_ID 0x00000008
1091	#define MAS4_MD 0x00000004
1092	#define MAS4_GD 0x00000002
1093	#define MAS4_ED 0x00000001
1094	#define MAS4_WIMGED_MASK 0x0000001f /* Default WIMGE */
1095	#define MAS4_WIMGED_SHIFT 0
1096
1097	#define MAS5_SGS 0x80000000
1098	#define MAS5_SLPID_MASK 0x00000fff
1099
1100	#define MAS6_SPID0 0x3fff0000
1101	#define MAS6_SPID1 0x00007ffe
1102	#define MAS6_ISIZE(x) MAS1_TSIZE(x)
1103	#define MAS6_SAS 0x00000001
1104	#define MAS6_SPID MAS6_SPID0
1105	#define MAS6_SIND 0x00000002 /* Indirect page */
1106	#define MAS6_SIND_SHIFT 1
1107	#define MAS6_SPID_MASK 0x3fff0000
1108	#define MAS6_SPID_SHIFT 16
1109	#define MAS6_ISIZE_MASK 0x00000f80
1110	#define MAS6_ISIZE_SHIFT 7
1111
1112	#define MAS7_RPN 0xffffffff
1113
1114	#define MAS8_TGS 0x80000000
1115	#define MAS8_VF 0x40000000
1116	#define MAS8_TLBPID 0x00000fff
1117
1118	/* Bit definitions for MMUCFG */
1119	#define MMUCFG_MAVN 0x00000003 /* MMU Architecture Version Number */
1120	#define MMUCFG_MAVN_V1 0x00000000 /* v1.0 */
1121	#define MMUCFG_MAVN_V2 0x00000001 /* v2.0 */
1122	#define MMUCFG_NTLBS 0x0000000c /* Number of TLBs */
1123	#define MMUCFG_PIDSIZE 0x000007c0 /* PID Reg Size */
1124	#define MMUCFG_TWC 0x00008000 /* TLB Write Conditional (v2.0) */
1125	#define MMUCFG_LRAT 0x00010000 /* LRAT Supported (v2.0) */
1126	#define MMUCFG_RASIZE 0x00fe0000 /* Real Addr Size */
1127	#define MMUCFG_LPIDSIZE 0x0f000000 /* LPID Reg Size */
1128
1129	/* Bit definitions for MMUCSR0 */
1130	#define MMUCSR0_TLB1FI 0x00000002 /* TLB1 Flash invalidate */
1131	#define MMUCSR0_TLB0FI 0x00000004 /* TLB0 Flash invalidate */
1132	#define MMUCSR0_TLB2FI 0x00000040 /* TLB2 Flash invalidate */
1133	#define MMUCSR0_TLB3FI 0x00000020 /* TLB3 Flash invalidate */
1134	#define MMUCSR0_TLBFI (MMUCSR0_TLB0FI \| MMUCSR0_TLB1FI \| \
1135	MMUCSR0_TLB2FI \| MMUCSR0_TLB3FI)
1136	#define MMUCSR0_TLB0PS 0x00000780 /* TLB0 Page Size */
1137	#define MMUCSR0_TLB1PS 0x00007800 /* TLB1 Page Size */
1138	#define MMUCSR0_TLB2PS 0x00078000 /* TLB2 Page Size */
1139	#define MMUCSR0_TLB3PS 0x00780000 /* TLB3 Page Size */
1140
1141	/* TLBnCFG encoding */
1142	#define TLBnCFG_N_ENTRY 0x00000fff /* number of entries */
1143	#define TLBnCFG_HES 0x00002000 /* HW select supported */
1144	#define TLBnCFG_AVAIL 0x00004000 /* variable page size */
1145	#define TLBnCFG_IPROT 0x00008000 /* IPROT supported */
1146	#define TLBnCFG_GTWE 0x00010000 /* Guest can write */
1147	#define TLBnCFG_IND 0x00020000 /* IND entries supported */
1148	#define TLBnCFG_PT 0x00040000 /* Can load from page table */
1149	#define TLBnCFG_MINSIZE 0x00f00000 /* Minimum Page Size (v1.0) */
1150	#define TLBnCFG_MINSIZE_SHIFT 20
1151	#define TLBnCFG_MAXSIZE 0x000f0000 /* Maximum Page Size (v1.0) */
1152	#define TLBnCFG_MAXSIZE_SHIFT 16
1153	#define TLBnCFG_ASSOC 0xff000000 /* Associativity */
1154	#define TLBnCFG_ASSOC_SHIFT 24
1155
1156	/* TLBnPS encoding */
1157	#define TLBnPS_4K 0x00000004
1158	#define TLBnPS_8K 0x00000008
1159	#define TLBnPS_16K 0x00000010
1160	#define TLBnPS_32K 0x00000020
1161	#define TLBnPS_64K 0x00000040
1162	#define TLBnPS_128K 0x00000080
1163	#define TLBnPS_256K 0x00000100
1164	#define TLBnPS_512K 0x00000200
1165	#define TLBnPS_1M 0x00000400
1166	#define TLBnPS_2M 0x00000800
1167	#define TLBnPS_4M 0x00001000
1168	#define TLBnPS_8M 0x00002000
1169	#define TLBnPS_16M 0x00004000
1170	#define TLBnPS_32M 0x00008000
1171	#define TLBnPS_64M 0x00010000
1172	#define TLBnPS_128M 0x00020000
1173	#define TLBnPS_256M 0x00040000
1174	#define TLBnPS_512M 0x00080000
1175	#define TLBnPS_1G 0x00100000
1176	#define TLBnPS_2G 0x00200000
1177	#define TLBnPS_4G 0x00400000
1178	#define TLBnPS_8G 0x00800000
1179	#define TLBnPS_16G 0x01000000
1180	#define TLBnPS_32G 0x02000000
1181	#define TLBnPS_64G 0x04000000
1182	#define TLBnPS_128G 0x08000000
1183	#define TLBnPS_256G 0x10000000
1184
1185	/* tlbilx action encoding */
1186	#define TLBILX_T_ALL 0
1187	#define TLBILX_T_TID 1
1188	#define TLBILX_T_FULLMATCH 3
1189	#define TLBILX_T_CLASS0 4
1190	#define TLBILX_T_CLASS1 5
1191	#define TLBILX_T_CLASS2 6
1192	#define TLBILX_T_CLASS3 7
1193
1194	/* BookE 2.06 helper defines */
1195
1196	#define BOOKE206_FLUSH_TLB0 (1 << 0)
1197	#define BOOKE206_FLUSH_TLB1 (1 << 1)
1198	#define BOOKE206_FLUSH_TLB2 (1 << 2)
1199	#define BOOKE206_FLUSH_TLB3 (1 << 3)
1200
1201	/* number of possible TLBs */
1202	#define BOOKE206_MAX_TLBN 4
1203
1204	#define EPID_EPID_SHIFT 0x0
1205	#define EPID_EPID 0xFF
1206	#define EPID_ELPID_SHIFT 0x10
1207	#define EPID_ELPID 0x3F0000
1208	#define EPID_EGS 0x20000000
1209	#define EPID_EGS_SHIFT 29
1210	#define EPID_EAS 0x40000000
1211	#define EPID_EAS_SHIFT 30
1212	#define EPID_EPR 0x80000000
1213	#define EPID_EPR_SHIFT 31
1214	/* We don't support EGS and ELPID */
1215	#define EPID_MASK (EPID_EPID \| EPID_EAS \| EPID_EPR)
1216
1217	/*****************************************************************************/
1218	/* Server and Embedded Processor Control */
1219
1220	#define DBELL_TYPE_SHIFT 27
1221	#define DBELL_TYPE_MASK (0x1f << DBELL_TYPE_SHIFT)
1222	#define DBELL_TYPE_DBELL (0x00 << DBELL_TYPE_SHIFT)
1223	#define DBELL_TYPE_DBELL_CRIT (0x01 << DBELL_TYPE_SHIFT)
1224	#define DBELL_TYPE_G_DBELL (0x02 << DBELL_TYPE_SHIFT)
1225	#define DBELL_TYPE_G_DBELL_CRIT (0x03 << DBELL_TYPE_SHIFT)
1226	#define DBELL_TYPE_G_DBELL_MC (0x04 << DBELL_TYPE_SHIFT)
1227
1228	#define DBELL_TYPE_DBELL_SERVER (0x05 << DBELL_TYPE_SHIFT)
1229
1230	#define DBELL_BRDCAST_MASK PPC_BITMASK(37, 38)
1231	#define DBELL_BRDCAST_SHIFT 25
1232	#define DBELL_BRDCAST_SUBPROC (0x1 << DBELL_BRDCAST_SHIFT)
1233	#define DBELL_BRDCAST_CORE (0x2 << DBELL_BRDCAST_SHIFT)
1234
1235	#define DBELL_LPIDTAG_SHIFT 14
1236	#define DBELL_LPIDTAG_MASK (0xfff << DBELL_LPIDTAG_SHIFT)
1237	#define DBELL_PIRTAG_MASK 0x3fff
1238
1239	#define DBELL_PROCIDTAG_MASK PPC_BITMASK(44, 63)
1240
1241	#define PPC_PAGE_SIZES_MAX_SZ 8
1242
1243	struct ppc_radix_page_info {
1244	uint32_t count;
1245	uint32_t entries[PPC_PAGE_SIZES_MAX_SZ];
1246	};
1247
1248	/*****************************************************************************/
1249	/* Dynamic Execution Control Register */
1250
1251	#define DEXCR_ASPECT(name, num) \
1252	FIELD(DEXCR, PNH_##name, PPC_BIT_NR(num), 1) \
1253	FIELD(DEXCR, PRO_##name, PPC_BIT_NR(num + 32), 1) \
1254	FIELD(HDEXCR, HNU_##name, PPC_BIT_NR(num), 1) \
1255	FIELD(HDEXCR, ENF_##name, PPC_BIT_NR(num + 32), 1) \
1256
1257	DEXCR_ASPECT(SBHE, 0)
1258	DEXCR_ASPECT(IBRTPD, 1)
1259	DEXCR_ASPECT(SRAPD, 4)
1260	DEXCR_ASPECT(NPHIE, 5)
1261	DEXCR_ASPECT(PHIE, 6)
1262
1263	/*****************************************************************************/
1264	/* The whole PowerPC CPU context */
1265
1266	/*
1267	* PowerPC needs eight modes for different hypervisor/supervisor/guest
1268	* + real/paged mode combinations. The other two modes are for
1269	* external PID load/store.
1270	*/
1271	#define PPC_TLB_EPID_LOAD 8
1272	#define PPC_TLB_EPID_STORE 9
1273
1274	#define PPC_CPU_OPCODES_LEN 0x40
1275	#define PPC_CPU_INDIRECT_OPCODES_LEN 0x20
1276
1277	#define BHRB_MAX_NUM_ENTRIES_LOG2 (5)
1278	#define BHRB_MAX_NUM_ENTRIES (1 << BHRB_MAX_NUM_ENTRIES_LOG2)
1279
1280	struct CPUArchState {
1281	/* Most commonly used resources during translated code execution first */
1282	target_ulong gpr[32]; /* general purpose registers */
1283	target_ulong gprh[32]; /* storage for GPR MSB, used by the SPE extension */
1284	target_ulong lr;
1285	target_ulong ctr;
1286	uint32_t crf[8]; /* condition register */
1287	#if defined(TARGET_PPC64)
1288	target_ulong cfar;
1289	#endif
1290	target_ulong xer; /* XER (with SO, OV, CA split out) */
1291	target_ulong so;
1292	target_ulong ov;
1293	target_ulong ca;
1294	target_ulong ov32;
1295	target_ulong ca32;
1296
1297	target_ulong reserve_addr; /* Reservation address */
1298	target_ulong reserve_length; /* Reservation larx op size (bytes) */
1299	target_ulong reserve_val; /* Reservation value */
1300	#if defined(TARGET_PPC64)
1301	target_ulong reserve_val2;
1302	#endif
1303
1304	/* These are used in supervisor mode only */
1305	target_ulong msr; /* machine state register */
1306	target_ulong tgpr[4]; /* temporary general purpose registers, */
1307	/* used to speed-up TLB assist handlers */
1308
1309	target_ulong nip; /* next instruction pointer */
1310
1311	/* when a memory exception occurs, the access type is stored here */
1312	int access_type;
1313
1314	/* For SMT processors */
1315	bool has_smt_siblings;
1316	int core_index;
1317	int chip_index;
1318
1319	#if !defined(CONFIG_USER_ONLY)
1320	/* MMU context, only relevant for full system emulation */
1321	#if defined(TARGET_PPC64)
1322	ppc_slb_t slb[MAX_SLB_ENTRIES]; /* PowerPC 64 SLB area */
1323	struct CPUBreakpoint *ciabr_breakpoint;
1324	struct CPUWatchpoint *dawr_watchpoint[2];
1325	#endif
1326	target_ulong sr[32]; /* segment registers */
1327	uint32_t nb_BATs; /* number of BATs */
1328	target_ulong DBAT[2][8];
1329	target_ulong IBAT[2][8];
1330	/* PowerPC TLB registers (for 4xx, e500 and 60x software driven TLBs) */
1331	int32_t nb_tlb; /* Total number of TLB */
1332	int tlb_per_way; /* Speed-up helper: used to avoid divisions at run time */
1333	int nb_ways; /* Number of ways in the TLB set */
1334	int last_way; /* Last used way used to allocate TLB in a LRU way */
1335	int nb_pids; /* Number of available PID registers */
1336	int tlb_type; /* Type of TLB we're dealing with */
1337	ppc_tlb_t tlb; /* TLB is optional. Allocate them only if needed */
1338	#ifdef CONFIG_KVM
1339	bool tlb_dirty; /* Set to non-zero when modifying TLB */
1340	bool kvm_sw_tlb; /* non-zero if KVM SW TLB API is active */
1341	#endif /* CONFIG_KVM */
1342	uint32_t tlb_need_flush; /* Delayed flush needed */
1343	#define TLB_NEED_LOCAL_FLUSH 0x1
1344	#define TLB_NEED_GLOBAL_FLUSH 0x2
1345	#endif
1346
1347	/* Other registers */
1348	target_ulong spr[1024]; /* special purpose registers */
1349	ppc_spr_t spr_cb[1024];
1350	/* Composite status for PMC[1-6] enabled and counting insns or cycles. */
1351	uint8_t pmc_ins_cnt;
1352	uint8_t pmc_cyc_cnt;
1353	/* Vector status and control register, minus VSCR_SAT */
1354	uint32_t vscr;
1355	/* VSX registers (including FP and AVR) */
1356	ppc_vsr_t vsr[64] QEMU_ALIGNED(16);
1357	/* Non-zero if and only if VSCR_SAT should be set */
1358	ppc_vsr_t vscr_sat QEMU_ALIGNED(16);
1359	/* SPE registers */
1360	uint64_t spe_acc;
1361	uint32_t spe_fscr;
1362	/* SPE and Altivec share status as they'll never be used simultaneously */
1363	float_status vec_status;
1364	float_status fp_status; /* Floating point execution context */
1365	target_ulong fpscr; /* Floating point status and control register */
1366
1367	/* Internal devices resources */
1368	ppc_tb_t tb_env; / Time base and decrementer */
1369	ppc_dcr_t dcr_env; / Device control registers */
1370
1371	int dcache_line_size;
1372	int icache_line_size;
1373
1374	#ifdef TARGET_PPC64
1375	/* Branch History Rolling Buffer (BHRB) resources */
1376	target_ulong bhrb_num_entries;
1377	intptr_t bhrb_base;
1378	target_ulong bhrb_filter;
1379	target_ulong bhrb_offset;
1380	target_ulong bhrb_offset_mask;
1381	uint64_t bhrb[BHRB_MAX_NUM_ENTRIES];
1382	#endif
1383
1384	/* These resources are used during exception processing */
1385	/* CPU model definition */
1386	target_ulong msr_mask;
1387	powerpc_mmu_t mmu_model;
1388	powerpc_excp_t excp_model;
1389	powerpc_input_t bus_model;
1390	int bfd_mach;
1391	uint32_t flags;
1392	uint64_t insns_flags;
1393	uint64_t insns_flags2;
1394
1395	int error_code;
1396	uint32_t pending_interrupts;
1397	#if !defined(CONFIG_USER_ONLY)
1398	uint64_t excp_stats[POWERPC_EXCP_NB];
1399	/*
1400	* This is the IRQ controller, which is implementation dependent and only
1401	* relevant when emulating a complete machine. Note that this isn't used
1402	* by recent Book3s compatible CPUs (POWER7 and newer).
1403	*/
1404	uint32_t irq_input_state;
1405
1406	target_ulong excp_vectors[POWERPC_EXCP_NB]; /* Exception vectors */
1407	target_ulong excp_prefix;
1408	target_ulong ivor_mask;
1409	target_ulong ivpr_mask;
1410	target_ulong hreset_vector;
1411	hwaddr mpic_iack;
1412	bool mpic_proxy; /* true if the external proxy facility mode is enabled */
1413	bool has_hv_mode; /* set when the processor has an HV mode, thus HV priv */
1414	/* instructions and SPRs are diallowed if MSR:HV is 0 */
1415	/*
1416	* On P7/P8/P9, set when in PM state so we need to handle resume in a
1417	* special way (such as routing some resume causes to 0x100, i.e. sreset).
1418	*/
1419	bool resume_as_sreset;
1420
1421	/*
1422	* On powernv, quiesced means the CPU has been stopped using PC direct
1423	* control xscom registers.
1424	*
1425	* On spapr, quiesced means it is in the "RTAS stopped" state.
1426	*
1427	* The core halted/stopped variables aren't sufficient for this, because
1428	* they can be changed with various side-band operations like qmp cont,
1429	* powersave interrupts, etc.
1430	*/
1431	bool quiesced;
1432	#endif
1433
1434	/* These resources are used only in TCG */
1435	uint32_t hflags;
1436	target_ulong hflags_compat_nmsr; /* for migration compatibility */
1437
1438	/* Power management */
1439	int (check_pow)(CPUPPCState env);
1440
1441	/* attn instruction enable */
1442	int (check_attn)(CPUPPCState env);
1443
1444	#if !defined(CONFIG_USER_ONLY)
1445	void load_info; / holds boot loading state */
1446	#endif
1447
1448	/* booke timers */
1449
1450	/*
1451	* Specifies bit locations of the Time Base used to signal a fixed timer
1452	* exception on a transition from 0 to 1 (watchdog or fixed-interval timer)
1453	*
1454	* 0 selects the least significant bit, 63 selects the most significant bit
1455	*/
1456	uint8_t fit_period[4];
1457	uint8_t wdt_period[4];
1458
1459	/* Transactional memory state */
1460	target_ulong tm_gpr[32];
1461	ppc_avr_t tm_vsr[64];
1462	uint64_t tm_cr;
1463	uint64_t tm_lr;
1464	uint64_t tm_ctr;
1465	uint64_t tm_fpscr;
1466	uint64_t tm_amr;
1467	uint64_t tm_ppr;
1468	uint64_t tm_vrsave;
1469	uint32_t tm_vscr;
1470	uint64_t tm_dscr;
1471	uint64_t tm_tar;
1472
1473	/*
1474	* Timers used to fire performance monitor alerts
1475	* when counting cycles.
1476	*/
1477	QEMUTimer *pmu_cyc_overflow_timers[PMU_COUNTERS_NUM];
1478
1479	/*
1480	* PMU base time value used by the PMU to calculate
1481	* running cycles.
1482	*/
1483	uint64_t pmu_base_time;
1484	};
1485
1486	#define THREAD_SIBLING_FOREACH(cs, cs_sibling) \
1487	CPU_FOREACH(cs_sibling) \
1488	if ((POWERPC_CPU(cs)->env.chip_index == \
1489	POWERPC_CPU(cs_sibling)->env.chip_index) && \
1490	(POWERPC_CPU(cs)->env.core_index == \
1491	POWERPC_CPU(cs_sibling)->env.core_index))
1492
1493	#define SET_FIT_PERIOD(a_, b_, c_, d_) \
1494	do { \
1495	env->fit_period[0] = (a_); \
1496	env->fit_period[1] = (b_); \
1497	env->fit_period[2] = (c_); \
1498	env->fit_period[3] = (d_); \
1499	} while (0)
1500
1501	#define SET_WDT_PERIOD(a_, b_, c_, d_) \
1502	do { \
1503	env->wdt_period[0] = (a_); \
1504	env->wdt_period[1] = (b_); \
1505	env->wdt_period[2] = (c_); \
1506	env->wdt_period[3] = (d_); \
1507	} while (0)
1508
1509	typedef struct PPCVirtualHypervisor PPCVirtualHypervisor;
1510	typedef struct PPCVirtualHypervisorClass PPCVirtualHypervisorClass;
1511
1512	/**
1513	* PowerPCCPU:
1514	* @env: #CPUPPCState
1515	* @vcpu_id: vCPU identifier given to KVM
1516	* @compat_pvr: Current logical PVR, zero if in "raw" mode
1517	*
1518	* A PowerPC CPU.
1519	*/
1520	struct ArchCPU {
1521	CPUState parent_obj;
1522
1523	CPUPPCState env;
1524
1525	int vcpu_id;
1526	uint32_t compat_pvr;
1527	PPCVirtualHypervisor *vhyp;
1528	PPCVirtualHypervisorClass *vhyp_class;
1529	void *machine_data;
1530	int32_t node_id; /* NUMA node this CPU belongs to */
1531	PPCHash64Options *hash64_opts;
1532	bool rtas_stopped_state;
1533
1534	/* Those resources are used only during code translation */
1535	/* opcode handlers */
1536	opc_handler_t *opcodes[PPC_CPU_OPCODES_LEN];
1537	};
1538
1539	/**
1540	* PowerPCCPUClass:
1541	* @parent_realize: The parent class' realize handler.
1542	* @parent_phases: The parent class' reset phase handlers.
1543	*
1544	* A PowerPC CPU model.
1545	*/
1546	struct PowerPCCPUClass {
1547	CPUClass parent_class;
1548
1549	DeviceRealize parent_realize;
1550	DeviceUnrealize parent_unrealize;
1551	ResettablePhases parent_phases;
1552	void (parent_parse_features)(const char type, char str, Error *errp);
1553
1554	uint32_t pvr;
1555	uint32_t spapr_logical_pvr;
1556	/*
1557	* If @best is false, match if pcc is in the family of pvr
1558	* Else match only if pcc is the best match for pvr in this family.
1559	*/
1560	bool (pvr_match)(struct PowerPCCPUClass pcc, uint32_t pvr, bool best);
1561	uint64_t pcr_mask; /* Available bits in PCR register */
1562	uint64_t pcr_supported; /* Bits for supported PowerISA versions */
1563	uint32_t svr;
1564	uint64_t insns_flags;
1565	uint64_t insns_flags2;
1566	uint64_t msr_mask;
1567	uint64_t lpcr_mask; /* Available bits in the LPCR */
1568	uint64_t lpcr_pm; /* Power-saving mode Exit Cause Enable bits */
1569	powerpc_mmu_t mmu_model;
1570	powerpc_excp_t excp_model;
1571	powerpc_input_t bus_model;
1572	uint32_t flags;
1573	int bfd_mach;
1574	uint32_t l1_dcache_size, l1_icache_size;
1575	#ifndef CONFIG_USER_ONLY
1576	GDBFeature gdb_spr;
1577	#endif
1578	const PPCHash64Options *hash64_opts;
1579	struct ppc_radix_page_info *radix_page_info;
1580	uint32_t lrg_decr_bits;
1581	int n_host_threads;
1582	void (init_proc)(CPUPPCState env);
1583	int (check_pow)(CPUPPCState env);
1584	int (check_attn)(CPUPPCState env);
1585
1586	/* Handlers to be set by the machine initialising the chips */
1587	uint64_t (load_sprd)(CPUPPCState env);
1588	void (store_sprd)(CPUPPCState env, uint64_t val);
1589	};
1590
1591	static inline bool ppc_cpu_core_single_threaded(CPUState *cs)
1592	{
1593	return !POWERPC_CPU(cs)->env.has_smt_siblings;
1594	}
1595
1596	static inline bool ppc_cpu_lpar_single_threaded(CPUState *cs)
1597	{
1598	return !(POWERPC_CPU(cs)->env.flags & POWERPC_FLAG_SMT_1LPAR) \|\|
1599	ppc_cpu_core_single_threaded(cs);
1600	}
1601
1602	ObjectClass ppc_cpu_class_by_name(const char name);
1603	PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr);
1604	PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr);
1605	PowerPCCPUClass ppc_cpu_get_family_class(PowerPCCPUClass pcc);
1606
1607	#ifndef CONFIG_USER_ONLY
1608	struct PPCVirtualHypervisorClass {
1609	InterfaceClass parent;
1610	bool (cpu_in_nested)(PowerPCCPU cpu);
1611	void (deliver_hv_excp)(PowerPCCPU cpu, int excp);
1612	void (hypercall)(PPCVirtualHypervisor vhyp, PowerPCCPU *cpu);
1613	hwaddr (hpt_mask)(PPCVirtualHypervisor vhyp);
1614	const ppc_hash_pte64_t (map_hptes)(PPCVirtualHypervisor *vhyp,
1615	hwaddr ptex, int n);
1616	void (unmap_hptes)(PPCVirtualHypervisor vhyp,
1617	const ppc_hash_pte64_t *hptes,
1618	hwaddr ptex, int n);
1619	void (hpte_set_c)(PPCVirtualHypervisor vhyp, hwaddr ptex, uint64_t pte1);
1620	void (hpte_set_r)(PPCVirtualHypervisor vhyp, hwaddr ptex, uint64_t pte1);
1621	bool (get_pate)(PPCVirtualHypervisor vhyp, PowerPCCPU *cpu,
1622	target_ulong lpid, ppc_v3_pate_t *entry);
1623	target_ulong (encode_hpt_for_kvm_pr)(PPCVirtualHypervisor vhyp);
1624	void (cpu_exec_enter)(PPCVirtualHypervisor vhyp, PowerPCCPU *cpu);
1625	void (cpu_exec_exit)(PPCVirtualHypervisor vhyp, PowerPCCPU *cpu);
1626	};
1627
1628	#define TYPE_PPC_VIRTUAL_HYPERVISOR "ppc-virtual-hypervisor"
1629	DECLARE_OBJ_CHECKERS(PPCVirtualHypervisor, PPCVirtualHypervisorClass,
1630	PPC_VIRTUAL_HYPERVISOR, TYPE_PPC_VIRTUAL_HYPERVISOR)
1631
1632	static inline bool vhyp_cpu_in_nested(PowerPCCPU *cpu)
1633	{
1634	return cpu->vhyp_class->cpu_in_nested(cpu);
1635	}
1636	#endif /* CONFIG_USER_ONLY */
1637
1638	void ppc_cpu_dump_state(CPUState cpu, FILE f, int flags);
1639	int ppc_cpu_gdb_read_register(CPUState cpu, GByteArray buf, int reg);
1640	int ppc_cpu_gdb_write_register(CPUState cpu, uint8_t buf, int reg);
1641	#ifndef CONFIG_USER_ONLY
1642	hwaddr ppc_cpu_get_phys_addr_debug(CPUState *cpu, vaddr addr);
1643	#endif
1644	int ppc64_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
1645	int cpuid, DumpState *s);
1646	int ppc32_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,
1647	int cpuid, DumpState *s);
1648	#ifndef CONFIG_USER_ONLY
1649	void ppc_maybe_interrupt(CPUPPCState *env);
1650	void ppc_cpu_do_interrupt(CPUState *cpu);
1651	bool ppc_cpu_exec_interrupt(CPUState *cpu, int int_req);
1652	void ppc_cpu_do_system_reset(CPUState *cs);
1653	void ppc_cpu_do_fwnmi_machine_check(CPUState *cs, target_ulong vector);
1654	extern const VMStateDescription vmstate_ppc_cpu;
1655	#endif
1656
1657	/*****************************************************************************/
1658	void ppc_translate_init(void);
1659	void ppc_translate_code(CPUState cs, TranslationBlock tb,
1660	int max_insns, vaddr pc, void host_pc);
1661
1662	#if !defined(CONFIG_USER_ONLY)
1663	void ppc_store_sdr1(CPUPPCState *env, target_ulong value);
1664	void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong val);
1665	void ppc_update_ciabr(CPUPPCState *env);
1666	void ppc_store_ciabr(CPUPPCState *env, target_ulong value);
1667	void ppc_update_daw(CPUPPCState *env, int rid);
1668	void ppc_store_dawr0(CPUPPCState *env, target_ulong value);
1669	void ppc_store_dawrx0(CPUPPCState *env, uint32_t value);
1670	void ppc_store_dawr1(CPUPPCState *env, target_ulong value);
1671	void ppc_store_dawrx1(CPUPPCState *env, uint32_t value);
1672	#endif /* !defined(CONFIG_USER_ONLY) */
1673	void ppc_store_msr(CPUPPCState *env, target_ulong value);
1674
1675	/* Time-base and decrementer management */
1676	uint64_t cpu_ppc_load_tbl(CPUPPCState *env);
1677	uint32_t cpu_ppc_load_tbu(CPUPPCState *env);
1678	void cpu_ppc_store_tbu(CPUPPCState *env, uint32_t value);
1679	void cpu_ppc_store_tbl(CPUPPCState *env, uint32_t value);
1680	uint64_t cpu_ppc_load_atbl(CPUPPCState *env);
1681	uint32_t cpu_ppc_load_atbu(CPUPPCState *env);
1682	void cpu_ppc_store_atbl(CPUPPCState *env, uint32_t value);
1683	void cpu_ppc_store_atbu(CPUPPCState *env, uint32_t value);
1684	void cpu_ppc_increase_tb_by_offset(CPUPPCState *env, int64_t offset);
1685	void cpu_ppc_decrease_tb_by_offset(CPUPPCState *env, int64_t offset);
1686	uint64_t cpu_ppc_load_vtb(CPUPPCState *env);
1687	void cpu_ppc_store_vtb(CPUPPCState *env, uint64_t value);
1688	bool ppc_decr_clear_on_delivery(CPUPPCState *env);
1689	target_ulong cpu_ppc_load_decr(CPUPPCState *env);
1690	void cpu_ppc_store_decr(CPUPPCState *env, target_ulong value);
1691	target_ulong cpu_ppc_load_hdecr(CPUPPCState *env);
1692	void cpu_ppc_store_hdecr(CPUPPCState *env, target_ulong value);
1693	void cpu_ppc_store_tbu40(CPUPPCState *env, uint64_t value);
1694	uint64_t cpu_ppc_load_purr(CPUPPCState *env);
1695	void cpu_ppc_store_purr(CPUPPCState *env, uint64_t value);
1696	int64_t cpu_ppc_load_tb_offset(CPUPPCState *env);
1697	#if !defined(CONFIG_USER_ONLY)
1698	target_ulong load_40x_pit(CPUPPCState *env);
1699	void store_40x_pit(CPUPPCState *env, target_ulong val);
1700	void store_40x_dbcr0(CPUPPCState *env, uint32_t val);
1701	void store_40x_sler(CPUPPCState *env, uint32_t val);
1702	void store_40x_tcr(CPUPPCState *env, target_ulong val);
1703	void store_40x_tsr(CPUPPCState *env, target_ulong val);
1704	void store_booke_tcr(CPUPPCState *env, target_ulong val);
1705	void store_booke_tsr(CPUPPCState *env, target_ulong val);
1706	void ppc_tlb_invalidate_all(CPUPPCState *env);
1707	void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr);
1708	void cpu_ppc_set_vhyp(PowerPCCPU cpu, PPCVirtualHypervisor vhyp);
1709	void cpu_ppc_set_1lpar(PowerPCCPU *cpu);
1710	#endif
1711
1712	void ppc_store_fpscr(CPUPPCState *env, target_ulong val);
1713	void helper_hfscr_facility_check(CPUPPCState *env, uint32_t bit,
1714	const char *caller, uint32_t cause);
1715
1716	static inline uint64_t ppc_dump_gpr(CPUPPCState *env, int gprn)
1717	{
1718	uint64_t gprv;
1719
1720	gprv = env->gpr[gprn];
1721	if (env->flags & POWERPC_FLAG_SPE) {
1722	/*
1723	* If the CPU implements the SPE extension, we have to get the
1724	* high bits of the GPR from the gprh storage area
1725	*/
1726	gprv &= 0xFFFFFFFFULL;
1727	gprv \|= (uint64_t)env->gprh[gprn] << 32;
1728	}
1729
1730	return gprv;
1731	}
1732
1733	/* Device control registers */
1734	int ppc_dcr_read(ppc_dcr_t dcr_env, int dcrn, uint32_t valp);
1735	int ppc_dcr_write(ppc_dcr_t *dcr_env, int dcrn, uint32_t val);
1736
1737	/* MMU modes definitions */
1738	#define MMU_USER_IDX 0
1739	static inline int ppc_env_mmu_index(CPUPPCState *env, bool ifetch)
1740	{
1741	#ifdef CONFIG_USER_ONLY
1742	return MMU_USER_IDX;
1743	#else
1744	return (env->hflags >> (ifetch ? HFLAGS_IMMU_IDX : HFLAGS_DMMU_IDX)) & 7;
1745	#endif
1746	}
1747
1748	/* Compatibility modes */
1749	#if defined(TARGET_PPC64)
1750	bool ppc_check_compat(PowerPCCPU *cpu, uint32_t compat_pvr,
1751	uint32_t min_compat_pvr, uint32_t max_compat_pvr);
1752	bool ppc_type_check_compat(const char *cputype, uint32_t compat_pvr,
1753	uint32_t min_compat_pvr, uint32_t max_compat_pvr);
1754
1755	int ppc_set_compat(PowerPCCPU cpu, uint32_t compat_pvr, Error *errp);
1756
1757	#if !defined(CONFIG_USER_ONLY)
1758	int ppc_set_compat_all(uint32_t compat_pvr, Error **errp);
1759	int ppc_init_compat_all(uint32_t compat_pvr, Error **errp);
1760	#endif
1761	int ppc_compat_max_vthreads(PowerPCCPU *cpu);
1762	void ppc_compat_add_property(Object obj, const char name,
1763	uint32_t compat_pvr, const char basedesc);
1764	#endif /* defined(TARGET_PPC64) */
1765
1766	/*****************************************************************************/
1767	/* CRF definitions */
1768	#define CRF_LT_BIT 3
1769	#define CRF_GT_BIT 2
1770	#define CRF_EQ_BIT 1
1771	#define CRF_SO_BIT 0
1772	#define CRF_LT (1 << CRF_LT_BIT)
1773	#define CRF_GT (1 << CRF_GT_BIT)
1774	#define CRF_EQ (1 << CRF_EQ_BIT)
1775	#define CRF_SO (1 << CRF_SO_BIT)
1776	/* For SPE extensions */
1777	#define CRF_CH (1 << CRF_LT_BIT)
1778	#define CRF_CL (1 << CRF_GT_BIT)
1779	#define CRF_CH_OR_CL (1 << CRF_EQ_BIT)
1780	#define CRF_CH_AND_CL (1 << CRF_SO_BIT)
1781
1782	/* XER definitions */
1783	#define XER_SO 31
1784	#define XER_OV 30
1785	#define XER_CA 29
1786	#define XER_OV32 19
1787	#define XER_CA32 18
1788	#define XER_CMP 8
1789	#define XER_BC 0
1790	#define xer_so (env->so)
1791	#define xer_cmp ((env->xer >> XER_CMP) & 0xFF)
1792	#define xer_bc ((env->xer >> XER_BC) & 0x7F)
1793
1794	/* SPR definitions */
1795	#define SPR_MQ (0x000)
1796	#define SPR_XER (0x001)
1797	#define SPR_LR (0x008)
1798	#define SPR_CTR (0x009)
1799	#define SPR_UAMR (0x00D)
1800	#define SPR_DSCR (0x011)
1801	#define SPR_DSISR (0x012)
1802	#define SPR_DAR (0x013)
1803	#define SPR_DECR (0x016)
1804	#define SPR_SDR1 (0x019)
1805	#define SPR_SRR0 (0x01A)
1806	#define SPR_SRR1 (0x01B)
1807	#define SPR_CFAR (0x01C)
1808	#define SPR_AMR (0x01D)
1809	#define SPR_ACOP (0x01F)
1810	#define SPR_BOOKE_PID (0x030)
1811	#define SPR_BOOKS_PID (0x030)
1812	#define SPR_BOOKE_DECAR (0x036)
1813	#define SPR_BOOKE_CSRR0 (0x03A)
1814	#define SPR_BOOKE_CSRR1 (0x03B)
1815	#define SPR_BOOKE_DEAR (0x03D)
1816	#define SPR_PPE42_EDR (0x03D)
1817	#define SPR_IAMR (0x03D)
1818	#define SPR_BOOKE_ESR (0x03E)
1819	#define SPR_PPE42_ISR (0x03E)
1820	#define SPR_BOOKE_IVPR (0x03F)
1821	#define SPR_PPE42_IVPR (0x03F)
1822	#define SPR_MPC_EIE (0x050)
1823	#define SPR_MPC_EID (0x051)
1824	#define SPR_MPC_NRI (0x052)
1825	#define SPR_TFHAR (0x080)
1826	#define SPR_TFIAR (0x081)
1827	#define SPR_TEXASR (0x082)
1828	#define SPR_TEXASRU (0x083)
1829	#define SPR_UCTRL (0x088)
1830	#define SPR_TIDR (0x090)
1831	#define SPR_MPC_CMPA (0x090)
1832	#define SPR_MPC_CMPB (0x091)
1833	#define SPR_MPC_CMPC (0x092)
1834	#define SPR_MPC_CMPD (0x093)
1835	#define SPR_MPC_ECR (0x094)
1836	#define SPR_MPC_DER (0x095)
1837	#define SPR_MPC_COUNTA (0x096)
1838	#define SPR_MPC_COUNTB (0x097)
1839	#define SPR_CTRL (0x098)
1840	#define SPR_MPC_CMPE (0x098)
1841	#define SPR_MPC_CMPF (0x099)
1842	#define SPR_FSCR (0x099)
1843	#define SPR_MPC_CMPG (0x09A)
1844	#define SPR_MPC_CMPH (0x09B)
1845	#define SPR_MPC_LCTRL1 (0x09C)
1846	#define SPR_MPC_LCTRL2 (0x09D)
1847	#define SPR_UAMOR (0x09D)
1848	#define SPR_MPC_ICTRL (0x09E)
1849	#define SPR_MPC_BAR (0x09F)
1850	#define SPR_PSPB (0x09F)
1851	#define SPR_DPDES (0x0B0)
1852	#define SPR_DAWR0 (0x0B4)
1853	#define SPR_DAWR1 (0x0B5)
1854	#define SPR_RPR (0x0BA)
1855	#define SPR_CIABR (0x0BB)
1856	#define SPR_DAWRX0 (0x0BC)
1857	#define SPR_DAWRX1 (0x0BD)
1858	#define SPR_HFSCR (0x0BE)
1859	#define SPR_VRSAVE (0x100)
1860	#define SPR_USPRG0 (0x100)
1861	#define SPR_USPRG1 (0x101)
1862	#define SPR_USPRG2 (0x102)
1863	#define SPR_USPRG3 (0x103)
1864	#define SPR_USPRG4 (0x104)
1865	#define SPR_USPRG5 (0x105)
1866	#define SPR_USPRG6 (0x106)
1867	#define SPR_USPRG7 (0x107)
1868	#define SPR_TBL (0x10C)
1869	#define SPR_TBU (0x10D)
1870	#define SPR_SPRG0 (0x110)
1871	#define SPR_SPRG1 (0x111)
1872	#define SPR_SPRG2 (0x112)
1873	#define SPR_SPRG3 (0x113)
1874	#define SPR_SPRG4 (0x114)
1875	#define SPR_POWER_SPRC (0x114)
1876	#define SPR_SPRG5 (0x115)
1877	#define SPR_POWER_SPRD (0x115)
1878	#define SPR_SPRG6 (0x116)
1879	#define SPR_SPRG7 (0x117)
1880	#define SPR_ASR (0x118)
1881	#define SPR_EAR (0x11A)
1882	#define SPR_WR_TBL (0x11C)
1883	#define SPR_WR_TBU (0x11D)
1884	#define SPR_TBU40 (0x11E)
1885	#define SPR_SVR (0x11E)
1886	#define SPR_BOOKE_PIR (0x11E)
1887	#define SPR_PPE42_PIR (0x11E)
1888	#define SPR_PVR (0x11F)
1889	#define SPR_HSPRG0 (0x130)
1890	#define SPR_BOOKE_DBSR (0x130)
1891	#define SPR_HSPRG1 (0x131)
1892	#define SPR_HDSISR (0x132)
1893	#define SPR_HDAR (0x133)
1894	#define SPR_BOOKE_EPCR (0x133)
1895	#define SPR_SPURR (0x134)
1896	#define SPR_BOOKE_DBCR0 (0x134)
1897	#define SPR_PPE42_DBCR (0x134)
1898	#define SPR_IBCR (0x135)
1899	#define SPR_PURR (0x135)
1900	#define SPR_BOOKE_DBCR1 (0x135)
1901	#define SPR_DBCR (0x136)
1902	#define SPR_HDEC (0x136)
1903	#define SPR_BOOKE_DBCR2 (0x136)
1904	#define SPR_HIOR (0x137)
1905	#define SPR_MBAR (0x137)
1906	#define SPR_RMOR (0x138)
1907	#define SPR_BOOKE_IAC1 (0x138)
1908	#define SPR_HRMOR (0x139)
1909	#define SPR_BOOKE_IAC2 (0x139)
1910	#define SPR_HSRR0 (0x13A)
1911	#define SPR_BOOKE_IAC3 (0x13A)
1912	#define SPR_HSRR1 (0x13B)
1913	#define SPR_BOOKE_IAC4 (0x13B)
1914	#define SPR_BOOKE_DAC1 (0x13C)
1915	#define SPR_PPE42_DACR (0x13C)
1916	#define SPR_MMCRH (0x13C)
1917	#define SPR_DABR2 (0x13D)
1918	#define SPR_BOOKE_DAC2 (0x13D)
1919	#define SPR_TFMR (0x13D)
1920	#define SPR_BOOKE_DVC1 (0x13E)
1921	#define SPR_LPCR (0x13E)
1922	#define SPR_BOOKE_DVC2 (0x13F)
1923	#define SPR_LPIDR (0x13F)
1924	#define SPR_BOOKE_TSR (0x150)
1925	#define SPR_PPE42_TSR (0x150)
1926	#define SPR_HMER (0x150)
1927	#define SPR_HMEER (0x151)
1928	#define SPR_PCR (0x152)
1929	#define SPR_HEIR (0x153)
1930	#define SPR_BOOKE_LPIDR (0x152)
1931	#define SPR_BOOKE_TCR (0x154)
1932	#define SPR_PPE42_TCR (0x154)
1933	#define SPR_BOOKE_TLB0PS (0x158)
1934	#define SPR_BOOKE_TLB1PS (0x159)
1935	#define SPR_BOOKE_TLB2PS (0x15A)
1936	#define SPR_BOOKE_TLB3PS (0x15B)
1937	#define SPR_AMOR (0x15D)
1938	#define SPR_BOOKE_MAS7_MAS3 (0x174)
1939	#define SPR_BOOKE_IVOR0 (0x190)
1940	#define SPR_BOOKE_IVOR1 (0x191)
1941	#define SPR_BOOKE_IVOR2 (0x192)
1942	#define SPR_BOOKE_IVOR3 (0x193)
1943	#define SPR_BOOKE_IVOR4 (0x194)
1944	#define SPR_BOOKE_IVOR5 (0x195)
1945	#define SPR_BOOKE_IVOR6 (0x196)
1946	#define SPR_BOOKE_IVOR7 (0x197)
1947	#define SPR_BOOKE_IVOR8 (0x198)
1948	#define SPR_BOOKE_IVOR9 (0x199)
1949	#define SPR_BOOKE_IVOR10 (0x19A)
1950	#define SPR_BOOKE_IVOR11 (0x19B)
1951	#define SPR_BOOKE_IVOR12 (0x19C)
1952	#define SPR_BOOKE_IVOR13 (0x19D)
1953	#define SPR_BOOKE_IVOR14 (0x19E)
1954	#define SPR_BOOKE_IVOR15 (0x19F)
1955	#define SPR_BOOKE_IVOR38 (0x1B0)
1956	#define SPR_BOOKE_IVOR39 (0x1B1)
1957	#define SPR_BOOKE_IVOR40 (0x1B2)
1958	#define SPR_BOOKE_IVOR41 (0x1B3)
1959	#define SPR_BOOKE_IVOR42 (0x1B4)
1960	#define SPR_BOOKE_GIVOR2 (0x1B8)
1961	#define SPR_BOOKE_GIVOR3 (0x1B9)
1962	#define SPR_BOOKE_GIVOR4 (0x1BA)
1963	#define SPR_BOOKE_GIVOR8 (0x1BB)
1964	#define SPR_BOOKE_GIVOR13 (0x1BC)
1965	#define SPR_BOOKE_GIVOR14 (0x1BD)
1966	#define SPR_TIR (0x1BE)
1967	#define SPR_UHDEXCR (0x1C7)
1968	#define SPR_PTCR (0x1D0)
1969	#define SPR_HASHKEYR (0x1D4)
1970	#define SPR_HASHPKEYR (0x1D5)
1971	#define SPR_HDEXCR (0x1D7)
1972	#define SPR_BOOKE_SPEFSCR (0x200)
1973	#define SPR_Exxx_BBEAR (0x201)
1974	#define SPR_Exxx_BBTAR (0x202)
1975	#define SPR_Exxx_L1CFG0 (0x203)
1976	#define SPR_Exxx_L1CFG1 (0x204)
1977	#define SPR_Exxx_NPIDR (0x205)
1978	#define SPR_ATBL (0x20E)
1979	#define SPR_ATBU (0x20F)
1980	#define SPR_IBAT0U (0x210)
1981	#define SPR_BOOKE_IVOR32 (0x210)
1982	#define SPR_RCPU_MI_GRA (0x210)
1983	#define SPR_IBAT0L (0x211)
1984	#define SPR_BOOKE_IVOR33 (0x211)
1985	#define SPR_IBAT1U (0x212)
1986	#define SPR_BOOKE_IVOR34 (0x212)
1987	#define SPR_IBAT1L (0x213)
1988	#define SPR_BOOKE_IVOR35 (0x213)
1989	#define SPR_IBAT2U (0x214)
1990	#define SPR_BOOKE_IVOR36 (0x214)
1991	#define SPR_IBAT2L (0x215)
1992	#define SPR_BOOKE_IVOR37 (0x215)
1993	#define SPR_IBAT3U (0x216)
1994	#define SPR_IBAT3L (0x217)
1995	#define SPR_DBAT0U (0x218)
1996	#define SPR_RCPU_L2U_GRA (0x218)
1997	#define SPR_DBAT0L (0x219)
1998	#define SPR_DBAT1U (0x21A)
1999	#define SPR_DBAT1L (0x21B)
2000	#define SPR_DBAT2U (0x21C)
2001	#define SPR_DBAT2L (0x21D)
2002	#define SPR_DBAT3U (0x21E)
2003	#define SPR_DBAT3L (0x21F)
2004	#define SPR_IBAT4U (0x230)
2005	#define SPR_RPCU_BBCMCR (0x230)
2006	#define SPR_MPC_IC_CST (0x230)
2007	#define SPR_Exxx_CTXCR (0x230)
2008	#define SPR_IBAT4L (0x231)
2009	#define SPR_MPC_IC_ADR (0x231)
2010	#define SPR_Exxx_DBCR3 (0x231)
2011	#define SPR_IBAT5U (0x232)
2012	#define SPR_MPC_IC_DAT (0x232)
2013	#define SPR_Exxx_DBCNT (0x232)
2014	#define SPR_IBAT5L (0x233)
2015	#define SPR_IBAT6U (0x234)
2016	#define SPR_IBAT6L (0x235)
2017	#define SPR_IBAT7U (0x236)
2018	#define SPR_IBAT7L (0x237)
2019	#define SPR_DBAT4U (0x238)
2020	#define SPR_RCPU_L2U_MCR (0x238)
2021	#define SPR_MPC_DC_CST (0x238)
2022	#define SPR_Exxx_ALTCTXCR (0x238)
2023	#define SPR_DBAT4L (0x239)
2024	#define SPR_MPC_DC_ADR (0x239)
2025	#define SPR_DBAT5U (0x23A)
2026	#define SPR_BOOKE_MCSRR0 (0x23A)
2027	#define SPR_MPC_DC_DAT (0x23A)
2028	#define SPR_DBAT5L (0x23B)
2029	#define SPR_BOOKE_MCSRR1 (0x23B)
2030	#define SPR_DBAT6U (0x23C)
2031	#define SPR_BOOKE_MCSR (0x23C)
2032	#define SPR_DBAT6L (0x23D)
2033	#define SPR_Exxx_MCAR (0x23D)
2034	#define SPR_DBAT7U (0x23E)
2035	#define SPR_BOOKE_DSRR0 (0x23E)
2036	#define SPR_DBAT7L (0x23F)
2037	#define SPR_BOOKE_DSRR1 (0x23F)
2038	#define SPR_BOOKE_SPRG8 (0x25C)
2039	#define SPR_BOOKE_SPRG9 (0x25D)
2040	#define SPR_BOOKE_MAS0 (0x270)
2041	#define SPR_BOOKE_MAS1 (0x271)
2042	#define SPR_BOOKE_MAS2 (0x272)
2043	#define SPR_BOOKE_MAS3 (0x273)
2044	#define SPR_BOOKE_MAS4 (0x274)
2045	#define SPR_BOOKE_MAS5 (0x275)
2046	#define SPR_BOOKE_MAS6 (0x276)
2047	#define SPR_BOOKE_PID1 (0x279)
2048	#define SPR_BOOKE_PID2 (0x27A)
2049	#define SPR_MPC_DPDR (0x280)
2050	#define SPR_MPC_IMMR (0x288)
2051	#define SPR_BOOKE_TLB0CFG (0x2B0)
2052	#define SPR_BOOKE_TLB1CFG (0x2B1)
2053	#define SPR_BOOKE_TLB2CFG (0x2B2)
2054	#define SPR_BOOKE_TLB3CFG (0x2B3)
2055	#define SPR_BOOKE_EPR (0x2BE)
2056	#define SPR_POWER_USIER2 (0x2E0)
2057	#define SPR_POWER_USIER3 (0x2E1)
2058	#define SPR_POWER_UMMCR3 (0x2E2)
2059	#define SPR_POWER_SIER2 (0x2F0)
2060	#define SPR_POWER_SIER3 (0x2F1)
2061	#define SPR_POWER_MMCR3 (0x2F2)
2062	#define SPR_PERF0 (0x300)
2063	#define SPR_RCPU_MI_RBA0 (0x300)
2064	#define SPR_MPC_MI_CTR (0x300)
2065	#define SPR_POWER_USIER (0x300)
2066	#define SPR_PERF1 (0x301)
2067	#define SPR_RCPU_MI_RBA1 (0x301)
2068	#define SPR_POWER_UMMCR2 (0x301)
2069	#define SPR_PERF2 (0x302)
2070	#define SPR_RCPU_MI_RBA2 (0x302)
2071	#define SPR_MPC_MI_AP (0x302)
2072	#define SPR_POWER_UMMCRA (0x302)
2073	#define SPR_PERF3 (0x303)
2074	#define SPR_RCPU_MI_RBA3 (0x303)
2075	#define SPR_MPC_MI_EPN (0x303)
2076	#define SPR_POWER_UPMC1 (0x303)
2077	#define SPR_PERF4 (0x304)
2078	#define SPR_POWER_UPMC2 (0x304)
2079	#define SPR_PERF5 (0x305)
2080	#define SPR_MPC_MI_TWC (0x305)
2081	#define SPR_POWER_UPMC3 (0x305)
2082	#define SPR_PERF6 (0x306)
2083	#define SPR_MPC_MI_RPN (0x306)
2084	#define SPR_POWER_UPMC4 (0x306)
2085	#define SPR_PERF7 (0x307)
2086	#define SPR_POWER_UPMC5 (0x307)
2087	#define SPR_PERF8 (0x308)
2088	#define SPR_RCPU_L2U_RBA0 (0x308)
2089	#define SPR_MPC_MD_CTR (0x308)
2090	#define SPR_POWER_UPMC6 (0x308)
2091	#define SPR_PERF9 (0x309)
2092	#define SPR_RCPU_L2U_RBA1 (0x309)
2093	#define SPR_MPC_MD_CASID (0x309)
2094	#define SPR_970_UPMC7 (0X309)
2095	#define SPR_PERFA (0x30A)
2096	#define SPR_RCPU_L2U_RBA2 (0x30A)
2097	#define SPR_MPC_MD_AP (0x30A)
2098	#define SPR_970_UPMC8 (0X30A)
2099	#define SPR_PERFB (0x30B)
2100	#define SPR_RCPU_L2U_RBA3 (0x30B)
2101	#define SPR_MPC_MD_EPN (0x30B)
2102	#define SPR_POWER_UMMCR0 (0X30B)
2103	#define SPR_PERFC (0x30C)
2104	#define SPR_MPC_MD_TWB (0x30C)
2105	#define SPR_POWER_USIAR (0X30C)
2106	#define SPR_PERFD (0x30D)
2107	#define SPR_MPC_MD_TWC (0x30D)
2108	#define SPR_POWER_USDAR (0X30D)
2109	#define SPR_PERFE (0x30E)
2110	#define SPR_MPC_MD_RPN (0x30E)
2111	#define SPR_POWER_UMMCR1 (0X30E)
2112	#define SPR_PERFF (0x30F)
2113	#define SPR_MPC_MD_TW (0x30F)
2114	#define SPR_UPERF0 (0x310)
2115	#define SPR_POWER_SIER (0x310)
2116	#define SPR_UPERF1 (0x311)
2117	#define SPR_POWER_MMCR2 (0x311)
2118	#define SPR_UPERF2 (0x312)
2119	#define SPR_POWER_MMCRA (0X312)
2120	#define SPR_UPERF3 (0x313)
2121	#define SPR_POWER_PMC1 (0X313)
2122	#define SPR_UPERF4 (0x314)
2123	#define SPR_POWER_PMC2 (0X314)
2124	#define SPR_UPERF5 (0x315)
2125	#define SPR_POWER_PMC3 (0X315)
2126	#define SPR_UPERF6 (0x316)
2127	#define SPR_POWER_PMC4 (0X316)
2128	#define SPR_UPERF7 (0x317)
2129	#define SPR_POWER_PMC5 (0X317)
2130	#define SPR_UPERF8 (0x318)
2131	#define SPR_POWER_PMC6 (0X318)
2132	#define SPR_UPERF9 (0x319)
2133	#define SPR_970_PMC7 (0X319)
2134	#define SPR_UPERFA (0x31A)
2135	#define SPR_970_PMC8 (0X31A)
2136	#define SPR_UPERFB (0x31B)
2137	#define SPR_POWER_MMCR0 (0X31B)
2138	#define SPR_UPERFC (0x31C)
2139	#define SPR_POWER_SIAR (0X31C)
2140	#define SPR_UPERFD (0x31D)
2141	#define SPR_POWER_SDAR (0X31D)
2142	#define SPR_UPERFE (0x31E)
2143	#define SPR_POWER_MMCR1 (0X31E)
2144	#define SPR_UPERFF (0x31F)
2145	#define SPR_RCPU_MI_RA0 (0x320)
2146	#define SPR_MPC_MI_DBCAM (0x320)
2147	#define SPR_BESCRS (0x320)
2148	#define SPR_RCPU_MI_RA1 (0x321)
2149	#define SPR_MPC_MI_DBRAM0 (0x321)
2150	#define SPR_BESCRSU (0x321)
2151	#define SPR_RCPU_MI_RA2 (0x322)
2152	#define SPR_MPC_MI_DBRAM1 (0x322)
2153	#define SPR_BESCRR (0x322)
2154	#define SPR_RCPU_MI_RA3 (0x323)
2155	#define SPR_BESCRRU (0x323)
2156	#define SPR_EBBHR (0x324)
2157	#define SPR_EBBRR (0x325)
2158	#define SPR_BESCR (0x326)
2159	#define SPR_RCPU_L2U_RA0 (0x328)
2160	#define SPR_MPC_MD_DBCAM (0x328)
2161	#define SPR_RCPU_L2U_RA1 (0x329)
2162	#define SPR_MPC_MD_DBRAM0 (0x329)
2163	#define SPR_RCPU_L2U_RA2 (0x32A)
2164	#define SPR_MPC_MD_DBRAM1 (0x32A)
2165	#define SPR_RCPU_L2U_RA3 (0x32B)
2166	#define SPR_UDEXCR (0x32C)
2167	#define SPR_TAR (0x32F)
2168	#define SPR_ASDR (0x330)
2169	#define SPR_DEXCR (0x33C)
2170	#define SPR_IC (0x350)
2171	#define SPR_VTB (0x351)
2172	#define SPR_LDBAR (0x352)
2173	#define SPR_MMCRC (0x353)
2174	#define SPR_PMSR (0x355)
2175	#define SPR_PSSCR (0x357)
2176	#define SPR_440_INV0 (0x370)
2177	#define SPR_440_INV1 (0x371)
2178	#define SPR_TRIG1 (0x371)
2179	#define SPR_440_INV2 (0x372)
2180	#define SPR_TRIG2 (0x372)
2181	#define SPR_440_INV3 (0x373)
2182	#define SPR_PMCR (0x374)
2183	#define SPR_440_ITV0 (0x374)
2184	#define SPR_440_ITV1 (0x375)
2185	#define SPR_RWMR (0x375)
2186	#define SPR_440_ITV2 (0x376)
2187	#define SPR_440_ITV3 (0x377)
2188	#define SPR_440_CCR1 (0x378)
2189	#define SPR_TACR (0x378)
2190	#define SPR_TCSCR (0x379)
2191	#define SPR_CSIGR (0x37a)
2192	#define SPR_DCRIPR (0x37B)
2193	#define SPR_POWER_SPMC1 (0x37C)
2194	#define SPR_POWER_SPMC2 (0x37D)
2195	#define SPR_POWER_MMCRS (0x37E)
2196	#define SPR_WORT (0x37F)
2197	#define SPR_PPR (0x380)
2198	#define SPR_PPR32 (0x382)
2199	#define SPR_750_GQR0 (0x390)
2200	#define SPR_440_DNV0 (0x390)
2201	#define SPR_750_GQR1 (0x391)
2202	#define SPR_440_DNV1 (0x391)
2203	#define SPR_750_GQR2 (0x392)
2204	#define SPR_440_DNV2 (0x392)
2205	#define SPR_750_GQR3 (0x393)
2206	#define SPR_440_DNV3 (0x393)
2207	#define SPR_750_GQR4 (0x394)
2208	#define SPR_440_DTV0 (0x394)
2209	#define SPR_750_GQR5 (0x395)
2210	#define SPR_440_DTV1 (0x395)
2211	#define SPR_750_GQR6 (0x396)
2212	#define SPR_440_DTV2 (0x396)
2213	#define SPR_750_GQR7 (0x397)
2214	#define SPR_440_DTV3 (0x397)
2215	#define SPR_750_THRM4 (0x398)
2216	#define SPR_750CL_HID2 (0x398)
2217	#define SPR_440_DVLIM (0x398)
2218	#define SPR_750_WPAR (0x399)
2219	#define SPR_440_IVLIM (0x399)
2220	#define SPR_TSCR (0x399)
2221	#define SPR_750_DMAU (0x39A)
2222	#define SPR_POWER_TTR (0x39A)
2223	#define SPR_750_DMAL (0x39B)
2224	#define SPR_440_RSTCFG (0x39B)
2225	#define SPR_BOOKE_DCDBTRL (0x39C)
2226	#define SPR_BOOKE_DCDBTRH (0x39D)
2227	#define SPR_BOOKE_ICDBTRL (0x39E)
2228	#define SPR_BOOKE_ICDBTRH (0x39F)
2229	#define SPR_74XX_UMMCR2 (0x3A0)
2230	#define SPR_7XX_UPMC5 (0x3A1)
2231	#define SPR_7XX_UPMC6 (0x3A2)
2232	#define SPR_UBAMR (0x3A7)
2233	#define SPR_7XX_UMMCR0 (0x3A8)
2234	#define SPR_7XX_UPMC1 (0x3A9)
2235	#define SPR_7XX_UPMC2 (0x3AA)
2236	#define SPR_7XX_USIAR (0x3AB)
2237	#define SPR_7XX_UMMCR1 (0x3AC)
2238	#define SPR_7XX_UPMC3 (0x3AD)
2239	#define SPR_7XX_UPMC4 (0x3AE)
2240	#define SPR_USDA (0x3AF)
2241	#define SPR_40x_ZPR (0x3B0)
2242	#define SPR_BOOKE_MAS7 (0x3B0)
2243	#define SPR_74XX_MMCR2 (0x3B0)
2244	#define SPR_7XX_PMC5 (0x3B1)
2245	#define SPR_40x_PID (0x3B1)
2246	#define SPR_7XX_PMC6 (0x3B2)
2247	#define SPR_440_MMUCR (0x3B2)
2248	#define SPR_4xx_CCR0 (0x3B3)
2249	#define SPR_BOOKE_EPLC (0x3B3)
2250	#define SPR_405_IAC3 (0x3B4)
2251	#define SPR_BOOKE_EPSC (0x3B4)
2252	#define SPR_405_IAC4 (0x3B5)
2253	#define SPR_405_DVC1 (0x3B6)
2254	#define SPR_405_DVC2 (0x3B7)
2255	#define SPR_BAMR (0x3B7)
2256	#define SPR_7XX_MMCR0 (0x3B8)
2257	#define SPR_7XX_PMC1 (0x3B9)
2258	#define SPR_40x_SGR (0x3B9)
2259	#define SPR_7XX_PMC2 (0x3BA)
2260	#define SPR_40x_DCWR (0x3BA)
2261	#define SPR_7XX_SIAR (0x3BB)
2262	#define SPR_405_SLER (0x3BB)
2263	#define SPR_7XX_MMCR1 (0x3BC)
2264	#define SPR_405_SU0R (0x3BC)
2265	#define SPR_401_SKR (0x3BC)
2266	#define SPR_7XX_PMC3 (0x3BD)
2267	#define SPR_405_DBCR1 (0x3BD)
2268	#define SPR_7XX_PMC4 (0x3BE)
2269	#define SPR_SDA (0x3BF)
2270	#define SPR_403_VTBL (0x3CC)
2271	#define SPR_403_VTBU (0x3CD)
2272	#define SPR_DMISS (0x3D0)
2273	#define SPR_DCMP (0x3D1)
2274	#define SPR_HASH1 (0x3D2)
2275	#define SPR_HASH2 (0x3D3)
2276	#define SPR_BOOKE_ICDBDR (0x3D3)
2277	#define SPR_TLBMISS (0x3D4)
2278	#define SPR_IMISS (0x3D4)
2279	#define SPR_40x_ESR (0x3D4)
2280	#define SPR_PTEHI (0x3D5)
2281	#define SPR_ICMP (0x3D5)
2282	#define SPR_40x_DEAR (0x3D5)
2283	#define SPR_PTELO (0x3D6)
2284	#define SPR_RPA (0x3D6)
2285	#define SPR_40x_EVPR (0x3D6)
2286	#define SPR_L3PM (0x3D7)
2287	#define SPR_403_CDBCR (0x3D7)
2288	#define SPR_L3ITCR0 (0x3D8)
2289	#define SPR_TCR (0x3D8)
2290	#define SPR_40x_TSR (0x3D8)
2291	#define SPR_IBR (0x3DA)
2292	#define SPR_40x_TCR (0x3DA)
2293	#define SPR_ESASRR (0x3DB)
2294	#define SPR_40x_PIT (0x3DB)
2295	#define SPR_403_TBL (0x3DC)
2296	#define SPR_403_TBU (0x3DD)
2297	#define SPR_SEBR (0x3DE)
2298	#define SPR_40x_SRR2 (0x3DE)
2299	#define SPR_SER (0x3DF)
2300	#define SPR_40x_SRR3 (0x3DF)
2301	#define SPR_L3OHCR (0x3E8)
2302	#define SPR_L3ITCR1 (0x3E9)
2303	#define SPR_L3ITCR2 (0x3EA)
2304	#define SPR_L3ITCR3 (0x3EB)
2305	#define SPR_HID0 (0x3F0)
2306	#define SPR_40x_DBSR (0x3F0)
2307	#define SPR_HID1 (0x3F1)
2308	#define SPR_IABR (0x3F2)
2309	#define SPR_40x_DBCR0 (0x3F2)
2310	#define SPR_Exxx_L1CSR0 (0x3F2)
2311	#define SPR_ICTRL (0x3F3)
2312	#define SPR_HID2 (0x3F3)
2313	#define SPR_750CL_HID4 (0x3F3)
2314	#define SPR_Exxx_L1CSR1 (0x3F3)
2315	#define SPR_440_DBDR (0x3F3)
2316	#define SPR_LDSTDB (0x3F4)
2317	#define SPR_750_TDCL (0x3F4)
2318	#define SPR_40x_IAC1 (0x3F4)
2319	#define SPR_MMUCSR0 (0x3F4)
2320	#define SPR_970_HID4 (0x3F4)
2321	#define SPR_DABR (0x3F5)
2322	#define DABR_MASK (~(target_ulong)0x7)
2323	#define SPR_Exxx_BUCSR (0x3F5)
2324	#define SPR_40x_IAC2 (0x3F5)
2325	#define SPR_40x_DAC1 (0x3F6)
2326	#define SPR_MSSCR0 (0x3F6)
2327	#define SPR_970_HID5 (0x3F6)
2328	#define SPR_MSSSR0 (0x3F7)
2329	#define SPR_MSSCR1 (0x3F7)
2330	#define SPR_DABRX (0x3F7)
2331	#define SPR_40x_DAC2 (0x3F7)
2332	#define SPR_MMUCFG (0x3F7)
2333	#define SPR_LDSTCR (0x3F8)
2334	#define SPR_L2PMCR (0x3F8)
2335	#define SPR_750FX_HID2 (0x3F8)
2336	#define SPR_Exxx_L1FINV0 (0x3F8)
2337	#define SPR_L2CR (0x3F9)
2338	#define SPR_Exxx_L2CSR0 (0x3F9)
2339	#define SPR_L3CR (0x3FA)
2340	#define SPR_750_TDCH (0x3FA)
2341	#define SPR_IABR2 (0x3FA)
2342	#define SPR_40x_DCCR (0x3FA)
2343	#define SPR_ICTC (0x3FB)
2344	#define SPR_40x_ICCR (0x3FB)
2345	#define SPR_THRM1 (0x3FC)
2346	#define SPR_403_PBL1 (0x3FC)
2347	#define SPR_SP (0x3FD)
2348	#define SPR_THRM2 (0x3FD)
2349	#define SPR_403_PBU1 (0x3FD)
2350	#define SPR_604_HID13 (0x3FD)
2351	#define SPR_LT (0x3FE)
2352	#define SPR_THRM3 (0x3FE)
2353	#define SPR_RCPU_FPECR (0x3FE)
2354	#define SPR_403_PBL2 (0x3FE)
2355	#define SPR_PIR (0x3FF)
2356	#define SPR_403_PBU2 (0x3FF)
2357	#define SPR_604_HID15 (0x3FF)
2358	#define SPR_E500_SVR (0x3FF)
2359
2360	/* Disable MAS Interrupt Updates for Hypervisor */
2361	#define EPCR_DMIUH (1 << 22)
2362	/* Disable Guest TLB Management Instructions */
2363	#define EPCR_DGTMI (1 << 23)
2364	/* Guest Interrupt Computation Mode */
2365	#define EPCR_GICM (1 << 24)
2366	/* Interrupt Computation Mode */
2367	#define EPCR_ICM (1 << 25)
2368	/* Disable Embedded Hypervisor Debug */
2369	#define EPCR_DUVD (1 << 26)
2370	/* Instruction Storage Interrupt Directed to Guest State */
2371	#define EPCR_ISIGS (1 << 27)
2372	/* Data Storage Interrupt Directed to Guest State */
2373	#define EPCR_DSIGS (1 << 28)
2374	/* Instruction TLB Error Interrupt Directed to Guest State */
2375	#define EPCR_ITLBGS (1 << 29)
2376	/* Data TLB Error Interrupt Directed to Guest State */
2377	#define EPCR_DTLBGS (1 << 30)
2378	/* External Input Interrupt Directed to Guest State */
2379	#define EPCR_EXTGS (1 << 31)
2380
2381	#define L1CSR0_CPE 0x00010000 /* Data Cache Parity Enable */
2382	#define L1CSR0_CUL 0x00000400 /* (D-)Cache Unable to Lock */
2383	#define L1CSR0_DCLFR 0x00000100 /* D-Cache Lock Flash Reset */
2384	#define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */
2385	#define L1CSR0_DCE 0x00000001 /* Data Cache Enable */
2386
2387	#define L1CSR1_CPE 0x00010000 /* Instruction Cache Parity Enable */
2388	#define L1CSR1_ICUL 0x00000400 /* I-Cache Unable to Lock */
2389	#define L1CSR1_ICLFR 0x00000100 /* I-Cache Lock Flash Reset */
2390	#define L1CSR1_ICFI 0x00000002 /* Instruction Cache Flash Invalidate */
2391	#define L1CSR1_ICE 0x00000001 /* Instruction Cache Enable */
2392
2393	/* E500 L2CSR0 */
2394	#define E500_L2CSR0_L2FI (1 << 21) /* L2 cache flash invalidate */
2395	#define E500_L2CSR0_L2FL (1 << 11) /* L2 cache flush */
2396	#define E500_L2CSR0_L2LFC (1 << 10) /* L2 cache lock flash clear */
2397
2398	/* HID0 bits */
2399	#define HID0_DEEPNAP (1 << 24) /* pre-2.06 */
2400	#define HID0_DOZE (1 << 23) /* pre-2.06 */
2401	#define HID0_NAP (1 << 22) /* pre-2.06 */
2402	#define HID0_HILE PPC_BIT(19) /* POWER8 */
2403	#define HID0_POWER9_HILE PPC_BIT(4)
2404	#define HID0_ENABLE_ATTN PPC_BIT(31) /* POWER8 */
2405	#define HID0_POWER9_ENABLE_ATTN PPC_BIT(3)
2406
2407	/*****************************************************************************/
2408	/* PowerPC Instructions types definitions */
2409	enum {
2410	PPC_NONE = 0x0000000000000000ULL,
2411	/* PowerPC base instructions set */
2412	PPC_INSNS_BASE = 0x0000000000000001ULL,
2413	/* integer operations instructions */
2414	#define PPC_INTEGER PPC_INSNS_BASE
2415	/* flow control instructions */
2416	#define PPC_FLOW PPC_INSNS_BASE
2417	/* virtual memory instructions */
2418	#define PPC_MEM PPC_INSNS_BASE
2419	/* ld/st with reservation instructions */
2420	#define PPC_RES PPC_INSNS_BASE
2421	/* spr/msr access instructions */
2422	#define PPC_MISC PPC_INSNS_BASE
2423	/* 64 bits PowerPC instruction set */
2424	PPC_64B = 0x0000000000000020ULL,
2425	/* New 64 bits extensions (PowerPC 2.0x) */
2426	PPC_64BX = 0x0000000000000040ULL,
2427	/* 64 bits hypervisor extensions */
2428	PPC_64H = 0x0000000000000080ULL,
2429	/* New wait instruction (PowerPC 2.0x) */
2430	PPC_WAIT = 0x0000000000000100ULL,
2431	/* Time base mftb instruction */
2432	PPC_MFTB = 0x0000000000000200ULL,
2433
2434	/* Fixed-point unit extensions */
2435	/* isel instruction */
2436	PPC_ISEL = 0x0000000000000800ULL,
2437	/* popcntb instruction */
2438	PPC_POPCNTB = 0x0000000000001000ULL,
2439	/* string load / store */
2440	PPC_STRING = 0x0000000000002000ULL,
2441	/* real mode cache inhibited load / store */
2442	PPC_CILDST = 0x0000000000004000ULL,
2443
2444	/* Floating-point unit extensions */
2445	/* Optional floating point instructions */
2446	PPC_FLOAT = 0x0000000000010000ULL,
2447	/* New floating-point extensions (PowerPC 2.0x) */
2448	PPC_FLOAT_EXT = 0x0000000000020000ULL,
2449	PPC_FLOAT_FSQRT = 0x0000000000040000ULL,
2450	PPC_FLOAT_FRES = 0x0000000000080000ULL,
2451	PPC_FLOAT_FRSQRTE = 0x0000000000100000ULL,
2452	PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
2453	PPC_FLOAT_FSEL = 0x0000000000400000ULL,
2454	PPC_FLOAT_STFIWX = 0x0000000000800000ULL,
2455
2456	/* Vector/SIMD extensions */
2457	/* Altivec support */
2458	PPC_ALTIVEC = 0x0000000001000000ULL,
2459	/* PowerPC 2.03 SPE extension */
2460	PPC_SPE = 0x0000000002000000ULL,
2461	/* PowerPC 2.03 SPE single-precision floating-point extension */
2462	PPC_SPE_SINGLE = 0x0000000004000000ULL,
2463	/* PowerPC 2.03 SPE double-precision floating-point extension */
2464	PPC_SPE_DOUBLE = 0x0000000008000000ULL,
2465
2466	/* Optional memory control instructions */
2467	PPC_MEM_TLBIA = 0x0000000010000000ULL,
2468	PPC_MEM_TLBIE = 0x0000000020000000ULL,
2469	PPC_MEM_TLBSYNC = 0x0000000040000000ULL,
2470	/* sync instruction */
2471	PPC_MEM_SYNC = 0x0000000080000000ULL,
2472	/* eieio instruction */
2473	PPC_MEM_EIEIO = 0x0000000100000000ULL,
2474
2475	/* Cache control instructions */
2476	PPC_CACHE = 0x0000000200000000ULL,
2477	/* icbi instruction */
2478	PPC_CACHE_ICBI = 0x0000000400000000ULL,
2479	/* dcbz instruction */
2480	PPC_CACHE_DCBZ = 0x0000000800000000ULL,
2481	/* dcba instruction */
2482	PPC_CACHE_DCBA = 0x0000002000000000ULL,
2483	/* Freescale cache locking instructions */
2484	PPC_CACHE_LOCK = 0x0000004000000000ULL,
2485
2486	/* MMU related extensions */
2487	/* external control instructions */
2488	PPC_EXTERN = 0x0000010000000000ULL,
2489	/* segment register access instructions */
2490	PPC_SEGMENT = 0x0000020000000000ULL,
2491	/* PowerPC 6xx TLB management instructions */
2492	PPC_6xx_TLB = 0x0000040000000000ULL,
2493	/* PowerPC 40x TLB management instructions */
2494	PPC_40x_TLB = 0x0000100000000000ULL,
2495	/* segment register access instructions for PowerPC 64 "bridge" */
2496	PPC_SEGMENT_64B = 0x0000200000000000ULL,
2497	/* SLB management */
2498	PPC_SLBI = 0x0000400000000000ULL,
2499
2500	/* Embedded PowerPC dedicated instructions */
2501	PPC_WRTEE = 0x0001000000000000ULL,
2502	/* PowerPC 40x exception model */
2503	PPC_40x_EXCP = 0x0002000000000000ULL,
2504	/* PowerPC 405 Mac instructions */
2505	PPC_405_MAC = 0x0004000000000000ULL,
2506	/* PowerPC 440 specific instructions */
2507	PPC_440_SPEC = 0x0008000000000000ULL,
2508	/* BookE (embedded) PowerPC specification */
2509	PPC_BOOKE = 0x0010000000000000ULL,
2510	/* mfapidi instruction */
2511	PPC_MFAPIDI = 0x0020000000000000ULL,
2512	/* tlbiva instruction */
2513	PPC_TLBIVA = 0x0040000000000000ULL,
2514	/* tlbivax instruction */
2515	PPC_TLBIVAX = 0x0080000000000000ULL,
2516	/* PowerPC 4xx dedicated instructions */
2517	PPC_4xx_COMMON = 0x0100000000000000ULL,
2518	/* PowerPC 40x ibct instructions */
2519	PPC_40x_ICBT = 0x0200000000000000ULL,
2520	/* rfmci is not implemented in all BookE PowerPC */
2521	PPC_RFMCI = 0x0400000000000000ULL,
2522	/* rfdi instruction */
2523	PPC_RFDI = 0x0800000000000000ULL,
2524	/* DCR accesses */
2525	PPC_DCR = 0x1000000000000000ULL,
2526	/* DCR extended accesse */
2527	PPC_DCRX = 0x2000000000000000ULL,
2528	/* popcntw and popcntd instructions */
2529	PPC_POPCNTWD = 0x8000000000000000ULL,
2530
2531	#define PPC_TCG_INSNS (PPC_INSNS_BASE \| PPC_64B \
2532	\| PPC_64BX \| PPC_64H \| PPC_WAIT \| PPC_MFTB \
2533	\| PPC_ISEL \| PPC_POPCNTB \
2534	\| PPC_STRING \| PPC_FLOAT \| PPC_FLOAT_EXT \
2535	\| PPC_FLOAT_FSQRT \| PPC_FLOAT_FRES \
2536	\| PPC_FLOAT_FRSQRTE \| PPC_FLOAT_FRSQRTES \
2537	\| PPC_FLOAT_FSEL \| PPC_FLOAT_STFIWX \
2538	\| PPC_ALTIVEC \| PPC_SPE \| PPC_SPE_SINGLE \
2539	\| PPC_SPE_DOUBLE \| PPC_MEM_TLBIA \
2540	\| PPC_MEM_TLBIE \| PPC_MEM_TLBSYNC \
2541	\| PPC_MEM_SYNC \| PPC_MEM_EIEIO \
2542	\| PPC_CACHE \| PPC_CACHE_ICBI \
2543	\| PPC_CACHE_DCBZ \
2544	\| PPC_CACHE_DCBA \| PPC_CACHE_LOCK \
2545	\| PPC_EXTERN \| PPC_SEGMENT \| PPC_6xx_TLB \
2546	\| PPC_40x_TLB \| PPC_SEGMENT_64B \
2547	\| PPC_SLBI \| PPC_WRTEE \| PPC_40x_EXCP \
2548	\| PPC_405_MAC \| PPC_440_SPEC \| PPC_BOOKE \
2549	\| PPC_MFAPIDI \| PPC_TLBIVA \| PPC_TLBIVAX \
2550	\| PPC_4xx_COMMON \| PPC_40x_ICBT \| PPC_RFMCI \
2551	\| PPC_RFDI \| PPC_DCR \| PPC_DCRX \| PPC_POPCNTWD \
2552	\| PPC_CILDST)
2553
2554	/* extended type values */
2555
2556	/* BookE 2.06 PowerPC specification */
2557	PPC2_BOOKE206 = 0x0000000000000001ULL,
2558	/* VSX (extensions to Altivec / VMX) */
2559	PPC2_VSX = 0x0000000000000002ULL,
2560	/* Decimal Floating Point (DFP) */
2561	PPC2_DFP = 0x0000000000000004ULL,
2562	/* Embedded.Processor Control */
2563	PPC2_PRCNTL = 0x0000000000000008ULL,
2564	/* Byte-reversed, indexed, double-word load and store */
2565	PPC2_DBRX = 0x0000000000000010ULL,
2566	/* Book I 2.05 PowerPC specification */
2567	PPC2_ISA205 = 0x0000000000000020ULL,
2568	/* POWER ISA 2.07 */
2569	PPC2_ISA207 = 0x0000000000000040ULL,
2570	/* ISA 2.06B bpermd */
2571	PPC2_PERM_ISA206 = 0x0000000000000080ULL,
2572	/* ISA 2.06B divide extended variants */
2573	PPC2_DIVE_ISA206 = 0x0000000000000100ULL,
2574	/* ISA 2.06B larx/stcx. instructions */
2575	PPC2_ATOMIC_ISA206 = 0x0000000000000200ULL,
2576	/* ISA 2.06B floating point integer conversion */
2577	PPC2_FP_CVT_ISA206 = 0x0000000000000400ULL,
2578	/* ISA 2.06B floating point test instructions */
2579	PPC2_FP_TST_ISA206 = 0x0000000000000800ULL,
2580	/* Double precision floating point conversion for signed integer 64 */
2581	PPC2_FP_CVT_S64 = 0x0000000000001000ULL,
2582	/* Transactional Memory (ISA 2.07, Book II) */
2583	PPC2_TM = 0x0000000000002000ULL,
2584	/* Server PM instructgions (ISA 2.06, Book III) */
2585	PPC2_PM_ISA206 = 0x0000000000004000ULL,
2586	/* POWER ISA 3.0 */
2587	PPC2_ISA300 = 0x0000000000008000ULL,
2588	/* POWER ISA 3.1 */
2589	PPC2_ISA310 = 0x0000000000010000ULL,
2590	/* lwsync instruction */
2591	PPC2_MEM_LWSYNC = 0x0000000000020000ULL,
2592	/* ISA 2.06 BCD assist instructions */
2593	PPC2_BCDA_ISA206 = 0x0000000000040000ULL,
2594	/* PPE42 instructions */
2595	PPC2_PPE42 = 0x0000000000080000ULL,
2596	/* PPE42X instructions */
2597	PPC2_PPE42X = 0x0000000000100000ULL,
2598	/* PPE42XM instructions */
2599	PPC2_PPE42XM = 0x0000000000200000ULL,
2600
2601	#define PPC_TCG_INSNS2 (PPC2_BOOKE206 \| PPC2_VSX \| PPC2_PRCNTL \| PPC2_DBRX \| \
2602	PPC2_ISA205 \| PPC2_ISA207 \| PPC2_PERM_ISA206 \| \
2603	PPC2_DIVE_ISA206 \| PPC2_ATOMIC_ISA206 \| \
2604	PPC2_FP_CVT_ISA206 \| PPC2_FP_TST_ISA206 \| PPC2_DFP \| \
2605	PPC2_FP_CVT_S64 \| PPC2_TM \| PPC2_PM_ISA206 \| \
2606	PPC2_ISA300 \| PPC2_ISA310 \| PPC2_MEM_LWSYNC \| \
2607	PPC2_BCDA_ISA206 \| PPC2_PPE42 \| PPC2_PPE42X \| \
2608	PPC2_PPE42XM)
2609	};
2610
2611	/*****************************************************************************/
2612	/*
2613	* Memory access type :
2614	* may be needed for precise access rights control and precise exceptions.
2615	*/
2616	enum {
2617	/* Type of instruction that generated the access */
2618	ACCESS_CODE = 0x10, /* Code fetch access */
2619	ACCESS_INT = 0x20, /* Integer load/store access */
2620	ACCESS_FLOAT = 0x30, /* floating point load/store access */
2621	ACCESS_RES = 0x40, /* load/store with reservation */
2622	ACCESS_EXT = 0x50, /* external access */
2623	ACCESS_CACHE = 0x60, /* Cache manipulation */
2624	};
2625
2626	/*
2627	* Hardware interrupt sources:
2628	* all those exception can be raised simulteaneously
2629	*/
2630	/* Input pins definitions */
2631	enum {
2632	/* 6xx bus input pins */
2633	PPC6xx_INPUT_HRESET = 0,
2634	PPC6xx_INPUT_SRESET = 1,
2635	PPC6xx_INPUT_CKSTP_IN = 2,
2636	PPC6xx_INPUT_MCP = 3,
2637	PPC6xx_INPUT_SMI = 4,
2638	PPC6xx_INPUT_INT = 5,
2639	PPC6xx_INPUT_TBEN = 6,
2640	PPC6xx_INPUT_WAKEUP = 7,
2641	PPC6xx_INPUT_NB,
2642	};
2643
2644	enum {
2645	/* Embedded PowerPC input pins */
2646	PPCBookE_INPUT_HRESET = 0,
2647	PPCBookE_INPUT_SRESET = 1,
2648	PPCBookE_INPUT_CKSTP_IN = 2,
2649	PPCBookE_INPUT_MCP = 3,
2650	PPCBookE_INPUT_SMI = 4,
2651	PPCBookE_INPUT_INT = 5,
2652	PPCBookE_INPUT_CINT = 6,
2653	PPCBookE_INPUT_NB,
2654	};
2655
2656	enum {
2657	/* PowerPC E500 input pins */
2658	PPCE500_INPUT_RESET_CORE = 0,
2659	PPCE500_INPUT_MCK = 1,
2660	PPCE500_INPUT_CINT = 3,
2661	PPCE500_INPUT_INT = 4,
2662	PPCE500_INPUT_DEBUG = 6,
2663	PPCE500_INPUT_NB,
2664	};
2665
2666	enum {
2667	/* PowerPC 40x input pins */
2668	PPC40x_INPUT_RESET_CORE = 0,
2669	PPC40x_INPUT_RESET_CHIP = 1,
2670	PPC40x_INPUT_RESET_SYS = 2,
2671	PPC40x_INPUT_CINT = 3,
2672	PPC40x_INPUT_INT = 4,
2673	PPC40x_INPUT_HALT = 5,
2674	PPC40x_INPUT_DEBUG = 6,
2675	PPC40x_INPUT_NB,
2676	};
2677
2678	enum {
2679	/* RCPU input pins */
2680	PPCRCPU_INPUT_PORESET = 0,
2681	PPCRCPU_INPUT_HRESET = 1,
2682	PPCRCPU_INPUT_SRESET = 2,
2683	PPCRCPU_INPUT_IRQ0 = 3,
2684	PPCRCPU_INPUT_IRQ1 = 4,
2685	PPCRCPU_INPUT_IRQ2 = 5,
2686	PPCRCPU_INPUT_IRQ3 = 6,
2687	PPCRCPU_INPUT_IRQ4 = 7,
2688	PPCRCPU_INPUT_IRQ5 = 8,
2689	PPCRCPU_INPUT_IRQ6 = 9,
2690	PPCRCPU_INPUT_IRQ7 = 10,
2691	PPCRCPU_INPUT_NB,
2692	};
2693
2694	#if defined(TARGET_PPC64)
2695	enum {
2696	/* PowerPC 970 input pins */
2697	PPC970_INPUT_HRESET = 0,
2698	PPC970_INPUT_SRESET = 1,
2699	PPC970_INPUT_CKSTP = 2,
2700	PPC970_INPUT_TBEN = 3,
2701	PPC970_INPUT_MCP = 4,
2702	PPC970_INPUT_INT = 5,
2703	PPC970_INPUT_THINT = 6,
2704	PPC970_INPUT_NB,
2705	};
2706
2707	enum {
2708	/* POWER7 input pins */
2709	POWER7_INPUT_INT = 0,
2710	/*
2711	* POWER7 probably has other inputs, but we don't care about them
2712	* for any existing machine. We can wire these up when we need
2713	* them
2714	*/
2715	POWER7_INPUT_NB,
2716	};
2717
2718	enum {
2719	/* POWER9 input pins */
2720	POWER9_INPUT_INT = 0,
2721	POWER9_INPUT_HINT = 1,
2722	POWER9_INPUT_NB,
2723	};
2724	#endif
2725
2726	/* Hardware exceptions definitions */
2727	enum {
2728	/* External hardware exception sources */
2729	PPC_INTERRUPT_RESET = 0x00001, /* Reset exception */
2730	PPC_INTERRUPT_WAKEUP = 0x00002, /* Wakeup exception */
2731	PPC_INTERRUPT_MCK = 0x00004, /* Machine check exception */
2732	PPC_INTERRUPT_EXT = 0x00008, /* External interrupt */
2733	PPC_INTERRUPT_SMI = 0x00010, /* System management interrupt */
2734	PPC_INTERRUPT_CEXT = 0x00020, /* Critical external interrupt */
2735	PPC_INTERRUPT_DEBUG = 0x00040, /* External debug exception */
2736	PPC_INTERRUPT_THERM = 0x00080, /* Thermal exception */
2737	/* Internal hardware exception sources */
2738	PPC_INTERRUPT_DECR = 0x00100, /* Decrementer exception */
2739	PPC_INTERRUPT_HDECR = 0x00200, /* Hypervisor decrementer exception */
2740	PPC_INTERRUPT_PIT = 0x00400, /* Programmable interval timer int. */
2741	PPC_INTERRUPT_FIT = 0x00800, /* Fixed interval timer interrupt */
2742	PPC_INTERRUPT_WDT = 0x01000, /* Watchdog timer interrupt */
2743	PPC_INTERRUPT_CDOORBELL = 0x02000, /* Critical doorbell interrupt */
2744	PPC_INTERRUPT_DOORBELL = 0x04000, /* Doorbell interrupt */
2745	PPC_INTERRUPT_PERFM = 0x08000, /* Performance monitor interrupt */
2746	PPC_INTERRUPT_HMI = 0x10000, /* Hypervisor Maintenance interrupt */
2747	PPC_INTERRUPT_HDOORBELL = 0x20000, /* Hypervisor Doorbell interrupt */
2748	PPC_INTERRUPT_HVIRT = 0x40000, /* Hypervisor virtualization interrupt */
2749	PPC_INTERRUPT_EBB = 0x80000, /* Event-based Branch exception */
2750	};
2751
2752	/* Processor Compatibility mask (PCR) */
2753	enum {
2754	PCR_COMPAT_2_05 = PPC_BIT(62),
2755	PCR_COMPAT_2_06 = PPC_BIT(61),
2756	PCR_COMPAT_2_07 = PPC_BIT(60),
2757	PCR_COMPAT_3_00 = PPC_BIT(59),
2758	PCR_COMPAT_3_10 = PPC_BIT(58),
2759	PCR_VEC_DIS = PPC_BIT(0), /* Vec. disable (bit NA since POWER8) */
2760	PCR_VSX_DIS = PPC_BIT(1), /* VSX disable (bit NA since POWER8) */
2761	PCR_TM_DIS = PPC_BIT(2), /* Trans. memory disable (POWER8) */
2762	};
2763
2764	/* HMER/HMEER */
2765	enum {
2766	HMER_MALFUNCTION_ALERT = PPC_BIT(0),
2767	HMER_PROC_RECV_DONE = PPC_BIT(2),
2768	HMER_PROC_RECV_ERROR_MASKED = PPC_BIT(3),
2769	HMER_TFAC_ERROR = PPC_BIT(4),
2770	HMER_TFMR_PARITY_ERROR = PPC_BIT(5),
2771	HMER_XSCOM_FAIL = PPC_BIT(8),
2772	HMER_XSCOM_DONE = PPC_BIT(9),
2773	HMER_PROC_RECV_AGAIN = PPC_BIT(11),
2774	HMER_WARN_RISE = PPC_BIT(14),
2775	HMER_WARN_FALL = PPC_BIT(15),
2776	HMER_SCOM_FIR_HMI = PPC_BIT(16),
2777	HMER_TRIG_FIR_HMI = PPC_BIT(17),
2778	HMER_HYP_RESOURCE_ERR = PPC_BIT(20),
2779	HMER_XSCOM_STATUS_MASK = PPC_BITMASK(21, 23),
2780	};
2781
2782	/* TFMR */
2783	enum {
2784	TFMR_CONTROL_MASK = PPC_BITMASK(0, 24),
2785	TFMR_MASK_HMI = PPC_BIT(10),
2786	TFMR_TB_ECLIPZ = PPC_BIT(14),
2787	TFMR_LOAD_TOD_MOD = PPC_BIT(16),
2788	TFMR_MOVE_CHIP_TOD_TO_TB = PPC_BIT(18),
2789	TFMR_CLEAR_TB_ERRORS = PPC_BIT(24),
2790	TFMR_STATUS_MASK = PPC_BITMASK(25, 63),
2791	TFMR_TBST_ENCODED = PPC_BITMASK(28, 31), /* TBST = TB State */
2792	TFMR_TBST_LAST = PPC_BITMASK(32, 35), /* Previous TBST */
2793	TFMR_TB_ENABLED = PPC_BIT(40),
2794	TFMR_TB_VALID = PPC_BIT(41),
2795	TFMR_TB_SYNC_OCCURED = PPC_BIT(42),
2796	TFMR_FIRMWARE_CONTROL_ERROR = PPC_BIT(46),
2797	};
2798
2799	/* TFMR TBST (Time Base State Machine). */
2800	enum {
2801	TBST_RESET = 0x0,
2802	TBST_SEND_TOD_MOD = 0x1,
2803	TBST_NOT_SET = 0x2,
2804	TBST_SYNC_WAIT = 0x6,
2805	TBST_GET_TOD = 0x7,
2806	TBST_TB_RUNNING = 0x8,
2807	TBST_TB_ERROR = 0x9,
2808	};
2809
2810	/*****************************************************************************/
2811
2812	#define is_isa300(ctx) (!!(ctx->insns_flags2 & PPC2_ISA300))
2813	target_ulong cpu_read_xer(const CPUPPCState *env);
2814	void cpu_write_xer(CPUPPCState *env, target_ulong xer);
2815
2816	/*
2817	* All 64-bit server processors compliant with arch 2.x, ie. 970 and newer,
2818	* have PPC_SEGMENT_64B.
2819	*/
2820	#define is_book3s_arch2x(ctx) (!!((ctx)->insns_flags & PPC_SEGMENT_64B))
2821
2822	G_NORETURN void raise_exception_err_ra(CPUPPCState *env, uint32_t exception,
2823	uint32_t error_code, uintptr_t raddr);
2824
2825	/* PERFM EBB helper*/
2826	#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
2827	void raise_ebb_perfm_exception(CPUPPCState *env);
2828	#endif
2829
2830	#if !defined(CONFIG_USER_ONLY)
2831	static inline int booke206_tlbm_id(CPUPPCState env, ppcmas_tlb_t tlbm)
2832	{
2833	uintptr_t tlbml = (uintptr_t)tlbm;
2834	uintptr_t tlbl = (uintptr_t)env->tlb.tlbm;
2835
2836	return (tlbml - tlbl) / sizeof(env->tlb.tlbm[0]);
2837	}
2838
2839	static inline int booke206_tlb_size(CPUPPCState *env, int tlbn)
2840	{
2841	uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2842	int r = tlbncfg & TLBnCFG_N_ENTRY;
2843	return r;
2844	}
2845
2846	static inline int booke206_tlb_ways(CPUPPCState *env, int tlbn)
2847	{
2848	uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2849	int r = tlbncfg >> TLBnCFG_ASSOC_SHIFT;
2850	return r;
2851	}
2852
2853	static inline int booke206_tlbm_to_tlbn(CPUPPCState env, ppcmas_tlb_t tlbm)
2854	{
2855	int id = booke206_tlbm_id(env, tlbm);
2856	int end = 0;
2857	int i;
2858
2859	for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
2860	end += booke206_tlb_size(env, i);
2861	if (id < end) {
2862	return i;
2863	}
2864	}
2865
2866	cpu_abort(env_cpu(env), "Unknown TLBe: %d\n", id);
2867	return 0;
2868	}
2869
2870	static inline int booke206_tlbm_to_way(CPUPPCState env, ppcmas_tlb_t tlb)
2871	{
2872	int tlbn = booke206_tlbm_to_tlbn(env, tlb);
2873	int tlbid = booke206_tlbm_id(env, tlb);
2874	return tlbid & (booke206_tlb_ways(env, tlbn) - 1);
2875	}
2876
2877	static inline ppcmas_tlb_t booke206_get_tlbm(CPUPPCState env, const int tlbn,
2878	target_ulong ea, int way)
2879	{
2880	int r;
2881	uint32_t ways = booke206_tlb_ways(env, tlbn);
2882	int ways_bits = ctz32(ways);
2883	int tlb_bits = ctz32(booke206_tlb_size(env, tlbn));
2884	int i;
2885
2886	way &= ways - 1;
2887	ea >>= MAS2_EPN_SHIFT;
2888	ea &= (1 << (tlb_bits - ways_bits)) - 1;
2889	r = (ea << ways_bits) \| way;
2890
2891	if (r >= booke206_tlb_size(env, tlbn)) {
2892	return NULL;
2893	}
2894
2895	/* bump up to tlbn index */
2896	for (i = 0; i < tlbn; i++) {
2897	r += booke206_tlb_size(env, i);
2898	}
2899
2900	return &env->tlb.tlbm[r];
2901	}
2902
2903	/* returns bitmap of supported page sizes for a given TLB */
2904	static inline uint32_t booke206_tlbnps(CPUPPCState *env, const int tlbn)
2905	{
2906	uint32_t ret = 0;
2907
2908	if ((env->spr[SPR_MMUCFG] & MMUCFG_MAVN) == MMUCFG_MAVN_V2) {
2909	/* MAV2 */
2910	ret = env->spr[SPR_BOOKE_TLB0PS + tlbn];
2911	} else {
2912	uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2913	uint32_t min = (tlbncfg & TLBnCFG_MINSIZE) >> TLBnCFG_MINSIZE_SHIFT;
2914	uint32_t max = (tlbncfg & TLBnCFG_MAXSIZE) >> TLBnCFG_MAXSIZE_SHIFT;
2915	int i;
2916	for (i = min; i <= max; i++) {
2917	ret \|= (1 << (i << 1));
2918	}
2919	}
2920
2921	return ret;
2922	}
2923
2924	static inline void booke206_fixed_size_tlbn(CPUPPCState *env, const int tlbn,
2925	ppcmas_tlb_t *tlb)
2926	{
2927	uint8_t i;
2928	int32_t tsize = -1;
2929
2930	for (i = 0; i < 32; i++) {
2931	if ((env->spr[SPR_BOOKE_TLB0PS + tlbn]) & (1ULL << i)) {
2932	if (tsize == -1) {
2933	tsize = i;
2934	} else {
2935	return;
2936	}
2937	}
2938	}
2939
2940	/* TLBnPS unimplemented? Odd.. */
2941	assert(tsize != -1);
2942	tlb->mas1 &= ~MAS1_TSIZE_MASK;
2943	tlb->mas1 \|= ((uint32_t)tsize) << MAS1_TSIZE_SHIFT;
2944	}
2945
2946	static inline bool ppc_is_split_tlb(PowerPCCPU *cpu)
2947	{
2948	return cpu->env.tlb_type == TLB_6XX;
2949	}
2950	#endif
2951
2952	static inline bool msr_is_64bit(CPUPPCState *env, target_ulong msr)
2953	{
2954	if (env->mmu_model == POWERPC_MMU_BOOKE206) {
2955	return msr & (1ULL << MSR_CM);
2956	}
2957
2958	return msr & (1ULL << MSR_SF);
2959	}
2960
2961	/**
2962	* Check whether register rx is in the range between start and
2963	* start + nregs (as needed by the LSWX and LSWI instructions)
2964	*/
2965	static inline bool lsw_reg_in_range(int start, int nregs, int rx)
2966	{
2967	return (start + nregs <= 32 && rx >= start && rx < start + nregs) \|\|
2968	(start + nregs > 32 && (rx >= start \|\| rx < start + nregs - 32));
2969	}
2970
2971	/* Accessors for FP, VMX and VSX registers */
2972	#if HOST_BIG_ENDIAN
2973	#define VsrB(i) u8[i]
2974	#define VsrSB(i) s8[i]
2975	#define VsrH(i) u16[i]
2976	#define VsrSH(i) s16[i]
2977	#define VsrW(i) u32[i]
2978	#define VsrSW(i) s32[i]
2979	#define VsrD(i) u64[i]
2980	#define VsrSD(i) s64[i]
2981	#define VsrHF(i) f16[i]
2982	#define VsrSF(i) f32[i]
2983	#define VsrDF(i) f64[i]
2984	#else
2985	#define VsrB(i) u8[15 - (i)]
2986	#define VsrSB(i) s8[15 - (i)]
2987	#define VsrH(i) u16[7 - (i)]
2988	#define VsrSH(i) s16[7 - (i)]
2989	#define VsrW(i) u32[3 - (i)]
2990	#define VsrSW(i) s32[3 - (i)]
2991	#define VsrD(i) u64[1 - (i)]
2992	#define VsrSD(i) s64[1 - (i)]
2993	#define VsrHF(i) f16[7 - (i)]
2994	#define VsrSF(i) f32[3 - (i)]
2995	#define VsrDF(i) f64[1 - (i)]
2996	#endif
2997
2998	static inline int vsr64_offset(int i, bool high)
2999	{
3000	return offsetof(CPUPPCState, vsr[i].VsrD(high ? 0 : 1));
3001	}
3002
3003	static inline int vsr_full_offset(int i)
3004	{
3005	return offsetof(CPUPPCState, vsr[i].u64[0]);
3006	}
3007
3008	static inline int acc_full_offset(int i)
3009	{
3010	return vsr_full_offset(i * 4);
3011	}
3012
3013	static inline int fpr_offset(int i)
3014	{
3015	return vsr64_offset(i, true);
3016	}
3017
3018	static inline uint64_t cpu_fpr_ptr(CPUPPCState env, int i)
3019	{
3020	return (uint64_t *)((uintptr_t)env + fpr_offset(i));
3021	}
3022
3023	static inline uint64_t cpu_vsrl_ptr(CPUPPCState env, int i)
3024	{
3025	return (uint64_t *)((uintptr_t)env + vsr64_offset(i, false));
3026	}
3027
3028	static inline long avr64_offset(int i, bool high)
3029	{
3030	return vsr64_offset(i + 32, high);
3031	}
3032
3033	static inline int avr_full_offset(int i)
3034	{
3035	return vsr_full_offset(i + 32);
3036	}
3037
3038	static inline ppc_avr_t cpu_avr_ptr(CPUPPCState env, int i)
3039	{
3040	return (ppc_avr_t *)((uintptr_t)env + avr_full_offset(i));
3041	}
3042
3043	static inline bool ppc_has_spr(PowerPCCPU *cpu, int spr)
3044	{
3045	/* We can test whether the SPR is defined by checking for a valid name */
3046	return cpu->env.spr_cb[spr].name != NULL;
3047	}
3048
3049	#if !defined(CONFIG_USER_ONLY)
3050	/* Sort out endianness of interrupt. Depends on the CPU, HV mode, etc. */
3051	static inline bool ppc_interrupts_little_endian(PowerPCCPU *cpu, bool hv)
3052	{
3053	PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
3054	CPUPPCState *env = &cpu->env;
3055	bool ile;
3056
3057	if (hv && env->has_hv_mode) {
3058	if (is_isa300(pcc)) {
3059	ile = !!(env->spr[SPR_HID0] & HID0_POWER9_HILE);
3060	} else {
3061	ile = !!(env->spr[SPR_HID0] & HID0_HILE);
3062	}
3063
3064	} else if (pcc->lpcr_mask & LPCR_ILE) {
3065	ile = !!(env->spr[SPR_LPCR] & LPCR_ILE);
3066	} else {
3067	ile = FIELD_EX64(env->msr, MSR, ILE);
3068	}
3069
3070	return ile;
3071	}
3072	#endif
3073
3074	void dump_mmu(CPUPPCState *env);
3075
3076	void ppc_maybe_bswap_register(CPUPPCState env, uint8_t mem_buf, int len);
3077	void ppc_store_vscr(CPUPPCState *env, uint32_t vscr);
3078	uint32_t ppc_get_vscr(CPUPPCState *env);
3079	void ppc_set_cr(CPUPPCState *env, uint64_t cr);
3080	uint64_t ppc_get_cr(const CPUPPCState *env);
3081
3082	/*****************************************************************************/
3083	/* Power management enable checks */
3084	static inline int check_pow_none(CPUPPCState *env)
3085	{
3086	return 0;
3087	}
3088
3089	static inline int check_pow_nocheck(CPUPPCState *env)
3090	{
3091	return 1;
3092	}
3093
3094	/* attn enable check */
3095	static inline int check_attn_none(CPUPPCState *env)
3096	{
3097	return 0;
3098	}
3099
3100	/*****************************************************************************/
3101	/* PowerPC implementations definitions */
3102
3103	#define POWERPC_FAMILY(_name) \
3104	static void \
3105	glue(glue(ppc_, _name), _cpu_family_class_init)(ObjectClass *, \
3106	const void *); \
3107	\
3108	static const TypeInfo \
3109	glue(glue(ppc_, _name), _cpu_family_type_info) = { \
3110	.name = stringify(_name) "-family-" TYPE_POWERPC_CPU, \
3111	.parent = TYPE_POWERPC_CPU, \
3112	.abstract = true, \
3113	.class_init = glue(glue(ppc_, _name), _cpu_family_class_init), \
3114	}; \
3115	\
3116	static void glue(glue(ppc_, _name), _cpu_family_register_types)(void) \
3117	{ \
3118	type_register_static( \
3119	&glue(glue(ppc_, _name), _cpu_family_type_info)); \
3120	} \
3121	\
3122	type_init(glue(glue(ppc_, _name), _cpu_family_register_types)) \
3123	\
3124	static void glue(glue(ppc_, _name), _cpu_family_class_init)
3125
3126
3127	#endif /* PPC_CPU_H */