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1
2 /*
3 * PowerPC CPU initialization for qemu.
4 *
5 * Copyright (c) 2003-2007 Jocelyn Mayer
6 * Copyright 2011 Freescale Semiconductor, Inc.
7 *
8 * This library is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2.1 of the License, or (at your option) any later version.
12 *
13 * This library is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
17 *
18 * You should have received a copy of the GNU Lesser General Public
19 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 */
21
22 #include "qemu/osdep.h"
23 #include "disas/dis-asm.h"
24 #include "gdbstub/helpers.h"
25 #include "system/cpus.h"
26 #include "system/hw_accel.h"
27 #include "system/tcg.h"
28 #include "cpu-models.h"
29 #include "mmu-hash32.h"
30 #include "mmu-hash64.h"
31 #include "qemu/error-report.h"
32 #include "qemu/module.h"
33 #include "qemu/qemu-print.h"
34 #include "qapi/error.h"
35 #include "qobject/qnull.h"
36 #include "qapi/visitor.h"
37 #include "hw/core/qdev-properties.h"
38 #include "hw/ppc/ppc.h"
39 #include "mmu-book3s-v3.h"
40 #include "qemu/cutils.h"
41 #include "disas/capstone.h"
42 #include "fpu/softfloat.h"
43 #include "exec/page-protection.h"
44 #include "exec/watchpoint.h"
45 #include "helper_regs.h"
46 #include "internal.h"
47 #include "spr_common.h"
48 #include "power8-pmu.h"
49 #ifndef CONFIG_USER_ONLY
50 #include "hw/core/boards.h"
51 #include "hw/intc/intc.h"
52 #include "kvm_ppc.h"
53 #endif
54
55 #include "cpu_init.h"
56
57 static const Property powerpc_cpu_properties[] = {
58 DEFINE_PROP_BOOL("rtas-stopped-state", PowerPCCPU,
59 rtas_stopped_state, true),
60 };
61
62 static inline void vscr_init(CPUPPCState *env, uint32_t val)
63 {
64 /* Altivec always uses round-to-nearest */
65 set_float_rounding_mode(float_round_nearest_even, &env->vec_status);
66 ppc_store_vscr(env, val);
67 }
68
69 static void register_745_sprs(CPUPPCState *env)
70 {
71 /* SGPRs */
72 spr_register(env, SPR_SPRG4, "SPRG4",
73 SPR_NOACCESS, SPR_NOACCESS,
74 &spr_read_generic, &spr_write_generic,
75 0x00000000);
76 spr_register(env, SPR_SPRG5, "SPRG5",
77 SPR_NOACCESS, SPR_NOACCESS,
78 &spr_read_generic, &spr_write_generic,
79 0x00000000);
80 spr_register(env, SPR_SPRG6, "SPRG6",
81 SPR_NOACCESS, SPR_NOACCESS,
82 &spr_read_generic, &spr_write_generic,
83 0x00000000);
84 spr_register(env, SPR_SPRG7, "SPRG7",
85 SPR_NOACCESS, SPR_NOACCESS,
86 &spr_read_generic, &spr_write_generic,
87 0x00000000);
88
89 /* Hardware implementation registers */
90 spr_register(env, SPR_HID0, "HID0",
91 SPR_NOACCESS, SPR_NOACCESS,
92 &spr_read_generic, &spr_write_generic,
93 0x00000000);
94
95 spr_register(env, SPR_HID1, "HID1",
96 SPR_NOACCESS, SPR_NOACCESS,
97 &spr_read_generic, &spr_write_generic,
98 0x00000000);
99
100 spr_register(env, SPR_HID2, "HID2",
101 SPR_NOACCESS, SPR_NOACCESS,
102 &spr_read_generic, &spr_write_generic,
103 0x00000000);
104 }
105
106 static void register_755_sprs(CPUPPCState *env)
107 {
108 /* L2 cache control */
109 spr_register(env, SPR_L2CR, "L2CR",
110 SPR_NOACCESS, SPR_NOACCESS,
111 &spr_read_generic, spr_access_nop,
112 0x00000000);
113
114 spr_register(env, SPR_L2PMCR, "L2PMCR",
115 SPR_NOACCESS, SPR_NOACCESS,
116 &spr_read_generic, &spr_write_generic,
117 0x00000000);
118 }
119
120 /* SPR common to all 7xx PowerPC implementations */
121 static void register_7xx_sprs(CPUPPCState *env)
122 {
123 /* Breakpoints */
124 spr_register_kvm(env, SPR_DABR, "DABR",
125 SPR_NOACCESS, SPR_NOACCESS,
126 &spr_read_generic, &spr_write_generic,
127 KVM_REG_PPC_DABR, 0x00000000);
128
129 spr_register(env, SPR_IABR, "IABR",
130 SPR_NOACCESS, SPR_NOACCESS,
131 &spr_read_generic, &spr_write_generic,
132 0x00000000);
133 /* Cache management */
134 spr_register(env, SPR_ICTC, "ICTC",
135 SPR_NOACCESS, SPR_NOACCESS,
136 &spr_read_generic, &spr_write_generic,
137 0x00000000);
138 /* Performance monitors */
139 spr_register(env, SPR_7XX_MMCR0, "MMCR0",
140 SPR_NOACCESS, SPR_NOACCESS,
141 &spr_read_generic, &spr_write_generic,
142 0x00000000);
143
144 spr_register(env, SPR_7XX_MMCR1, "MMCR1",
145 SPR_NOACCESS, SPR_NOACCESS,
146 &spr_read_generic, &spr_write_generic,
147 0x00000000);
148
149 spr_register(env, SPR_7XX_PMC1, "PMC1",
150 SPR_NOACCESS, SPR_NOACCESS,
151 &spr_read_generic, &spr_write_generic,
152 0x00000000);
153
154 spr_register(env, SPR_7XX_PMC2, "PMC2",
155 SPR_NOACCESS, SPR_NOACCESS,
156 &spr_read_generic, &spr_write_generic,
157 0x00000000);
158
159 spr_register(env, SPR_7XX_PMC3, "PMC3",
160 SPR_NOACCESS, SPR_NOACCESS,
161 &spr_read_generic, &spr_write_generic,
162 0x00000000);
163
164 spr_register(env, SPR_7XX_PMC4, "PMC4",
165 SPR_NOACCESS, SPR_NOACCESS,
166 &spr_read_generic, &spr_write_generic,
167 0x00000000);
168
169 spr_register(env, SPR_7XX_SIAR, "SIAR",
170 SPR_NOACCESS, SPR_NOACCESS,
171 &spr_read_generic, SPR_NOACCESS,
172 0x00000000);
173
174 spr_register(env, SPR_7XX_UMMCR0, "UMMCR0",
175 &spr_read_ureg, SPR_NOACCESS,
176 &spr_read_ureg, SPR_NOACCESS,
177 0x00000000);
178
179 spr_register(env, SPR_7XX_UMMCR1, "UMMCR1",
180 &spr_read_ureg, SPR_NOACCESS,
181 &spr_read_ureg, SPR_NOACCESS,
182 0x00000000);
183
184 spr_register(env, SPR_7XX_UPMC1, "UPMC1",
185 &spr_read_ureg, SPR_NOACCESS,
186 &spr_read_ureg, SPR_NOACCESS,
187 0x00000000);
188
189 spr_register(env, SPR_7XX_UPMC2, "UPMC2",
190 &spr_read_ureg, SPR_NOACCESS,
191 &spr_read_ureg, SPR_NOACCESS,
192 0x00000000);
193
194 spr_register(env, SPR_7XX_UPMC3, "UPMC3",
195 &spr_read_ureg, SPR_NOACCESS,
196 &spr_read_ureg, SPR_NOACCESS,
197 0x00000000);
198
199 spr_register(env, SPR_7XX_UPMC4, "UPMC4",
200 &spr_read_ureg, SPR_NOACCESS,
201 &spr_read_ureg, SPR_NOACCESS,
202 0x00000000);
203
204 spr_register(env, SPR_7XX_USIAR, "USIAR",
205 &spr_read_ureg, SPR_NOACCESS,
206 &spr_read_ureg, SPR_NOACCESS,
207 0x00000000);
208 /* External access control */
209 spr_register(env, SPR_EAR, "EAR",
210 SPR_NOACCESS, SPR_NOACCESS,
211 &spr_read_generic, &spr_write_generic,
212 0x00000000);
213
214 /* Hardware implementation registers */
215 spr_register(env, SPR_HID0, "HID0",
216 SPR_NOACCESS, SPR_NOACCESS,
217 &spr_read_generic, &spr_write_generic,
218 0x00000000);
219
220 spr_register(env, SPR_HID1, "HID1",
221 SPR_NOACCESS, SPR_NOACCESS,
222 &spr_read_generic, &spr_write_generic,
223 0x00000000);
224 }
225
226 #ifdef TARGET_PPC64
227 static void register_amr_sprs(CPUPPCState *env)
228 {
229 #ifndef CONFIG_USER_ONLY
230 /*
231 * Virtual Page Class Key protection
232 *
233 * The AMR is accessible either via SPR 13 or SPR 29. 13 is
234 * userspace accessible, 29 is privileged. So we only need to set
235 * the kvm ONE_REG id on one of them, we use 29
236 */
237 spr_register(env, SPR_UAMR, "UAMR",
238 &spr_read_generic, &spr_write_amr,
239 &spr_read_generic, &spr_write_amr,
240 0);
241 spr_register_kvm_hv(env, SPR_AMR, "AMR",
242 SPR_NOACCESS, SPR_NOACCESS,
243 &spr_read_generic, &spr_write_amr,
244 &spr_read_generic, &spr_write_generic,
245 KVM_REG_PPC_AMR, 0);
246 spr_register_kvm_hv(env, SPR_UAMOR, "UAMOR",
247 SPR_NOACCESS, SPR_NOACCESS,
248 &spr_read_generic, &spr_write_uamor,
249 &spr_read_generic, &spr_write_generic,
250 KVM_REG_PPC_UAMOR, 0);
251 spr_register_hv(env, SPR_AMOR, "AMOR",
252 SPR_NOACCESS, SPR_NOACCESS,
253 SPR_NOACCESS, SPR_NOACCESS,
254 &spr_read_generic, &spr_core_lpar_write_generic,
255 0);
256 #endif /* !CONFIG_USER_ONLY */
257 }
258
259 static void register_iamr_sprs(CPUPPCState *env)
260 {
261 #ifndef CONFIG_USER_ONLY
262 spr_register_kvm_hv(env, SPR_IAMR, "IAMR",
263 SPR_NOACCESS, SPR_NOACCESS,
264 &spr_read_generic, &spr_write_iamr,
265 &spr_read_generic, &spr_write_generic,
266 KVM_REG_PPC_IAMR, 0);
267 #endif /* !CONFIG_USER_ONLY */
268 }
269 #endif /* TARGET_PPC64 */
270
271 /* SPR specific to PowerPC 604 implementation */
272 static void register_604_sprs(CPUPPCState *env)
273 {
274 /* Processor identification */
275 spr_register(env, SPR_PIR, "PIR",
276 SPR_NOACCESS, SPR_NOACCESS,
277 &spr_read_generic, &spr_write_pir,
278 0x00000000);
279 /* Breakpoints */
280 spr_register(env, SPR_IABR, "IABR",
281 SPR_NOACCESS, SPR_NOACCESS,
282 &spr_read_generic, &spr_write_generic,
283 0x00000000);
284
285 spr_register_kvm(env, SPR_DABR, "DABR",
286 SPR_NOACCESS, SPR_NOACCESS,
287 &spr_read_generic, &spr_write_generic,
288 KVM_REG_PPC_DABR, 0x00000000);
289 /* Performance counters */
290 spr_register(env, SPR_7XX_MMCR0, "MMCR0",
291 SPR_NOACCESS, SPR_NOACCESS,
292 &spr_read_generic, &spr_write_generic,
293 0x00000000);
294
295 spr_register(env, SPR_7XX_PMC1, "PMC1",
296 SPR_NOACCESS, SPR_NOACCESS,
297 &spr_read_generic, &spr_write_generic,
298 0x00000000);
299
300 spr_register(env, SPR_7XX_PMC2, "PMC2",
301 SPR_NOACCESS, SPR_NOACCESS,
302 &spr_read_generic, &spr_write_generic,
303 0x00000000);
304
305 spr_register(env, SPR_7XX_SIAR, "SIAR",
306 SPR_NOACCESS, SPR_NOACCESS,
307 &spr_read_generic, SPR_NOACCESS,
308 0x00000000);
309
310 spr_register(env, SPR_SDA, "SDA",
311 SPR_NOACCESS, SPR_NOACCESS,
312 &spr_read_generic, SPR_NOACCESS,
313 0x00000000);
314 /* External access control */
315 spr_register(env, SPR_EAR, "EAR",
316 SPR_NOACCESS, SPR_NOACCESS,
317 &spr_read_generic, &spr_write_generic,
318 0x00000000);
319
320 /* Hardware implementation registers */
321 spr_register(env, SPR_HID0, "HID0",
322 SPR_NOACCESS, SPR_NOACCESS,
323 &spr_read_generic, &spr_write_generic,
324 0x00000000);
325 }
326
327 static void register_604e_sprs(CPUPPCState *env)
328 {
329 spr_register(env, SPR_7XX_MMCR1, "MMCR1",
330 SPR_NOACCESS, SPR_NOACCESS,
331 &spr_read_generic, &spr_write_generic,
332 0x00000000);
333
334 spr_register(env, SPR_7XX_PMC3, "PMC3",
335 SPR_NOACCESS, SPR_NOACCESS,
336 &spr_read_generic, &spr_write_generic,
337 0x00000000);
338
339 spr_register(env, SPR_7XX_PMC4, "PMC4",
340 SPR_NOACCESS, SPR_NOACCESS,
341 &spr_read_generic, &spr_write_generic,
342 0x00000000);
343 /* Hardware implementation registers */
344 spr_register(env, SPR_HID1, "HID1",
345 SPR_NOACCESS, SPR_NOACCESS,
346 &spr_read_generic, &spr_write_generic,
347 0x00000000);
348 }
349
350 /* SPR specific to PowerPC 603 implementation */
351 static void register_603_sprs(CPUPPCState *env)
352 {
353 /* External access control */
354 spr_register(env, SPR_EAR, "EAR",
355 SPR_NOACCESS, SPR_NOACCESS,
356 &spr_read_generic, &spr_write_generic,
357 0x00000000);
358 /* Breakpoints */
359 spr_register(env, SPR_IABR, "IABR",
360 SPR_NOACCESS, SPR_NOACCESS,
361 &spr_read_generic, &spr_write_generic,
362 0x00000000);
363
364 spr_register(env, SPR_HID0, "HID0",
365 SPR_NOACCESS, SPR_NOACCESS,
366 &spr_read_generic, &spr_write_generic,
367 0x00000000);
368
369 spr_register(env, SPR_HID1, "HID1",
370 SPR_NOACCESS, SPR_NOACCESS,
371 &spr_read_generic, &spr_write_generic,
372 0x00000000);
373 }
374
375 static void register_e300_sprs(CPUPPCState *env)
376 {
377 /* hardware implementation registers */
378 spr_register(env, SPR_HID2, "HID2",
379 SPR_NOACCESS, SPR_NOACCESS,
380 &spr_read_generic, &spr_write_generic,
381 0x00000000);
382 /* Breakpoints */
383 spr_register(env, SPR_DABR, "DABR",
384 SPR_NOACCESS, SPR_NOACCESS,
385 &spr_read_generic, &spr_write_generic,
386 0x00000000);
387
388 spr_register(env, SPR_DABR2, "DABR2",
389 SPR_NOACCESS, SPR_NOACCESS,
390 &spr_read_generic, &spr_write_generic,
391 0x00000000);
392
393 spr_register(env, SPR_IABR2, "IABR2",
394 SPR_NOACCESS, SPR_NOACCESS,
395 &spr_read_generic, &spr_write_generic,
396 0x00000000);
397
398 spr_register(env, SPR_IBCR, "IBCR",
399 SPR_NOACCESS, SPR_NOACCESS,
400 &spr_read_generic, &spr_write_generic,
401 0x00000000);
402
403 spr_register(env, SPR_DBCR, "DBCR",
404 SPR_NOACCESS, SPR_NOACCESS,
405 &spr_read_generic, &spr_write_generic,
406 0x00000000);
407 }
408
409 /* SPR specific to PowerPC G2 implementation */
410 static void register_G2_sprs(CPUPPCState *env)
411 {
412 /* Memory base address */
413 /* MBAR */
414 spr_register(env, SPR_MBAR, "MBAR",
415 SPR_NOACCESS, SPR_NOACCESS,
416 &spr_read_generic, &spr_write_generic,
417 0x00000000);
418 /* Exception processing */
419 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
420 SPR_NOACCESS, SPR_NOACCESS,
421 &spr_read_generic, &spr_write_generic,
422 0x00000000);
423 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
424 SPR_NOACCESS, SPR_NOACCESS,
425 &spr_read_generic, &spr_write_generic,
426 0x00000000);
427 /* Breakpoints */
428 spr_register(env, SPR_DABR, "DABR",
429 SPR_NOACCESS, SPR_NOACCESS,
430 &spr_read_generic, &spr_write_generic,
431 0x00000000);
432
433 spr_register(env, SPR_DABR2, "DABR2",
434 SPR_NOACCESS, SPR_NOACCESS,
435 &spr_read_generic, &spr_write_generic,
436 0x00000000);
437
438 spr_register(env, SPR_IABR, "IABR",
439 SPR_NOACCESS, SPR_NOACCESS,
440 &spr_read_generic, &spr_write_generic,
441 0x00000000);
442
443 spr_register(env, SPR_IABR2, "IABR2",
444 SPR_NOACCESS, SPR_NOACCESS,
445 &spr_read_generic, &spr_write_generic,
446 0x00000000);
447
448 spr_register(env, SPR_IBCR, "IBCR",
449 SPR_NOACCESS, SPR_NOACCESS,
450 &spr_read_generic, &spr_write_generic,
451 0x00000000);
452
453 spr_register(env, SPR_DBCR, "DBCR",
454 SPR_NOACCESS, SPR_NOACCESS,
455 &spr_read_generic, &spr_write_generic,
456 0x00000000);
457
458 /* External access control */
459 spr_register(env, SPR_EAR, "EAR",
460 SPR_NOACCESS, SPR_NOACCESS,
461 &spr_read_generic, &spr_write_generic,
462 0x00000000);
463 /* Hardware implementation register */
464 spr_register(env, SPR_HID0, "HID0",
465 SPR_NOACCESS, SPR_NOACCESS,
466 &spr_read_generic, &spr_write_generic,
467 0x00000000);
468
469 spr_register(env, SPR_HID1, "HID1",
470 SPR_NOACCESS, SPR_NOACCESS,
471 &spr_read_generic, &spr_write_generic,
472 0x00000000);
473
474 spr_register(env, SPR_HID2, "HID2",
475 SPR_NOACCESS, SPR_NOACCESS,
476 &spr_read_generic, &spr_write_generic,
477 0x00000000);
478
479 /* SGPRs */
480 spr_register(env, SPR_SPRG4, "SPRG4",
481 SPR_NOACCESS, SPR_NOACCESS,
482 &spr_read_generic, &spr_write_generic,
483 0x00000000);
484 spr_register(env, SPR_SPRG5, "SPRG5",
485 SPR_NOACCESS, SPR_NOACCESS,
486 &spr_read_generic, &spr_write_generic,
487 0x00000000);
488 spr_register(env, SPR_SPRG6, "SPRG6",
489 SPR_NOACCESS, SPR_NOACCESS,
490 &spr_read_generic, &spr_write_generic,
491 0x00000000);
492 spr_register(env, SPR_SPRG7, "SPRG7",
493 SPR_NOACCESS, SPR_NOACCESS,
494 &spr_read_generic, &spr_write_generic,
495 0x00000000);
496 }
497
498 static void register_74xx_sprs(CPUPPCState *env)
499 {
500 /* Breakpoints */
501 spr_register_kvm(env, SPR_DABR, "DABR",
502 SPR_NOACCESS, SPR_NOACCESS,
503 &spr_read_generic, &spr_write_generic,
504 KVM_REG_PPC_DABR, 0x00000000);
505
506 spr_register(env, SPR_IABR, "IABR",
507 SPR_NOACCESS, SPR_NOACCESS,
508 &spr_read_generic, &spr_write_generic,
509 0x00000000);
510 /* Cache management */
511 spr_register(env, SPR_ICTC, "ICTC",
512 SPR_NOACCESS, SPR_NOACCESS,
513 &spr_read_generic, &spr_write_generic,
514 0x00000000);
515 /* Performance monitors */
516 spr_register(env, SPR_7XX_MMCR0, "MMCR0",
517 SPR_NOACCESS, SPR_NOACCESS,
518 &spr_read_generic, &spr_write_generic,
519 0x00000000);
520
521 spr_register(env, SPR_7XX_MMCR1, "MMCR1",
522 SPR_NOACCESS, SPR_NOACCESS,
523 &spr_read_generic, &spr_write_generic,
524 0x00000000);
525
526 spr_register(env, SPR_7XX_PMC1, "PMC1",
527 SPR_NOACCESS, SPR_NOACCESS,
528 &spr_read_generic, &spr_write_generic,
529 0x00000000);
530
531 spr_register(env, SPR_7XX_PMC2, "PMC2",
532 SPR_NOACCESS, SPR_NOACCESS,
533 &spr_read_generic, &spr_write_generic,
534 0x00000000);
535
536 spr_register(env, SPR_7XX_PMC3, "PMC3",
537 SPR_NOACCESS, SPR_NOACCESS,
538 &spr_read_generic, &spr_write_generic,
539 0x00000000);
540
541 spr_register(env, SPR_7XX_PMC4, "PMC4",
542 SPR_NOACCESS, SPR_NOACCESS,
543 &spr_read_generic, &spr_write_generic,
544 0x00000000);
545
546 spr_register(env, SPR_7XX_SIAR, "SIAR",
547 SPR_NOACCESS, SPR_NOACCESS,
548 &spr_read_generic, SPR_NOACCESS,
549 0x00000000);
550
551 spr_register(env, SPR_7XX_UMMCR0, "UMMCR0",
552 &spr_read_ureg, SPR_NOACCESS,
553 &spr_read_ureg, SPR_NOACCESS,
554 0x00000000);
555
556 spr_register(env, SPR_7XX_UMMCR1, "UMMCR1",
557 &spr_read_ureg, SPR_NOACCESS,
558 &spr_read_ureg, SPR_NOACCESS,
559 0x00000000);
560
561 spr_register(env, SPR_7XX_UPMC1, "UPMC1",
562 &spr_read_ureg, SPR_NOACCESS,
563 &spr_read_ureg, SPR_NOACCESS,
564 0x00000000);
565
566 spr_register(env, SPR_7XX_UPMC2, "UPMC2",
567 &spr_read_ureg, SPR_NOACCESS,
568 &spr_read_ureg, SPR_NOACCESS,
569 0x00000000);
570
571 spr_register(env, SPR_7XX_UPMC3, "UPMC3",
572 &spr_read_ureg, SPR_NOACCESS,
573 &spr_read_ureg, SPR_NOACCESS,
574 0x00000000);
575
576 spr_register(env, SPR_7XX_UPMC4, "UPMC4",
577 &spr_read_ureg, SPR_NOACCESS,
578 &spr_read_ureg, SPR_NOACCESS,
579 0x00000000);
580
581 spr_register(env, SPR_7XX_USIAR, "USIAR",
582 &spr_read_ureg, SPR_NOACCESS,
583 &spr_read_ureg, SPR_NOACCESS,
584 0x00000000);
585 /* External access control */
586 spr_register(env, SPR_EAR, "EAR",
587 SPR_NOACCESS, SPR_NOACCESS,
588 &spr_read_generic, &spr_write_generic,
589 0x00000000);
590
591 /* Processor identification */
592 spr_register(env, SPR_PIR, "PIR",
593 SPR_NOACCESS, SPR_NOACCESS,
594 &spr_read_generic, &spr_write_pir,
595 0x00000000);
596
597 spr_register(env, SPR_74XX_MMCR2, "MMCR2",
598 SPR_NOACCESS, SPR_NOACCESS,
599 &spr_read_generic, &spr_write_generic,
600 0x00000000);
601
602 spr_register(env, SPR_74XX_UMMCR2, "UMMCR2",
603 &spr_read_ureg, SPR_NOACCESS,
604 &spr_read_ureg, SPR_NOACCESS,
605 0x00000000);
606
607 spr_register(env, SPR_BAMR, "BAMR",
608 SPR_NOACCESS, SPR_NOACCESS,
609 &spr_read_generic, &spr_write_generic,
610 0x00000000);
611
612 spr_register(env, SPR_MSSCR0, "MSSCR0",
613 SPR_NOACCESS, SPR_NOACCESS,
614 &spr_read_generic, &spr_write_generic,
615 0x00000000);
616 /* Hardware implementation registers */
617 spr_register(env, SPR_HID0, "HID0",
618 SPR_NOACCESS, SPR_NOACCESS,
619 &spr_read_generic, &spr_write_generic,
620 0x00000000);
621
622 spr_register(env, SPR_HID1, "HID1",
623 SPR_NOACCESS, SPR_NOACCESS,
624 &spr_read_generic, &spr_write_generic,
625 0x00000000);
626 /* Altivec */
627 spr_register(env, SPR_VRSAVE, "VRSAVE",
628 &spr_read_generic, &spr_write_generic,
629 &spr_read_generic, &spr_write_generic,
630 0x00000000);
631
632 spr_register(env, SPR_L2CR, "L2CR",
633 SPR_NOACCESS, SPR_NOACCESS,
634 &spr_read_generic, spr_access_nop,
635 0x00000000);
636 }
637
638 static void register_l3_ctrl(CPUPPCState *env)
639 {
640 /* L3CR */
641 spr_register(env, SPR_L3CR, "L3CR",
642 SPR_NOACCESS, SPR_NOACCESS,
643 &spr_read_generic, &spr_write_generic,
644 0x00000000);
645 /* L3ITCR0 */
646 spr_register(env, SPR_L3ITCR0, "L3ITCR0",
647 SPR_NOACCESS, SPR_NOACCESS,
648 &spr_read_generic, &spr_write_generic,
649 0x00000000);
650 /* L3PM */
651 spr_register(env, SPR_L3PM, "L3PM",
652 SPR_NOACCESS, SPR_NOACCESS,
653 &spr_read_generic, &spr_write_generic,
654 0x00000000);
655 }
656
657 /* PowerPC BookE SPR */
658 static void register_BookE_sprs(CPUPPCState *env, uint64_t ivor_mask)
659 {
660 const char *ivor_names[64] = {
661 "IVOR0", "IVOR1", "IVOR2", "IVOR3",
662 "IVOR4", "IVOR5", "IVOR6", "IVOR7",
663 "IVOR8", "IVOR9", "IVOR10", "IVOR11",
664 "IVOR12", "IVOR13", "IVOR14", "IVOR15",
665 "IVOR16", "IVOR17", "IVOR18", "IVOR19",
666 "IVOR20", "IVOR21", "IVOR22", "IVOR23",
667 "IVOR24", "IVOR25", "IVOR26", "IVOR27",
668 "IVOR28", "IVOR29", "IVOR30", "IVOR31",
669 "IVOR32", "IVOR33", "IVOR34", "IVOR35",
670 "IVOR36", "IVOR37", "IVOR38", "IVOR39",
671 "IVOR40", "IVOR41", "IVOR42", "IVOR43",
672 "IVOR44", "IVOR45", "IVOR46", "IVOR47",
673 "IVOR48", "IVOR49", "IVOR50", "IVOR51",
674 "IVOR52", "IVOR53", "IVOR54", "IVOR55",
675 "IVOR56", "IVOR57", "IVOR58", "IVOR59",
676 "IVOR60", "IVOR61", "IVOR62", "IVOR63",
677 };
678 #define SPR_BOOKE_IVORxx (-1)
679 int ivor_sprn[64] = {
680 SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3,
681 SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7,
682 SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11,
683 SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15,
684 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
685 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
686 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
687 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
688 SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35,
689 SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVOR38, SPR_BOOKE_IVOR39,
690 SPR_BOOKE_IVOR40, SPR_BOOKE_IVOR41, SPR_BOOKE_IVOR42, SPR_BOOKE_IVORxx,
691 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
692 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
693 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
694 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
695 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
696 };
697 int i;
698
699 /* Interrupt processing */
700 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
701 SPR_NOACCESS, SPR_NOACCESS,
702 &spr_read_generic, &spr_write_generic,
703 0x00000000);
704 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
705 SPR_NOACCESS, SPR_NOACCESS,
706 &spr_read_generic, &spr_write_generic,
707 0x00000000);
708 /* Debug */
709 spr_register(env, SPR_BOOKE_IAC1, "IAC1",
710 SPR_NOACCESS, SPR_NOACCESS,
711 &spr_read_generic, &spr_write_generic,
712 0x00000000);
713
714 spr_register(env, SPR_BOOKE_IAC2, "IAC2",
715 SPR_NOACCESS, SPR_NOACCESS,
716 &spr_read_generic, &spr_write_generic,
717 0x00000000);
718
719 spr_register(env, SPR_BOOKE_DAC1, "DAC1",
720 SPR_NOACCESS, SPR_NOACCESS,
721 &spr_read_generic, &spr_write_generic,
722 0x00000000);
723
724 spr_register(env, SPR_BOOKE_DAC2, "DAC2",
725 SPR_NOACCESS, SPR_NOACCESS,
726 &spr_read_generic, &spr_write_generic,
727 0x00000000);
728
729 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
730 SPR_NOACCESS, SPR_NOACCESS,
731 &spr_read_generic, &spr_write_40x_dbcr0,
732 0x00000000);
733
734 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
735 SPR_NOACCESS, SPR_NOACCESS,
736 &spr_read_generic, &spr_write_generic,
737 0x00000000);
738
739 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
740 SPR_NOACCESS, SPR_NOACCESS,
741 &spr_read_generic, &spr_write_generic,
742 0x00000000);
743 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
744 SPR_NOACCESS, SPR_NOACCESS,
745 &spr_read_generic, &spr_write_generic,
746 0x00000000);
747 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
748 SPR_NOACCESS, SPR_NOACCESS,
749 &spr_read_generic, &spr_write_generic,
750 0x00000000);
751
752 spr_register(env, SPR_BOOKE_DBSR, "DBSR",
753 SPR_NOACCESS, SPR_NOACCESS,
754 &spr_read_generic, &spr_write_clear,
755 0x00000000);
756 spr_register(env, SPR_BOOKE_DEAR, "DEAR",
757 SPR_NOACCESS, SPR_NOACCESS,
758 &spr_read_generic, &spr_write_generic,
759 0x00000000);
760 spr_register(env, SPR_BOOKE_ESR, "ESR",
761 SPR_NOACCESS, SPR_NOACCESS,
762 &spr_read_generic, &spr_write_generic,
763 0x00000000);
764 spr_register(env, SPR_BOOKE_IVPR, "IVPR",
765 SPR_NOACCESS, SPR_NOACCESS,
766 &spr_read_generic, &spr_write_excp_prefix,
767 0x00000000);
768 /* Exception vectors */
769 for (i = 0; i < 64; i++) {
770 if (ivor_mask & (1ULL << i)) {
771 if (ivor_sprn[i] == SPR_BOOKE_IVORxx) {
772 fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i);
773 exit(1);
774 }
775 spr_register(env, ivor_sprn[i], ivor_names[i],
776 SPR_NOACCESS, SPR_NOACCESS,
777 &spr_read_generic, &spr_write_excp_vector,
778 0x00000000);
779 }
780 }
781 spr_register(env, SPR_BOOKE_PID, "PID",
782 SPR_NOACCESS, SPR_NOACCESS,
783 &spr_read_generic, &spr_write_booke_pid,
784 0x00000000);
785 spr_register(env, SPR_BOOKE_TCR, "TCR",
786 SPR_NOACCESS, SPR_NOACCESS,
787 &spr_read_generic, &spr_write_booke_tcr,
788 0x00000000);
789 spr_register(env, SPR_BOOKE_TSR, "TSR",
790 SPR_NOACCESS, SPR_NOACCESS,
791 &spr_read_generic, &spr_write_booke_tsr,
792 0x00000000);
793 /* Timer */
794 spr_register(env, SPR_DECR, "DECR",
795 SPR_NOACCESS, SPR_NOACCESS,
796 &spr_read_decr, &spr_write_decr,
797 0x00000000);
798 spr_register(env, SPR_BOOKE_DECAR, "DECAR",
799 SPR_NOACCESS, SPR_NOACCESS,
800 SPR_NOACCESS, &spr_write_generic32,
801 0x00000000);
802 /* SPRGs */
803 spr_register(env, SPR_USPRG0, "USPRG0",
804 &spr_read_generic, &spr_write_generic,
805 &spr_read_generic, &spr_write_generic,
806 0x00000000);
807 spr_register(env, SPR_SPRG4, "SPRG4",
808 SPR_NOACCESS, SPR_NOACCESS,
809 &spr_read_generic, &spr_write_generic,
810 0x00000000);
811 spr_register(env, SPR_SPRG5, "SPRG5",
812 SPR_NOACCESS, SPR_NOACCESS,
813 &spr_read_generic, &spr_write_generic,
814 0x00000000);
815 spr_register(env, SPR_SPRG6, "SPRG6",
816 SPR_NOACCESS, SPR_NOACCESS,
817 &spr_read_generic, &spr_write_generic,
818 0x00000000);
819 spr_register(env, SPR_SPRG7, "SPRG7",
820 SPR_NOACCESS, SPR_NOACCESS,
821 &spr_read_generic, &spr_write_generic,
822 0x00000000);
823 spr_register(env, SPR_BOOKE_SPRG8, "SPRG8",
824 SPR_NOACCESS, SPR_NOACCESS,
825 &spr_read_generic, &spr_write_generic,
826 0x00000000);
827 spr_register(env, SPR_BOOKE_SPRG9, "SPRG9",
828 SPR_NOACCESS, SPR_NOACCESS,
829 &spr_read_generic, &spr_write_generic,
830 0x00000000);
831 }
832
833 #if !defined(CONFIG_USER_ONLY)
834 static inline uint32_t register_tlbncfg(uint32_t assoc, uint32_t minsize,
835 uint32_t maxsize, uint32_t flags,
836 uint32_t nentries)
837 {
838 return (assoc << TLBnCFG_ASSOC_SHIFT) |
839 (minsize << TLBnCFG_MINSIZE_SHIFT) |
840 (maxsize << TLBnCFG_MAXSIZE_SHIFT) |
841 flags | nentries;
842 }
843 #endif /* !CONFIG_USER_ONLY */
844
845 /* BookE 2.06 storage control registers */
846 static void register_BookE206_sprs(CPUPPCState *env, uint32_t mas_mask,
847 uint32_t *tlbncfg, uint32_t mmucfg)
848 {
849 #if !defined(CONFIG_USER_ONLY)
850 const char *mas_names[8] = {
851 "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7",
852 };
853 int mas_sprn[8] = {
854 SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3,
855 SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7,
856 };
857 const char *tlbcfg_names[4] = {
858 "TLB0CFG", "TLB1CFG", "TLB2CFG", "TLB3CFG",
859 };
860 const int tlbcfg_sprn[4] = {
861 SPR_BOOKE_TLB0CFG, SPR_BOOKE_TLB1CFG,
862 SPR_BOOKE_TLB2CFG, SPR_BOOKE_TLB3CFG,
863 };
864 int i;
865
866 /* TLB assist registers */
867 for (i = 0; i < 8; i++) {
868 if (mas_mask & (1 << i)) {
869 spr_register(env, mas_sprn[i], mas_names[i],
870 SPR_NOACCESS, SPR_NOACCESS,
871 &spr_read_generic,
872 (i == 2 && (env->insns_flags & PPC_64B))
873 ? &spr_write_generic : &spr_write_generic32,
874 0x00000000);
875 }
876 }
877 if (env->nb_pids > 1) {
878 spr_register(env, SPR_BOOKE_PID1, "PID1",
879 SPR_NOACCESS, SPR_NOACCESS,
880 &spr_read_generic, &spr_write_booke_pid,
881 0x00000000);
882 }
883 if (env->nb_pids > 2) {
884 spr_register(env, SPR_BOOKE_PID2, "PID2",
885 SPR_NOACCESS, SPR_NOACCESS,
886 &spr_read_generic, &spr_write_booke_pid,
887 0x00000000);
888 }
889
890 spr_register(env, SPR_BOOKE_EPLC, "EPLC",
891 SPR_NOACCESS, SPR_NOACCESS,
892 &spr_read_generic, &spr_write_eplc,
893 0x00000000);
894 spr_register(env, SPR_BOOKE_EPSC, "EPSC",
895 SPR_NOACCESS, SPR_NOACCESS,
896 &spr_read_generic, &spr_write_epsc,
897 0x00000000);
898
899 spr_register(env, SPR_MMUCFG, "MMUCFG",
900 SPR_NOACCESS, SPR_NOACCESS,
901 &spr_read_generic, SPR_NOACCESS,
902 mmucfg);
903
904 assert(env->nb_ways <= ARRAY_SIZE(tlbcfg_names));
905 for (i = 0; i < env->nb_ways; i++) {
906 spr_register(env, tlbcfg_sprn[i], tlbcfg_names[i],
907 SPR_NOACCESS, SPR_NOACCESS,
908 &spr_read_generic, SPR_NOACCESS,
909 tlbncfg[i]);
910 }
911 #endif
912 }
913
914 static void register_atb_sprs(CPUPPCState *env)
915 {
916 spr_register(env, SPR_ATBL, "ATBL",
917 &spr_read_atbl, SPR_NOACCESS,
918 &spr_read_atbl, SPR_NOACCESS,
919 0x00000000);
920 spr_register(env, SPR_ATBU, "ATBU",
921 &spr_read_atbu, SPR_NOACCESS,
922 &spr_read_atbu, SPR_NOACCESS,
923 0x00000000);
924 }
925
926 /* SPR specific to PowerPC 440 implementation */
927 static void register_440_sprs(CPUPPCState *env)
928 {
929 /* Cache control */
930 spr_register(env, SPR_440_DNV0, "DNV0",
931 SPR_NOACCESS, SPR_NOACCESS,
932 &spr_read_generic, &spr_write_generic,
933 0x00000000);
934
935 spr_register(env, SPR_440_DNV1, "DNV1",
936 SPR_NOACCESS, SPR_NOACCESS,
937 &spr_read_generic, &spr_write_generic,
938 0x00000000);
939
940 spr_register(env, SPR_440_DNV2, "DNV2",
941 SPR_NOACCESS, SPR_NOACCESS,
942 &spr_read_generic, &spr_write_generic,
943 0x00000000);
944
945 spr_register(env, SPR_440_DNV3, "DNV3",
946 SPR_NOACCESS, SPR_NOACCESS,
947 &spr_read_generic, &spr_write_generic,
948 0x00000000);
949
950 spr_register(env, SPR_440_DTV0, "DTV0",
951 SPR_NOACCESS, SPR_NOACCESS,
952 &spr_read_generic, &spr_write_generic,
953 0x00000000);
954
955 spr_register(env, SPR_440_DTV1, "DTV1",
956 SPR_NOACCESS, SPR_NOACCESS,
957 &spr_read_generic, &spr_write_generic,
958 0x00000000);
959
960 spr_register(env, SPR_440_DTV2, "DTV2",
961 SPR_NOACCESS, SPR_NOACCESS,
962 &spr_read_generic, &spr_write_generic,
963 0x00000000);
964
965 spr_register(env, SPR_440_DTV3, "DTV3",
966 SPR_NOACCESS, SPR_NOACCESS,
967 &spr_read_generic, &spr_write_generic,
968 0x00000000);
969
970 spr_register(env, SPR_440_DVLIM, "DVLIM",
971 SPR_NOACCESS, SPR_NOACCESS,
972 &spr_read_generic, &spr_write_generic,
973 0x00000000);
974
975 spr_register(env, SPR_440_INV0, "INV0",
976 SPR_NOACCESS, SPR_NOACCESS,
977 &spr_read_generic, &spr_write_generic,
978 0x00000000);
979
980 spr_register(env, SPR_440_INV1, "INV1",
981 SPR_NOACCESS, SPR_NOACCESS,
982 &spr_read_generic, &spr_write_generic,
983 0x00000000);
984
985 spr_register(env, SPR_440_INV2, "INV2",
986 SPR_NOACCESS, SPR_NOACCESS,
987 &spr_read_generic, &spr_write_generic,
988 0x00000000);
989
990 spr_register(env, SPR_440_INV3, "INV3",
991 SPR_NOACCESS, SPR_NOACCESS,
992 &spr_read_generic, &spr_write_generic,
993 0x00000000);
994
995 spr_register(env, SPR_440_ITV0, "ITV0",
996 SPR_NOACCESS, SPR_NOACCESS,
997 &spr_read_generic, &spr_write_generic,
998 0x00000000);
999
1000 spr_register(env, SPR_440_ITV1, "ITV1",
1001 SPR_NOACCESS, SPR_NOACCESS,
1002 &spr_read_generic, &spr_write_generic,
1003 0x00000000);
1004
1005 spr_register(env, SPR_440_ITV2, "ITV2",
1006 SPR_NOACCESS, SPR_NOACCESS,
1007 &spr_read_generic, &spr_write_generic,
1008 0x00000000);
1009
1010 spr_register(env, SPR_440_ITV3, "ITV3",
1011 SPR_NOACCESS, SPR_NOACCESS,
1012 &spr_read_generic, &spr_write_generic,
1013 0x00000000);
1014
1015 spr_register(env, SPR_440_IVLIM, "IVLIM",
1016 SPR_NOACCESS, SPR_NOACCESS,
1017 &spr_read_generic, &spr_write_generic,
1018 0x00000000);
1019 /* Cache debug */
1020 spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
1021 SPR_NOACCESS, SPR_NOACCESS,
1022 &spr_read_generic, SPR_NOACCESS,
1023 0x00000000);
1024
1025 spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
1026 SPR_NOACCESS, SPR_NOACCESS,
1027 &spr_read_generic, SPR_NOACCESS,
1028 0x00000000);
1029
1030 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1031 SPR_NOACCESS, SPR_NOACCESS,
1032 &spr_read_generic, SPR_NOACCESS,
1033 0x00000000);
1034
1035 spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
1036 SPR_NOACCESS, SPR_NOACCESS,
1037 &spr_read_generic, SPR_NOACCESS,
1038 0x00000000);
1039
1040 spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
1041 SPR_NOACCESS, SPR_NOACCESS,
1042 &spr_read_generic, SPR_NOACCESS,
1043 0x00000000);
1044
1045 spr_register(env, SPR_440_DBDR, "DBDR",
1046 SPR_NOACCESS, SPR_NOACCESS,
1047 &spr_read_generic, &spr_write_generic,
1048 0x00000000);
1049 /* Processor control */
1050 spr_register(env, SPR_4xx_CCR0, "CCR0",
1051 SPR_NOACCESS, SPR_NOACCESS,
1052 &spr_read_generic, &spr_write_generic,
1053 0x00000000);
1054 spr_register(env, SPR_440_RSTCFG, "RSTCFG",
1055 SPR_NOACCESS, SPR_NOACCESS,
1056 &spr_read_generic, SPR_NOACCESS,
1057 0x00000000);
1058 /* Storage control */
1059 spr_register(env, SPR_440_MMUCR, "MMUCR",
1060 SPR_NOACCESS, SPR_NOACCESS,
1061 &spr_read_generic, &spr_write_generic,
1062 0x00000000);
1063
1064 /* Processor identification */
1065 spr_register(env, SPR_BOOKE_PIR, "PIR",
1066 SPR_NOACCESS, SPR_NOACCESS,
1067 &spr_read_generic, &spr_write_pir,
1068 0x00000000);
1069
1070 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
1071 SPR_NOACCESS, SPR_NOACCESS,
1072 &spr_read_generic, &spr_write_generic,
1073 0x00000000);
1074
1075 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
1076 SPR_NOACCESS, SPR_NOACCESS,
1077 &spr_read_generic, &spr_write_generic,
1078 0x00000000);
1079
1080 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
1081 SPR_NOACCESS, SPR_NOACCESS,
1082 &spr_read_generic, &spr_write_generic,
1083 0x00000000);
1084
1085 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
1086 SPR_NOACCESS, SPR_NOACCESS,
1087 &spr_read_generic, &spr_write_generic,
1088 0x00000000);
1089 }
1090
1091 /* SPR shared between PowerPC 40x implementations */
1092 static void register_40x_sprs(CPUPPCState *env)
1093 {
1094 /* Cache */
1095 /* not emulated, as QEMU do not emulate caches */
1096 spr_register(env, SPR_40x_DCCR, "DCCR",
1097 SPR_NOACCESS, SPR_NOACCESS,
1098 &spr_read_generic, &spr_write_generic,
1099 0x00000000);
1100 /* not emulated, as QEMU do not emulate caches */
1101 spr_register(env, SPR_40x_ICCR, "ICCR",
1102 SPR_NOACCESS, SPR_NOACCESS,
1103 &spr_read_generic, &spr_write_generic,
1104 0x00000000);
1105 /* not emulated, as QEMU do not emulate caches */
1106 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1107 SPR_NOACCESS, SPR_NOACCESS,
1108 &spr_read_generic, SPR_NOACCESS,
1109 0x00000000);
1110 /* Exception */
1111 spr_register(env, SPR_40x_DEAR, "DEAR",
1112 SPR_NOACCESS, SPR_NOACCESS,
1113 &spr_read_generic, &spr_write_generic,
1114 0x00000000);
1115 spr_register(env, SPR_40x_ESR, "ESR",
1116 SPR_NOACCESS, SPR_NOACCESS,
1117 &spr_read_generic, &spr_write_generic,
1118 0x00000000);
1119 spr_register(env, SPR_40x_EVPR, "EVPR",
1120 SPR_NOACCESS, SPR_NOACCESS,
1121 &spr_read_generic, &spr_write_excp_prefix,
1122 0x00000000);
1123 spr_register(env, SPR_40x_SRR2, "SRR2",
1124 &spr_read_generic, &spr_write_generic,
1125 &spr_read_generic, &spr_write_generic,
1126 0x00000000);
1127 spr_register(env, SPR_40x_SRR3, "SRR3",
1128 &spr_read_generic, &spr_write_generic,
1129 &spr_read_generic, &spr_write_generic,
1130 0x00000000);
1131 /* Timers */
1132 spr_register(env, SPR_40x_PIT, "PIT",
1133 SPR_NOACCESS, SPR_NOACCESS,
1134 &spr_read_40x_pit, &spr_write_40x_pit,
1135 0x00000000);
1136 spr_register(env, SPR_40x_TCR, "TCR",
1137 SPR_NOACCESS, SPR_NOACCESS,
1138 &spr_read_generic, &spr_write_40x_tcr,
1139 0x00000000);
1140 spr_register(env, SPR_40x_TSR, "TSR",
1141 SPR_NOACCESS, SPR_NOACCESS,
1142 &spr_read_generic, &spr_write_40x_tsr,
1143 0x00000000);
1144 }
1145
1146 /* SPR specific to PowerPC 405 implementation */
1147 static void register_405_sprs(CPUPPCState *env)
1148 {
1149 /* MMU */
1150 spr_register(env, SPR_40x_PID, "PID",
1151 SPR_NOACCESS, SPR_NOACCESS,
1152 &spr_read_generic, &spr_write_40x_pid,
1153 0x00000000);
1154 spr_register(env, SPR_4xx_CCR0, "CCR0",
1155 SPR_NOACCESS, SPR_NOACCESS,
1156 &spr_read_generic, &spr_write_generic,
1157 0x00700000);
1158 /* Debug interface */
1159 spr_register(env, SPR_40x_DBCR0, "DBCR0",
1160 SPR_NOACCESS, SPR_NOACCESS,
1161 &spr_read_generic, &spr_write_40x_dbcr0,
1162 0x00000000);
1163
1164 spr_register(env, SPR_405_DBCR1, "DBCR1",
1165 SPR_NOACCESS, SPR_NOACCESS,
1166 &spr_read_generic, &spr_write_generic,
1167 0x00000000);
1168
1169 spr_register(env, SPR_40x_DBSR, "DBSR",
1170 SPR_NOACCESS, SPR_NOACCESS,
1171 &spr_read_generic, &spr_write_clear,
1172 /* Last reset was system reset */
1173 0x00000300);
1174
1175 spr_register(env, SPR_40x_DAC1, "DAC1",
1176 SPR_NOACCESS, SPR_NOACCESS,
1177 &spr_read_generic, &spr_write_generic,
1178 0x00000000);
1179 spr_register(env, SPR_40x_DAC2, "DAC2",
1180 SPR_NOACCESS, SPR_NOACCESS,
1181 &spr_read_generic, &spr_write_generic,
1182 0x00000000);
1183
1184 spr_register(env, SPR_405_DVC1, "DVC1",
1185 SPR_NOACCESS, SPR_NOACCESS,
1186 &spr_read_generic, &spr_write_generic,
1187 0x00000000);
1188
1189 spr_register(env, SPR_405_DVC2, "DVC2",
1190 SPR_NOACCESS, SPR_NOACCESS,
1191 &spr_read_generic, &spr_write_generic,
1192 0x00000000);
1193
1194 spr_register(env, SPR_40x_IAC1, "IAC1",
1195 SPR_NOACCESS, SPR_NOACCESS,
1196 &spr_read_generic, &spr_write_generic,
1197 0x00000000);
1198 spr_register(env, SPR_40x_IAC2, "IAC2",
1199 SPR_NOACCESS, SPR_NOACCESS,
1200 &spr_read_generic, &spr_write_generic,
1201 0x00000000);
1202
1203 spr_register(env, SPR_405_IAC3, "IAC3",
1204 SPR_NOACCESS, SPR_NOACCESS,
1205 &spr_read_generic, &spr_write_generic,
1206 0x00000000);
1207
1208 spr_register(env, SPR_405_IAC4, "IAC4",
1209 SPR_NOACCESS, SPR_NOACCESS,
1210 &spr_read_generic, &spr_write_generic,
1211 0x00000000);
1212 /* Storage control */
1213 spr_register(env, SPR_405_SLER, "SLER",
1214 SPR_NOACCESS, SPR_NOACCESS,
1215 &spr_read_generic, &spr_write_40x_sler,
1216 0x00000000);
1217 spr_register(env, SPR_40x_ZPR, "ZPR",
1218 SPR_NOACCESS, SPR_NOACCESS,
1219 &spr_read_generic, &spr_write_generic,
1220 0x00000000);
1221
1222 spr_register(env, SPR_405_SU0R, "SU0R",
1223 SPR_NOACCESS, SPR_NOACCESS,
1224 &spr_read_generic, &spr_write_generic,
1225 0x00000000);
1226 /* SPRG */
1227 spr_register(env, SPR_USPRG0, "USPRG0",
1228 &spr_read_ureg, SPR_NOACCESS,
1229 &spr_read_ureg, SPR_NOACCESS,
1230 0x00000000);
1231 spr_register(env, SPR_SPRG4, "SPRG4",
1232 SPR_NOACCESS, SPR_NOACCESS,
1233 &spr_read_generic, &spr_write_generic,
1234 0x00000000);
1235 spr_register(env, SPR_SPRG5, "SPRG5",
1236 SPR_NOACCESS, SPR_NOACCESS,
1237 spr_read_generic, &spr_write_generic,
1238 0x00000000);
1239 spr_register(env, SPR_SPRG6, "SPRG6",
1240 SPR_NOACCESS, SPR_NOACCESS,
1241 spr_read_generic, &spr_write_generic,
1242 0x00000000);
1243 spr_register(env, SPR_SPRG7, "SPRG7",
1244 SPR_NOACCESS, SPR_NOACCESS,
1245 spr_read_generic, &spr_write_generic,
1246 0x00000000);
1247
1248 /* Bus access control */
1249 /* not emulated, as QEMU never does speculative access */
1250 spr_register(env, SPR_40x_SGR, "SGR",
1251 SPR_NOACCESS, SPR_NOACCESS,
1252 &spr_read_generic, &spr_write_generic,
1253 0xFFFFFFFF);
1254 /* not emulated, as QEMU do not emulate caches */
1255 spr_register(env, SPR_40x_DCWR, "DCWR",
1256 SPR_NOACCESS, SPR_NOACCESS,
1257 &spr_read_generic, &spr_write_generic,
1258 0x00000000);
1259 }
1260
1261
1262 static void register_5xx_8xx_sprs(CPUPPCState *env)
1263 {
1264 /* Exception processing */
1265 spr_register_kvm(env, SPR_DSISR, "DSISR",
1266 SPR_NOACCESS, SPR_NOACCESS,
1267 &spr_read_generic, &spr_write_generic,
1268 KVM_REG_PPC_DSISR, 0x00000000);
1269 spr_register_kvm(env, SPR_DAR, "DAR",
1270 SPR_NOACCESS, SPR_NOACCESS,
1271 &spr_read_generic, &spr_write_generic,
1272 KVM_REG_PPC_DAR, 0x00000000);
1273 /* Timer */
1274 spr_register(env, SPR_DECR, "DECR",
1275 SPR_NOACCESS, SPR_NOACCESS,
1276 &spr_read_decr, &spr_write_decr,
1277 0x00000000);
1278
1279 spr_register(env, SPR_MPC_EIE, "EIE",
1280 SPR_NOACCESS, SPR_NOACCESS,
1281 &spr_read_generic, &spr_write_generic,
1282 0x00000000);
1283
1284 spr_register(env, SPR_MPC_EID, "EID",
1285 SPR_NOACCESS, SPR_NOACCESS,
1286 &spr_read_generic, &spr_write_generic,
1287 0x00000000);
1288
1289 spr_register(env, SPR_MPC_NRI, "NRI",
1290 SPR_NOACCESS, SPR_NOACCESS,
1291 &spr_read_generic, &spr_write_generic,
1292 0x00000000);
1293
1294 spr_register(env, SPR_MPC_CMPA, "CMPA",
1295 SPR_NOACCESS, SPR_NOACCESS,
1296 &spr_read_generic, &spr_write_generic,
1297 0x00000000);
1298
1299 spr_register(env, SPR_MPC_CMPB, "CMPB",
1300 SPR_NOACCESS, SPR_NOACCESS,
1301 &spr_read_generic, &spr_write_generic,
1302 0x00000000);
1303
1304 spr_register(env, SPR_MPC_CMPC, "CMPC",
1305 SPR_NOACCESS, SPR_NOACCESS,
1306 &spr_read_generic, &spr_write_generic,
1307 0x00000000);
1308
1309 spr_register(env, SPR_MPC_CMPD, "CMPD",
1310 SPR_NOACCESS, SPR_NOACCESS,
1311 &spr_read_generic, &spr_write_generic,
1312 0x00000000);
1313
1314 spr_register(env, SPR_MPC_ECR, "ECR",
1315 SPR_NOACCESS, SPR_NOACCESS,
1316 &spr_read_generic, &spr_write_generic,
1317 0x00000000);
1318
1319 spr_register(env, SPR_MPC_DER, "DER",
1320 SPR_NOACCESS, SPR_NOACCESS,
1321 &spr_read_generic, &spr_write_generic,
1322 0x00000000);
1323
1324 spr_register(env, SPR_MPC_COUNTA, "COUNTA",
1325 SPR_NOACCESS, SPR_NOACCESS,
1326 &spr_read_generic, &spr_write_generic,
1327 0x00000000);
1328
1329 spr_register(env, SPR_MPC_COUNTB, "COUNTB",
1330 SPR_NOACCESS, SPR_NOACCESS,
1331 &spr_read_generic, &spr_write_generic,
1332 0x00000000);
1333
1334 spr_register(env, SPR_MPC_CMPE, "CMPE",
1335 SPR_NOACCESS, SPR_NOACCESS,
1336 &spr_read_generic, &spr_write_generic,
1337 0x00000000);
1338
1339 spr_register(env, SPR_MPC_CMPF, "CMPF",
1340 SPR_NOACCESS, SPR_NOACCESS,
1341 &spr_read_generic, &spr_write_generic,
1342 0x00000000);
1343
1344 spr_register(env, SPR_MPC_CMPG, "CMPG",
1345 SPR_NOACCESS, SPR_NOACCESS,
1346 &spr_read_generic, &spr_write_generic,
1347 0x00000000);
1348
1349 spr_register(env, SPR_MPC_CMPH, "CMPH",
1350 SPR_NOACCESS, SPR_NOACCESS,
1351 &spr_read_generic, &spr_write_generic,
1352 0x00000000);
1353
1354 spr_register(env, SPR_MPC_LCTRL1, "LCTRL1",
1355 SPR_NOACCESS, SPR_NOACCESS,
1356 &spr_read_generic, &spr_write_generic,
1357 0x00000000);
1358
1359 spr_register(env, SPR_MPC_LCTRL2, "LCTRL2",
1360 SPR_NOACCESS, SPR_NOACCESS,
1361 &spr_read_generic, &spr_write_generic,
1362 0x00000000);
1363
1364 spr_register(env, SPR_MPC_BAR, "BAR",
1365 SPR_NOACCESS, SPR_NOACCESS,
1366 &spr_read_generic, &spr_write_generic,
1367 0x00000000);
1368
1369 spr_register(env, SPR_MPC_DPDR, "DPDR",
1370 SPR_NOACCESS, SPR_NOACCESS,
1371 &spr_read_generic, &spr_write_generic,
1372 0x00000000);
1373
1374 spr_register(env, SPR_MPC_IMMR, "IMMR",
1375 SPR_NOACCESS, SPR_NOACCESS,
1376 &spr_read_generic, &spr_write_generic,
1377 0x00000000);
1378 }
1379
1380 static void register_5xx_sprs(CPUPPCState *env)
1381 {
1382 spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA",
1383 SPR_NOACCESS, SPR_NOACCESS,
1384 &spr_read_generic, &spr_write_generic,
1385 0x00000000);
1386
1387 spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA",
1388 SPR_NOACCESS, SPR_NOACCESS,
1389 &spr_read_generic, &spr_write_generic,
1390 0x00000000);
1391
1392 spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR",
1393 SPR_NOACCESS, SPR_NOACCESS,
1394 &spr_read_generic, &spr_write_generic,
1395 0x00000000);
1396
1397 spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR",
1398 SPR_NOACCESS, SPR_NOACCESS,
1399 &spr_read_generic, &spr_write_generic,
1400 0x00000000);
1401
1402 spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0",
1403 SPR_NOACCESS, SPR_NOACCESS,
1404 &spr_read_generic, &spr_write_generic,
1405 0x00000000);
1406
1407 spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1",
1408 SPR_NOACCESS, SPR_NOACCESS,
1409 &spr_read_generic, &spr_write_generic,
1410 0x00000000);
1411
1412 spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2",
1413 SPR_NOACCESS, SPR_NOACCESS,
1414 &spr_read_generic, &spr_write_generic,
1415 0x00000000);
1416
1417 spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3",
1418 SPR_NOACCESS, SPR_NOACCESS,
1419 &spr_read_generic, &spr_write_generic,
1420 0x00000000);
1421
1422 spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0",
1423 SPR_NOACCESS, SPR_NOACCESS,
1424 &spr_read_generic, &spr_write_generic,
1425 0x00000000);
1426
1427 spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1",
1428 SPR_NOACCESS, SPR_NOACCESS,
1429 &spr_read_generic, &spr_write_generic,
1430 0x00000000);
1431
1432 spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2",
1433 SPR_NOACCESS, SPR_NOACCESS,
1434 &spr_read_generic, &spr_write_generic,
1435 0x00000000);
1436
1437 spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3",
1438 SPR_NOACCESS, SPR_NOACCESS,
1439 &spr_read_generic, &spr_write_generic,
1440 0x00000000);
1441
1442 spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0",
1443 SPR_NOACCESS, SPR_NOACCESS,
1444 &spr_read_generic, &spr_write_generic,
1445 0x00000000);
1446
1447 spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1",
1448 SPR_NOACCESS, SPR_NOACCESS,
1449 &spr_read_generic, &spr_write_generic,
1450 0x00000000);
1451
1452 spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2",
1453 SPR_NOACCESS, SPR_NOACCESS,
1454 &spr_read_generic, &spr_write_generic,
1455 0x00000000);
1456
1457 spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3",
1458 SPR_NOACCESS, SPR_NOACCESS,
1459 &spr_read_generic, &spr_write_generic,
1460 0x00000000);
1461
1462 spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0",
1463 SPR_NOACCESS, SPR_NOACCESS,
1464 &spr_read_generic, &spr_write_generic,
1465 0x00000000);
1466
1467 spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1",
1468 SPR_NOACCESS, SPR_NOACCESS,
1469 &spr_read_generic, &spr_write_generic,
1470 0x00000000);
1471
1472 spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2",
1473 SPR_NOACCESS, SPR_NOACCESS,
1474 &spr_read_generic, &spr_write_generic,
1475 0x00000000);
1476
1477 spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3",
1478 SPR_NOACCESS, SPR_NOACCESS,
1479 &spr_read_generic, &spr_write_generic,
1480 0x00000000);
1481
1482 spr_register(env, SPR_RCPU_FPECR, "FPECR",
1483 SPR_NOACCESS, SPR_NOACCESS,
1484 &spr_read_generic, &spr_write_generic,
1485 0x00000000);
1486 }
1487
1488 static void register_8xx_sprs(CPUPPCState *env)
1489 {
1490
1491 spr_register(env, SPR_MPC_IC_CST, "IC_CST",
1492 SPR_NOACCESS, SPR_NOACCESS,
1493 &spr_read_generic, &spr_write_generic,
1494 0x00000000);
1495
1496 spr_register(env, SPR_MPC_IC_ADR, "IC_ADR",
1497 SPR_NOACCESS, SPR_NOACCESS,
1498 &spr_read_generic, &spr_write_generic,
1499 0x00000000);
1500
1501 spr_register(env, SPR_MPC_IC_DAT, "IC_DAT",
1502 SPR_NOACCESS, SPR_NOACCESS,
1503 &spr_read_generic, &spr_write_generic,
1504 0x00000000);
1505
1506 spr_register(env, SPR_MPC_DC_CST, "DC_CST",
1507 SPR_NOACCESS, SPR_NOACCESS,
1508 &spr_read_generic, &spr_write_generic,
1509 0x00000000);
1510
1511 spr_register(env, SPR_MPC_DC_ADR, "DC_ADR",
1512 SPR_NOACCESS, SPR_NOACCESS,
1513 &spr_read_generic, &spr_write_generic,
1514 0x00000000);
1515
1516 spr_register(env, SPR_MPC_DC_DAT, "DC_DAT",
1517 SPR_NOACCESS, SPR_NOACCESS,
1518 &spr_read_generic, &spr_write_generic,
1519 0x00000000);
1520
1521 spr_register(env, SPR_MPC_MI_CTR, "MI_CTR",
1522 SPR_NOACCESS, SPR_NOACCESS,
1523 &spr_read_generic, &spr_write_generic,
1524 0x00000000);
1525
1526 spr_register(env, SPR_MPC_MI_AP, "MI_AP",
1527 SPR_NOACCESS, SPR_NOACCESS,
1528 &spr_read_generic, &spr_write_generic,
1529 0x00000000);
1530
1531 spr_register(env, SPR_MPC_MI_EPN, "MI_EPN",
1532 SPR_NOACCESS, SPR_NOACCESS,
1533 &spr_read_generic, &spr_write_generic,
1534 0x00000000);
1535
1536 spr_register(env, SPR_MPC_MI_TWC, "MI_TWC",
1537 SPR_NOACCESS, SPR_NOACCESS,
1538 &spr_read_generic, &spr_write_generic,
1539 0x00000000);
1540
1541 spr_register(env, SPR_MPC_MI_RPN, "MI_RPN",
1542 SPR_NOACCESS, SPR_NOACCESS,
1543 &spr_read_generic, &spr_write_generic,
1544 0x00000000);
1545
1546 spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM",
1547 SPR_NOACCESS, SPR_NOACCESS,
1548 &spr_read_generic, &spr_write_generic,
1549 0x00000000);
1550
1551 spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0",
1552 SPR_NOACCESS, SPR_NOACCESS,
1553 &spr_read_generic, &spr_write_generic,
1554 0x00000000);
1555
1556 spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1",
1557 SPR_NOACCESS, SPR_NOACCESS,
1558 &spr_read_generic, &spr_write_generic,
1559 0x00000000);
1560
1561 spr_register(env, SPR_MPC_MD_CTR, "MD_CTR",
1562 SPR_NOACCESS, SPR_NOACCESS,
1563 &spr_read_generic, &spr_write_generic,
1564 0x00000000);
1565
1566 spr_register(env, SPR_MPC_MD_CASID, "MD_CASID",
1567 SPR_NOACCESS, SPR_NOACCESS,
1568 &spr_read_generic, &spr_write_generic,
1569 0x00000000);
1570
1571 spr_register(env, SPR_MPC_MD_AP, "MD_AP",
1572 SPR_NOACCESS, SPR_NOACCESS,
1573 &spr_read_generic, &spr_write_generic,
1574 0x00000000);
1575
1576 spr_register(env, SPR_MPC_MD_EPN, "MD_EPN",
1577 SPR_NOACCESS, SPR_NOACCESS,
1578 &spr_read_generic, &spr_write_generic,
1579 0x00000000);
1580
1581 spr_register(env, SPR_MPC_MD_TWB, "MD_TWB",
1582 SPR_NOACCESS, SPR_NOACCESS,
1583 &spr_read_generic, &spr_write_generic,
1584 0x00000000);
1585
1586 spr_register(env, SPR_MPC_MD_TWC, "MD_TWC",
1587 SPR_NOACCESS, SPR_NOACCESS,
1588 &spr_read_generic, &spr_write_generic,
1589 0x00000000);
1590
1591 spr_register(env, SPR_MPC_MD_RPN, "MD_RPN",
1592 SPR_NOACCESS, SPR_NOACCESS,
1593 &spr_read_generic, &spr_write_generic,
1594 0x00000000);
1595
1596 spr_register(env, SPR_MPC_MD_TW, "MD_TW",
1597 SPR_NOACCESS, SPR_NOACCESS,
1598 &spr_read_generic, &spr_write_generic,
1599 0x00000000);
1600
1601 spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM",
1602 SPR_NOACCESS, SPR_NOACCESS,
1603 &spr_read_generic, &spr_write_generic,
1604 0x00000000);
1605
1606 spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0",
1607 SPR_NOACCESS, SPR_NOACCESS,
1608 &spr_read_generic, &spr_write_generic,
1609 0x00000000);
1610
1611 spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1",
1612 SPR_NOACCESS, SPR_NOACCESS,
1613 &spr_read_generic, &spr_write_generic,
1614 0x00000000);
1615 }
1616
1617 /*
1618 * AMR => SPR 29 (Power 2.04)
1619 * CTRL => SPR 136 (Power 2.04)
1620 * CTRL => SPR 152 (Power 2.04)
1621 * SCOMC => SPR 276 (64 bits ?)
1622 * SCOMD => SPR 277 (64 bits ?)
1623 * TBU40 => SPR 286 (Power 2.04 hypv)
1624 * HSPRG0 => SPR 304 (Power 2.04 hypv)
1625 * HSPRG1 => SPR 305 (Power 2.04 hypv)
1626 * HDSISR => SPR 306 (Power 2.04 hypv)
1627 * HDAR => SPR 307 (Power 2.04 hypv)
1628 * PURR => SPR 309 (Power 2.04 hypv)
1629 * HDEC => SPR 310 (Power 2.04 hypv)
1630 * HIOR => SPR 311 (hypv)
1631 * RMOR => SPR 312 (970)
1632 * HRMOR => SPR 313 (Power 2.04 hypv)
1633 * HSRR0 => SPR 314 (Power 2.04 hypv)
1634 * HSRR1 => SPR 315 (Power 2.04 hypv)
1635 * LPIDR => SPR 317 (970)
1636 * HEIR => SPR 339 (Power 2.05 hypv) (64-bit reg from 3.1)
1637 * EPR => SPR 702 (Power 2.04 emb)
1638 * perf => 768-783 (Power 2.04)
1639 * perf => 784-799 (Power 2.04)
1640 * PPR => SPR 896 (Power 2.04)
1641 * DABRX => 1015 (Power 2.04 hypv)
1642 * FPECR => SPR 1022 (?)
1643 * ... and more (thermal management, performance counters, ...)
1644 */
1645
1646 static void register_ppe42_sprs(CPUPPCState *env)
1647 {
1648 spr_register(env, SPR_PPE42_EDR, "EDR",
1649 SPR_NOACCESS, SPR_NOACCESS,
1650 &spr_read_generic, &spr_write_generic,
1651 0x00000000);
1652 spr_register(env, SPR_PPE42_ISR, "ISR",
1653 SPR_NOACCESS, SPR_NOACCESS,
1654 &spr_read_generic, &spr_write_generic,
1655 0x00000000);
1656 spr_register(env, SPR_PPE42_IVPR, "IVPR",
1657 SPR_NOACCESS, SPR_NOACCESS,
1658 &spr_read_generic, SPR_NOACCESS,
1659 0xfff80000);
1660 spr_register(env, SPR_PPE42_PIR, "PIR",
1661 SPR_NOACCESS, SPR_NOACCESS,
1662 &spr_read_generic, &spr_write_pir,
1663 0x00000000);
1664 spr_register(env, SPR_PPE42_DBCR, "DBCR",
1665 SPR_NOACCESS, SPR_NOACCESS,
1666 &spr_read_generic, &spr_write_40x_dbcr0,
1667 0x00000000);
1668 spr_register(env, SPR_PPE42_DACR, "DACR",
1669 SPR_NOACCESS, SPR_NOACCESS,
1670 &spr_read_generic, &spr_write_generic,
1671 0x00000000);
1672 /* Timer */
1673 spr_register(env, SPR_DECR, "DECR",
1674 SPR_NOACCESS, SPR_NOACCESS,
1675 &spr_read_decr, &spr_write_decr,
1676 0x00000000);
1677 spr_register(env, SPR_PPE42_TSR, "TSR",
1678 SPR_NOACCESS, SPR_NOACCESS,
1679 &spr_read_generic, &spr_write_booke_tsr,
1680 0x00000000);
1681 spr_register(env, SPR_BOOKE_TCR, "TCR",
1682 SPR_NOACCESS, SPR_NOACCESS,
1683 &spr_read_generic, &spr_write_booke_tcr,
1684 0x00000000);
1685 }
1686
1687 /*****************************************************************************/
1688 /* Exception vectors models */
1689 static void init_excp_4xx(CPUPPCState *env)
1690 {
1691 #if !defined(CONFIG_USER_ONLY)
1692 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
1693 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1694 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
1695 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
1696 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1697 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1698 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1699 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1700 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
1701 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
1702 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
1703 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100;
1704 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200;
1705 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
1706 env->ivor_mask = 0x0000FFF0UL;
1707 env->ivpr_mask = 0xFFFF0000UL;
1708 /* Hardware reset vector */
1709 env->hreset_vector = 0xFFFFFFFCUL;
1710 #endif
1711 }
1712
1713 static void init_excp_ppe42(CPUPPCState *env)
1714 {
1715 #if !defined(CONFIG_USER_ONLY)
1716 /* Machine Check vector changed after version 0 */
1717 if (((env->spr[SPR_PVR] & 0xf00000ul) >> 20) == 0) {
1718 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
1719 } else {
1720 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000020;
1721 }
1722 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000040;
1723 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000060;
1724 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000080;
1725 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x000000A0;
1726 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x000000C0;
1727 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x000000E0;
1728 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000100;
1729 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000120;
1730 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000140;
1731 env->ivpr_mask = 0xFFFFFE00UL;
1732 /* Hardware reset vector */
1733 env->hreset_vector = 0x00000040UL;
1734 #endif
1735 }
1736
1737 static void init_excp_MPC5xx(CPUPPCState *env)
1738 {
1739 #if !defined(CONFIG_USER_ONLY)
1740 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
1741 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1742 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1743 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1744 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1745 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
1746 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
1747 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1748 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
1749 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
1750 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
1751 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
1752 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
1753 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
1754 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
1755 env->ivor_mask = 0x0000FFF0UL;
1756 env->ivpr_mask = 0xFFFF0000UL;
1757 /* Hardware reset vector */
1758 env->hreset_vector = 0x00000100UL;
1759 #endif
1760 }
1761
1762 static void init_excp_MPC8xx(CPUPPCState *env)
1763 {
1764 #if !defined(CONFIG_USER_ONLY)
1765 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
1766 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1767 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
1768 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
1769 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1770 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1771 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1772 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
1773 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
1774 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1775 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
1776 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
1777 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
1778 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001100;
1779 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001200;
1780 env->excp_vectors[POWERPC_EXCP_ITLBE] = 0x00001300;
1781 env->excp_vectors[POWERPC_EXCP_DTLBE] = 0x00001400;
1782 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
1783 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
1784 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
1785 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
1786 env->ivor_mask = 0x0000FFF0UL;
1787 env->ivpr_mask = 0xFFFF0000UL;
1788 /* Hardware reset vector */
1789 env->hreset_vector = 0x00000100UL;
1790 #endif
1791 }
1792
1793 static void init_excp_G2(CPUPPCState *env)
1794 {
1795 #if !defined(CONFIG_USER_ONLY)
1796 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
1797 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1798 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
1799 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
1800 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1801 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1802 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1803 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
1804 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
1805 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00;
1806 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1807 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
1808 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
1809 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
1810 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
1811 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
1812 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
1813 /* Hardware reset vector */
1814 env->hreset_vector = 0x00000100UL;
1815 #endif
1816 }
1817
1818 static void init_excp_e500(CPUPPCState *env, target_ulong ivpr_mask)
1819 {
1820 #if !defined(CONFIG_USER_ONLY)
1821 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC;
1822 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
1823 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
1824 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
1825 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
1826 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
1827 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
1828 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
1829 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
1830 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
1831 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
1832 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
1833 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
1834 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
1835 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
1836 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
1837 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
1838 /*
1839 * These two are the same IVOR as POWERPC_EXCP_VPU and
1840 * POWERPC_EXCP_VPUA. We deal with that when dispatching at
1841 * powerpc_excp().
1842 */
1843 env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000;
1844 env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000;
1845
1846 env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000;
1847 env->ivor_mask = 0x0000FFF7UL;
1848 env->ivpr_mask = ivpr_mask;
1849 /* Hardware reset vector */
1850 env->hreset_vector = 0xFFFFFFFCUL;
1851 #endif
1852 }
1853
1854 static void init_excp_BookE(CPUPPCState *env)
1855 {
1856 #if !defined(CONFIG_USER_ONLY)
1857 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
1858 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
1859 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
1860 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
1861 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
1862 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
1863 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
1864 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
1865 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
1866 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
1867 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
1868 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
1869 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
1870 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
1871 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
1872 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
1873 env->ivor_mask = 0x0000FFF0UL;
1874 env->ivpr_mask = 0xFFFF0000UL;
1875 /* Hardware reset vector */
1876 env->hreset_vector = 0xFFFFFFFCUL;
1877 #endif
1878 }
1879
1880 static void init_excp_603(CPUPPCState *env)
1881 {
1882 #if !defined(CONFIG_USER_ONLY)
1883 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
1884 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1885 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
1886 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
1887 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1888 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1889 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1890 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
1891 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
1892 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1893 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
1894 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
1895 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
1896 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
1897 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
1898 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
1899 /* Hardware reset vector */
1900 env->hreset_vector = 0x00000100UL;
1901 #endif
1902 }
1903
1904 static void init_excp_604(CPUPPCState *env)
1905 {
1906 #if !defined(CONFIG_USER_ONLY)
1907 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
1908 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1909 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
1910 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
1911 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1912 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1913 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1914 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
1915 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
1916 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1917 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
1918 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
1919 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
1920 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
1921 /* Hardware reset vector */
1922 env->hreset_vector = 0x00000100UL;
1923 #endif
1924 }
1925
1926 static void init_excp_7x0(CPUPPCState *env)
1927 {
1928 #if !defined(CONFIG_USER_ONLY)
1929 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
1930 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1931 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
1932 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
1933 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1934 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1935 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1936 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
1937 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
1938 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1939 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
1940 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
1941 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
1942 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
1943 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
1944 /* Hardware reset vector */
1945 env->hreset_vector = 0x00000100UL;
1946 #endif
1947 }
1948
1949 static void init_excp_750cl(CPUPPCState *env)
1950 {
1951 #if !defined(CONFIG_USER_ONLY)
1952 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
1953 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1954 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
1955 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
1956 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1957 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1958 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1959 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
1960 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
1961 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1962 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
1963 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
1964 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
1965 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
1966 /* Hardware reset vector */
1967 env->hreset_vector = 0x00000100UL;
1968 #endif
1969 }
1970
1971 static void init_excp_750cx(CPUPPCState *env)
1972 {
1973 #if !defined(CONFIG_USER_ONLY)
1974 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
1975 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1976 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
1977 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
1978 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1979 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1980 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1981 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
1982 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
1983 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1984 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
1985 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
1986 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
1987 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
1988 /* Hardware reset vector */
1989 env->hreset_vector = 0x00000100UL;
1990 #endif
1991 }
1992
1993 /* XXX: Check if this is correct */
1994 static void init_excp_7x5(CPUPPCState *env)
1995 {
1996 #if !defined(CONFIG_USER_ONLY)
1997 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
1998 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1999 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2000 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2001 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2002 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2003 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2004 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2005 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2006 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2007 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2008 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2009 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2010 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2011 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2012 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2013 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2014 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
2015 /* Hardware reset vector */
2016 env->hreset_vector = 0x00000100UL;
2017 #endif
2018 }
2019
2020 static void init_excp_7400(CPUPPCState *env)
2021 {
2022 #if !defined(CONFIG_USER_ONLY)
2023 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2024 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2025 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2026 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2027 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2028 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2029 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2030 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2031 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2032 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2033 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2034 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2035 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
2036 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2037 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2038 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
2039 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
2040 /* Hardware reset vector */
2041 env->hreset_vector = 0x00000100UL;
2042 #endif
2043 }
2044
2045 static void init_excp_7450(CPUPPCState *env)
2046 {
2047 #if !defined(CONFIG_USER_ONLY)
2048 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2049 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2050 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2051 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2052 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2053 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2054 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2055 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2056 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2057 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2058 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2059 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2060 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
2061 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2062 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2063 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
2064 /* Hardware reset vector */
2065 env->hreset_vector = 0x00000100UL;
2066 #endif
2067 }
2068
2069 #if defined(TARGET_PPC64)
2070 static void init_excp_970(CPUPPCState *env)
2071 {
2072 #if !defined(CONFIG_USER_ONLY)
2073 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2074 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2075 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2076 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
2077 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2078 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
2079 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2080 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2081 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2082 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2083 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2084 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
2085 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2086 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2087 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2088 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
2089 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2090 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
2091 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
2092 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
2093 /* Hardware reset vector */
2094 env->hreset_vector = 0x0000000000000100ULL;
2095 #endif
2096 }
2097
2098 static void init_excp_POWER7(CPUPPCState *env)
2099 {
2100 #if !defined(CONFIG_USER_ONLY)
2101 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2102 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2103 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2104 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
2105 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2106 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
2107 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2108 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2109 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2110 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2111 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2112 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
2113 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2114 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2115 env->excp_vectors[POWERPC_EXCP_HDSI] = 0x00000E00;
2116 env->excp_vectors[POWERPC_EXCP_HISI] = 0x00000E20;
2117 env->excp_vectors[POWERPC_EXCP_HV_EMU] = 0x00000E40;
2118 env->excp_vectors[POWERPC_EXCP_HV_MAINT] = 0x00000E60;
2119 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2120 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
2121 env->excp_vectors[POWERPC_EXCP_VSXU] = 0x00000F40;
2122 /* Hardware reset vector */
2123 env->hreset_vector = 0x0000000000000100ULL;
2124 #endif
2125 }
2126
2127 static void init_excp_POWER8(CPUPPCState *env)
2128 {
2129 init_excp_POWER7(env);
2130
2131 #if !defined(CONFIG_USER_ONLY)
2132 env->excp_vectors[POWERPC_EXCP_SDOOR] = 0x00000A00;
2133 env->excp_vectors[POWERPC_EXCP_FU] = 0x00000F60;
2134 env->excp_vectors[POWERPC_EXCP_HV_FU] = 0x00000F80;
2135 env->excp_vectors[POWERPC_EXCP_SDOOR_HV] = 0x00000E80;
2136
2137 /* Userland exceptions without vector value in PowerISA v3.1 */
2138 env->excp_vectors[POWERPC_EXCP_PERFM_EBB] = 0x0;
2139 env->excp_vectors[POWERPC_EXCP_EXTERNAL_EBB] = 0x0;
2140 #endif
2141 }
2142
2143 static void init_excp_POWER9(CPUPPCState *env)
2144 {
2145 init_excp_POWER8(env);
2146
2147 #if !defined(CONFIG_USER_ONLY)
2148 env->excp_vectors[POWERPC_EXCP_HVIRT] = 0x00000EA0;
2149 env->excp_vectors[POWERPC_EXCP_SYSCALL_VECTORED] = 0x00017000;
2150 #endif
2151 }
2152
2153 static void init_excp_POWER10(CPUPPCState *env)
2154 {
2155 init_excp_POWER9(env);
2156 }
2157
2158 #endif
2159
2160 static int check_pow_hid0(CPUPPCState *env)
2161 {
2162 if (env->spr[SPR_HID0] & 0x00E00000) {
2163 return 1;
2164 }
2165
2166 return 0;
2167 }
2168
2169 static int check_pow_hid0_74xx(CPUPPCState *env)
2170 {
2171 if (env->spr[SPR_HID0] & 0x00600000) {
2172 return 1;
2173 }
2174
2175 return 0;
2176 }
2177
2178 #if defined(TARGET_PPC64)
2179 static int check_attn_hid0(CPUPPCState *env)
2180 {
2181 if (env->spr[SPR_HID0] & HID0_ENABLE_ATTN) {
2182 return 1;
2183 }
2184
2185 return 0;
2186 }
2187
2188 static int check_attn_hid0_power9(CPUPPCState *env)
2189 {
2190 if (env->spr[SPR_HID0] & HID0_POWER9_ENABLE_ATTN) {
2191 return 1;
2192 }
2193
2194 return 0;
2195 }
2196 #endif
2197
2198 static void init_tlbs_emb(CPUPPCState *env)
2199 {
2200 #ifndef CONFIG_USER_ONLY
2201 env->nb_tlb = 64;
2202 env->nb_ways = 1;
2203 env->tlb_type = TLB_EMB;
2204 #endif
2205 }
2206
2207 static void init_proc_405(CPUPPCState *env)
2208 {
2209 register_40x_sprs(env);
2210 register_405_sprs(env);
2211 register_usprgh_sprs(env);
2212
2213 init_tlbs_emb(env);
2214 init_excp_4xx(env);
2215 env->dcache_line_size = 32;
2216 env->icache_line_size = 32;
2217 /* Allocate hardware IRQ controller */
2218 ppc40x_irq_init(env_archcpu(env));
2219
2220 SET_FIT_PERIOD(8, 12, 16, 20);
2221 SET_WDT_PERIOD(16, 20, 24, 28);
2222 }
2223
2224 POWERPC_FAMILY(405)(ObjectClass *oc, const void *data)
2225 {
2226 DeviceClass *dc = DEVICE_CLASS(oc);
2227 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2228
2229 dc->desc = "PowerPC 405";
2230 pcc->init_proc = init_proc_405;
2231 pcc->check_pow = check_pow_nocheck;
2232 pcc->check_attn = check_attn_none;
2233 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
2234 PPC_DCR | PPC_WRTEE |
2235 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
2236 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
2237 PPC_MEM_SYNC | PPC_MEM_EIEIO |
2238 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
2239 PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP;
2240 pcc->msr_mask = (1ull << MSR_WE) |
2241 (1ull << MSR_CE) |
2242 (1ull << MSR_EE) |
2243 (1ull << MSR_PR) |
2244 (1ull << MSR_FP) |
2245 (1ull << MSR_ME) |
2246 (1ull << MSR_DWE) |
2247 (1ull << MSR_DE) |
2248 (1ull << MSR_IR) |
2249 (1ull << MSR_DR);
2250 pcc->mmu_model = POWERPC_MMU_SOFT_4xx;
2251 pcc->excp_model = POWERPC_EXCP_40x;
2252 pcc->bus_model = PPC_FLAGS_INPUT_405;
2253 pcc->bfd_mach = bfd_mach_ppc_403;
2254 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
2255 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
2256 }
2257
2258 static void init_proc_ppe42(CPUPPCState *env)
2259 {
2260 register_ppe42_sprs(env);
2261
2262 init_excp_ppe42(env);
2263 env->dcache_line_size = 32;
2264 env->icache_line_size = 32;
2265 /* Allocate hardware IRQ controller */
2266 ppc40x_irq_init(env_archcpu(env));
2267
2268 SET_FIT_PERIOD(8, 12, 16, 20);
2269 SET_WDT_PERIOD(16, 20, 24, 28);
2270 }
2271
2272 static void ppe42_class_common_init(PowerPCCPUClass *pcc)
2273 {
2274 pcc->init_proc = init_proc_ppe42;
2275 pcc->check_pow = check_pow_nocheck;
2276 pcc->check_attn = check_attn_none;
2277 pcc->insns_flags = PPC_INSNS_BASE |
2278 PPC_WRTEE |
2279 PPC_CACHE |
2280 PPC_CACHE_DCBZ |
2281 PPC_MEM_SYNC;
2282 pcc->msr_mask = R_MSR_SEM_MASK |
2283 (1ull << MSR_IS0) |
2284 R_MSR_SIBRC_MASK |
2285 (1ull << MSR_LP) |
2286 (1ull << MSR_WE) |
2287 (1ull << MSR_IS1) |
2288 (1ull << MSR_UIE) |
2289 (1ull << MSR_EE) |
2290 (1ull << MSR_ME) |
2291 (1ull << MSR_IS2) |
2292 (1ull << MSR_IS3) |
2293 (1ull << MSR_IPE) |
2294 R_MSR_SIBRCA_MASK;
2295 pcc->mmu_model = POWERPC_MMU_REAL;
2296 pcc->excp_model = POWERPC_EXCP_PPE42;
2297 pcc->bus_model = PPC_FLAGS_INPUT_PPE42;
2298 pcc->bfd_mach = bfd_mach_ppc_403;
2299 pcc->flags = POWERPC_FLAG_PPE42 | POWERPC_FLAG_BUS_CLK;
2300 }
2301
2302 POWERPC_FAMILY(ppe42)(ObjectClass *oc, const void *data)
2303 {
2304 DeviceClass *dc = DEVICE_CLASS(oc);
2305 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2306
2307 dc->desc = "PPE 42";
2308 pcc->insns_flags2 = PPC2_PPE42;
2309 ppe42_class_common_init(pcc);
2310 }
2311
2312 POWERPC_FAMILY(ppe42x)(ObjectClass *oc, const void *data)
2313 {
2314 DeviceClass *dc = DEVICE_CLASS(oc);
2315 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2316
2317 dc->desc = "PPE 42X";
2318 pcc->insns_flags2 = PPC2_PPE42 | PPC2_PPE42X;
2319 ppe42_class_common_init(pcc);
2320 }
2321
2322 POWERPC_FAMILY(ppe42xm)(ObjectClass *oc, const void *data)
2323 {
2324 DeviceClass *dc = DEVICE_CLASS(oc);
2325 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2326
2327 dc->desc = "PPE 42XM";
2328 pcc->insns_flags2 = PPC2_PPE42 | PPC2_PPE42X | PPC2_PPE42XM;
2329 ppe42_class_common_init(pcc);
2330 }
2331
2332 static void init_proc_440EP(CPUPPCState *env)
2333 {
2334 register_BookE_sprs(env, 0x000000000000FFFFULL);
2335 register_440_sprs(env);
2336 register_usprgh_sprs(env);
2337
2338 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
2339 SPR_NOACCESS, SPR_NOACCESS,
2340 &spr_read_generic, &spr_write_generic,
2341 0x00000000);
2342 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
2343 SPR_NOACCESS, SPR_NOACCESS,
2344 &spr_read_generic, &spr_write_generic,
2345 0x00000000);
2346 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
2347 SPR_NOACCESS, SPR_NOACCESS,
2348 &spr_read_generic, &spr_write_generic,
2349 0x00000000);
2350
2351 spr_register(env, SPR_440_CCR1, "CCR1",
2352 SPR_NOACCESS, SPR_NOACCESS,
2353 &spr_read_generic, &spr_write_generic,
2354 0x00000000);
2355
2356 init_tlbs_emb(env);
2357 init_excp_BookE(env);
2358 env->dcache_line_size = 32;
2359 env->icache_line_size = 32;
2360 ppc40x_irq_init(env_archcpu(env));
2361
2362 SET_FIT_PERIOD(12, 16, 20, 24);
2363 SET_WDT_PERIOD(20, 24, 28, 32);
2364 }
2365
2366 POWERPC_FAMILY(440EP)(ObjectClass *oc, const void *data)
2367 {
2368 DeviceClass *dc = DEVICE_CLASS(oc);
2369 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2370
2371 dc->desc = "PowerPC 440 EP";
2372 pcc->init_proc = init_proc_440EP;
2373 pcc->check_pow = check_pow_nocheck;
2374 pcc->check_attn = check_attn_none;
2375 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2376 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |
2377 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
2378 PPC_FLOAT_STFIWX |
2379 PPC_DCR | PPC_WRTEE | PPC_RFMCI |
2380 PPC_CACHE | PPC_CACHE_ICBI |
2381 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
2382 PPC_MEM_TLBSYNC | PPC_MFTB |
2383 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
2384 PPC_440_SPEC;
2385 pcc->msr_mask = (1ull << MSR_POW) |
2386 (1ull << MSR_CE) |
2387 (1ull << MSR_EE) |
2388 (1ull << MSR_PR) |
2389 (1ull << MSR_FP) |
2390 (1ull << MSR_ME) |
2391 (1ull << MSR_FE0) |
2392 (1ull << MSR_DWE) |
2393 (1ull << MSR_DE) |
2394 (1ull << MSR_FE1) |
2395 (1ull << MSR_IR) |
2396 (1ull << MSR_DR);
2397 pcc->mmu_model = POWERPC_MMU_BOOKE;
2398 pcc->excp_model = POWERPC_EXCP_BOOKE;
2399 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
2400 pcc->bfd_mach = bfd_mach_ppc_403;
2401 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
2402 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
2403 }
2404
2405 POWERPC_FAMILY(460EX)(ObjectClass *oc, const void *data)
2406 {
2407 DeviceClass *dc = DEVICE_CLASS(oc);
2408 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2409
2410 dc->desc = "PowerPC 460 EX";
2411 pcc->init_proc = init_proc_440EP;
2412 pcc->check_pow = check_pow_nocheck;
2413 pcc->check_attn = check_attn_none;
2414 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2415 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |
2416 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
2417 PPC_FLOAT_STFIWX |
2418 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_RFMCI |
2419 PPC_CACHE | PPC_CACHE_ICBI |
2420 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
2421 PPC_MEM_TLBSYNC | PPC_MFTB |
2422 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
2423 PPC_440_SPEC;
2424 pcc->msr_mask = (1ull << MSR_POW) |
2425 (1ull << MSR_CE) |
2426 (1ull << MSR_EE) |
2427 (1ull << MSR_PR) |
2428 (1ull << MSR_FP) |
2429 (1ull << MSR_ME) |
2430 (1ull << MSR_FE0) |
2431 (1ull << MSR_DWE) |
2432 (1ull << MSR_DE) |
2433 (1ull << MSR_FE1) |
2434 (1ull << MSR_IR) |
2435 (1ull << MSR_DR);
2436 pcc->mmu_model = POWERPC_MMU_BOOKE;
2437 pcc->excp_model = POWERPC_EXCP_BOOKE;
2438 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
2439 pcc->bfd_mach = bfd_mach_ppc_403;
2440 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
2441 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
2442 }
2443
2444 static void init_proc_440GP(CPUPPCState *env)
2445 {
2446 register_BookE_sprs(env, 0x000000000000FFFFULL);
2447 register_440_sprs(env);
2448 register_usprgh_sprs(env);
2449
2450 init_tlbs_emb(env);
2451 init_excp_BookE(env);
2452 env->dcache_line_size = 32;
2453 env->icache_line_size = 32;
2454 /* XXX: TODO: allocate internal IRQ controller */
2455
2456 SET_FIT_PERIOD(12, 16, 20, 24);
2457 SET_WDT_PERIOD(20, 24, 28, 32);
2458 }
2459
2460 POWERPC_FAMILY(440GP)(ObjectClass *oc, const void *data)
2461 {
2462 DeviceClass *dc = DEVICE_CLASS(oc);
2463 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2464
2465 dc->desc = "PowerPC 440 GP";
2466 pcc->init_proc = init_proc_440GP;
2467 pcc->check_pow = check_pow_nocheck;
2468 pcc->check_attn = check_attn_none;
2469 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2470 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI |
2471 PPC_CACHE | PPC_CACHE_ICBI |
2472 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
2473 PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_MFTB |
2474 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
2475 PPC_440_SPEC;
2476 pcc->msr_mask = (1ull << MSR_POW) |
2477 (1ull << MSR_CE) |
2478 (1ull << MSR_EE) |
2479 (1ull << MSR_PR) |
2480 (1ull << MSR_FP) |
2481 (1ull << MSR_ME) |
2482 (1ull << MSR_FE0) |
2483 (1ull << MSR_DWE) |
2484 (1ull << MSR_DE) |
2485 (1ull << MSR_FE1) |
2486 (1ull << MSR_IR) |
2487 (1ull << MSR_DR);
2488 pcc->mmu_model = POWERPC_MMU_BOOKE;
2489 pcc->excp_model = POWERPC_EXCP_BOOKE;
2490 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
2491 pcc->bfd_mach = bfd_mach_ppc_403;
2492 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
2493 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
2494 }
2495
2496 static void init_proc_440x5(CPUPPCState *env)
2497 {
2498 register_BookE_sprs(env, 0x000000000000FFFFULL);
2499 register_440_sprs(env);
2500 register_usprgh_sprs(env);
2501
2502 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
2503 SPR_NOACCESS, SPR_NOACCESS,
2504 &spr_read_generic, &spr_write_generic,
2505 0x00000000);
2506 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
2507 SPR_NOACCESS, SPR_NOACCESS,
2508 &spr_read_generic, &spr_write_generic,
2509 0x00000000);
2510 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
2511 SPR_NOACCESS, SPR_NOACCESS,
2512 &spr_read_generic, &spr_write_generic,
2513 0x00000000);
2514
2515 spr_register(env, SPR_440_CCR1, "CCR1",
2516 SPR_NOACCESS, SPR_NOACCESS,
2517 &spr_read_generic, &spr_write_generic,
2518 0x00000000);
2519
2520 init_tlbs_emb(env);
2521 init_excp_BookE(env);
2522 env->dcache_line_size = 32;
2523 env->icache_line_size = 32;
2524 ppc40x_irq_init(env_archcpu(env));
2525
2526 SET_FIT_PERIOD(12, 16, 20, 24);
2527 SET_WDT_PERIOD(20, 24, 28, 32);
2528 }
2529
2530 POWERPC_FAMILY(440x5)(ObjectClass *oc, const void *data)
2531 {
2532 DeviceClass *dc = DEVICE_CLASS(oc);
2533 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2534
2535 dc->desc = "PowerPC 440x5";
2536 pcc->init_proc = init_proc_440x5;
2537 pcc->check_pow = check_pow_nocheck;
2538 pcc->check_attn = check_attn_none;
2539 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2540 PPC_DCR | PPC_WRTEE | PPC_RFMCI |
2541 PPC_CACHE | PPC_CACHE_ICBI |
2542 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
2543 PPC_MEM_TLBSYNC | PPC_MFTB |
2544 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
2545 PPC_440_SPEC;
2546 pcc->msr_mask = (1ull << MSR_POW) |
2547 (1ull << MSR_CE) |
2548 (1ull << MSR_EE) |
2549 (1ull << MSR_PR) |
2550 (1ull << MSR_FP) |
2551 (1ull << MSR_ME) |
2552 (1ull << MSR_FE0) |
2553 (1ull << MSR_DWE) |
2554 (1ull << MSR_DE) |
2555 (1ull << MSR_FE1) |
2556 (1ull << MSR_IR) |
2557 (1ull << MSR_DR);
2558 pcc->mmu_model = POWERPC_MMU_BOOKE;
2559 pcc->excp_model = POWERPC_EXCP_BOOKE;
2560 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
2561 pcc->bfd_mach = bfd_mach_ppc_403;
2562 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
2563 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
2564 }
2565
2566 POWERPC_FAMILY(440x5wDFPU)(ObjectClass *oc, const void *data)
2567 {
2568 DeviceClass *dc = DEVICE_CLASS(oc);
2569 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2570
2571 dc->desc = "PowerPC 440x5 with double precision FPU";
2572 pcc->init_proc = init_proc_440x5;
2573 pcc->check_pow = check_pow_nocheck;
2574 pcc->check_attn = check_attn_none;
2575 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2576 PPC_FLOAT | PPC_FLOAT_FSQRT |
2577 PPC_FLOAT_STFIWX |
2578 PPC_DCR | PPC_WRTEE | PPC_RFMCI |
2579 PPC_CACHE | PPC_CACHE_ICBI |
2580 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
2581 PPC_MEM_TLBSYNC | PPC_MFTB |
2582 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
2583 PPC_440_SPEC;
2584 pcc->insns_flags2 = PPC2_FP_CVT_S64;
2585 pcc->msr_mask = (1ull << MSR_POW) |
2586 (1ull << MSR_CE) |
2587 (1ull << MSR_EE) |
2588 (1ull << MSR_PR) |
2589 (1ull << MSR_FP) |
2590 (1ull << MSR_ME) |
2591 (1ull << MSR_FE0) |
2592 (1ull << MSR_DWE) |
2593 (1ull << MSR_DE) |
2594 (1ull << MSR_FE1) |
2595 (1ull << MSR_IR) |
2596 (1ull << MSR_DR);
2597 pcc->mmu_model = POWERPC_MMU_BOOKE;
2598 pcc->excp_model = POWERPC_EXCP_BOOKE;
2599 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
2600 pcc->bfd_mach = bfd_mach_ppc_403;
2601 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
2602 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
2603 }
2604
2605 static void init_proc_MPC5xx(CPUPPCState *env)
2606 {
2607 register_5xx_8xx_sprs(env);
2608 register_5xx_sprs(env);
2609 init_excp_MPC5xx(env);
2610 env->dcache_line_size = 32;
2611 env->icache_line_size = 32;
2612 /* XXX: TODO: allocate internal IRQ controller */
2613 }
2614
2615 POWERPC_FAMILY(MPC5xx)(ObjectClass *oc, const void *data)
2616 {
2617 DeviceClass *dc = DEVICE_CLASS(oc);
2618 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2619
2620 dc->desc = "Freescale 5xx cores (aka RCPU)";
2621 pcc->init_proc = init_proc_MPC5xx;
2622 pcc->check_pow = check_pow_none;
2623 pcc->check_attn = check_attn_none;
2624 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2625 PPC_MEM_EIEIO | PPC_MEM_SYNC |
2626 PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX |
2627 PPC_MFTB;
2628 pcc->msr_mask = (1ull << MSR_ILE) |
2629 (1ull << MSR_EE) |
2630 (1ull << MSR_PR) |
2631 (1ull << MSR_FP) |
2632 (1ull << MSR_ME) |
2633 (1ull << MSR_FE0) |
2634 (1ull << MSR_SE) |
2635 (1ull << MSR_DE) |
2636 (1ull << MSR_FE1) |
2637 (1ull << MSR_EP) |
2638 (1ull << MSR_RI) |
2639 (1ull << MSR_LE);
2640 pcc->mmu_model = POWERPC_MMU_REAL;
2641 pcc->excp_model = POWERPC_EXCP_6xx;
2642 pcc->bus_model = PPC_FLAGS_INPUT_RCPU;
2643 pcc->bfd_mach = bfd_mach_ppc_505;
2644 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
2645 POWERPC_FLAG_BUS_CLK;
2646 }
2647
2648 static void init_proc_MPC8xx(CPUPPCState *env)
2649 {
2650 register_5xx_8xx_sprs(env);
2651 register_8xx_sprs(env);
2652 init_excp_MPC8xx(env);
2653 env->dcache_line_size = 32;
2654 env->icache_line_size = 32;
2655 /* XXX: TODO: allocate internal IRQ controller */
2656 }
2657
2658 POWERPC_FAMILY(MPC8xx)(ObjectClass *oc, const void *data)
2659 {
2660 DeviceClass *dc = DEVICE_CLASS(oc);
2661 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2662
2663 dc->desc = "Freescale 8xx cores (aka PowerQUICC)";
2664 pcc->init_proc = init_proc_MPC8xx;
2665 pcc->check_pow = check_pow_none;
2666 pcc->check_attn = check_attn_none;
2667 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2668 PPC_MEM_EIEIO | PPC_MEM_SYNC |
2669 PPC_CACHE_ICBI | PPC_MFTB;
2670 pcc->msr_mask = (1ull << MSR_ILE) |
2671 (1ull << MSR_EE) |
2672 (1ull << MSR_PR) |
2673 (1ull << MSR_FP) |
2674 (1ull << MSR_ME) |
2675 (1ull << MSR_SE) |
2676 (1ull << MSR_DE) |
2677 (1ull << MSR_EP) |
2678 (1ull << MSR_IR) |
2679 (1ull << MSR_DR) |
2680 (1ull << MSR_RI) |
2681 (1ull << MSR_LE);
2682 pcc->mmu_model = POWERPC_MMU_MPC8xx;
2683 pcc->excp_model = POWERPC_EXCP_6xx;
2684 pcc->bus_model = PPC_FLAGS_INPUT_RCPU;
2685 pcc->bfd_mach = bfd_mach_ppc_860;
2686 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
2687 POWERPC_FLAG_BUS_CLK;
2688 }
2689
2690 /* Freescale 82xx cores (aka PowerQUICC-II) */
2691
2692 static void init_proc_G2(CPUPPCState *env)
2693 {
2694 register_non_embedded_sprs(env);
2695 register_sdr1_sprs(env);
2696 register_G2_sprs(env);
2697
2698 /* Memory management */
2699 register_low_BATs(env);
2700 register_high_BATs(env);
2701 register_6xx_7xx_soft_tlb(env, 64, 2);
2702 init_excp_G2(env);
2703 env->dcache_line_size = 32;
2704 env->icache_line_size = 32;
2705 /* Allocate hardware IRQ controller */
2706 ppc6xx_irq_init(env_archcpu(env));
2707 }
2708
2709 POWERPC_FAMILY(G2)(ObjectClass *oc, const void *data)
2710 {
2711 DeviceClass *dc = DEVICE_CLASS(oc);
2712 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2713
2714 dc->desc = "PowerPC G2";
2715 pcc->init_proc = init_proc_G2;
2716 pcc->check_pow = check_pow_hid0;
2717 pcc->check_attn = check_attn_none;
2718 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
2719 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
2720 PPC_FLOAT_STFIWX |
2721 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
2722 PPC_MEM_SYNC | PPC_MEM_EIEIO |
2723 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
2724 PPC_SEGMENT | PPC_EXTERN;
2725 pcc->msr_mask = (1ull << MSR_POW) |
2726 (1ull << MSR_TGPR) |
2727 (1ull << MSR_EE) |
2728 (1ull << MSR_PR) |
2729 (1ull << MSR_FP) |
2730 (1ull << MSR_ME) |
2731 (1ull << MSR_FE0) |
2732 (1ull << MSR_SE) |
2733 (1ull << MSR_DE) |
2734 (1ull << MSR_FE1) |
2735 (1ull << MSR_AL) |
2736 (1ull << MSR_EP) |
2737 (1ull << MSR_IR) |
2738 (1ull << MSR_DR) |
2739 (1ull << MSR_RI);
2740 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
2741 pcc->excp_model = POWERPC_EXCP_6xx;
2742 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
2743 pcc->bfd_mach = bfd_mach_ppc_ec603e;
2744 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
2745 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
2746 }
2747
2748 POWERPC_FAMILY(G2LE)(ObjectClass *oc, const void *data)
2749 {
2750 DeviceClass *dc = DEVICE_CLASS(oc);
2751 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2752
2753 dc->desc = "PowerPC G2LE";
2754 pcc->init_proc = init_proc_G2;
2755 pcc->check_pow = check_pow_hid0;
2756 pcc->check_attn = check_attn_none;
2757 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
2758 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
2759 PPC_FLOAT_STFIWX |
2760 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
2761 PPC_MEM_SYNC | PPC_MEM_EIEIO |
2762 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
2763 PPC_SEGMENT | PPC_EXTERN;
2764 pcc->msr_mask = (1ull << MSR_POW) |
2765 (1ull << MSR_TGPR) |
2766 (1ull << MSR_ILE) |
2767 (1ull << MSR_EE) |
2768 (1ull << MSR_PR) |
2769 (1ull << MSR_FP) |
2770 (1ull << MSR_ME) |
2771 (1ull << MSR_FE0) |
2772 (1ull << MSR_SE) |
2773 (1ull << MSR_DE) |
2774 (1ull << MSR_FE1) |
2775 (1ull << MSR_AL) |
2776 (1ull << MSR_EP) |
2777 (1ull << MSR_IR) |
2778 (1ull << MSR_DR) |
2779 (1ull << MSR_RI) |
2780 (1ull << MSR_LE);
2781 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
2782 pcc->excp_model = POWERPC_EXCP_6xx;
2783 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
2784 pcc->bfd_mach = bfd_mach_ppc_ec603e;
2785 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
2786 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
2787 }
2788
2789 enum fsl_e500_version {
2790 fsl_e500v1,
2791 fsl_e500v2,
2792 fsl_e500mc,
2793 fsl_e5500,
2794 fsl_e6500,
2795 };
2796
2797 static void init_proc_e500(CPUPPCState *env, int version)
2798 {
2799 uint32_t tlbncfg[2];
2800 uint64_t ivor_mask;
2801 uint64_t ivpr_mask = 0xFFFF0000ULL;
2802 uint32_t l1cfg0 = 0x3800 /* 8 ways */
2803 | 0x0020; /* 32 kb */
2804 uint32_t l1cfg1 = 0x3800 /* 8 ways */
2805 | 0x0020; /* 32 kb */
2806 uint32_t mmucfg = 0;
2807 #if !defined(CONFIG_USER_ONLY)
2808 int i;
2809 #endif
2810
2811 /*
2812 * XXX The e500 doesn't implement IVOR7 and IVOR9, but doesn't
2813 * complain when accessing them.
2814 * register_BookE_sprs(env, 0x0000000F0000FD7FULL);
2815 */
2816 switch (version) {
2817 case fsl_e500v1:
2818 case fsl_e500v2:
2819 default:
2820 ivor_mask = 0x0000000F0000FFFFULL;
2821 break;
2822 case fsl_e500mc:
2823 case fsl_e5500:
2824 ivor_mask = 0x000003FE0000FFFFULL;
2825 break;
2826 case fsl_e6500:
2827 ivor_mask = 0x000003FF0000FFFFULL;
2828 break;
2829 }
2830 register_BookE_sprs(env, ivor_mask);
2831
2832 spr_register(env, SPR_USPRG3, "USPRG3",
2833 &spr_read_ureg, SPR_NOACCESS,
2834 &spr_read_ureg, SPR_NOACCESS,
2835 0x00000000);
2836
2837 /* Processor identification */
2838 spr_register(env, SPR_BOOKE_PIR, "PIR",
2839 SPR_NOACCESS, SPR_NOACCESS,
2840 &spr_read_generic, &spr_write_pir,
2841 0x00000000);
2842
2843 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
2844 &spr_read_spefscr, &spr_write_spefscr,
2845 &spr_read_spefscr, &spr_write_spefscr,
2846 0x00000000);
2847 #if !defined(CONFIG_USER_ONLY)
2848 /* Memory management */
2849 env->nb_pids = 3;
2850 env->nb_ways = 2;
2851 switch (version) {
2852 case fsl_e500v1:
2853 tlbncfg[0] = register_tlbncfg(2, 1, 1, 0, 256);
2854 tlbncfg[1] = register_tlbncfg(16, 1, 9, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
2855 break;
2856 case fsl_e500v2:
2857 tlbncfg[0] = register_tlbncfg(4, 1, 1, 0, 512);
2858 tlbncfg[1] = register_tlbncfg(16, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
2859 break;
2860 case fsl_e500mc:
2861 case fsl_e5500:
2862 tlbncfg[0] = register_tlbncfg(4, 1, 1, 0, 512);
2863 tlbncfg[1] = register_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64);
2864 break;
2865 case fsl_e6500:
2866 mmucfg = 0x6510B45;
2867 env->nb_pids = 1;
2868 tlbncfg[0] = 0x08052400;
2869 tlbncfg[1] = 0x40028040;
2870 break;
2871 default:
2872 cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n",
2873 env->spr[SPR_PVR]);
2874 }
2875 #endif
2876 /* Cache sizes */
2877 switch (version) {
2878 case fsl_e500v1:
2879 case fsl_e500v2:
2880 env->dcache_line_size = 32;
2881 env->icache_line_size = 32;
2882 break;
2883 case fsl_e500mc:
2884 case fsl_e5500:
2885 env->dcache_line_size = 64;
2886 env->icache_line_size = 64;
2887 l1cfg0 |= 0x1000000; /* 64 byte cache block size */
2888 l1cfg1 |= 0x1000000; /* 64 byte cache block size */
2889 break;
2890 case fsl_e6500:
2891 env->dcache_line_size = 32;
2892 env->icache_line_size = 32;
2893 l1cfg0 |= 0x0F83820;
2894 l1cfg1 |= 0x0B83820;
2895 break;
2896 default:
2897 cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n",
2898 env->spr[SPR_PVR]);
2899 }
2900 register_BookE206_sprs(env, 0x000000DF, tlbncfg, mmucfg);
2901 register_usprgh_sprs(env);
2902
2903 if (version != fsl_e500v1) {
2904 /* e500v1 has no support for alternate timebase */
2905 register_atb_sprs(env);
2906 }
2907
2908 spr_register(env, SPR_HID0, "HID0",
2909 SPR_NOACCESS, SPR_NOACCESS,
2910 &spr_read_generic, &spr_write_generic,
2911 0x00000000);
2912
2913 spr_register(env, SPR_HID1, "HID1",
2914 SPR_NOACCESS, SPR_NOACCESS,
2915 &spr_read_generic, &spr_write_generic,
2916 0x00000000);
2917
2918 spr_register(env, SPR_Exxx_BBEAR, "BBEAR",
2919 SPR_NOACCESS, SPR_NOACCESS,
2920 &spr_read_generic, &spr_write_generic,
2921 0x00000000);
2922
2923 spr_register(env, SPR_Exxx_BBTAR, "BBTAR",
2924 SPR_NOACCESS, SPR_NOACCESS,
2925 &spr_read_generic, &spr_write_generic,
2926 0x00000000);
2927
2928 spr_register(env, SPR_Exxx_MCAR, "MCAR",
2929 SPR_NOACCESS, SPR_NOACCESS,
2930 &spr_read_generic, &spr_write_generic,
2931 0x00000000);
2932
2933 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
2934 SPR_NOACCESS, SPR_NOACCESS,
2935 &spr_read_generic, &spr_write_generic,
2936 0x00000000);
2937
2938 spr_register(env, SPR_Exxx_NPIDR, "NPIDR",
2939 SPR_NOACCESS, SPR_NOACCESS,
2940 &spr_read_generic, &spr_write_generic,
2941 0x00000000);
2942
2943 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
2944 SPR_NOACCESS, SPR_NOACCESS,
2945 &spr_read_generic, &spr_write_generic,
2946 0x00000000);
2947
2948 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
2949 &spr_read_generic, SPR_NOACCESS,
2950 &spr_read_generic, SPR_NOACCESS,
2951 l1cfg0);
2952 spr_register(env, SPR_Exxx_L1CFG1, "L1CFG1",
2953 &spr_read_generic, SPR_NOACCESS,
2954 &spr_read_generic, SPR_NOACCESS,
2955 l1cfg1);
2956 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
2957 SPR_NOACCESS, SPR_NOACCESS,
2958 &spr_read_generic, &spr_write_e500_l1csr0,
2959 0x00000000);
2960 spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1",
2961 SPR_NOACCESS, SPR_NOACCESS,
2962 &spr_read_generic, &spr_write_e500_l1csr1,
2963 0x00000000);
2964 if (version != fsl_e500v1 && version != fsl_e500v2) {
2965 spr_register(env, SPR_Exxx_L2CSR0, "L2CSR0",
2966 SPR_NOACCESS, SPR_NOACCESS,
2967 &spr_read_generic, &spr_write_e500_l2csr0,
2968 0x00000000);
2969 }
2970 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
2971 SPR_NOACCESS, SPR_NOACCESS,
2972 &spr_read_generic, &spr_write_generic,
2973 0x00000000);
2974 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
2975 SPR_NOACCESS, SPR_NOACCESS,
2976 &spr_read_generic, &spr_write_generic,
2977 0x00000000);
2978 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
2979 SPR_NOACCESS, SPR_NOACCESS,
2980 &spr_read_generic, &spr_write_booke206_mmucsr0,
2981 0x00000000);
2982 spr_register(env, SPR_BOOKE_EPR, "EPR",
2983 SPR_NOACCESS, SPR_NOACCESS,
2984 &spr_read_generic, SPR_NOACCESS,
2985 0x00000000);
2986 /* XXX better abstract into Emb.xxx features */
2987 if ((version == fsl_e5500) || (version == fsl_e6500)) {
2988 spr_register(env, SPR_BOOKE_EPCR, "EPCR",
2989 SPR_NOACCESS, SPR_NOACCESS,
2990 &spr_read_generic, &spr_write_generic,
2991 0x00000000);
2992 spr_register(env, SPR_BOOKE_MAS7_MAS3, "MAS7_MAS3",
2993 SPR_NOACCESS, SPR_NOACCESS,
2994 &spr_read_mas73, &spr_write_mas73,
2995 0x00000000);
2996 ivpr_mask = (target_ulong)~0xFFFFULL;
2997 }
2998
2999 if (version == fsl_e6500) {
3000 /* Thread identification */
3001 spr_register(env, SPR_TIR, "TIR",
3002 SPR_NOACCESS, SPR_NOACCESS,
3003 &spr_read_generic, SPR_NOACCESS,
3004 0x00000000);
3005 spr_register(env, SPR_BOOKE_TLB0PS, "TLB0PS",
3006 SPR_NOACCESS, SPR_NOACCESS,
3007 &spr_read_generic, SPR_NOACCESS,
3008 0x00000004);
3009 spr_register(env, SPR_BOOKE_TLB1PS, "TLB1PS",
3010 SPR_NOACCESS, SPR_NOACCESS,
3011 &spr_read_generic, SPR_NOACCESS,
3012 0x7FFFFFFC);
3013 }
3014
3015 #if !defined(CONFIG_USER_ONLY)
3016 env->nb_tlb = 0;
3017 env->tlb_type = TLB_MAS;
3018 for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
3019 env->nb_tlb += booke206_tlb_size(env, i);
3020 }
3021 #endif
3022
3023 init_excp_e500(env, ivpr_mask);
3024 /* Allocate hardware IRQ controller */
3025 ppce500_irq_init(env_archcpu(env));
3026 }
3027
3028 static void init_proc_e500v1(CPUPPCState *env)
3029 {
3030 init_proc_e500(env, fsl_e500v1);
3031 }
3032
3033 POWERPC_FAMILY(e500v1)(ObjectClass *oc, const void *data)
3034 {
3035 DeviceClass *dc = DEVICE_CLASS(oc);
3036 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3037
3038 dc->desc = "e500v1 core";
3039 pcc->init_proc = init_proc_e500v1;
3040 pcc->check_pow = check_pow_hid0;
3041 pcc->check_attn = check_attn_none;
3042 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
3043 PPC_SPE | PPC_SPE_SINGLE |
3044 PPC_WRTEE | PPC_RFDI |
3045 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
3046 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3047 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
3048 pcc->insns_flags2 = PPC2_BOOKE206;
3049 pcc->msr_mask = (1ull << MSR_UCLE) |
3050 (1ull << MSR_SPE) |
3051 (1ull << MSR_POW) |
3052 (1ull << MSR_CE) |
3053 (1ull << MSR_EE) |
3054 (1ull << MSR_PR) |
3055 (1ull << MSR_FP) |
3056 (1ull << MSR_ME) |
3057 (1ull << MSR_FE0) |
3058 (1ull << MSR_DWE) |
3059 (1ull << MSR_DE) |
3060 (1ull << MSR_FE1) |
3061 (1ull << MSR_IR) |
3062 (1ull << MSR_DR);
3063 pcc->mmu_model = POWERPC_MMU_BOOKE206;
3064 pcc->excp_model = POWERPC_EXCP_BOOKE;
3065 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3066 pcc->bfd_mach = bfd_mach_ppc_860;
3067 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
3068 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
3069 POWERPC_FLAG_BUS_CLK;
3070 }
3071
3072 static void init_proc_e500v2(CPUPPCState *env)
3073 {
3074 init_proc_e500(env, fsl_e500v2);
3075 }
3076
3077 POWERPC_FAMILY(e500v2)(ObjectClass *oc, const void *data)
3078 {
3079 DeviceClass *dc = DEVICE_CLASS(oc);
3080 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3081
3082 dc->desc = "e500v2 core";
3083 pcc->init_proc = init_proc_e500v2;
3084 pcc->check_pow = check_pow_hid0;
3085 pcc->check_attn = check_attn_none;
3086 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
3087 PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE |
3088 PPC_WRTEE | PPC_RFDI |
3089 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
3090 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3091 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
3092 pcc->insns_flags2 = PPC2_BOOKE206;
3093 pcc->msr_mask = (1ull << MSR_UCLE) |
3094 (1ull << MSR_SPE) |
3095 (1ull << MSR_POW) |
3096 (1ull << MSR_CE) |
3097 (1ull << MSR_EE) |
3098 (1ull << MSR_PR) |
3099 (1ull << MSR_FP) |
3100 (1ull << MSR_ME) |
3101 (1ull << MSR_FE0) |
3102 (1ull << MSR_DWE) |
3103 (1ull << MSR_DE) |
3104 (1ull << MSR_FE1) |
3105 (1ull << MSR_IR) |
3106 (1ull << MSR_DR);
3107 pcc->mmu_model = POWERPC_MMU_BOOKE206;
3108 pcc->excp_model = POWERPC_EXCP_BOOKE;
3109 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3110 pcc->bfd_mach = bfd_mach_ppc_860;
3111 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
3112 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
3113 POWERPC_FLAG_BUS_CLK;
3114 }
3115
3116 static void init_proc_e500mc(CPUPPCState *env)
3117 {
3118 init_proc_e500(env, fsl_e500mc);
3119 }
3120
3121 POWERPC_FAMILY(e500mc)(ObjectClass *oc, const void *data)
3122 {
3123 DeviceClass *dc = DEVICE_CLASS(oc);
3124 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3125
3126 dc->desc = "e500mc core";
3127 pcc->init_proc = init_proc_e500mc;
3128 pcc->check_pow = check_pow_none;
3129 pcc->check_attn = check_attn_none;
3130 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB |
3131 PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
3132 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
3133 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3134 PPC_FLOAT | PPC_FLOAT_FRES |
3135 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
3136 PPC_FLOAT_STFIWX | PPC_WAIT |
3137 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
3138 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL;
3139 pcc->msr_mask = (1ull << MSR_GS) |
3140 (1ull << MSR_UCLE) |
3141 (1ull << MSR_CE) |
3142 (1ull << MSR_EE) |
3143 (1ull << MSR_PR) |
3144 (1ull << MSR_FP) |
3145 (1ull << MSR_ME) |
3146 (1ull << MSR_FE0) |
3147 (1ull << MSR_DE) |
3148 (1ull << MSR_FE1) |
3149 (1ull << MSR_IR) |
3150 (1ull << MSR_DR) |
3151 (1ull << MSR_PX) |
3152 (1ull << MSR_RI);
3153 pcc->mmu_model = POWERPC_MMU_BOOKE206;
3154 pcc->excp_model = POWERPC_EXCP_BOOKE;
3155 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3156 /* FIXME: figure out the correct flag for e500mc */
3157 pcc->bfd_mach = bfd_mach_ppc_e500;
3158 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3159 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
3160 }
3161
3162 #ifdef TARGET_PPC64
3163 static void init_proc_e5500(CPUPPCState *env)
3164 {
3165 init_proc_e500(env, fsl_e5500);
3166 }
3167
3168 POWERPC_FAMILY(e5500)(ObjectClass *oc, const void *data)
3169 {
3170 DeviceClass *dc = DEVICE_CLASS(oc);
3171 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3172
3173 dc->desc = "e5500 core";
3174 pcc->init_proc = init_proc_e5500;
3175 pcc->check_pow = check_pow_none;
3176 pcc->check_attn = check_attn_none;
3177 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB |
3178 PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
3179 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
3180 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3181 PPC_FLOAT | PPC_FLOAT_FRES |
3182 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
3183 PPC_FLOAT_STFIWX | PPC_WAIT |
3184 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC |
3185 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD;
3186 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 |
3187 PPC2_FP_CVT_S64;
3188 pcc->msr_mask = (1ull << MSR_CM) |
3189 (1ull << MSR_GS) |
3190 (1ull << MSR_UCLE) |
3191 (1ull << MSR_CE) |
3192 (1ull << MSR_EE) |
3193 (1ull << MSR_PR) |
3194 (1ull << MSR_FP) |
3195 (1ull << MSR_ME) |
3196 (1ull << MSR_FE0) |
3197 (1ull << MSR_DE) |
3198 (1ull << MSR_FE1) |
3199 (1ull << MSR_IR) |
3200 (1ull << MSR_DR) |
3201 (1ull << MSR_PX) |
3202 (1ull << MSR_RI);
3203 pcc->mmu_model = POWERPC_MMU_BOOKE206;
3204 pcc->excp_model = POWERPC_EXCP_BOOKE;
3205 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3206 /* FIXME: figure out the correct flag for e5500 */
3207 pcc->bfd_mach = bfd_mach_ppc_e500;
3208 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3209 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
3210 }
3211
3212 static void init_proc_e6500(CPUPPCState *env)
3213 {
3214 init_proc_e500(env, fsl_e6500);
3215 }
3216
3217 POWERPC_FAMILY(e6500)(ObjectClass *oc, const void *data)
3218 {
3219 DeviceClass *dc = DEVICE_CLASS(oc);
3220 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3221
3222 dc->desc = "e6500 core";
3223 pcc->init_proc = init_proc_e6500;
3224 pcc->check_pow = check_pow_none;
3225 pcc->check_attn = check_attn_none;
3226 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB |
3227 PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
3228 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
3229 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3230 PPC_FLOAT | PPC_FLOAT_FRES |
3231 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
3232 PPC_FLOAT_STFIWX | PPC_WAIT |
3233 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC |
3234 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD | PPC_ALTIVEC;
3235 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 |
3236 PPC2_FP_CVT_S64 | PPC2_ATOMIC_ISA206;
3237 pcc->msr_mask = (1ull << MSR_CM) |
3238 (1ull << MSR_GS) |
3239 (1ull << MSR_UCLE) |
3240 (1ull << MSR_CE) |
3241 (1ull << MSR_EE) |
3242 (1ull << MSR_PR) |
3243 (1ull << MSR_FP) |
3244 (1ull << MSR_ME) |
3245 (1ull << MSR_FE0) |
3246 (1ull << MSR_DE) |
3247 (1ull << MSR_FE1) |
3248 (1ull << MSR_IS) |
3249 (1ull << MSR_DS) |
3250 (1ull << MSR_PX) |
3251 (1ull << MSR_RI) |
3252 (1ull << MSR_VR);
3253 pcc->mmu_model = POWERPC_MMU_BOOKE206;
3254 pcc->excp_model = POWERPC_EXCP_BOOKE;
3255 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3256 pcc->bfd_mach = bfd_mach_ppc_e500;
3257 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3258 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_VRE;
3259 }
3260
3261 #endif
3262
3263 /* Non-embedded PowerPC */
3264 static void init_proc_603(CPUPPCState *env)
3265 {
3266 register_non_embedded_sprs(env);
3267 register_sdr1_sprs(env);
3268 register_603_sprs(env);
3269
3270 /* Memory management */
3271 register_low_BATs(env);
3272 register_6xx_7xx_soft_tlb(env, 64, 2);
3273 init_excp_603(env);
3274 env->dcache_line_size = 32;
3275 env->icache_line_size = 32;
3276 /* Allocate hardware IRQ controller */
3277 ppc6xx_irq_init(env_archcpu(env));
3278 }
3279
3280 POWERPC_FAMILY(603)(ObjectClass *oc, const void *data)
3281 {
3282 DeviceClass *dc = DEVICE_CLASS(oc);
3283 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3284
3285 dc->desc = "PowerPC 603";
3286 pcc->init_proc = init_proc_603;
3287 pcc->check_pow = check_pow_hid0;
3288 pcc->check_attn = check_attn_none;
3289 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3290 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3291 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
3292 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3293 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3294 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
3295 PPC_SEGMENT | PPC_EXTERN;
3296 pcc->msr_mask = (1ull << MSR_POW) |
3297 (1ull << MSR_TGPR) |
3298 (1ull << MSR_ILE) |
3299 (1ull << MSR_EE) |
3300 (1ull << MSR_PR) |
3301 (1ull << MSR_FP) |
3302 (1ull << MSR_ME) |
3303 (1ull << MSR_FE0) |
3304 (1ull << MSR_SE) |
3305 (1ull << MSR_DE) |
3306 (1ull << MSR_FE1) |
3307 (1ull << MSR_EP) |
3308 (1ull << MSR_IR) |
3309 (1ull << MSR_DR) |
3310 (1ull << MSR_RI) |
3311 (1ull << MSR_LE);
3312 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
3313 pcc->excp_model = POWERPC_EXCP_6xx;
3314 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3315 pcc->bfd_mach = bfd_mach_ppc_603;
3316 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
3317 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
3318 }
3319
3320 POWERPC_FAMILY(603E)(ObjectClass *oc, const void *data)
3321 {
3322 DeviceClass *dc = DEVICE_CLASS(oc);
3323 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3324
3325 dc->desc = "PowerPC 603e";
3326 pcc->init_proc = init_proc_603;
3327 pcc->check_pow = check_pow_hid0;
3328 pcc->check_attn = check_attn_none;
3329 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3330 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3331 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
3332 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3333 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3334 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
3335 PPC_SEGMENT | PPC_EXTERN;
3336 pcc->msr_mask = (1ull << MSR_POW) |
3337 (1ull << MSR_TGPR) |
3338 (1ull << MSR_ILE) |
3339 (1ull << MSR_EE) |
3340 (1ull << MSR_PR) |
3341 (1ull << MSR_FP) |
3342 (1ull << MSR_ME) |
3343 (1ull << MSR_FE0) |
3344 (1ull << MSR_SE) |
3345 (1ull << MSR_DE) |
3346 (1ull << MSR_FE1) |
3347 (1ull << MSR_EP) |
3348 (1ull << MSR_IR) |
3349 (1ull << MSR_DR) |
3350 (1ull << MSR_RI) |
3351 (1ull << MSR_LE);
3352 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
3353 pcc->excp_model = POWERPC_EXCP_6xx;
3354 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3355 pcc->bfd_mach = bfd_mach_ppc_ec603e;
3356 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
3357 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
3358 }
3359
3360 static void init_proc_e300(CPUPPCState *env)
3361 {
3362 init_proc_603(env);
3363 register_e300_sprs(env);
3364 }
3365
3366 POWERPC_FAMILY(e300)(ObjectClass *oc, const void *data)
3367 {
3368 DeviceClass *dc = DEVICE_CLASS(oc);
3369 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3370
3371 dc->desc = "e300 core";
3372 pcc->init_proc = init_proc_e300;
3373 pcc->check_pow = check_pow_hid0;
3374 pcc->check_attn = check_attn_none;
3375 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3376 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3377 PPC_FLOAT_STFIWX |
3378 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3379 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3380 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
3381 PPC_SEGMENT | PPC_EXTERN;
3382 pcc->msr_mask = (1ull << MSR_POW) |
3383 (1ull << MSR_TGPR) |
3384 (1ull << MSR_ILE) |
3385 (1ull << MSR_EE) |
3386 (1ull << MSR_PR) |
3387 (1ull << MSR_FP) |
3388 (1ull << MSR_ME) |
3389 (1ull << MSR_FE0) |
3390 (1ull << MSR_SE) |
3391 (1ull << MSR_DE) |
3392 (1ull << MSR_FE1) |
3393 (1ull << MSR_AL) |
3394 (1ull << MSR_EP) |
3395 (1ull << MSR_IR) |
3396 (1ull << MSR_DR) |
3397 (1ull << MSR_RI) |
3398 (1ull << MSR_LE);
3399 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
3400 pcc->excp_model = POWERPC_EXCP_6xx;
3401 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3402 pcc->bfd_mach = bfd_mach_ppc_603;
3403 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
3404 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
3405 }
3406
3407 static void init_proc_604(CPUPPCState *env)
3408 {
3409 register_non_embedded_sprs(env);
3410 register_sdr1_sprs(env);
3411 register_604_sprs(env);
3412
3413 /* Memory management */
3414 register_low_BATs(env);
3415 init_excp_604(env);
3416 env->dcache_line_size = 32;
3417 env->icache_line_size = 32;
3418 /* Allocate hardware IRQ controller */
3419 ppc6xx_irq_init(env_archcpu(env));
3420 }
3421
3422 POWERPC_FAMILY(604)(ObjectClass *oc, const void *data)
3423 {
3424 DeviceClass *dc = DEVICE_CLASS(oc);
3425 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3426
3427 dc->desc = "PowerPC 604";
3428 pcc->init_proc = init_proc_604;
3429 pcc->check_pow = check_pow_nocheck;
3430 pcc->check_attn = check_attn_none;
3431 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3432 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3433 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
3434 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3435 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3436 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
3437 PPC_SEGMENT | PPC_EXTERN;
3438 pcc->msr_mask = (1ull << MSR_POW) |
3439 (1ull << MSR_ILE) |
3440 (1ull << MSR_EE) |
3441 (1ull << MSR_PR) |
3442 (1ull << MSR_FP) |
3443 (1ull << MSR_ME) |
3444 (1ull << MSR_FE0) |
3445 (1ull << MSR_SE) |
3446 (1ull << MSR_DE) |
3447 (1ull << MSR_FE1) |
3448 (1ull << MSR_EP) |
3449 (1ull << MSR_IR) |
3450 (1ull << MSR_DR) |
3451 (1ull << MSR_PMM) |
3452 (1ull << MSR_RI) |
3453 (1ull << MSR_LE);
3454 pcc->mmu_model = POWERPC_MMU_32B;
3455 pcc->excp_model = POWERPC_EXCP_6xx;
3456 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3457 pcc->bfd_mach = bfd_mach_ppc_604;
3458 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
3459 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
3460 }
3461
3462 static void init_proc_604E(CPUPPCState *env)
3463 {
3464 init_proc_604(env);
3465 register_604e_sprs(env);
3466 }
3467
3468 POWERPC_FAMILY(604E)(ObjectClass *oc, const void *data)
3469 {
3470 DeviceClass *dc = DEVICE_CLASS(oc);
3471 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3472
3473 dc->desc = "PowerPC 604E";
3474 pcc->init_proc = init_proc_604E;
3475 pcc->check_pow = check_pow_nocheck;
3476 pcc->check_attn = check_attn_none;
3477 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3478 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3479 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
3480 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3481 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3482 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
3483 PPC_SEGMENT | PPC_EXTERN;
3484 pcc->msr_mask = (1ull << MSR_POW) |
3485 (1ull << MSR_ILE) |
3486 (1ull << MSR_EE) |
3487 (1ull << MSR_PR) |
3488 (1ull << MSR_FP) |
3489 (1ull << MSR_ME) |
3490 (1ull << MSR_FE0) |
3491 (1ull << MSR_SE) |
3492 (1ull << MSR_DE) |
3493 (1ull << MSR_FE1) |
3494 (1ull << MSR_EP) |
3495 (1ull << MSR_IR) |
3496 (1ull << MSR_DR) |
3497 (1ull << MSR_PMM) |
3498 (1ull << MSR_RI) |
3499 (1ull << MSR_LE);
3500 pcc->mmu_model = POWERPC_MMU_32B;
3501 pcc->excp_model = POWERPC_EXCP_6xx;
3502 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3503 pcc->bfd_mach = bfd_mach_ppc_604;
3504 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
3505 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
3506 }
3507
3508 static void init_proc_740(CPUPPCState *env)
3509 {
3510 register_non_embedded_sprs(env);
3511 register_sdr1_sprs(env);
3512 register_7xx_sprs(env);
3513 /* Thermal management */
3514 register_thrm_sprs(env);
3515
3516 /* Memory management */
3517 register_low_BATs(env);
3518 init_excp_7x0(env);
3519 env->dcache_line_size = 32;
3520 env->icache_line_size = 32;
3521 /* Allocate hardware IRQ controller */
3522 ppc6xx_irq_init(env_archcpu(env));
3523 }
3524
3525 POWERPC_FAMILY(740)(ObjectClass *oc, const void *data)
3526 {
3527 DeviceClass *dc = DEVICE_CLASS(oc);
3528 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3529
3530 dc->desc = "PowerPC 740";
3531 pcc->init_proc = init_proc_740;
3532 pcc->check_pow = check_pow_hid0;
3533 pcc->check_attn = check_attn_none;
3534 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3535 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3536 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
3537 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3538 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3539 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
3540 PPC_SEGMENT | PPC_EXTERN;
3541 pcc->msr_mask = (1ull << MSR_POW) |
3542 (1ull << MSR_ILE) |
3543 (1ull << MSR_EE) |
3544 (1ull << MSR_PR) |
3545 (1ull << MSR_FP) |
3546 (1ull << MSR_ME) |
3547 (1ull << MSR_FE0) |
3548 (1ull << MSR_SE) |
3549 (1ull << MSR_DE) |
3550 (1ull << MSR_FE1) |
3551 (1ull << MSR_EP) |
3552 (1ull << MSR_IR) |
3553 (1ull << MSR_DR) |
3554 (1ull << MSR_PMM) |
3555 (1ull << MSR_RI) |
3556 (1ull << MSR_LE);
3557 pcc->mmu_model = POWERPC_MMU_32B;
3558 pcc->excp_model = POWERPC_EXCP_7xx;
3559 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3560 pcc->bfd_mach = bfd_mach_ppc_750;
3561 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
3562 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
3563 }
3564
3565 static void init_proc_750(CPUPPCState *env)
3566 {
3567 register_non_embedded_sprs(env);
3568 register_sdr1_sprs(env);
3569 register_7xx_sprs(env);
3570
3571 spr_register(env, SPR_L2CR, "L2CR",
3572 SPR_NOACCESS, SPR_NOACCESS,
3573 &spr_read_generic, spr_access_nop,
3574 0x00000000);
3575 /* Thermal management */
3576 register_thrm_sprs(env);
3577
3578 /* Memory management */
3579 register_low_BATs(env);
3580 /*
3581 * XXX: high BATs are also present but are known to be bugged on
3582 * die version 1.x
3583 */
3584 init_excp_7x0(env);
3585 env->dcache_line_size = 32;
3586 env->icache_line_size = 32;
3587 /* Allocate hardware IRQ controller */
3588 ppc6xx_irq_init(env_archcpu(env));
3589 }
3590
3591 POWERPC_FAMILY(750)(ObjectClass *oc, const void *data)
3592 {
3593 DeviceClass *dc = DEVICE_CLASS(oc);
3594 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3595
3596 dc->desc = "PowerPC 750";
3597 pcc->init_proc = init_proc_750;
3598 pcc->check_pow = check_pow_hid0;
3599 pcc->check_attn = check_attn_none;
3600 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3601 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3602 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
3603 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3604 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3605 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
3606 PPC_SEGMENT | PPC_EXTERN;
3607 pcc->msr_mask = (1ull << MSR_POW) |
3608 (1ull << MSR_ILE) |
3609 (1ull << MSR_EE) |
3610 (1ull << MSR_PR) |
3611 (1ull << MSR_FP) |
3612 (1ull << MSR_ME) |
3613 (1ull << MSR_FE0) |
3614 (1ull << MSR_SE) |
3615 (1ull << MSR_DE) |
3616 (1ull << MSR_FE1) |
3617 (1ull << MSR_EP) |
3618 (1ull << MSR_IR) |
3619 (1ull << MSR_DR) |
3620 (1ull << MSR_PMM) |
3621 (1ull << MSR_RI) |
3622 (1ull << MSR_LE);
3623 pcc->mmu_model = POWERPC_MMU_32B;
3624 pcc->excp_model = POWERPC_EXCP_7xx;
3625 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3626 pcc->bfd_mach = bfd_mach_ppc_750;
3627 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
3628 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
3629 }
3630
3631 static void init_proc_750cl(CPUPPCState *env)
3632 {
3633 register_non_embedded_sprs(env);
3634 register_sdr1_sprs(env);
3635 register_7xx_sprs(env);
3636
3637 spr_register(env, SPR_L2CR, "L2CR",
3638 SPR_NOACCESS, SPR_NOACCESS,
3639 &spr_read_generic, spr_access_nop,
3640 0x00000000);
3641 /* Thermal management */
3642 /* Those registers are fake on 750CL */
3643 spr_register(env, SPR_THRM1, "THRM1",
3644 SPR_NOACCESS, SPR_NOACCESS,
3645 &spr_read_generic, &spr_write_generic,
3646 0x00000000);
3647 spr_register(env, SPR_THRM2, "THRM2",
3648 SPR_NOACCESS, SPR_NOACCESS,
3649 &spr_read_generic, &spr_write_generic,
3650 0x00000000);
3651 spr_register(env, SPR_THRM3, "THRM3",
3652 SPR_NOACCESS, SPR_NOACCESS,
3653 &spr_read_generic, &spr_write_generic,
3654 0x00000000);
3655
3656 spr_register(env, SPR_750_TDCL, "TDCL",
3657 SPR_NOACCESS, SPR_NOACCESS,
3658 &spr_read_generic, &spr_write_generic,
3659 0x00000000);
3660 spr_register(env, SPR_750_TDCH, "TDCH",
3661 SPR_NOACCESS, SPR_NOACCESS,
3662 &spr_read_generic, &spr_write_generic,
3663 0x00000000);
3664 /* DMA */
3665 spr_register(env, SPR_750_WPAR, "WPAR",
3666 SPR_NOACCESS, SPR_NOACCESS,
3667 &spr_read_generic, &spr_write_generic,
3668 0x00000000);
3669 spr_register(env, SPR_750_DMAL, "DMAL",
3670 SPR_NOACCESS, SPR_NOACCESS,
3671 &spr_read_generic, &spr_write_generic,
3672 0x00000000);
3673 spr_register(env, SPR_750_DMAU, "DMAU",
3674 SPR_NOACCESS, SPR_NOACCESS,
3675 &spr_read_generic, &spr_write_generic,
3676 0x00000000);
3677 /* Hardware implementation registers */
3678 spr_register(env, SPR_750CL_HID2, "HID2",
3679 SPR_NOACCESS, SPR_NOACCESS,
3680 &spr_read_generic, &spr_write_generic,
3681 0x00000000);
3682
3683 spr_register(env, SPR_750CL_HID4, "HID4",
3684 SPR_NOACCESS, SPR_NOACCESS,
3685 &spr_read_generic, &spr_write_generic,
3686 0x00000000);
3687 /* Quantization registers */
3688 spr_register(env, SPR_750_GQR0, "GQR0",
3689 SPR_NOACCESS, SPR_NOACCESS,
3690 &spr_read_generic, &spr_write_generic,
3691 0x00000000);
3692
3693 spr_register(env, SPR_750_GQR1, "GQR1",
3694 SPR_NOACCESS, SPR_NOACCESS,
3695 &spr_read_generic, &spr_write_generic,
3696 0x00000000);
3697
3698 spr_register(env, SPR_750_GQR2, "GQR2",
3699 SPR_NOACCESS, SPR_NOACCESS,
3700 &spr_read_generic, &spr_write_generic,
3701 0x00000000);
3702
3703 spr_register(env, SPR_750_GQR3, "GQR3",
3704 SPR_NOACCESS, SPR_NOACCESS,
3705 &spr_read_generic, &spr_write_generic,
3706 0x00000000);
3707
3708 spr_register(env, SPR_750_GQR4, "GQR4",
3709 SPR_NOACCESS, SPR_NOACCESS,
3710 &spr_read_generic, &spr_write_generic,
3711 0x00000000);
3712
3713 spr_register(env, SPR_750_GQR5, "GQR5",
3714 SPR_NOACCESS, SPR_NOACCESS,
3715 &spr_read_generic, &spr_write_generic,
3716 0x00000000);
3717
3718 spr_register(env, SPR_750_GQR6, "GQR6",
3719 SPR_NOACCESS, SPR_NOACCESS,
3720 &spr_read_generic, &spr_write_generic,
3721 0x00000000);
3722
3723 spr_register(env, SPR_750_GQR7, "GQR7",
3724 SPR_NOACCESS, SPR_NOACCESS,
3725 &spr_read_generic, &spr_write_generic,
3726 0x00000000);
3727 /* Memory management */
3728 register_low_BATs(env);
3729 /* PowerPC 750cl has 8 DBATs and 8 IBATs */
3730 register_high_BATs(env);
3731 init_excp_750cl(env);
3732 env->dcache_line_size = 32;
3733 env->icache_line_size = 32;
3734 /* Allocate hardware IRQ controller */
3735 ppc6xx_irq_init(env_archcpu(env));
3736 }
3737
3738 POWERPC_FAMILY(750cl)(ObjectClass *oc, const void *data)
3739 {
3740 DeviceClass *dc = DEVICE_CLASS(oc);
3741 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3742
3743 dc->desc = "PowerPC 750 CL";
3744 pcc->init_proc = init_proc_750cl;
3745 pcc->check_pow = check_pow_hid0;
3746 pcc->check_attn = check_attn_none;
3747 /*
3748 * XXX: not implemented:
3749 * cache lock instructions:
3750 * dcbz_l
3751 * floating point paired instructions
3752 * psq_lux
3753 * psq_lx
3754 * psq_stux
3755 * psq_stx
3756 * ps_abs
3757 * ps_add
3758 * ps_cmpo0
3759 * ps_cmpo1
3760 * ps_cmpu0
3761 * ps_cmpu1
3762 * ps_div
3763 * ps_madd
3764 * ps_madds0
3765 * ps_madds1
3766 * ps_merge00
3767 * ps_merge01
3768 * ps_merge10
3769 * ps_merge11
3770 * ps_mr
3771 * ps_msub
3772 * ps_mul
3773 * ps_muls0
3774 * ps_muls1
3775 * ps_nabs
3776 * ps_neg
3777 * ps_nmadd
3778 * ps_nmsub
3779 * ps_res
3780 * ps_rsqrte
3781 * ps_sel
3782 * ps_sub
3783 * ps_sum0
3784 * ps_sum1
3785 */
3786 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3787 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3788 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
3789 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3790 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3791 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
3792 PPC_SEGMENT | PPC_EXTERN;
3793 pcc->msr_mask = (1ull << MSR_POW) |
3794 (1ull << MSR_ILE) |
3795 (1ull << MSR_EE) |
3796 (1ull << MSR_PR) |
3797 (1ull << MSR_FP) |
3798 (1ull << MSR_ME) |
3799 (1ull << MSR_FE0) |
3800 (1ull << MSR_SE) |
3801 (1ull << MSR_DE) |
3802 (1ull << MSR_FE1) |
3803 (1ull << MSR_EP) |
3804 (1ull << MSR_IR) |
3805 (1ull << MSR_DR) |
3806 (1ull << MSR_PMM) |
3807 (1ull << MSR_RI) |
3808 (1ull << MSR_LE);
3809 pcc->mmu_model = POWERPC_MMU_32B;
3810 pcc->excp_model = POWERPC_EXCP_7xx;
3811 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3812 pcc->bfd_mach = bfd_mach_ppc_750;
3813 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
3814 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
3815 }
3816
3817 static void init_proc_750cx(CPUPPCState *env)
3818 {
3819 register_non_embedded_sprs(env);
3820 register_sdr1_sprs(env);
3821 register_7xx_sprs(env);
3822
3823 spr_register(env, SPR_L2CR, "L2CR",
3824 SPR_NOACCESS, SPR_NOACCESS,
3825 &spr_read_generic, spr_access_nop,
3826 0x00000000);
3827 /* Thermal management */
3828 register_thrm_sprs(env);
3829
3830 spr_register(env, SPR_SDA, "SDA",
3831 SPR_NOACCESS, SPR_NOACCESS,
3832 &spr_read_generic, &spr_write_generic,
3833 0x00000000);
3834
3835 /* Memory management */
3836 register_low_BATs(env);
3837 /* PowerPC 750cx has 8 DBATs and 8 IBATs */
3838 register_high_BATs(env);
3839 init_excp_750cx(env);
3840 env->dcache_line_size = 32;
3841 env->icache_line_size = 32;
3842 /* Allocate hardware IRQ controller */
3843 ppc6xx_irq_init(env_archcpu(env));
3844 }
3845
3846 POWERPC_FAMILY(750cx)(ObjectClass *oc, const void *data)
3847 {
3848 DeviceClass *dc = DEVICE_CLASS(oc);
3849 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3850
3851 dc->desc = "PowerPC 750CX";
3852 pcc->init_proc = init_proc_750cx;
3853 pcc->check_pow = check_pow_hid0;
3854 pcc->check_attn = check_attn_none;
3855 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3856 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3857 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
3858 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3859 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3860 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
3861 PPC_SEGMENT | PPC_EXTERN;
3862 pcc->msr_mask = (1ull << MSR_POW) |
3863 (1ull << MSR_ILE) |
3864 (1ull << MSR_EE) |
3865 (1ull << MSR_PR) |
3866 (1ull << MSR_FP) |
3867 (1ull << MSR_ME) |
3868 (1ull << MSR_FE0) |
3869 (1ull << MSR_SE) |
3870 (1ull << MSR_DE) |
3871 (1ull << MSR_FE1) |
3872 (1ull << MSR_EP) |
3873 (1ull << MSR_IR) |
3874 (1ull << MSR_DR) |
3875 (1ull << MSR_PMM) |
3876 (1ull << MSR_RI) |
3877 (1ull << MSR_LE);
3878 pcc->mmu_model = POWERPC_MMU_32B;
3879 pcc->excp_model = POWERPC_EXCP_7xx;
3880 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3881 pcc->bfd_mach = bfd_mach_ppc_750;
3882 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
3883 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
3884 }
3885
3886 static void init_proc_750fx(CPUPPCState *env)
3887 {
3888 register_non_embedded_sprs(env);
3889 register_sdr1_sprs(env);
3890 register_7xx_sprs(env);
3891
3892 spr_register(env, SPR_L2CR, "L2CR",
3893 SPR_NOACCESS, SPR_NOACCESS,
3894 &spr_read_generic, spr_access_nop,
3895 0x00000000);
3896 /* Thermal management */
3897 register_thrm_sprs(env);
3898
3899 spr_register(env, SPR_750_THRM4, "THRM4",
3900 SPR_NOACCESS, SPR_NOACCESS,
3901 &spr_read_generic, &spr_write_generic,
3902 0x00000000);
3903 /* Hardware implementation registers */
3904 spr_register(env, SPR_750FX_HID2, "HID2",
3905 SPR_NOACCESS, SPR_NOACCESS,
3906 &spr_read_generic, &spr_write_generic,
3907 0x00000000);
3908 /* Memory management */
3909 register_low_BATs(env);
3910 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
3911 register_high_BATs(env);
3912 init_excp_7x0(env);
3913 env->dcache_line_size = 32;
3914 env->icache_line_size = 32;
3915 /* Allocate hardware IRQ controller */
3916 ppc6xx_irq_init(env_archcpu(env));
3917 }
3918
3919 POWERPC_FAMILY(750fx)(ObjectClass *oc, const void *data)
3920 {
3921 DeviceClass *dc = DEVICE_CLASS(oc);
3922 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3923
3924 dc->desc = "PowerPC 750FX";
3925 pcc->init_proc = init_proc_750fx;
3926 pcc->check_pow = check_pow_hid0;
3927 pcc->check_attn = check_attn_none;
3928 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3929 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3930 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
3931 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3932 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3933 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
3934 PPC_SEGMENT | PPC_EXTERN;
3935 pcc->msr_mask = (1ull << MSR_POW) |
3936 (1ull << MSR_ILE) |
3937 (1ull << MSR_EE) |
3938 (1ull << MSR_PR) |
3939 (1ull << MSR_FP) |
3940 (1ull << MSR_ME) |
3941 (1ull << MSR_FE0) |
3942 (1ull << MSR_SE) |
3943 (1ull << MSR_DE) |
3944 (1ull << MSR_FE1) |
3945 (1ull << MSR_EP) |
3946 (1ull << MSR_IR) |
3947 (1ull << MSR_DR) |
3948 (1ull << MSR_PMM) |
3949 (1ull << MSR_RI) |
3950 (1ull << MSR_LE);
3951 pcc->mmu_model = POWERPC_MMU_32B;
3952 pcc->excp_model = POWERPC_EXCP_7xx;
3953 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3954 pcc->bfd_mach = bfd_mach_ppc_750;
3955 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
3956 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
3957 }
3958
3959 static void init_proc_750gx(CPUPPCState *env)
3960 {
3961 register_non_embedded_sprs(env);
3962 register_sdr1_sprs(env);
3963 register_7xx_sprs(env);
3964
3965 spr_register(env, SPR_L2CR, "L2CR",
3966 SPR_NOACCESS, SPR_NOACCESS,
3967 &spr_read_generic, spr_access_nop,
3968 0x00000000);
3969 /* Thermal management */
3970 register_thrm_sprs(env);
3971
3972 spr_register(env, SPR_750_THRM4, "THRM4",
3973 SPR_NOACCESS, SPR_NOACCESS,
3974 &spr_read_generic, &spr_write_generic,
3975 0x00000000);
3976 /* Hardware implementation registers */
3977 spr_register(env, SPR_750FX_HID2, "HID2",
3978 SPR_NOACCESS, SPR_NOACCESS,
3979 &spr_read_generic, &spr_write_generic,
3980 0x00000000);
3981 /* Memory management */
3982 register_low_BATs(env);
3983 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
3984 register_high_BATs(env);
3985 init_excp_7x0(env);
3986 env->dcache_line_size = 32;
3987 env->icache_line_size = 32;
3988 /* Allocate hardware IRQ controller */
3989 ppc6xx_irq_init(env_archcpu(env));
3990 }
3991
3992 POWERPC_FAMILY(750gx)(ObjectClass *oc, const void *data)
3993 {
3994 DeviceClass *dc = DEVICE_CLASS(oc);
3995 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3996
3997 dc->desc = "PowerPC 750GX";
3998 pcc->init_proc = init_proc_750gx;
3999 pcc->check_pow = check_pow_hid0;
4000 pcc->check_attn = check_attn_none;
4001 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4002 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4003 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
4004 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4005 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4006 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4007 PPC_SEGMENT | PPC_EXTERN;
4008 pcc->msr_mask = (1ull << MSR_POW) |
4009 (1ull << MSR_ILE) |
4010 (1ull << MSR_EE) |
4011 (1ull << MSR_PR) |
4012 (1ull << MSR_FP) |
4013 (1ull << MSR_ME) |
4014 (1ull << MSR_FE0) |
4015 (1ull << MSR_SE) |
4016 (1ull << MSR_DE) |
4017 (1ull << MSR_FE1) |
4018 (1ull << MSR_EP) |
4019 (1ull << MSR_IR) |
4020 (1ull << MSR_DR) |
4021 (1ull << MSR_PMM) |
4022 (1ull << MSR_RI) |
4023 (1ull << MSR_LE);
4024 pcc->mmu_model = POWERPC_MMU_32B;
4025 pcc->excp_model = POWERPC_EXCP_7xx;
4026 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4027 pcc->bfd_mach = bfd_mach_ppc_750;
4028 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4029 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
4030 }
4031
4032 static void init_proc_745(CPUPPCState *env)
4033 {
4034 register_non_embedded_sprs(env);
4035 register_sdr1_sprs(env);
4036 register_7xx_sprs(env);
4037 register_745_sprs(env);
4038 /* Thermal management */
4039 register_thrm_sprs(env);
4040
4041 /* Memory management */
4042 register_low_BATs(env);
4043 register_high_BATs(env);
4044 register_6xx_7xx_soft_tlb(env, 64, 2);
4045 init_excp_7x5(env);
4046 env->dcache_line_size = 32;
4047 env->icache_line_size = 32;
4048 /* Allocate hardware IRQ controller */
4049 ppc6xx_irq_init(env_archcpu(env));
4050 }
4051
4052 POWERPC_FAMILY(745)(ObjectClass *oc, const void *data)
4053 {
4054 DeviceClass *dc = DEVICE_CLASS(oc);
4055 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4056
4057 dc->desc = "PowerPC 745";
4058 pcc->init_proc = init_proc_745;
4059 pcc->check_pow = check_pow_hid0;
4060 pcc->check_attn = check_attn_none;
4061 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4062 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4063 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
4064 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4065 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4066 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4067 PPC_SEGMENT | PPC_EXTERN;
4068 pcc->msr_mask = (1ull << MSR_POW) |
4069 (1ull << MSR_ILE) |
4070 (1ull << MSR_EE) |
4071 (1ull << MSR_PR) |
4072 (1ull << MSR_FP) |
4073 (1ull << MSR_ME) |
4074 (1ull << MSR_FE0) |
4075 (1ull << MSR_SE) |
4076 (1ull << MSR_DE) |
4077 (1ull << MSR_FE1) |
4078 (1ull << MSR_EP) |
4079 (1ull << MSR_IR) |
4080 (1ull << MSR_DR) |
4081 (1ull << MSR_PMM) |
4082 (1ull << MSR_RI) |
4083 (1ull << MSR_LE);
4084 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4085 pcc->excp_model = POWERPC_EXCP_7xx;
4086 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4087 pcc->bfd_mach = bfd_mach_ppc_750;
4088 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4089 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
4090 }
4091
4092 static void init_proc_755(CPUPPCState *env)
4093 {
4094 init_proc_745(env);
4095 register_755_sprs(env);
4096 }
4097
4098 POWERPC_FAMILY(755)(ObjectClass *oc, const void *data)
4099 {
4100 DeviceClass *dc = DEVICE_CLASS(oc);
4101 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4102
4103 dc->desc = "PowerPC 755";
4104 pcc->init_proc = init_proc_755;
4105 pcc->check_pow = check_pow_hid0;
4106 pcc->check_attn = check_attn_none;
4107 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4108 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4109 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
4110 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4111 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4112 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4113 PPC_SEGMENT | PPC_EXTERN;
4114 pcc->msr_mask = (1ull << MSR_POW) |
4115 (1ull << MSR_ILE) |
4116 (1ull << MSR_EE) |
4117 (1ull << MSR_PR) |
4118 (1ull << MSR_FP) |
4119 (1ull << MSR_ME) |
4120 (1ull << MSR_FE0) |
4121 (1ull << MSR_SE) |
4122 (1ull << MSR_DE) |
4123 (1ull << MSR_FE1) |
4124 (1ull << MSR_EP) |
4125 (1ull << MSR_IR) |
4126 (1ull << MSR_DR) |
4127 (1ull << MSR_PMM) |
4128 (1ull << MSR_RI) |
4129 (1ull << MSR_LE);
4130 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4131 pcc->excp_model = POWERPC_EXCP_7xx;
4132 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4133 pcc->bfd_mach = bfd_mach_ppc_750;
4134 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4135 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
4136 }
4137
4138 static void init_proc_7400(CPUPPCState *env)
4139 {
4140 register_non_embedded_sprs(env);
4141 register_sdr1_sprs(env);
4142 register_74xx_sprs(env);
4143 vscr_init(env, 0x00010000);
4144
4145 spr_register(env, SPR_UBAMR, "UBAMR",
4146 &spr_read_ureg, SPR_NOACCESS,
4147 &spr_read_ureg, SPR_NOACCESS,
4148 0x00000000);
4149
4150 spr_register(env, SPR_MSSCR1, "MSSCR1",
4151 SPR_NOACCESS, SPR_NOACCESS,
4152 &spr_read_generic, &spr_write_generic,
4153 0x00000000);
4154 /* Thermal management */
4155 register_thrm_sprs(env);
4156 /* Memory management */
4157 register_low_BATs(env);
4158 init_excp_7400(env);
4159 env->dcache_line_size = 32;
4160 env->icache_line_size = 32;
4161 /* Allocate hardware IRQ controller */
4162 ppc6xx_irq_init(env_archcpu(env));
4163 }
4164
4165 POWERPC_FAMILY(7400)(ObjectClass *oc, const void *data)
4166 {
4167 DeviceClass *dc = DEVICE_CLASS(oc);
4168 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4169
4170 dc->desc = "PowerPC 7400 (aka G4)";
4171 pcc->init_proc = init_proc_7400;
4172 pcc->check_pow = check_pow_hid0;
4173 pcc->check_attn = check_attn_none;
4174 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4175 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4176 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
4177 PPC_FLOAT_STFIWX |
4178 PPC_CACHE | PPC_CACHE_ICBI |
4179 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
4180 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4181 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4182 PPC_MEM_TLBIA |
4183 PPC_SEGMENT | PPC_EXTERN |
4184 PPC_ALTIVEC;
4185 pcc->msr_mask = (1ull << MSR_VR) |
4186 (1ull << MSR_POW) |
4187 (1ull << MSR_ILE) |
4188 (1ull << MSR_EE) |
4189 (1ull << MSR_PR) |
4190 (1ull << MSR_FP) |
4191 (1ull << MSR_ME) |
4192 (1ull << MSR_FE0) |
4193 (1ull << MSR_SE) |
4194 (1ull << MSR_DE) |
4195 (1ull << MSR_FE1) |
4196 (1ull << MSR_EP) |
4197 (1ull << MSR_IR) |
4198 (1ull << MSR_DR) |
4199 (1ull << MSR_PMM) |
4200 (1ull << MSR_RI) |
4201 (1ull << MSR_LE);
4202 pcc->mmu_model = POWERPC_MMU_32B;
4203 pcc->excp_model = POWERPC_EXCP_74xx;
4204 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4205 pcc->bfd_mach = bfd_mach_ppc_7400;
4206 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
4207 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
4208 POWERPC_FLAG_BUS_CLK;
4209 }
4210
4211 static void init_proc_7410(CPUPPCState *env)
4212 {
4213 register_non_embedded_sprs(env);
4214 register_sdr1_sprs(env);
4215 register_74xx_sprs(env);
4216 vscr_init(env, 0x00010000);
4217
4218 spr_register(env, SPR_UBAMR, "UBAMR",
4219 &spr_read_ureg, SPR_NOACCESS,
4220 &spr_read_ureg, SPR_NOACCESS,
4221 0x00000000);
4222 /* Thermal management */
4223 register_thrm_sprs(env);
4224 /* L2PMCR */
4225
4226 spr_register(env, SPR_L2PMCR, "L2PMCR",
4227 SPR_NOACCESS, SPR_NOACCESS,
4228 &spr_read_generic, &spr_write_generic,
4229 0x00000000);
4230 /* LDSTDB */
4231
4232 spr_register(env, SPR_LDSTDB, "LDSTDB",
4233 SPR_NOACCESS, SPR_NOACCESS,
4234 &spr_read_generic, &spr_write_generic,
4235 0x00000000);
4236 /* Memory management */
4237 register_low_BATs(env);
4238 init_excp_7400(env);
4239 env->dcache_line_size = 32;
4240 env->icache_line_size = 32;
4241 /* Allocate hardware IRQ controller */
4242 ppc6xx_irq_init(env_archcpu(env));
4243 }
4244
4245 POWERPC_FAMILY(7410)(ObjectClass *oc, const void *data)
4246 {
4247 DeviceClass *dc = DEVICE_CLASS(oc);
4248 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4249
4250 dc->desc = "PowerPC 7410 (aka G4)";
4251 pcc->init_proc = init_proc_7410;
4252 pcc->check_pow = check_pow_hid0;
4253 pcc->check_attn = check_attn_none;
4254 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4255 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4256 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
4257 PPC_FLOAT_STFIWX |
4258 PPC_CACHE | PPC_CACHE_ICBI |
4259 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
4260 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4261 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4262 PPC_MEM_TLBIA |
4263 PPC_SEGMENT | PPC_EXTERN |
4264 PPC_ALTIVEC;
4265 pcc->msr_mask = (1ull << MSR_VR) |
4266 (1ull << MSR_POW) |
4267 (1ull << MSR_ILE) |
4268 (1ull << MSR_EE) |
4269 (1ull << MSR_PR) |
4270 (1ull << MSR_FP) |
4271 (1ull << MSR_ME) |
4272 (1ull << MSR_FE0) |
4273 (1ull << MSR_SE) |
4274 (1ull << MSR_DE) |
4275 (1ull << MSR_FE1) |
4276 (1ull << MSR_EP) |
4277 (1ull << MSR_IR) |
4278 (1ull << MSR_DR) |
4279 (1ull << MSR_PMM) |
4280 (1ull << MSR_RI) |
4281 (1ull << MSR_LE);
4282 pcc->mmu_model = POWERPC_MMU_32B;
4283 pcc->excp_model = POWERPC_EXCP_74xx;
4284 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4285 pcc->bfd_mach = bfd_mach_ppc_7400;
4286 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
4287 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
4288 POWERPC_FLAG_BUS_CLK;
4289 }
4290
4291 static void init_proc_7440(CPUPPCState *env)
4292 {
4293 register_non_embedded_sprs(env);
4294 register_sdr1_sprs(env);
4295 register_74xx_sprs(env);
4296 vscr_init(env, 0x00010000);
4297
4298 spr_register(env, SPR_UBAMR, "UBAMR",
4299 &spr_read_ureg, SPR_NOACCESS,
4300 &spr_read_ureg, SPR_NOACCESS,
4301 0x00000000);
4302 /* LDSTCR */
4303 spr_register(env, SPR_LDSTCR, "LDSTCR",
4304 SPR_NOACCESS, SPR_NOACCESS,
4305 &spr_read_generic, &spr_write_generic,
4306 0x00000000);
4307 /* ICTRL */
4308 spr_register(env, SPR_ICTRL, "ICTRL",
4309 SPR_NOACCESS, SPR_NOACCESS,
4310 &spr_read_generic, &spr_write_generic,
4311 0x00000000);
4312 /* MSSSR0 */
4313 spr_register(env, SPR_MSSSR0, "MSSSR0",
4314 SPR_NOACCESS, SPR_NOACCESS,
4315 &spr_read_generic, &spr_write_generic,
4316 0x00000000);
4317 /* PMC */
4318 spr_register(env, SPR_7XX_PMC5, "PMC5",
4319 SPR_NOACCESS, SPR_NOACCESS,
4320 &spr_read_generic, &spr_write_generic,
4321 0x00000000);
4322
4323 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
4324 &spr_read_ureg, SPR_NOACCESS,
4325 &spr_read_ureg, SPR_NOACCESS,
4326 0x00000000);
4327
4328 spr_register(env, SPR_7XX_PMC6, "PMC6",
4329 SPR_NOACCESS, SPR_NOACCESS,
4330 &spr_read_generic, &spr_write_generic,
4331 0x00000000);
4332
4333 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
4334 &spr_read_ureg, SPR_NOACCESS,
4335 &spr_read_ureg, SPR_NOACCESS,
4336 0x00000000);
4337 /* Memory management */
4338 register_low_BATs(env);
4339 init_excp_7450(env);
4340 env->dcache_line_size = 32;
4341 env->icache_line_size = 32;
4342 /* Allocate hardware IRQ controller */
4343 ppc6xx_irq_init(env_archcpu(env));
4344 }
4345
4346 POWERPC_FAMILY(7440)(ObjectClass *oc, const void *data)
4347 {
4348 DeviceClass *dc = DEVICE_CLASS(oc);
4349 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4350
4351 dc->desc = "PowerPC 7440 (aka G4)";
4352 pcc->init_proc = init_proc_7440;
4353 pcc->check_pow = check_pow_hid0_74xx;
4354 pcc->check_attn = check_attn_none;
4355 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4356 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4357 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
4358 PPC_FLOAT_STFIWX |
4359 PPC_CACHE | PPC_CACHE_ICBI |
4360 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
4361 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4362 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4363 PPC_MEM_TLBIA |
4364 PPC_SEGMENT | PPC_EXTERN |
4365 PPC_ALTIVEC;
4366 pcc->msr_mask = (1ull << MSR_VR) |
4367 (1ull << MSR_POW) |
4368 (1ull << MSR_ILE) |
4369 (1ull << MSR_EE) |
4370 (1ull << MSR_PR) |
4371 (1ull << MSR_FP) |
4372 (1ull << MSR_ME) |
4373 (1ull << MSR_FE0) |
4374 (1ull << MSR_SE) |
4375 (1ull << MSR_DE) |
4376 (1ull << MSR_FE1) |
4377 (1ull << MSR_EP) |
4378 (1ull << MSR_IR) |
4379 (1ull << MSR_DR) |
4380 (1ull << MSR_PMM) |
4381 (1ull << MSR_RI) |
4382 (1ull << MSR_LE);
4383 pcc->mmu_model = POWERPC_MMU_32B;
4384 pcc->excp_model = POWERPC_EXCP_74xx;
4385 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4386 pcc->bfd_mach = bfd_mach_ppc_7400;
4387 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
4388 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
4389 POWERPC_FLAG_BUS_CLK;
4390 }
4391
4392 static void init_proc_7450(CPUPPCState *env)
4393 {
4394 register_non_embedded_sprs(env);
4395 register_sdr1_sprs(env);
4396 register_74xx_sprs(env);
4397 vscr_init(env, 0x00010000);
4398 /* Level 3 cache control */
4399 register_l3_ctrl(env);
4400 /* L3ITCR1 */
4401 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
4402 SPR_NOACCESS, SPR_NOACCESS,
4403 &spr_read_generic, &spr_write_generic,
4404 0x00000000);
4405 /* L3ITCR2 */
4406 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
4407 SPR_NOACCESS, SPR_NOACCESS,
4408 &spr_read_generic, &spr_write_generic,
4409 0x00000000);
4410 /* L3ITCR3 */
4411 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
4412 SPR_NOACCESS, SPR_NOACCESS,
4413 &spr_read_generic, &spr_write_generic,
4414 0x00000000);
4415 /* L3OHCR */
4416 spr_register(env, SPR_L3OHCR, "L3OHCR",
4417 SPR_NOACCESS, SPR_NOACCESS,
4418 &spr_read_generic, &spr_write_generic,
4419 0x00000000);
4420
4421 spr_register(env, SPR_UBAMR, "UBAMR",
4422 &spr_read_ureg, SPR_NOACCESS,
4423 &spr_read_ureg, SPR_NOACCESS,
4424 0x00000000);
4425 /* LDSTCR */
4426 spr_register(env, SPR_LDSTCR, "LDSTCR",
4427 SPR_NOACCESS, SPR_NOACCESS,
4428 &spr_read_generic, &spr_write_generic,
4429 0x00000000);
4430 /* ICTRL */
4431 spr_register(env, SPR_ICTRL, "ICTRL",
4432 SPR_NOACCESS, SPR_NOACCESS,
4433 &spr_read_generic, &spr_write_generic,
4434 0x00000000);
4435 /* MSSSR0 */
4436 spr_register(env, SPR_MSSSR0, "MSSSR0",
4437 SPR_NOACCESS, SPR_NOACCESS,
4438 &spr_read_generic, &spr_write_generic,
4439 0x00000000);
4440 /* PMC */
4441 spr_register(env, SPR_7XX_PMC5, "PMC5",
4442 SPR_NOACCESS, SPR_NOACCESS,
4443 &spr_read_generic, &spr_write_generic,
4444 0x00000000);
4445
4446 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
4447 &spr_read_ureg, SPR_NOACCESS,
4448 &spr_read_ureg, SPR_NOACCESS,
4449 0x00000000);
4450
4451 spr_register(env, SPR_7XX_PMC6, "PMC6",
4452 SPR_NOACCESS, SPR_NOACCESS,
4453 &spr_read_generic, &spr_write_generic,
4454 0x00000000);
4455
4456 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
4457 &spr_read_ureg, SPR_NOACCESS,
4458 &spr_read_ureg, SPR_NOACCESS,
4459 0x00000000);
4460 /* Memory management */
4461 register_low_BATs(env);
4462 init_excp_7450(env);
4463 env->dcache_line_size = 32;
4464 env->icache_line_size = 32;
4465 /* Allocate hardware IRQ controller */
4466 ppc6xx_irq_init(env_archcpu(env));
4467 }
4468
4469 POWERPC_FAMILY(7450)(ObjectClass *oc, const void *data)
4470 {
4471 DeviceClass *dc = DEVICE_CLASS(oc);
4472 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4473
4474 dc->desc = "PowerPC 7450 (aka G4)";
4475 pcc->init_proc = init_proc_7450;
4476 pcc->check_pow = check_pow_hid0_74xx;
4477 pcc->check_attn = check_attn_none;
4478 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4479 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4480 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
4481 PPC_FLOAT_STFIWX |
4482 PPC_CACHE | PPC_CACHE_ICBI |
4483 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
4484 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4485 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4486 PPC_MEM_TLBIA |
4487 PPC_SEGMENT | PPC_EXTERN |
4488 PPC_ALTIVEC;
4489 pcc->msr_mask = (1ull << MSR_VR) |
4490 (1ull << MSR_POW) |
4491 (1ull << MSR_ILE) |
4492 (1ull << MSR_EE) |
4493 (1ull << MSR_PR) |
4494 (1ull << MSR_FP) |
4495 (1ull << MSR_ME) |
4496 (1ull << MSR_FE0) |
4497 (1ull << MSR_SE) |
4498 (1ull << MSR_DE) |
4499 (1ull << MSR_FE1) |
4500 (1ull << MSR_EP) |
4501 (1ull << MSR_IR) |
4502 (1ull << MSR_DR) |
4503 (1ull << MSR_PMM) |
4504 (1ull << MSR_RI) |
4505 (1ull << MSR_LE);
4506 pcc->mmu_model = POWERPC_MMU_32B;
4507 pcc->excp_model = POWERPC_EXCP_74xx;
4508 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4509 pcc->bfd_mach = bfd_mach_ppc_7400;
4510 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
4511 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
4512 POWERPC_FLAG_BUS_CLK;
4513 }
4514
4515 static void init_proc_7445(CPUPPCState *env)
4516 {
4517 register_non_embedded_sprs(env);
4518 register_sdr1_sprs(env);
4519 register_74xx_sprs(env);
4520 vscr_init(env, 0x00010000);
4521 /* LDSTCR */
4522 spr_register(env, SPR_LDSTCR, "LDSTCR",
4523 SPR_NOACCESS, SPR_NOACCESS,
4524 &spr_read_generic, &spr_write_generic,
4525 0x00000000);
4526 /* ICTRL */
4527 spr_register(env, SPR_ICTRL, "ICTRL",
4528 SPR_NOACCESS, SPR_NOACCESS,
4529 &spr_read_generic, &spr_write_generic,
4530 0x00000000);
4531 /* MSSSR0 */
4532 spr_register(env, SPR_MSSSR0, "MSSSR0",
4533 SPR_NOACCESS, SPR_NOACCESS,
4534 &spr_read_generic, &spr_write_generic,
4535 0x00000000);
4536 /* PMC */
4537 spr_register(env, SPR_7XX_PMC5, "PMC5",
4538 SPR_NOACCESS, SPR_NOACCESS,
4539 &spr_read_generic, &spr_write_generic,
4540 0x00000000);
4541
4542 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
4543 &spr_read_ureg, SPR_NOACCESS,
4544 &spr_read_ureg, SPR_NOACCESS,
4545 0x00000000);
4546
4547 spr_register(env, SPR_7XX_PMC6, "PMC6",
4548 SPR_NOACCESS, SPR_NOACCESS,
4549 &spr_read_generic, &spr_write_generic,
4550 0x00000000);
4551
4552 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
4553 &spr_read_ureg, SPR_NOACCESS,
4554 &spr_read_ureg, SPR_NOACCESS,
4555 0x00000000);
4556 /* SPRGs */
4557 spr_register(env, SPR_SPRG4, "SPRG4",
4558 SPR_NOACCESS, SPR_NOACCESS,
4559 &spr_read_generic, &spr_write_generic,
4560 0x00000000);
4561 spr_register(env, SPR_USPRG4, "USPRG4",
4562 &spr_read_ureg, SPR_NOACCESS,
4563 &spr_read_ureg, SPR_NOACCESS,
4564 0x00000000);
4565 spr_register(env, SPR_SPRG5, "SPRG5",
4566 SPR_NOACCESS, SPR_NOACCESS,
4567 &spr_read_generic, &spr_write_generic,
4568 0x00000000);
4569 spr_register(env, SPR_USPRG5, "USPRG5",
4570 &spr_read_ureg, SPR_NOACCESS,
4571 &spr_read_ureg, SPR_NOACCESS,
4572 0x00000000);
4573 spr_register(env, SPR_SPRG6, "SPRG6",
4574 SPR_NOACCESS, SPR_NOACCESS,
4575 &spr_read_generic, &spr_write_generic,
4576 0x00000000);
4577 spr_register(env, SPR_USPRG6, "USPRG6",
4578 &spr_read_ureg, SPR_NOACCESS,
4579 &spr_read_ureg, SPR_NOACCESS,
4580 0x00000000);
4581 spr_register(env, SPR_SPRG7, "SPRG7",
4582 SPR_NOACCESS, SPR_NOACCESS,
4583 &spr_read_generic, &spr_write_generic,
4584 0x00000000);
4585 spr_register(env, SPR_USPRG7, "USPRG7",
4586 &spr_read_ureg, SPR_NOACCESS,
4587 &spr_read_ureg, SPR_NOACCESS,
4588 0x00000000);
4589 /* Memory management */
4590 register_low_BATs(env);
4591 register_high_BATs(env);
4592 init_excp_7450(env);
4593 env->dcache_line_size = 32;
4594 env->icache_line_size = 32;
4595 /* Allocate hardware IRQ controller */
4596 ppc6xx_irq_init(env_archcpu(env));
4597 }
4598
4599 POWERPC_FAMILY(7445)(ObjectClass *oc, const void *data)
4600 {
4601 DeviceClass *dc = DEVICE_CLASS(oc);
4602 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4603
4604 dc->desc = "PowerPC 7445 (aka G4)";
4605 pcc->init_proc = init_proc_7445;
4606 pcc->check_pow = check_pow_hid0_74xx;
4607 pcc->check_attn = check_attn_none;
4608 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4609 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4610 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
4611 PPC_FLOAT_STFIWX |
4612 PPC_CACHE | PPC_CACHE_ICBI |
4613 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
4614 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4615 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4616 PPC_MEM_TLBIA |
4617 PPC_SEGMENT | PPC_EXTERN |
4618 PPC_ALTIVEC;
4619 pcc->msr_mask = (1ull << MSR_VR) |
4620 (1ull << MSR_POW) |
4621 (1ull << MSR_ILE) |
4622 (1ull << MSR_EE) |
4623 (1ull << MSR_PR) |
4624 (1ull << MSR_FP) |
4625 (1ull << MSR_ME) |
4626 (1ull << MSR_FE0) |
4627 (1ull << MSR_SE) |
4628 (1ull << MSR_DE) |
4629 (1ull << MSR_FE1) |
4630 (1ull << MSR_EP) |
4631 (1ull << MSR_IR) |
4632 (1ull << MSR_DR) |
4633 (1ull << MSR_PMM) |
4634 (1ull << MSR_RI) |
4635 (1ull << MSR_LE);
4636 pcc->mmu_model = POWERPC_MMU_32B;
4637 pcc->excp_model = POWERPC_EXCP_74xx;
4638 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4639 pcc->bfd_mach = bfd_mach_ppc_7400;
4640 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
4641 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
4642 POWERPC_FLAG_BUS_CLK;
4643 }
4644
4645 static void init_proc_7455(CPUPPCState *env)
4646 {
4647 register_non_embedded_sprs(env);
4648 register_sdr1_sprs(env);
4649 register_74xx_sprs(env);
4650 vscr_init(env, 0x00010000);
4651 /* Level 3 cache control */
4652 register_l3_ctrl(env);
4653 /* LDSTCR */
4654 spr_register(env, SPR_LDSTCR, "LDSTCR",
4655 SPR_NOACCESS, SPR_NOACCESS,
4656 &spr_read_generic, &spr_write_generic,
4657 0x00000000);
4658 /* ICTRL */
4659 spr_register(env, SPR_ICTRL, "ICTRL",
4660 SPR_NOACCESS, SPR_NOACCESS,
4661 &spr_read_generic, &spr_write_generic,
4662 0x00000000);
4663 /* MSSSR0 */
4664 spr_register(env, SPR_MSSSR0, "MSSSR0",
4665 SPR_NOACCESS, SPR_NOACCESS,
4666 &spr_read_generic, &spr_write_generic,
4667 0x00000000);
4668 /* PMC */
4669 spr_register(env, SPR_7XX_PMC5, "PMC5",
4670 SPR_NOACCESS, SPR_NOACCESS,
4671 &spr_read_generic, &spr_write_generic,
4672 0x00000000);
4673
4674 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
4675 &spr_read_ureg, SPR_NOACCESS,
4676 &spr_read_ureg, SPR_NOACCESS,
4677 0x00000000);
4678
4679 spr_register(env, SPR_7XX_PMC6, "PMC6",
4680 SPR_NOACCESS, SPR_NOACCESS,
4681 &spr_read_generic, &spr_write_generic,
4682 0x00000000);
4683
4684 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
4685 &spr_read_ureg, SPR_NOACCESS,
4686 &spr_read_ureg, SPR_NOACCESS,
4687 0x00000000);
4688 /* SPRGs */
4689 spr_register(env, SPR_SPRG4, "SPRG4",
4690 SPR_NOACCESS, SPR_NOACCESS,
4691 &spr_read_generic, &spr_write_generic,
4692 0x00000000);
4693 spr_register(env, SPR_USPRG4, "USPRG4",
4694 &spr_read_ureg, SPR_NOACCESS,
4695 &spr_read_ureg, SPR_NOACCESS,
4696 0x00000000);
4697 spr_register(env, SPR_SPRG5, "SPRG5",
4698 SPR_NOACCESS, SPR_NOACCESS,
4699 &spr_read_generic, &spr_write_generic,
4700 0x00000000);
4701 spr_register(env, SPR_USPRG5, "USPRG5",
4702 &spr_read_ureg, SPR_NOACCESS,
4703 &spr_read_ureg, SPR_NOACCESS,
4704 0x00000000);
4705 spr_register(env, SPR_SPRG6, "SPRG6",
4706 SPR_NOACCESS, SPR_NOACCESS,
4707 &spr_read_generic, &spr_write_generic,
4708 0x00000000);
4709 spr_register(env, SPR_USPRG6, "USPRG6",
4710 &spr_read_ureg, SPR_NOACCESS,
4711 &spr_read_ureg, SPR_NOACCESS,
4712 0x00000000);
4713 spr_register(env, SPR_SPRG7, "SPRG7",
4714 SPR_NOACCESS, SPR_NOACCESS,
4715 &spr_read_generic, &spr_write_generic,
4716 0x00000000);
4717 spr_register(env, SPR_USPRG7, "USPRG7",
4718 &spr_read_ureg, SPR_NOACCESS,
4719 &spr_read_ureg, SPR_NOACCESS,
4720 0x00000000);
4721 /* Memory management */
4722 register_low_BATs(env);
4723 register_high_BATs(env);
4724 init_excp_7450(env);
4725 env->dcache_line_size = 32;
4726 env->icache_line_size = 32;
4727 /* Allocate hardware IRQ controller */
4728 ppc6xx_irq_init(env_archcpu(env));
4729 }
4730
4731 POWERPC_FAMILY(7455)(ObjectClass *oc, const void *data)
4732 {
4733 DeviceClass *dc = DEVICE_CLASS(oc);
4734 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4735
4736 dc->desc = "PowerPC 7455 (aka G4)";
4737 pcc->init_proc = init_proc_7455;
4738 pcc->check_pow = check_pow_hid0_74xx;
4739 pcc->check_attn = check_attn_none;
4740 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4741 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4742 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
4743 PPC_FLOAT_STFIWX |
4744 PPC_CACHE | PPC_CACHE_ICBI |
4745 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
4746 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4747 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4748 PPC_MEM_TLBIA |
4749 PPC_SEGMENT | PPC_EXTERN |
4750 PPC_ALTIVEC;
4751 pcc->msr_mask = (1ull << MSR_VR) |
4752 (1ull << MSR_POW) |
4753 (1ull << MSR_ILE) |
4754 (1ull << MSR_EE) |
4755 (1ull << MSR_PR) |
4756 (1ull << MSR_FP) |
4757 (1ull << MSR_ME) |
4758 (1ull << MSR_FE0) |
4759 (1ull << MSR_SE) |
4760 (1ull << MSR_DE) |
4761 (1ull << MSR_FE1) |
4762 (1ull << MSR_EP) |
4763 (1ull << MSR_IR) |
4764 (1ull << MSR_DR) |
4765 (1ull << MSR_PMM) |
4766 (1ull << MSR_RI) |
4767 (1ull << MSR_LE);
4768 pcc->mmu_model = POWERPC_MMU_32B;
4769 pcc->excp_model = POWERPC_EXCP_74xx;
4770 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4771 pcc->bfd_mach = bfd_mach_ppc_7400;
4772 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
4773 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
4774 POWERPC_FLAG_BUS_CLK;
4775 }
4776
4777 static void init_proc_7457(CPUPPCState *env)
4778 {
4779 register_non_embedded_sprs(env);
4780 register_sdr1_sprs(env);
4781 register_74xx_sprs(env);
4782 vscr_init(env, 0x00010000);
4783 /* Level 3 cache control */
4784 register_l3_ctrl(env);
4785 /* L3ITCR1 */
4786 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
4787 SPR_NOACCESS, SPR_NOACCESS,
4788 &spr_read_generic, &spr_write_generic,
4789 0x00000000);
4790 /* L3ITCR2 */
4791 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
4792 SPR_NOACCESS, SPR_NOACCESS,
4793 &spr_read_generic, &spr_write_generic,
4794 0x00000000);
4795 /* L3ITCR3 */
4796 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
4797 SPR_NOACCESS, SPR_NOACCESS,
4798 &spr_read_generic, &spr_write_generic,
4799 0x00000000);
4800 /* L3OHCR */
4801 spr_register(env, SPR_L3OHCR, "L3OHCR",
4802 SPR_NOACCESS, SPR_NOACCESS,
4803 &spr_read_generic, &spr_write_generic,
4804 0x00000000);
4805 /* LDSTCR */
4806 spr_register(env, SPR_LDSTCR, "LDSTCR",
4807 SPR_NOACCESS, SPR_NOACCESS,
4808 &spr_read_generic, &spr_write_generic,
4809 0x00000000);
4810 /* ICTRL */
4811 spr_register(env, SPR_ICTRL, "ICTRL",
4812 SPR_NOACCESS, SPR_NOACCESS,
4813 &spr_read_generic, &spr_write_generic,
4814 0x00000000);
4815 /* MSSSR0 */
4816 spr_register(env, SPR_MSSSR0, "MSSSR0",
4817 SPR_NOACCESS, SPR_NOACCESS,
4818 &spr_read_generic, &spr_write_generic,
4819 0x00000000);
4820 /* PMC */
4821 spr_register(env, SPR_7XX_PMC5, "PMC5",
4822 SPR_NOACCESS, SPR_NOACCESS,
4823 &spr_read_generic, &spr_write_generic,
4824 0x00000000);
4825
4826 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
4827 &spr_read_ureg, SPR_NOACCESS,
4828 &spr_read_ureg, SPR_NOACCESS,
4829 0x00000000);
4830
4831 spr_register(env, SPR_7XX_PMC6, "PMC6",
4832 SPR_NOACCESS, SPR_NOACCESS,
4833 &spr_read_generic, &spr_write_generic,
4834 0x00000000);
4835
4836 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
4837 &spr_read_ureg, SPR_NOACCESS,
4838 &spr_read_ureg, SPR_NOACCESS,
4839 0x00000000);
4840 /* SPRGs */
4841 spr_register(env, SPR_SPRG4, "SPRG4",
4842 SPR_NOACCESS, SPR_NOACCESS,
4843 &spr_read_generic, &spr_write_generic,
4844 0x00000000);
4845 spr_register(env, SPR_USPRG4, "USPRG4",
4846 &spr_read_ureg, SPR_NOACCESS,
4847 &spr_read_ureg, SPR_NOACCESS,
4848 0x00000000);
4849 spr_register(env, SPR_SPRG5, "SPRG5",
4850 SPR_NOACCESS, SPR_NOACCESS,
4851 &spr_read_generic, &spr_write_generic,
4852 0x00000000);
4853 spr_register(env, SPR_USPRG5, "USPRG5",
4854 &spr_read_ureg, SPR_NOACCESS,
4855 &spr_read_ureg, SPR_NOACCESS,
4856 0x00000000);
4857 spr_register(env, SPR_SPRG6, "SPRG6",
4858 SPR_NOACCESS, SPR_NOACCESS,
4859 &spr_read_generic, &spr_write_generic,
4860 0x00000000);
4861 spr_register(env, SPR_USPRG6, "USPRG6",
4862 &spr_read_ureg, SPR_NOACCESS,
4863 &spr_read_ureg, SPR_NOACCESS,
4864 0x00000000);
4865 spr_register(env, SPR_SPRG7, "SPRG7",
4866 SPR_NOACCESS, SPR_NOACCESS,
4867 &spr_read_generic, &spr_write_generic,
4868 0x00000000);
4869 spr_register(env, SPR_USPRG7, "USPRG7",
4870 &spr_read_ureg, SPR_NOACCESS,
4871 &spr_read_ureg, SPR_NOACCESS,
4872 0x00000000);
4873 /* Memory management */
4874 register_low_BATs(env);
4875 register_high_BATs(env);
4876 init_excp_7450(env);
4877 env->dcache_line_size = 32;
4878 env->icache_line_size = 32;
4879 /* Allocate hardware IRQ controller */
4880 ppc6xx_irq_init(env_archcpu(env));
4881 }
4882
4883 POWERPC_FAMILY(7457)(ObjectClass *oc, const void *data)
4884 {
4885 DeviceClass *dc = DEVICE_CLASS(oc);
4886 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4887
4888 dc->desc = "PowerPC 7457 (aka G4)";
4889 pcc->init_proc = init_proc_7457;
4890 pcc->check_pow = check_pow_hid0_74xx;
4891 pcc->check_attn = check_attn_none;
4892 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4893 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4894 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
4895 PPC_FLOAT_STFIWX |
4896 PPC_CACHE | PPC_CACHE_ICBI |
4897 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
4898 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4899 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4900 PPC_MEM_TLBIA |
4901 PPC_SEGMENT | PPC_EXTERN |
4902 PPC_ALTIVEC;
4903 pcc->msr_mask = (1ull << MSR_VR) |
4904 (1ull << MSR_POW) |
4905 (1ull << MSR_ILE) |
4906 (1ull << MSR_EE) |
4907 (1ull << MSR_PR) |
4908 (1ull << MSR_FP) |
4909 (1ull << MSR_ME) |
4910 (1ull << MSR_FE0) |
4911 (1ull << MSR_SE) |
4912 (1ull << MSR_DE) |
4913 (1ull << MSR_FE1) |
4914 (1ull << MSR_EP) |
4915 (1ull << MSR_IR) |
4916 (1ull << MSR_DR) |
4917 (1ull << MSR_PMM) |
4918 (1ull << MSR_RI) |
4919 (1ull << MSR_LE);
4920 pcc->mmu_model = POWERPC_MMU_32B;
4921 pcc->excp_model = POWERPC_EXCP_74xx;
4922 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4923 pcc->bfd_mach = bfd_mach_ppc_7400;
4924 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
4925 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
4926 POWERPC_FLAG_BUS_CLK;
4927 }
4928
4929 static void init_proc_e600(CPUPPCState *env)
4930 {
4931 register_non_embedded_sprs(env);
4932 register_sdr1_sprs(env);
4933 register_74xx_sprs(env);
4934 vscr_init(env, 0x00010000);
4935
4936 spr_register(env, SPR_UBAMR, "UBAMR",
4937 &spr_read_ureg, SPR_NOACCESS,
4938 &spr_read_ureg, SPR_NOACCESS,
4939 0x00000000);
4940
4941 spr_register(env, SPR_LDSTCR, "LDSTCR",
4942 SPR_NOACCESS, SPR_NOACCESS,
4943 &spr_read_generic, &spr_write_generic,
4944 0x00000000);
4945
4946 spr_register(env, SPR_ICTRL, "ICTRL",
4947 SPR_NOACCESS, SPR_NOACCESS,
4948 &spr_read_generic, &spr_write_generic,
4949 0x00000000);
4950
4951 spr_register(env, SPR_MSSSR0, "MSSSR0",
4952 SPR_NOACCESS, SPR_NOACCESS,
4953 &spr_read_generic, &spr_write_generic,
4954 0x00000000);
4955
4956 spr_register(env, SPR_7XX_PMC5, "PMC5",
4957 SPR_NOACCESS, SPR_NOACCESS,
4958 &spr_read_generic, &spr_write_generic,
4959 0x00000000);
4960
4961 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
4962 &spr_read_ureg, SPR_NOACCESS,
4963 &spr_read_ureg, SPR_NOACCESS,
4964 0x00000000);
4965
4966 spr_register(env, SPR_7XX_PMC6, "PMC6",
4967 SPR_NOACCESS, SPR_NOACCESS,
4968 &spr_read_generic, &spr_write_generic,
4969 0x00000000);
4970
4971 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
4972 &spr_read_ureg, SPR_NOACCESS,
4973 &spr_read_ureg, SPR_NOACCESS,
4974 0x00000000);
4975 /* SPRGs */
4976 spr_register(env, SPR_SPRG4, "SPRG4",
4977 SPR_NOACCESS, SPR_NOACCESS,
4978 &spr_read_generic, &spr_write_generic,
4979 0x00000000);
4980 spr_register(env, SPR_USPRG4, "USPRG4",
4981 &spr_read_ureg, SPR_NOACCESS,
4982 &spr_read_ureg, SPR_NOACCESS,
4983 0x00000000);
4984 spr_register(env, SPR_SPRG5, "SPRG5",
4985 SPR_NOACCESS, SPR_NOACCESS,
4986 &spr_read_generic, &spr_write_generic,
4987 0x00000000);
4988 spr_register(env, SPR_USPRG5, "USPRG5",
4989 &spr_read_ureg, SPR_NOACCESS,
4990 &spr_read_ureg, SPR_NOACCESS,
4991 0x00000000);
4992 spr_register(env, SPR_SPRG6, "SPRG6",
4993 SPR_NOACCESS, SPR_NOACCESS,
4994 &spr_read_generic, &spr_write_generic,
4995 0x00000000);
4996 spr_register(env, SPR_USPRG6, "USPRG6",
4997 &spr_read_ureg, SPR_NOACCESS,
4998 &spr_read_ureg, SPR_NOACCESS,
4999 0x00000000);
5000 spr_register(env, SPR_SPRG7, "SPRG7",
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