kvm.c · samitouri/QOSamiQemu · siGit Code & Deploy

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1	/*
2	* PowerPC implementation of KVM hooks
3	*
4	* Copyright IBM Corp. 2007
5	* Copyright (C) 2011 Freescale Semiconductor, Inc.
6	*
7	* Authors:
8	* Jerone Young <jyoung5@us.ibm.com>
9	* Christian Ehrhardt <ehrhardt@linux.vnet.ibm.com>
10	* Hollis Blanchard <hollisb@us.ibm.com>
11	*
12	* This work is licensed under the terms of the GNU GPL, version 2 or later.
13	* See the COPYING file in the top-level directory.
14	*
15	*/
16
17	#include "qemu/osdep.h"
18	#include <dirent.h>
19	#include <sys/ioctl.h>
20	#include <sys/vfs.h>
21
22	#include <linux/kvm.h>
23
24	#include "qapi/error.h"
25	#include "qemu/error-report.h"
26	#include "cpu.h"
27	#include "cpu-models.h"
28	#include "qemu/timer.h"
29	#include "system/hw_accel.h"
30	#include "kvm_ppc.h"
31	#include "system/cpus.h"
32	#include "system/device_tree.h"
33	#include "mmu-hash64.h"
34
35	#include "hw/ppc/spapr.h"
36	#include "hw/ppc/spapr_cpu_core.h"
37	#include "hw/core/hw-error.h"
38	#include "hw/ppc/ppc.h"
39	#include "migration/qemu-file-types.h"
40	#include "system/watchdog.h"
41	#include "trace.h"
42	#include "gdbstub/enums.h"
43	#include "exec/memattrs.h"
44	#include "system/ramblock.h"
45	#include "system/hostmem.h"
46	#include "qemu/cutils.h"
47	#include "qemu/main-loop.h"
48	#include "qemu/mmap-alloc.h"
49	#include "elf.h"
50	#include "system/kvm_int.h"
51	#include "system/kvm.h"
52	#include "accel/accel-cpu-target.h"
53
54	#include CONFIG_DEVICES
55
56	#define PROC_DEVTREE_CPU "/proc/device-tree/cpus/"
57
58	#define DEBUG_RETURN_GUEST 0
59	#define DEBUG_RETURN_GDB 1
60
61	const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
62	KVM_CAP_LAST_INFO
63	};
64
65	static int cap_interrupt_unset;
66	static int cap_segstate;
67	static int cap_booke_sregs;
68	static int cap_ppc_smt;
69	static int cap_ppc_smt_possible;
70	static int cap_spapr_tce;
71	static int cap_spapr_tce_64;
72	static int cap_spapr_multitce;
73	static int cap_spapr_vfio;
74	static int cap_hior;
75	static int cap_one_reg;
76	static int cap_epr;
77	static int cap_ppc_watchdog;
78	static int cap_htab_fd;
79	static int cap_fixup_hcalls;
80	static int cap_htm; /* Hardware transactional memory support */
81	static int cap_mmu_radix;
82	static int cap_mmu_hash_v3;
83	static int cap_xive;
84	static int cap_resize_hpt;
85	static int cap_ppc_pvr_compat;
86	static int cap_ppc_safe_cache;
87	static int cap_ppc_safe_bounds_check;
88	static int cap_ppc_safe_indirect_branch;
89	static int cap_ppc_count_cache_flush_assist;
90	static int cap_ppc_nested_kvm_hv;
91	static int cap_large_decr;
92	static int cap_fwnmi;
93	static int cap_rpt_invalidate;
94	static int cap_ail_mode_3;
95	static int cap_dawr1;
96
97	#ifdef CONFIG_PSERIES
98	static int cap_papr;
99	#else
100	#define cap_papr (0)
101	#endif
102
103	static uint32_t debug_inst_opcode;
104
105	/*
106	* Check whether we are running with KVM-PR (instead of KVM-HV). This
107	* should only be used for fallback tests - generally we should use
108	* explicit capabilities for the features we want, rather than
109	* assuming what is/isn't available depending on the KVM variant.
110	*/
111	static bool kvmppc_is_pr(KVMState *ks)
112	{
113	/* Assume KVM-PR if the GET_PVINFO capability is available */
114	return kvm_vm_check_extension(ks, KVM_CAP_PPC_GET_PVINFO) != 0;
115	}
116
117	static int kvm_ppc_register_host_cpu_type(void);
118	static void kvmppc_get_cpu_characteristics(KVMState *s);
119	static int kvmppc_get_dec_bits(void);
120
121	int kvm_arch_get_default_type(MachineState *ms)
122	{
123	return 0;
124	}
125
126	int kvm_arch_init(MachineState ms, KVMState s)
127	{
128	cap_interrupt_unset = kvm_check_extension(s, KVM_CAP_PPC_UNSET_IRQ);
129	cap_segstate = kvm_check_extension(s, KVM_CAP_PPC_SEGSTATE);
130	cap_booke_sregs = kvm_check_extension(s, KVM_CAP_PPC_BOOKE_SREGS);
131	cap_ppc_smt_possible = kvm_vm_check_extension(s, KVM_CAP_PPC_SMT_POSSIBLE);
132	cap_spapr_tce = kvm_check_extension(s, KVM_CAP_SPAPR_TCE);
133	cap_spapr_tce_64 = kvm_check_extension(s, KVM_CAP_SPAPR_TCE_64);
134	cap_spapr_multitce = kvm_check_extension(s, KVM_CAP_SPAPR_MULTITCE);
135	cap_spapr_vfio = kvm_vm_check_extension(s, KVM_CAP_SPAPR_TCE_VFIO);
136	cap_one_reg = kvm_check_extension(s, KVM_CAP_ONE_REG);
137	cap_hior = kvm_check_extension(s, KVM_CAP_PPC_HIOR);
138	cap_epr = kvm_check_extension(s, KVM_CAP_PPC_EPR);
139	cap_ppc_watchdog = kvm_check_extension(s, KVM_CAP_PPC_BOOKE_WATCHDOG);
140	/*
141	* Note: we don't set cap_papr here, because this capability is
142	* only activated after this by kvmppc_set_papr()
143	*/
144	cap_htab_fd = kvm_vm_check_extension(s, KVM_CAP_PPC_HTAB_FD);
145	cap_fixup_hcalls = kvm_check_extension(s, KVM_CAP_PPC_FIXUP_HCALL);
146	cap_ppc_smt = kvm_vm_check_extension(s, KVM_CAP_PPC_SMT);
147	cap_htm = kvm_vm_check_extension(s, KVM_CAP_PPC_HTM);
148	cap_mmu_radix = kvm_vm_check_extension(s, KVM_CAP_PPC_MMU_RADIX);
149	cap_mmu_hash_v3 = kvm_vm_check_extension(s, KVM_CAP_PPC_MMU_HASH_V3);
150	cap_xive = kvm_vm_check_extension(s, KVM_CAP_PPC_IRQ_XIVE);
151	cap_resize_hpt = kvm_vm_check_extension(s, KVM_CAP_SPAPR_RESIZE_HPT);
152	kvmppc_get_cpu_characteristics(s);
153	cap_ppc_nested_kvm_hv = kvm_vm_check_extension(s, KVM_CAP_PPC_NESTED_HV);
154	cap_large_decr = kvmppc_get_dec_bits();
155	cap_fwnmi = kvm_vm_check_extension(s, KVM_CAP_PPC_FWNMI);
156	cap_dawr1 = kvm_vm_check_extension(s, KVM_CAP_PPC_DAWR1);
157	/*
158	* Note: setting it to false because there is not such capability
159	* in KVM at this moment.
160	*
161	* TODO: call kvm_vm_check_extension() with the right capability
162	* after the kernel starts implementing it.
163	*/
164	cap_ppc_pvr_compat = false;
165
166	if (!kvm_check_extension(s, KVM_CAP_PPC_IRQ_LEVEL)) {
167	error_report("KVM: Host kernel doesn't have level irq capability");
168	exit(1);
169	}
170
171	cap_rpt_invalidate = kvm_vm_check_extension(s, KVM_CAP_PPC_RPT_INVALIDATE);
172	cap_ail_mode_3 = kvm_vm_check_extension(s, KVM_CAP_PPC_AIL_MODE_3);
173	kvm_ppc_register_host_cpu_type();
174
175	return 0;
176	}
177
178	int kvm_arch_irqchip_create(KVMState *s)
179	{
180	return 0;
181	}
182
183	static int kvm_arch_sync_sregs(PowerPCCPU *cpu)
184	{
185	CPUPPCState *cenv = &cpu->env;
186	CPUState *cs = CPU(cpu);
187	struct kvm_sregs sregs;
188	int ret;
189
190	if (cenv->excp_model == POWERPC_EXCP_BOOKE) {
191	/*
192	* What we're really trying to say is "if we're on BookE, we
193	* use the native PVR for now". This is the only sane way to
194	* check it though, so we potentially confuse users that they
195	* can run BookE guests on BookS. Let's hope nobody dares
196	* enough :)
197	*/
198	return 0;
199	} else {
200	if (!cap_segstate) {
201	fprintf(stderr, "kvm error: missing PVR setting capability\n");
202	return -ENOSYS;
203	}
204	}
205
206	ret = kvm_vcpu_ioctl(cs, KVM_GET_SREGS, &sregs);
207	if (ret) {
208	return ret;
209	}
210
211	sregs.pvr = cenv->spr[SPR_PVR];
212	return kvm_vcpu_ioctl(cs, KVM_SET_SREGS, &sregs);
213	}
214
215	/* Set up a shared TLB array with KVM */
216	static int kvm_booke206_tlb_init(PowerPCCPU *cpu)
217	{
218	CPUPPCState *env = &cpu->env;
219	CPUState *cs = CPU(cpu);
220	struct kvm_book3e_206_tlb_params params = {};
221	struct kvm_config_tlb cfg = {};
222	unsigned int entries = 0;
223	int ret, i;
224
225	if (!kvm_enabled() \|\|
226	!kvm_check_extension(cs->kvm_state, KVM_CAP_SW_TLB)) {
227	return 0;
228	}
229
230	assert(ARRAY_SIZE(params.tlb_sizes) == BOOKE206_MAX_TLBN);
231
232	for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
233	params.tlb_sizes[i] = booke206_tlb_size(env, i);
234	params.tlb_ways[i] = booke206_tlb_ways(env, i);
235	entries += params.tlb_sizes[i];
236	}
237
238	assert(entries == env->nb_tlb);
239	assert(sizeof(struct kvm_book3e_206_tlb_entry) == sizeof(ppcmas_tlb_t));
240
241	env->tlb_dirty = true;
242
243	cfg.array = (uintptr_t)env->tlb.tlbm;
244	cfg.array_len = sizeof(ppcmas_tlb_t) * entries;
245	cfg.params = (uintptr_t)&params;
246	cfg.mmu_type = KVM_MMU_FSL_BOOKE_NOHV;
247
248	ret = kvm_vcpu_enable_cap(cs, KVM_CAP_SW_TLB, 0, (uintptr_t)&cfg);
249	if (ret < 0) {
250	fprintf(stderr, "%s: couldn't enable KVM_CAP_SW_TLB: %s\n",
251	__func__, strerror(-ret));
252	return ret;
253	}
254
255	env->kvm_sw_tlb = true;
256	return 0;
257	}
258
259
260	#if defined(TARGET_PPC64)
261	static void kvm_get_smmu_info(struct kvm_ppc_smmu_info info, Error *errp)
262	{
263	int ret;
264
265	assert(kvm_state != NULL);
266
267	if (!kvm_check_extension(kvm_state, KVM_CAP_PPC_GET_SMMU_INFO)) {
268	error_setg(errp, "KVM doesn't expose the MMU features it supports");
269	error_append_hint(errp, "Consider switching to a newer KVM\n");
270	return;
271	}
272
273	ret = kvm_vm_ioctl(kvm_state, KVM_PPC_GET_SMMU_INFO, info);
274	if (ret == 0) {
275	return;
276	}
277
278	error_setg_errno(errp, -ret,
279	"KVM failed to provide the MMU features it supports");
280	}
281
282	static struct ppc_radix_page_info *kvmppc_get_radix_page_info(void)
283	{
284	KVMState *s = KVM_STATE(current_accel());
285	struct ppc_radix_page_info *radix_page_info;
286	struct kvm_ppc_rmmu_info rmmu_info = { };
287	int i;
288
289	if (!kvm_check_extension(s, KVM_CAP_PPC_MMU_RADIX)) {
290	return NULL;
291	}
292	if (kvm_vm_ioctl(s, KVM_PPC_GET_RMMU_INFO, &rmmu_info)) {
293	return NULL;
294	}
295	radix_page_info = g_malloc0(sizeof(*radix_page_info));
296	radix_page_info->count = 0;
297	for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) {
298	if (rmmu_info.ap_encodings[i]) {
299	radix_page_info->entries[i] = rmmu_info.ap_encodings[i];
300	radix_page_info->count++;
301	}
302	}
303	return radix_page_info;
304	}
305
306	target_ulong kvmppc_configure_v3_mmu(PowerPCCPU *cpu,
307	bool radix, bool gtse,
308	uint64_t proc_tbl)
309	{
310	CPUState *cs = CPU(cpu);
311	int ret;
312	uint64_t flags = 0;
313	struct kvm_ppc_mmuv3_cfg cfg = {
314	.process_table = proc_tbl,
315	};
316
317	if (radix) {
318	flags \|= KVM_PPC_MMUV3_RADIX;
319	}
320	if (gtse) {
321	flags \|= KVM_PPC_MMUV3_GTSE;
322	}
323	cfg.flags = flags;
324	ret = kvm_vm_ioctl(cs->kvm_state, KVM_PPC_CONFIGURE_V3_MMU, &cfg);
325	switch (ret) {
326	case 0:
327	return H_SUCCESS;
328	case -EINVAL:
329	return H_PARAMETER;
330	case -ENODEV:
331	return H_NOT_AVAILABLE;
332	default:
333	return H_HARDWARE;
334	}
335	}
336
337	bool kvmppc_hpt_needs_host_contiguous_pages(void)
338	{
339	static struct kvm_ppc_smmu_info smmu_info;
340
341	if (!kvm_enabled()) {
342	return false;
343	}
344
345	kvm_get_smmu_info(&smmu_info, &error_fatal);
346	return !!(smmu_info.flags & KVM_PPC_PAGE_SIZES_REAL);
347	}
348
349	void kvm_check_mmu(PowerPCCPU cpu, Error *errp)
350	{
351	struct kvm_ppc_smmu_info smmu_info;
352	int iq, ik, jq, jk;
353	Error *local_err = NULL;
354
355	/* For now, we only have anything to check on hash64 MMUs */
356	if (!cpu->hash64_opts \|\| !kvm_enabled()) {
357	return;
358	}
359
360	kvm_get_smmu_info(&smmu_info, &local_err);
361	if (local_err) {
362	error_propagate(errp, local_err);
363	return;
364	}
365
366	if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)
367	&& !(smmu_info.flags & KVM_PPC_1T_SEGMENTS)) {
368	error_setg(errp,
369	"KVM does not support 1TiB segments which guest expects");
370	return;
371	}
372
373	if (smmu_info.slb_size < cpu->hash64_opts->slb_size) {
374	error_setg(errp, "KVM only supports %u SLB entries, but guest needs %u",
375	smmu_info.slb_size, cpu->hash64_opts->slb_size);
376	return;
377	}
378
379	/*
380	* Verify that every pagesize supported by the cpu model is
381	* supported by KVM with the same encodings
382	*/
383	for (iq = 0; iq < ARRAY_SIZE(cpu->hash64_opts->sps); iq++) {
384	PPCHash64SegmentPageSizes *qsps = &cpu->hash64_opts->sps[iq];
385	struct kvm_ppc_one_seg_page_size *ksps;
386
387	for (ik = 0; ik < ARRAY_SIZE(smmu_info.sps); ik++) {
388	if (qsps->page_shift == smmu_info.sps[ik].page_shift) {
389	break;
390	}
391	}
392	if (ik >= ARRAY_SIZE(smmu_info.sps)) {
393	error_setg(errp, "KVM doesn't support for base page shift %u",
394	qsps->page_shift);
395	return;
396	}
397
398	ksps = &smmu_info.sps[ik];
399	if (ksps->slb_enc != qsps->slb_enc) {
400	error_setg(errp,
401	"KVM uses SLB encoding 0x%x for page shift %u, but guest expects 0x%x",
402	ksps->slb_enc, ksps->page_shift, qsps->slb_enc);
403	return;
404	}
405
406	for (jq = 0; jq < ARRAY_SIZE(qsps->enc); jq++) {
407	for (jk = 0; jk < ARRAY_SIZE(ksps->enc); jk++) {
408	if (qsps->enc[jq].page_shift == ksps->enc[jk].page_shift) {
409	break;
410	}
411	}
412
413	if (jk >= ARRAY_SIZE(ksps->enc)) {
414	error_setg(errp, "KVM doesn't support page shift %u/%u",
415	qsps->enc[jq].page_shift, qsps->page_shift);
416	return;
417	}
418	if (qsps->enc[jq].pte_enc != ksps->enc[jk].pte_enc) {
419	error_setg(errp,
420	"KVM uses PTE encoding 0x%x for page shift %u/%u, but guest expects 0x%x",
421	ksps->enc[jk].pte_enc, qsps->enc[jq].page_shift,
422	qsps->page_shift, qsps->enc[jq].pte_enc);
423	return;
424	}
425	}
426	}
427
428	if (ppc_hash64_has(cpu, PPC_HASH64_CI_LARGEPAGE)) {
429	/*
430	* Mostly what guest pagesizes we can use are related to the
431	* host pages used to map guest RAM, which is handled in the
432	* platform code. Cache-Inhibited largepages (64k) however are
433	* used for I/O, so if they're mapped to the host at all it
434	* will be a normal mapping, not a special hugepage one used
435	* for RAM.
436	*/
437	if (qemu_real_host_page_size() < 0x10000) {
438	error_setg(errp,
439	"KVM can't supply 64kiB CI pages, which guest expects");
440	}
441	}
442	}
443	#endif /* !defined (TARGET_PPC64) */
444
445	unsigned long kvm_arch_vcpu_id(CPUState *cpu)
446	{
447	return POWERPC_CPU(cpu)->vcpu_id;
448	}
449
450	/*
451	* e500 supports 2 h/w breakpoint and 2 watchpoint. book3s supports
452	* only 1 watchpoint, so array size of 4 is sufficient for now.
453	*/
454	#define MAX_HW_BKPTS 4
455
456	static struct HWBreakpoint {
457	target_ulong addr;
458	GdbBreakpointType type;
459	} hw_debug_points[MAX_HW_BKPTS];
460
461	static CPUWatchpoint hw_watchpoint;
462
463	/* Default there is no breakpoint and watchpoint supported */
464	static int max_hw_breakpoint;
465	static int max_hw_watchpoint;
466	static int nb_hw_breakpoint;
467	static int nb_hw_watchpoint;
468
469	static void kvmppc_hw_debug_points_init(CPUPPCState *cenv)
470	{
471	if (cenv->excp_model == POWERPC_EXCP_BOOKE) {
472	max_hw_breakpoint = 2;
473	max_hw_watchpoint = 2;
474	}
475
476	if ((max_hw_breakpoint + max_hw_watchpoint) > MAX_HW_BKPTS) {
477	fprintf(stderr, "Error initializing h/w breakpoints\n");
478	return;
479	}
480	}
481
482	int kvm_arch_pre_create_vcpu(CPUState cpu, Error *errp)
483	{
484	return 0;
485	}
486
487	int kvm_arch_init_vcpu(CPUState *cs)
488	{
489	PowerPCCPU *cpu = POWERPC_CPU(cs);
490	CPUPPCState *cenv = &cpu->env;
491	int ret;
492
493	/* Synchronize sregs with kvm */
494	ret = kvm_arch_sync_sregs(cpu);
495	if (ret) {
496	if (ret == -EINVAL) {
497	error_report("Register sync failed... If you're using kvm-hv.ko,"
498	" only \"-cpu host\" is possible");
499	}
500	return ret;
501	}
502
503	switch (cenv->mmu_model) {
504	case POWERPC_MMU_BOOKE206:
505	/* This target supports access to KVM's guest TLB */
506	ret = kvm_booke206_tlb_init(cpu);
507	break;
508	case POWERPC_MMU_2_07:
509	if (!cap_htm && !kvmppc_is_pr(cs->kvm_state)) {
510	/*
511	* KVM-HV has transactional memory on POWER8 also without
512	* the KVM_CAP_PPC_HTM extension, so enable it here
513	* instead as long as it's available to userspace on the
514	* host.
515	*/
516	if (qemu_getauxval(AT_HWCAP2) & PPC_FEATURE2_HAS_HTM) {
517	cap_htm = true;
518	}
519	}
520	break;
521	default:
522	break;
523	}
524
525	kvm_get_one_reg(cs, KVM_REG_PPC_DEBUG_INST, &debug_inst_opcode);
526	kvmppc_hw_debug_points_init(cenv);
527
528	return ret;
529	}
530
531	int kvm_arch_destroy_vcpu(CPUState *cs)
532	{
533	return 0;
534	}
535
536	static void kvm_sw_tlb_put(PowerPCCPU *cpu)
537	{
538	CPUPPCState *env = &cpu->env;
539	CPUState *cs = CPU(cpu);
540	struct kvm_dirty_tlb dirty_tlb;
541	unsigned char *bitmap;
542	int ret;
543
544	if (!env->kvm_sw_tlb) {
545	return;
546	}
547
548	bitmap = g_malloc((env->nb_tlb + 7) / 8);
549	memset(bitmap, 0xFF, (env->nb_tlb + 7) / 8);
550
551	dirty_tlb.bitmap = (uintptr_t)bitmap;
552	dirty_tlb.num_dirty = env->nb_tlb;
553
554	ret = kvm_vcpu_ioctl(cs, KVM_DIRTY_TLB, &dirty_tlb);
555	if (ret) {
556	fprintf(stderr, "%s: KVM_DIRTY_TLB: %s\n",
557	__func__, strerror(-ret));
558	}
559
560	g_free(bitmap);
561	}
562
563	static void kvm_get_one_spr(CPUState *cs, uint64_t id, int spr)
564	{
565	CPUPPCState *env = cpu_env(cs);
566	/* Init 'val' to avoid "uninitialised value" Valgrind warnings */
567	union {
568	uint32_t u32;
569	uint64_t u64;
570	} val = { };
571	struct kvm_one_reg reg = {
572	.id = id,
573	.addr = (uintptr_t) &val,
574	};
575	int ret;
576
577	ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
578	if (ret != 0) {
579	trace_kvm_failed_spr_get(spr, strerror(errno));
580	} else {
581	switch (id & KVM_REG_SIZE_MASK) {
582	case KVM_REG_SIZE_U32:
583	env->spr[spr] = val.u32;
584	break;
585
586	case KVM_REG_SIZE_U64:
587	env->spr[spr] = val.u64;
588	break;
589
590	default:
591	/* Don't handle this size yet */
592	abort();
593	}
594	}
595	}
596
597	static void kvm_put_one_spr(CPUState *cs, uint64_t id, int spr)
598	{
599	CPUPPCState *env = cpu_env(cs);
600	union {
601	uint32_t u32;
602	uint64_t u64;
603	} val;
604	struct kvm_one_reg reg = {
605	.id = id,
606	.addr = (uintptr_t) &val,
607	};
608	int ret;
609
610	switch (id & KVM_REG_SIZE_MASK) {
611	case KVM_REG_SIZE_U32:
612	val.u32 = env->spr[spr];
613	break;
614
615	case KVM_REG_SIZE_U64:
616	val.u64 = env->spr[spr];
617	break;
618
619	default:
620	/* Don't handle this size yet */
621	abort();
622	}
623
624	ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
625	if (ret != 0) {
626	trace_kvm_failed_spr_set(spr, strerror(errno));
627	}
628	}
629
630	static int kvm_put_fp(CPUState *cs)
631	{
632	CPUPPCState *env = cpu_env(cs);
633	struct kvm_one_reg reg;
634	int i;
635	int ret;
636
637	if (env->insns_flags & PPC_FLOAT) {
638	uint64_t fpscr = env->fpscr;
639	bool vsx = !!(env->insns_flags2 & PPC2_VSX);
640
641	reg.id = KVM_REG_PPC_FPSCR;
642	reg.addr = (uintptr_t)&fpscr;
643	ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
644	if (ret < 0) {
645	trace_kvm_failed_fpscr_set(strerror(errno));
646	return ret;
647	}
648
649	for (i = 0; i < 32; i++) {
650	uint64_t vsr[2];
651	uint64_t *fpr = cpu_fpr_ptr(env, i);
652	uint64_t *vsrl = cpu_vsrl_ptr(env, i);
653
654	#if HOST_BIG_ENDIAN
655	vsr[0] = float64_val(*fpr);
656	vsr[1] = *vsrl;
657	#else
658	vsr[0] = *vsrl;
659	vsr[1] = float64_val(*fpr);
660	#endif
661	reg.addr = (uintptr_t) &vsr;
662	reg.id = vsx ? KVM_REG_PPC_VSR(i) : KVM_REG_PPC_FPR(i);
663
664	ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
665	if (ret < 0) {
666	trace_kvm_failed_fp_set(vsx ? "VSR" : "FPR", i,
667	strerror(errno));
668	return ret;
669	}
670	}
671	}
672
673	if (env->insns_flags & PPC_ALTIVEC) {
674	reg.id = KVM_REG_PPC_VSCR;
675	reg.addr = (uintptr_t)&env->vscr;
676	ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
677	if (ret < 0) {
678	trace_kvm_failed_vscr_set(strerror(errno));
679	return ret;
680	}
681
682	for (i = 0; i < 32; i++) {
683	reg.id = KVM_REG_PPC_VR(i);
684	reg.addr = (uintptr_t)cpu_avr_ptr(env, i);
685	ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
686	if (ret < 0) {
687	trace_kvm_failed_vr_set(i, strerror(errno));
688	return ret;
689	}
690	}
691	}
692
693	return 0;
694	}
695
696	static int kvm_get_fp(CPUState *cs)
697	{
698	CPUPPCState *env = cpu_env(cs);
699	struct kvm_one_reg reg;
700	int i;
701	int ret;
702
703	if (env->insns_flags & PPC_FLOAT) {
704	uint64_t fpscr;
705	bool vsx = !!(env->insns_flags2 & PPC2_VSX);
706
707	reg.id = KVM_REG_PPC_FPSCR;
708	reg.addr = (uintptr_t)&fpscr;
709	ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
710	if (ret < 0) {
711	trace_kvm_failed_fpscr_get(strerror(errno));
712	return ret;
713	} else {
714	env->fpscr = fpscr;
715	}
716
717	for (i = 0; i < 32; i++) {
718	uint64_t vsr[2];
719	uint64_t *fpr = cpu_fpr_ptr(env, i);
720	uint64_t *vsrl = cpu_vsrl_ptr(env, i);
721
722	reg.addr = (uintptr_t) &vsr;
723	reg.id = vsx ? KVM_REG_PPC_VSR(i) : KVM_REG_PPC_FPR(i);
724
725	ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
726	if (ret < 0) {
727	trace_kvm_failed_fp_get(vsx ? "VSR" : "FPR", i,
728	strerror(errno));
729	return ret;
730	} else {
731	#if HOST_BIG_ENDIAN
732	*fpr = vsr[0];
733	if (vsx) {
734	*vsrl = vsr[1];
735	}
736	#else
737	*fpr = vsr[1];
738	if (vsx) {
739	*vsrl = vsr[0];
740	}
741	#endif
742	}
743	}
744	}
745
746	if (env->insns_flags & PPC_ALTIVEC) {
747	reg.id = KVM_REG_PPC_VSCR;
748	reg.addr = (uintptr_t)&env->vscr;
749	ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
750	if (ret < 0) {
751	trace_kvm_failed_vscr_get(strerror(errno));
752	return ret;
753	}
754
755	for (i = 0; i < 32; i++) {
756	reg.id = KVM_REG_PPC_VR(i);
757	reg.addr = (uintptr_t)cpu_avr_ptr(env, i);
758	ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
759	if (ret < 0) {
760	trace_kvm_failed_vr_get(i, strerror(errno));
761	return ret;
762	}
763	}
764	}
765
766	return 0;
767	}
768
769	#if defined(TARGET_PPC64)
770	static int kvm_get_vpa(CPUState *cs)
771	{
772	PowerPCCPU *cpu = POWERPC_CPU(cs);
773	SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
774	struct kvm_one_reg reg;
775	int ret;
776
777	reg.id = KVM_REG_PPC_VPA_ADDR;
778	reg.addr = (uintptr_t)&spapr_cpu->vpa_addr;
779	ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
780	if (ret < 0) {
781	trace_kvm_failed_vpa_addr_get(strerror(errno));
782	return ret;
783	}
784
785	assert((uintptr_t)&spapr_cpu->slb_shadow_size
786	== ((uintptr_t)&spapr_cpu->slb_shadow_addr + 8));
787	reg.id = KVM_REG_PPC_VPA_SLB;
788	reg.addr = (uintptr_t)&spapr_cpu->slb_shadow_addr;
789	ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
790	if (ret < 0) {
791	trace_kvm_failed_slb_get(strerror(errno));
792	return ret;
793	}
794
795	assert((uintptr_t)&spapr_cpu->dtl_size
796	== ((uintptr_t)&spapr_cpu->dtl_addr + 8));
797	reg.id = KVM_REG_PPC_VPA_DTL;
798	reg.addr = (uintptr_t)&spapr_cpu->dtl_addr;
799	ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
800	if (ret < 0) {
801	trace_kvm_failed_dtl_get(strerror(errno));
802	return ret;
803	}
804
805	return 0;
806	}
807
808	static int kvm_put_vpa(CPUState *cs)
809	{
810	PowerPCCPU *cpu = POWERPC_CPU(cs);
811	SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
812	struct kvm_one_reg reg;
813	int ret;
814
815	/*
816	* SLB shadow or DTL can't be registered unless a master VPA is
817	* registered. That means when restoring state, if a VPA is
818	* registered, we need to set that up first. If not, we need to
819	* deregister the others before deregistering the master VPA
820	*/
821	assert(spapr_cpu->vpa_addr
822	\|\| !(spapr_cpu->slb_shadow_addr \|\| spapr_cpu->dtl_addr));
823
824	if (spapr_cpu->vpa_addr) {
825	reg.id = KVM_REG_PPC_VPA_ADDR;
826	reg.addr = (uintptr_t)&spapr_cpu->vpa_addr;
827	ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
828	if (ret < 0) {
829	trace_kvm_failed_vpa_addr_set(strerror(errno));
830	return ret;
831	}
832	}
833
834	assert((uintptr_t)&spapr_cpu->slb_shadow_size
835	== ((uintptr_t)&spapr_cpu->slb_shadow_addr + 8));
836	reg.id = KVM_REG_PPC_VPA_SLB;
837	reg.addr = (uintptr_t)&spapr_cpu->slb_shadow_addr;
838	ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
839	if (ret < 0) {
840	trace_kvm_failed_slb_set(strerror(errno));
841	return ret;
842	}
843
844	assert((uintptr_t)&spapr_cpu->dtl_size
845	== ((uintptr_t)&spapr_cpu->dtl_addr + 8));
846	reg.id = KVM_REG_PPC_VPA_DTL;
847	reg.addr = (uintptr_t)&spapr_cpu->dtl_addr;
848	ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
849	if (ret < 0) {
850	trace_kvm_failed_dtl_set(strerror(errno));
851	return ret;
852	}
853
854	if (!spapr_cpu->vpa_addr) {
855	reg.id = KVM_REG_PPC_VPA_ADDR;
856	reg.addr = (uintptr_t)&spapr_cpu->vpa_addr;
857	ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
858	if (ret < 0) {
859	trace_kvm_failed_null_vpa_addr_set(strerror(errno));
860	return ret;
861	}
862	}
863
864	return 0;
865	}
866	#endif /* TARGET_PPC64 */
867
868	int kvmppc_put_books_sregs(PowerPCCPU *cpu)
869	{
870	CPUPPCState *env = &cpu->env;
871	struct kvm_sregs sregs = { };
872	int i;
873
874	sregs.pvr = env->spr[SPR_PVR];
875
876	if (cpu->vhyp) {
877	sregs.u.s.sdr1 = cpu->vhyp_class->encode_hpt_for_kvm_pr(cpu->vhyp);
878	} else {
879	sregs.u.s.sdr1 = env->spr[SPR_SDR1];
880	}
881
882	/* Sync SLB */
883	#ifdef TARGET_PPC64
884	for (i = 0; i < ARRAY_SIZE(env->slb); i++) {
885	sregs.u.s.ppc64.slb[i].slbe = env->slb[i].esid;
886	if (env->slb[i].esid & SLB_ESID_V) {
887	sregs.u.s.ppc64.slb[i].slbe \|= i;
888	}
889	sregs.u.s.ppc64.slb[i].slbv = env->slb[i].vsid;
890	}
891	#endif
892
893	/* Sync SRs */
894	for (i = 0; i < 16; i++) {
895	sregs.u.s.ppc32.sr[i] = env->sr[i];
896	}
897
898	/* Sync BATs */
899	for (i = 0; i < 8; i++) {
900	/* Beware. We have to swap upper and lower bits here */
901	sregs.u.s.ppc32.dbat[i] = ((uint64_t)env->DBAT[0][i] << 32)
902	\| env->DBAT[1][i];
903	sregs.u.s.ppc32.ibat[i] = ((uint64_t)env->IBAT[0][i] << 32)
904	\| env->IBAT[1][i];
905	}
906
907	return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
908	}
909
910	int kvm_arch_put_registers(CPUState cs, KvmPutState level, Error *errp)
911	{
912	PowerPCCPU *cpu = POWERPC_CPU(cs);
913	CPUPPCState *env = &cpu->env;
914	struct kvm_regs regs;
915	int ret;
916	int i;
917
918	ret = kvm_vcpu_ioctl(cs, KVM_GET_REGS, &regs);
919	if (ret < 0) {
920	return ret;
921	}
922
923	regs.ctr = env->ctr;
924	regs.lr = env->lr;
925	regs.xer = cpu_read_xer(env);
926	regs.msr = env->msr;
927	regs.pc = env->nip;
928
929	regs.srr0 = env->spr[SPR_SRR0];
930	regs.srr1 = env->spr[SPR_SRR1];
931
932	regs.sprg0 = env->spr[SPR_SPRG0];
933	regs.sprg1 = env->spr[SPR_SPRG1];
934	regs.sprg2 = env->spr[SPR_SPRG2];
935	regs.sprg3 = env->spr[SPR_SPRG3];
936	regs.sprg4 = env->spr[SPR_SPRG4];
937	regs.sprg5 = env->spr[SPR_SPRG5];
938	regs.sprg6 = env->spr[SPR_SPRG6];
939	regs.sprg7 = env->spr[SPR_SPRG7];
940
941	regs.pid = env->spr[SPR_BOOKE_PID];
942
943	for (i = 0; i < 32; i++) {
944	regs.gpr[i] = env->gpr[i];
945	}
946
947	regs.cr = ppc_get_cr(env);
948
949	ret = kvm_vcpu_ioctl(cs, KVM_SET_REGS, &regs);
950	if (ret < 0) {
951	return ret;
952	}
953
954	kvm_put_fp(cs);
955
956	if (env->tlb_dirty) {
957	kvm_sw_tlb_put(cpu);
958	env->tlb_dirty = false;
959	}
960
961	if (cap_segstate && (level >= KVM_PUT_RESET_STATE)) {
962	ret = kvmppc_put_books_sregs(cpu);
963	if (ret < 0) {
964	return ret;
965	}
966	}
967
968	if (cap_hior && (level >= KVM_PUT_RESET_STATE)) {
969	kvm_put_one_spr(cs, KVM_REG_PPC_HIOR, SPR_HIOR);
970	}
971
972	if (cap_one_reg) {
973	/*
974	* We deliberately ignore errors here, for kernels which have
975	* the ONE_REG calls, but don't support the specific
976	* registers, there's a reasonable chance things will still
977	* work, at least until we try to migrate.
978	*/
979	for (i = 0; i < 1024; i++) {
980	uint64_t id = env->spr_cb[i].one_reg_id;
981
982	if (id != 0) {
983	kvm_put_one_spr(cs, id, i);
984	}
985	}
986
987	#ifdef TARGET_PPC64
988	if (FIELD_EX64(env->msr, MSR, TS)) {
989	for (i = 0; i < ARRAY_SIZE(env->tm_gpr); i++) {
990	kvm_set_one_reg(cs, KVM_REG_PPC_TM_GPR(i), &env->tm_gpr[i]);
991	}
992	for (i = 0; i < ARRAY_SIZE(env->tm_vsr); i++) {
993	kvm_set_one_reg(cs, KVM_REG_PPC_TM_VSR(i), &env->tm_vsr[i]);
994	}
995	kvm_set_one_reg(cs, KVM_REG_PPC_TM_CR, &env->tm_cr);
996	kvm_set_one_reg(cs, KVM_REG_PPC_TM_LR, &env->tm_lr);
997	kvm_set_one_reg(cs, KVM_REG_PPC_TM_CTR, &env->tm_ctr);
998	kvm_set_one_reg(cs, KVM_REG_PPC_TM_FPSCR, &env->tm_fpscr);
999	kvm_set_one_reg(cs, KVM_REG_PPC_TM_AMR, &env->tm_amr);
1000	kvm_set_one_reg(cs, KVM_REG_PPC_TM_PPR, &env->tm_ppr);
1001	kvm_set_one_reg(cs, KVM_REG_PPC_TM_VRSAVE, &env->tm_vrsave);
1002	kvm_set_one_reg(cs, KVM_REG_PPC_TM_VSCR, &env->tm_vscr);
1003	kvm_set_one_reg(cs, KVM_REG_PPC_TM_DSCR, &env->tm_dscr);
1004	kvm_set_one_reg(cs, KVM_REG_PPC_TM_TAR, &env->tm_tar);
1005	}
1006
1007	if (cap_papr) {
1008	if (kvm_put_vpa(cs) < 0) {
1009	trace_kvm_failed_put_vpa();
1010	}
1011	}
1012
1013	kvm_set_one_reg(cs, KVM_REG_PPC_TB_OFFSET, &env->tb_env->tb_offset);
1014
1015	if (level > KVM_PUT_RUNTIME_STATE) {
1016	kvm_put_one_spr(cs, KVM_REG_PPC_DPDES, SPR_DPDES);
1017	}
1018	#endif /* TARGET_PPC64 */
1019	}
1020
1021	return ret;
1022	}
1023
1024	static void kvm_sync_excp(CPUPPCState *env, int vector, int ivor)
1025	{
1026	env->excp_vectors[vector] = env->spr[ivor] + env->spr[SPR_BOOKE_IVPR];
1027	}
1028
1029	static int kvmppc_get_booke_sregs(PowerPCCPU *cpu)
1030	{
1031	CPUPPCState *env = &cpu->env;
1032	struct kvm_sregs sregs;
1033	int ret;
1034
1035	ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
1036	if (ret < 0) {
1037	return ret;
1038	}
1039
1040	if (sregs.u.e.features & KVM_SREGS_E_BASE) {
1041	env->spr[SPR_BOOKE_CSRR0] = sregs.u.e.csrr0;
1042	env->spr[SPR_BOOKE_CSRR1] = sregs.u.e.csrr1;
1043	env->spr[SPR_BOOKE_ESR] = sregs.u.e.esr;
1044	env->spr[SPR_BOOKE_DEAR] = sregs.u.e.dear;
1045	env->spr[SPR_BOOKE_MCSR] = sregs.u.e.mcsr;
1046	env->spr[SPR_BOOKE_TSR] = sregs.u.e.tsr;
1047	env->spr[SPR_BOOKE_TCR] = sregs.u.e.tcr;
1048	env->spr[SPR_DECR] = sregs.u.e.dec;
1049	env->spr[SPR_TBL] = sregs.u.e.tb & 0xffffffff;
1050	env->spr[SPR_TBU] = sregs.u.e.tb >> 32;
1051	env->spr[SPR_VRSAVE] = sregs.u.e.vrsave;
1052	}
1053
1054	if (sregs.u.e.features & KVM_SREGS_E_ARCH206) {
1055	env->spr[SPR_BOOKE_PIR] = sregs.u.e.pir;
1056	env->spr[SPR_BOOKE_MCSRR0] = sregs.u.e.mcsrr0;
1057	env->spr[SPR_BOOKE_MCSRR1] = sregs.u.e.mcsrr1;
1058	env->spr[SPR_BOOKE_DECAR] = sregs.u.e.decar;
1059	env->spr[SPR_BOOKE_IVPR] = sregs.u.e.ivpr;
1060	}
1061
1062	if (sregs.u.e.features & KVM_SREGS_E_64) {
1063	env->spr[SPR_BOOKE_EPCR] = sregs.u.e.epcr;
1064	}
1065
1066	if (sregs.u.e.features & KVM_SREGS_E_SPRG8) {
1067	env->spr[SPR_BOOKE_SPRG8] = sregs.u.e.sprg8;
1068	}
1069
1070	if (sregs.u.e.features & KVM_SREGS_E_IVOR) {
1071	env->spr[SPR_BOOKE_IVOR0] = sregs.u.e.ivor_low[0];
1072	kvm_sync_excp(env, POWERPC_EXCP_CRITICAL, SPR_BOOKE_IVOR0);
1073	env->spr[SPR_BOOKE_IVOR1] = sregs.u.e.ivor_low[1];
1074	kvm_sync_excp(env, POWERPC_EXCP_MCHECK, SPR_BOOKE_IVOR1);
1075	env->spr[SPR_BOOKE_IVOR2] = sregs.u.e.ivor_low[2];
1076	kvm_sync_excp(env, POWERPC_EXCP_DSI, SPR_BOOKE_IVOR2);
1077	env->spr[SPR_BOOKE_IVOR3] = sregs.u.e.ivor_low[3];
1078	kvm_sync_excp(env, POWERPC_EXCP_ISI, SPR_BOOKE_IVOR3);
1079	env->spr[SPR_BOOKE_IVOR4] = sregs.u.e.ivor_low[4];
1080	kvm_sync_excp(env, POWERPC_EXCP_EXTERNAL, SPR_BOOKE_IVOR4);
1081	env->spr[SPR_BOOKE_IVOR5] = sregs.u.e.ivor_low[5];
1082	kvm_sync_excp(env, POWERPC_EXCP_ALIGN, SPR_BOOKE_IVOR5);
1083	env->spr[SPR_BOOKE_IVOR6] = sregs.u.e.ivor_low[6];
1084	kvm_sync_excp(env, POWERPC_EXCP_PROGRAM, SPR_BOOKE_IVOR6);
1085	env->spr[SPR_BOOKE_IVOR7] = sregs.u.e.ivor_low[7];
1086	kvm_sync_excp(env, POWERPC_EXCP_FPU, SPR_BOOKE_IVOR7);
1087	env->spr[SPR_BOOKE_IVOR8] = sregs.u.e.ivor_low[8];
1088	kvm_sync_excp(env, POWERPC_EXCP_SYSCALL, SPR_BOOKE_IVOR8);
1089	env->spr[SPR_BOOKE_IVOR9] = sregs.u.e.ivor_low[9];
1090	kvm_sync_excp(env, POWERPC_EXCP_APU, SPR_BOOKE_IVOR9);
1091	env->spr[SPR_BOOKE_IVOR10] = sregs.u.e.ivor_low[10];
1092	kvm_sync_excp(env, POWERPC_EXCP_DECR, SPR_BOOKE_IVOR10);
1093	env->spr[SPR_BOOKE_IVOR11] = sregs.u.e.ivor_low[11];
1094	kvm_sync_excp(env, POWERPC_EXCP_FIT, SPR_BOOKE_IVOR11);
1095	env->spr[SPR_BOOKE_IVOR12] = sregs.u.e.ivor_low[12];
1096	kvm_sync_excp(env, POWERPC_EXCP_WDT, SPR_BOOKE_IVOR12);
1097	env->spr[SPR_BOOKE_IVOR13] = sregs.u.e.ivor_low[13];
1098	kvm_sync_excp(env, POWERPC_EXCP_DTLB, SPR_BOOKE_IVOR13);
1099	env->spr[SPR_BOOKE_IVOR14] = sregs.u.e.ivor_low[14];
1100	kvm_sync_excp(env, POWERPC_EXCP_ITLB, SPR_BOOKE_IVOR14);
1101	env->spr[SPR_BOOKE_IVOR15] = sregs.u.e.ivor_low[15];
1102	kvm_sync_excp(env, POWERPC_EXCP_DEBUG, SPR_BOOKE_IVOR15);
1103
1104	if (sregs.u.e.features & KVM_SREGS_E_SPE) {
1105	env->spr[SPR_BOOKE_IVOR32] = sregs.u.e.ivor_high[0];
1106	kvm_sync_excp(env, POWERPC_EXCP_SPEU, SPR_BOOKE_IVOR32);
1107	env->spr[SPR_BOOKE_IVOR33] = sregs.u.e.ivor_high[1];
1108	kvm_sync_excp(env, POWERPC_EXCP_EFPDI, SPR_BOOKE_IVOR33);
1109	env->spr[SPR_BOOKE_IVOR34] = sregs.u.e.ivor_high[2];
1110	kvm_sync_excp(env, POWERPC_EXCP_EFPRI, SPR_BOOKE_IVOR34);
1111	}
1112
1113	if (sregs.u.e.features & KVM_SREGS_E_PM) {
1114	env->spr[SPR_BOOKE_IVOR35] = sregs.u.e.ivor_high[3];
1115	kvm_sync_excp(env, POWERPC_EXCP_EPERFM, SPR_BOOKE_IVOR35);
1116	}
1117
1118	if (sregs.u.e.features & KVM_SREGS_E_PC) {
1119	env->spr[SPR_BOOKE_IVOR36] = sregs.u.e.ivor_high[4];
1120	kvm_sync_excp(env, POWERPC_EXCP_DOORI, SPR_BOOKE_IVOR36);
1121	env->spr[SPR_BOOKE_IVOR37] = sregs.u.e.ivor_high[5];
1122	kvm_sync_excp(env, POWERPC_EXCP_DOORCI, SPR_BOOKE_IVOR37);
1123	}
1124	}
1125
1126	if (sregs.u.e.features & KVM_SREGS_E_ARCH206_MMU) {
1127	env->spr[SPR_BOOKE_MAS0] = sregs.u.e.mas0;
1128	env->spr[SPR_BOOKE_MAS1] = sregs.u.e.mas1;
1129	env->spr[SPR_BOOKE_MAS2] = sregs.u.e.mas2;
1130	env->spr[SPR_BOOKE_MAS3] = sregs.u.e.mas7_3 & 0xffffffff;
1131	env->spr[SPR_BOOKE_MAS4] = sregs.u.e.mas4;
1132	env->spr[SPR_BOOKE_MAS6] = sregs.u.e.mas6;
1133	env->spr[SPR_BOOKE_MAS7] = sregs.u.e.mas7_3 >> 32;
1134	env->spr[SPR_MMUCFG] = sregs.u.e.mmucfg;
1135	env->spr[SPR_BOOKE_TLB0CFG] = sregs.u.e.tlbcfg[0];
1136	env->spr[SPR_BOOKE_TLB1CFG] = sregs.u.e.tlbcfg[1];
1137	}
1138
1139	if (sregs.u.e.features & KVM_SREGS_EXP) {
1140	env->spr[SPR_BOOKE_EPR] = sregs.u.e.epr;
1141	}
1142
1143	if (sregs.u.e.features & KVM_SREGS_E_PD) {
1144	env->spr[SPR_BOOKE_EPLC] = sregs.u.e.eplc;
1145	env->spr[SPR_BOOKE_EPSC] = sregs.u.e.epsc;
1146	}
1147
1148	if (sregs.u.e.impl_id == KVM_SREGS_E_IMPL_FSL) {
1149	env->spr[SPR_E500_SVR] = sregs.u.e.impl.fsl.svr;
1150	env->spr[SPR_Exxx_MCAR] = sregs.u.e.impl.fsl.mcar;
1151	env->spr[SPR_HID0] = sregs.u.e.impl.fsl.hid0;
1152
1153	if (sregs.u.e.impl.fsl.features & KVM_SREGS_E_FSL_PIDn) {
1154	env->spr[SPR_BOOKE_PID1] = sregs.u.e.impl.fsl.pid1;
1155	env->spr[SPR_BOOKE_PID2] = sregs.u.e.impl.fsl.pid2;
1156	}
1157	}
1158
1159	return 0;
1160	}
1161
1162	static int kvmppc_get_books_sregs(PowerPCCPU *cpu)
1163	{
1164	CPUPPCState *env = &cpu->env;
1165	struct kvm_sregs sregs;
1166	int ret;
1167	int i;
1168
1169	ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
1170	if (ret < 0) {
1171	return ret;
1172	}
1173
1174	if (!cpu->vhyp) {
1175	ppc_store_sdr1(env, sregs.u.s.sdr1);
1176	}
1177
1178	/* Sync SLB */
1179	#ifdef TARGET_PPC64
1180	/*
1181	* The packed SLB array we get from KVM_GET_SREGS only contains
1182	* information about valid entries. So we flush our internal copy
1183	* to get rid of stale ones, then put all valid SLB entries back
1184	* in.
1185	*/
1186	memset(env->slb, 0, sizeof(env->slb));
1187	for (i = 0; i < ARRAY_SIZE(env->slb); i++) {
1188	target_ulong rb = sregs.u.s.ppc64.slb[i].slbe;
1189	target_ulong rs = sregs.u.s.ppc64.slb[i].slbv;
1190	/*
1191	* Only restore valid entries
1192	*/
1193	if (rb & SLB_ESID_V) {
1194	ppc_store_slb(cpu, rb & 0xfff, rb & ~0xfffULL, rs);
1195	}
1196	}
1197	#endif
1198
1199	/* Sync SRs */
1200	for (i = 0; i < 16; i++) {
1201	env->sr[i] = sregs.u.s.ppc32.sr[i];
1202	}
1203
1204	/* Sync BATs */
1205	for (i = 0; i < 8; i++) {
1206	env->DBAT[0][i] = sregs.u.s.ppc32.dbat[i] & 0xffffffff;
1207	env->DBAT[1][i] = sregs.u.s.ppc32.dbat[i] >> 32;
1208	env->IBAT[0][i] = sregs.u.s.ppc32.ibat[i] & 0xffffffff;
1209	env->IBAT[1][i] = sregs.u.s.ppc32.ibat[i] >> 32;
1210	}
1211
1212	return 0;
1213	}
1214
1215	int kvm_arch_get_registers(CPUState cs, Error *errp)
1216	{
1217	PowerPCCPU *cpu = POWERPC_CPU(cs);
1218	CPUPPCState *env = &cpu->env;
1219	struct kvm_regs regs;
1220	int i, ret;
1221
1222	ret = kvm_vcpu_ioctl(cs, KVM_GET_REGS, &regs);
1223	if (ret < 0) {
1224	return ret;
1225	}
1226
1227	ppc_set_cr(env, regs.cr);
1228	env->ctr = regs.ctr;
1229	env->lr = regs.lr;
1230	cpu_write_xer(env, regs.xer);
1231	env->msr = regs.msr;
1232	env->nip = regs.pc;
1233
1234	env->spr[SPR_SRR0] = regs.srr0;
1235	env->spr[SPR_SRR1] = regs.srr1;
1236
1237	env->spr[SPR_SPRG0] = regs.sprg0;
1238	env->spr[SPR_SPRG1] = regs.sprg1;
1239	env->spr[SPR_SPRG2] = regs.sprg2;
1240	env->spr[SPR_SPRG3] = regs.sprg3;
1241	env->spr[SPR_SPRG4] = regs.sprg4;
1242	env->spr[SPR_SPRG5] = regs.sprg5;
1243	env->spr[SPR_SPRG6] = regs.sprg6;
1244	env->spr[SPR_SPRG7] = regs.sprg7;
1245
1246	env->spr[SPR_BOOKE_PID] = regs.pid;
1247
1248	for (i = 0; i < 32; i++) {
1249	env->gpr[i] = regs.gpr[i];
1250	}
1251
1252	kvm_get_fp(cs);
1253
1254	if (cap_booke_sregs) {
1255	ret = kvmppc_get_booke_sregs(cpu);
1256	if (ret < 0) {
1257	return ret;
1258	}
1259	}
1260
1261	if (cap_segstate) {
1262	ret = kvmppc_get_books_sregs(cpu);
1263	if (ret < 0) {
1264	return ret;
1265	}
1266	}
1267
1268	if (cap_hior) {
1269	kvm_get_one_spr(cs, KVM_REG_PPC_HIOR, SPR_HIOR);
1270	}
1271
1272	if (cap_one_reg) {
1273	/*
1274	* We deliberately ignore errors here, for kernels which have
1275	* the ONE_REG calls, but don't support the specific
1276	* registers, there's a reasonable chance things will still
1277	* work, at least until we try to migrate.
1278	*/
1279	for (i = 0; i < 1024; i++) {
1280	uint64_t id = env->spr_cb[i].one_reg_id;
1281
1282	if (id != 0) {
1283	kvm_get_one_spr(cs, id, i);
1284	}
1285	}
1286
1287	#ifdef TARGET_PPC64
1288	if (FIELD_EX64(env->msr, MSR, TS)) {
1289	for (i = 0; i < ARRAY_SIZE(env->tm_gpr); i++) {
1290	kvm_get_one_reg(cs, KVM_REG_PPC_TM_GPR(i), &env->tm_gpr[i]);
1291	}
1292	for (i = 0; i < ARRAY_SIZE(env->tm_vsr); i++) {
1293	kvm_get_one_reg(cs, KVM_REG_PPC_TM_VSR(i), &env->tm_vsr[i]);
1294	}
1295	kvm_get_one_reg(cs, KVM_REG_PPC_TM_CR, &env->tm_cr);
1296	kvm_get_one_reg(cs, KVM_REG_PPC_TM_LR, &env->tm_lr);
1297	kvm_get_one_reg(cs, KVM_REG_PPC_TM_CTR, &env->tm_ctr);
1298	kvm_get_one_reg(cs, KVM_REG_PPC_TM_FPSCR, &env->tm_fpscr);
1299	kvm_get_one_reg(cs, KVM_REG_PPC_TM_AMR, &env->tm_amr);
1300	kvm_get_one_reg(cs, KVM_REG_PPC_TM_PPR, &env->tm_ppr);
1301	kvm_get_one_reg(cs, KVM_REG_PPC_TM_VRSAVE, &env->tm_vrsave);
1302	kvm_get_one_reg(cs, KVM_REG_PPC_TM_VSCR, &env->tm_vscr);
1303	kvm_get_one_reg(cs, KVM_REG_PPC_TM_DSCR, &env->tm_dscr);
1304	kvm_get_one_reg(cs, KVM_REG_PPC_TM_TAR, &env->tm_tar);
1305	}
1306
1307	if (cap_papr) {
1308	if (kvm_get_vpa(cs) < 0) {
1309	trace_kvm_failed_get_vpa();
1310	}
1311	}
1312
1313	kvm_get_one_reg(cs, KVM_REG_PPC_TB_OFFSET, &env->tb_env->tb_offset);
1314	kvm_get_one_spr(cs, KVM_REG_PPC_DPDES, SPR_DPDES);
1315	#endif
1316	}
1317
1318	return 0;
1319	}
1320
1321	int kvmppc_set_interrupt(PowerPCCPU *cpu, int irq, int level)
1322	{
1323	unsigned virq = level ? KVM_INTERRUPT_SET_LEVEL : KVM_INTERRUPT_UNSET;
1324
1325	if (irq != PPC_INTERRUPT_EXT) {
1326	return 0;
1327	}
1328
1329	if (!cap_interrupt_unset) {
1330	return 0;
1331	}
1332
1333	kvm_vcpu_ioctl(CPU(cpu), KVM_INTERRUPT, &virq);
1334
1335	return 0;
1336	}
1337
1338	void kvm_arch_pre_run(CPUState cs, struct kvm_run run)
1339	{
1340	}
1341
1342	MemTxAttrs kvm_arch_post_run(CPUState cs, struct kvm_run run)
1343	{
1344	return MEMTXATTRS_UNSPECIFIED;
1345	}
1346
1347	int kvm_arch_process_async_events(CPUState *cs)
1348	{
1349	return cs->halted;
1350	}
1351
1352	static int kvmppc_handle_halt(PowerPCCPU *cpu)
1353	{
1354	CPUState *cs = CPU(cpu);
1355	CPUPPCState *env = &cpu->env;
1356
1357	if (!cpu_test_interrupt(cs, CPU_INTERRUPT_HARD) &&
1358	FIELD_EX64(env->msr, MSR, EE)) {
1359	cs->halted = 1;
1360	cs->exception_index = EXCP_HLT;
1361	}
1362
1363	return 0;
1364	}
1365
1366	/* map dcr access to existing qemu dcr emulation */
1367	static int kvmppc_handle_dcr_read(CPUPPCState *env,
1368	uint32_t dcrn, uint32_t *data)
1369	{
1370	if (ppc_dcr_read(env->dcr_env, dcrn, data) < 0) {
1371	fprintf(stderr, "Read to unhandled DCR (0x%x)\n", dcrn);
1372	}
1373
1374	return 0;
1375	}
1376
1377	static int kvmppc_handle_dcr_write(CPUPPCState *env,
1378	uint32_t dcrn, uint32_t data)
1379	{
1380	if (ppc_dcr_write(env->dcr_env, dcrn, data) < 0) {
1381	fprintf(stderr, "Write to unhandled DCR (0x%x)\n", dcrn);
1382	}
1383
1384	return 0;
1385	}
1386
1387	int kvm_arch_insert_sw_breakpoint(CPUState cs, struct kvm_sw_breakpoint bp)
1388	{
1389	/* Mixed endian case is not handled */
1390	uint32_t sc = debug_inst_opcode;
1391
1392	if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn,
1393	sizeof(sc), 0) \|\|
1394	cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&sc, sizeof(sc), 1)) {
1395	return -EINVAL;
1396	}
1397
1398	return 0;
1399	}
1400
1401	int kvm_arch_remove_sw_breakpoint(CPUState cs, struct kvm_sw_breakpoint bp)
1402	{
1403	uint32_t sc;
1404
1405	if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&sc, sizeof(sc), 0) \|\|
1406	sc != debug_inst_opcode \|\|
1407	cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn,
1408	sizeof(sc), 1)) {
1409	return -EINVAL;
1410	}
1411
1412	return 0;
1413	}
1414
1415	static int find_hw_breakpoint(target_ulong addr, GdbBreakpointType type)
1416	{
1417	int n;
1418
1419	assert((nb_hw_breakpoint + nb_hw_watchpoint)
1420	<= ARRAY_SIZE(hw_debug_points));
1421
1422	for (n = 0; n < nb_hw_breakpoint + nb_hw_watchpoint; n++) {
1423	if (hw_debug_points[n].addr == addr &&
1424	hw_debug_points[n].type == type) {
1425	return n;
1426	}
1427	}
1428
1429	return -1;
1430	}
1431
1432	static int find_hw_watchpoint(target_ulong addr, int *flag)
1433	{
1434	int n;
1435
1436	n = find_hw_breakpoint(addr, GDB_WATCHPOINT_ACCESS);
1437	if (n >= 0) {
1438	*flag = BP_MEM_ACCESS;
1439	return n;
1440	}
1441
1442	n = find_hw_breakpoint(addr, GDB_WATCHPOINT_WRITE);
1443	if (n >= 0) {
1444	*flag = BP_MEM_WRITE;
1445	return n;
1446	}
1447
1448	n = find_hw_breakpoint(addr, GDB_WATCHPOINT_READ);
1449	if (n >= 0) {
1450	*flag = BP_MEM_READ;
1451	return n;
1452	}
1453
1454	return -1;
1455	}
1456
1457	int kvm_arch_insert_gdbstub_hw_breakpoint(vaddr addr, vaddr len,
1458	GdbBreakpointType type)
1459	{
1460	const unsigned breakpoint_index = nb_hw_breakpoint + nb_hw_watchpoint;
1461	if (breakpoint_index >= ARRAY_SIZE(hw_debug_points)) {
1462	return -ENOBUFS;
1463	}
1464
1465	hw_debug_points[breakpoint_index].addr = addr;
1466	hw_debug_points[breakpoint_index].type = type;
1467
1468	switch (type) {
1469	case GDB_BREAKPOINT_HW:
1470	if (nb_hw_breakpoint >= max_hw_breakpoint) {
1471	return -ENOBUFS;
1472	}
1473
1474	if (find_hw_breakpoint(addr, type) >= 0) {
1475	return -EEXIST;
1476	}
1477
1478	nb_hw_breakpoint++;
1479	break;
1480
1481	case GDB_WATCHPOINT_WRITE:
1482	case GDB_WATCHPOINT_READ:
1483	case GDB_WATCHPOINT_ACCESS:
1484	if (nb_hw_watchpoint >= max_hw_watchpoint) {
1485	return -ENOBUFS;
1486	}
1487
1488	if (find_hw_breakpoint(addr, type) >= 0) {
1489	return -EEXIST;
1490	}
1491
1492	nb_hw_watchpoint++;
1493	break;
1494
1495	default:
1496	return -ENOSYS;
1497	}
1498
1499	return 0;
1500	}
1501
1502	int kvm_arch_remove_gdbstub_hw_breakpoint(vaddr addr, vaddr len,
1503	GdbBreakpointType type)
1504	{
1505	int n;
1506
1507	n = find_hw_breakpoint(addr, type);
1508	if (n < 0) {
1509	return -ENOENT;
1510	}
1511
1512	switch (type) {
1513	case GDB_BREAKPOINT_HW:
1514	nb_hw_breakpoint--;
1515	break;
1516
1517	case GDB_WATCHPOINT_WRITE:
1518	case GDB_WATCHPOINT_READ:
1519	case GDB_WATCHPOINT_ACCESS:
1520	nb_hw_watchpoint--;
1521	break;
1522
1523	default:
1524	return -ENOSYS;
1525	}
1526	hw_debug_points[n] = hw_debug_points[nb_hw_breakpoint + nb_hw_watchpoint];
1527
1528	return 0;
1529	}
1530
1531	void kvm_arch_remove_all_gdbstub_hw_breakpoints(void)
1532	{
1533	nb_hw_breakpoint = nb_hw_watchpoint = 0;
1534	}
1535
1536	void kvm_arch_update_guest_debug(CPUState cs, struct kvm_guest_debug dbg)
1537	{
1538	int n;
1539
1540	/* Software Breakpoint updates */
1541	if (kvm_sw_breakpoints_active(cs)) {
1542	dbg->control \|= KVM_GUESTDBG_ENABLE \| KVM_GUESTDBG_USE_SW_BP;
1543	}
1544
1545	assert((nb_hw_breakpoint + nb_hw_watchpoint)
1546	<= ARRAY_SIZE(hw_debug_points));
1547	assert((nb_hw_breakpoint + nb_hw_watchpoint) <= ARRAY_SIZE(dbg->arch.bp));
1548
1549	if (nb_hw_breakpoint + nb_hw_watchpoint > 0) {
1550	dbg->control \|= KVM_GUESTDBG_ENABLE \| KVM_GUESTDBG_USE_HW_BP;
1551	memset(dbg->arch.bp, 0, sizeof(dbg->arch.bp));
1552	for (n = 0; n < nb_hw_breakpoint + nb_hw_watchpoint; n++) {
1553	switch (hw_debug_points[n].type) {
1554	case GDB_BREAKPOINT_HW:
1555	dbg->arch.bp[n].type = KVMPPC_DEBUG_BREAKPOINT;
1556	break;
1557	case GDB_WATCHPOINT_WRITE:
1558	dbg->arch.bp[n].type = KVMPPC_DEBUG_WATCH_WRITE;
1559	break;
1560	case GDB_WATCHPOINT_READ:
1561	dbg->arch.bp[n].type = KVMPPC_DEBUG_WATCH_READ;
1562	break;
1563	case GDB_WATCHPOINT_ACCESS:
1564	dbg->arch.bp[n].type = KVMPPC_DEBUG_WATCH_WRITE \|
1565	KVMPPC_DEBUG_WATCH_READ;
1566	break;
1567	default:
1568	cpu_abort(cs, "Unsupported breakpoint type\n");
1569	}
1570	dbg->arch.bp[n].addr = hw_debug_points[n].addr;
1571	}
1572	}
1573	}
1574
1575	static int kvm_handle_hw_breakpoint(CPUState *cs,
1576	struct kvm_debug_exit_arch *arch_info)
1577	{
1578	int handle = DEBUG_RETURN_GUEST;
1579	int n;
1580	int flag = 0;
1581
1582	if (nb_hw_breakpoint + nb_hw_watchpoint > 0) {
1583	if (arch_info->status & KVMPPC_DEBUG_BREAKPOINT) {
1584	n = find_hw_breakpoint(arch_info->address, GDB_BREAKPOINT_HW);
1585	if (n >= 0) {
1586	handle = DEBUG_RETURN_GDB;
1587	}
1588	} else if (arch_info->status & (KVMPPC_DEBUG_WATCH_READ \|
1589	KVMPPC_DEBUG_WATCH_WRITE)) {
1590	n = find_hw_watchpoint(arch_info->address, &flag);
1591	if (n >= 0) {
1592	handle = DEBUG_RETURN_GDB;
1593	cs->watchpoint_hit = &hw_watchpoint;
1594	hw_watchpoint.vaddr = hw_debug_points[n].addr;
1595	hw_watchpoint.flags = flag;
1596	}
1597	}
1598	}
1599	return handle;
1600	}
1601
1602	static int kvm_handle_singlestep(void)
1603	{
1604	return DEBUG_RETURN_GDB;
1605	}
1606
1607	static int kvm_handle_sw_breakpoint(void)
1608	{
1609	return DEBUG_RETURN_GDB;
1610	}
1611
1612	static int kvm_handle_debug(PowerPCCPU cpu, struct kvm_run run)
1613	{
1614	CPUState *cs = CPU(cpu);
1615	CPUPPCState *env = &cpu->env;
1616	struct kvm_debug_exit_arch *arch_info = &run->debug.arch;
1617
1618	if (cpu_single_stepping(cs)) {
1619	return kvm_handle_singlestep();
1620	}
1621
1622	if (arch_info->status) {
1623	return kvm_handle_hw_breakpoint(cs, arch_info);
1624	}
1625
1626	if (kvm_find_sw_breakpoint(cs, arch_info->address)) {
1627	return kvm_handle_sw_breakpoint();
1628	}
1629
1630	/*
1631	* QEMU is not able to handle debug exception, so inject
1632	* program exception to guest;
1633	* Yes program exception NOT debug exception !!
1634	* When QEMU is using debug resources then debug exception must
1635	* be always set. To achieve this we set MSR_DE and also set
1636	* MSRP_DEP so guest cannot change MSR_DE.
1637	* When emulating debug resource for guest we want guest
1638	* to control MSR_DE (enable/disable debug interrupt on need).
1639	* Supporting both configurations are NOT possible.
1640	* So the result is that we cannot share debug resources
1641	* between QEMU and Guest on BOOKE architecture.
1642	* In the current design QEMU gets the priority over guest,
1643	* this means that if QEMU is using debug resources then guest
1644	* cannot use them;
1645	* For software breakpoint QEMU uses a privileged instruction;
1646	* So there cannot be any reason that we are here for guest
1647	* set debug exception, only possibility is guest executed a
1648	* privileged / illegal instruction and that's why we are
1649	* injecting a program interrupt.
1650	*/
1651	cpu_synchronize_state(cs);
1652	/*
1653	* env->nip is PC, so increment this by 4 to use
1654	* ppc_cpu_do_interrupt(), which set srr0 = env->nip - 4.
1655	*/
1656	env->nip += 4;
1657	cs->exception_index = POWERPC_EXCP_PROGRAM;
1658	env->error_code = POWERPC_EXCP_INVAL;
1659	ppc_cpu_do_interrupt(cs);
1660
1661	return DEBUG_RETURN_GUEST;
1662	}
1663
1664	int kvm_arch_handle_exit(CPUState cs, struct kvm_run run)
1665	{
1666	PowerPCCPU *cpu = POWERPC_CPU(cs);
1667	CPUPPCState *env = &cpu->env;
1668	int ret;
1669
1670	bql_lock();
1671
1672	switch (run->exit_reason) {
1673	case KVM_EXIT_DCR:
1674	if (run->dcr.is_write) {
1675	trace_kvm_handle_dcr_write();
1676	ret = kvmppc_handle_dcr_write(env, run->dcr.dcrn, run->dcr.data);
1677	} else {
1678	trace_kvm_handle_dcr_read();
1679	ret = kvmppc_handle_dcr_read(env, run->dcr.dcrn, &run->dcr.data);
1680	}
1681	break;
1682	case KVM_EXIT_HLT:
1683	trace_kvm_handle_halt();
1684	ret = kvmppc_handle_halt(cpu);
1685	break;
1686	#if defined(CONFIG_PSERIES)
1687	case KVM_EXIT_PAPR_HCALL:
1688	trace_kvm_handle_papr_hcall(run->papr_hcall.nr);
1689	run->papr_hcall.ret = spapr_hypercall(cpu,
1690	run->papr_hcall.nr,
1691	run->papr_hcall.args);
1692	ret = 0;
1693	break;
1694	#endif
1695	case KVM_EXIT_EPR:
1696	trace_kvm_handle_epr();
1697	run->epr.epr = ldl_phys(cs->as, env->mpic_iack);
1698	ret = 0;
1699	break;
1700	case KVM_EXIT_WATCHDOG:
1701	trace_kvm_handle_watchdog_expiry();
1702	watchdog_perform_action();
1703	ret = 0;
1704	break;
1705
1706	case KVM_EXIT_DEBUG:
1707	trace_kvm_handle_debug_exception();
1708	if (kvm_handle_debug(cpu, run)) {
1709	ret = EXCP_DEBUG;
1710	break;
1711	}
1712	/* re-enter, this exception was guest-internal */
1713	ret = 0;
1714	break;
1715
1716	#if defined(CONFIG_PSERIES)
1717	case KVM_EXIT_NMI:
1718	trace_kvm_handle_nmi_exception();
1719	ret = kvm_handle_nmi(cpu, run);
1720	break;
1721	#endif
1722
1723	default:
1724	fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
1725	ret = -1;
1726	break;
1727	}
1728
1729	bql_unlock();
1730	return ret;
1731	}
1732
1733	int kvmppc_or_tsr_bits(PowerPCCPU *cpu, uint32_t tsr_bits)
1734	{
1735	CPUState *cs = CPU(cpu);
1736	uint32_t bits = tsr_bits;
1737	struct kvm_one_reg reg = {
1738	.id = KVM_REG_PPC_OR_TSR,
1739	.addr = (uintptr_t) &bits,
1740	};
1741
1742	if (!kvm_enabled()) {
1743	return 0;
1744	}
1745
1746	return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
1747	}
1748
1749	int kvmppc_clear_tsr_bits(PowerPCCPU *cpu, uint32_t tsr_bits)
1750	{
1751
1752	CPUState *cs = CPU(cpu);
1753	uint32_t bits = tsr_bits;
1754	struct kvm_one_reg reg = {
1755	.id = KVM_REG_PPC_CLEAR_TSR,
1756	.addr = (uintptr_t) &bits,
1757	};
1758
1759	if (!kvm_enabled()) {
1760	return 0;
1761	}
1762
1763	return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
1764	}
1765
1766	int kvmppc_set_tcr(PowerPCCPU *cpu)
1767	{
1768	CPUState *cs = CPU(cpu);
1769	CPUPPCState *env = &cpu->env;
1770	uint32_t tcr = env->spr[SPR_BOOKE_TCR];
1771
1772	struct kvm_one_reg reg = {
1773	.id = KVM_REG_PPC_TCR,
1774	.addr = (uintptr_t) &tcr,
1775	};
1776
1777	if (!kvm_enabled()) {
1778	return 0;
1779	}
1780
1781	return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
1782	}
1783
1784	int kvmppc_booke_watchdog_enable(PowerPCCPU *cpu)
1785	{
1786	CPUState *cs = CPU(cpu);
1787	int ret;
1788
1789	if (!kvm_enabled()) {
1790	return -1;
1791	}
1792
1793	if (!cap_ppc_watchdog) {
1794	printf("warning: KVM does not support watchdog");
1795	return -1;
1796	}
1797
1798	ret = kvm_vcpu_enable_cap(cs, KVM_CAP_PPC_BOOKE_WATCHDOG, 0);
1799	if (ret < 0) {
1800	fprintf(stderr, "%s: couldn't enable KVM_CAP_PPC_BOOKE_WATCHDOG: %s\n",
1801	__func__, strerror(-ret));
1802	return ret;
1803	}
1804
1805	return ret;
1806	}
1807
1808	static int read_cpuinfo(const char field, char value, int len)
1809	{
1810	FILE *f;
1811	int ret = -1;
1812	int field_len = strlen(field);
1813	char line[512];
1814
1815	f = fopen("/proc/cpuinfo", "r");
1816	if (!f) {
1817	return -1;
1818	}
1819
1820	do {
1821	if (!fgets(line, sizeof(line), f)) {
1822	break;
1823	}
1824	if (!strncmp(line, field, field_len)) {
1825	pstrcpy(value, len, line);
1826	ret = 0;
1827	break;
1828	}
1829	} while (*line);
1830
1831	fclose(f);
1832
1833	return ret;
1834	}
1835
1836	static uint32_t kvmppc_get_tbfreq_procfs(void)
1837	{
1838	char line[512];
1839	char *ns;
1840	uint32_t tbfreq_fallback = NANOSECONDS_PER_SECOND;
1841	uint32_t tbfreq_procfs;
1842
1843	if (read_cpuinfo("timebase", line, sizeof(line))) {
1844	return tbfreq_fallback;
1845	}
1846
1847	ns = strchr(line, ':');
1848	if (!ns) {
1849	return tbfreq_fallback;
1850	}
1851
1852	tbfreq_procfs = atoi(++ns);
1853
1854	/* 0 is certainly not acceptable by the guest, return fallback value */
1855	return tbfreq_procfs ? tbfreq_procfs : tbfreq_fallback;
1856	}
1857
1858	uint32_t kvmppc_get_tbfreq(void)
1859	{
1860	static uint32_t cached_tbfreq;
1861
1862	if (!cached_tbfreq) {
1863	cached_tbfreq = kvmppc_get_tbfreq_procfs();
1864	}
1865
1866	return cached_tbfreq;
1867	}
1868
1869	/* Try to find a device tree node for a CPU with clock-frequency property */
1870	static int kvmppc_find_cpu_dt(char *buf, int buf_len)
1871	{
1872	struct dirent *dirp;
1873	DIR *dp;
1874
1875	dp = opendir(PROC_DEVTREE_CPU);
1876	if (!dp) {
1877	printf("Can't open directory " PROC_DEVTREE_CPU "\n");
1878	return -1;
1879	}
1880
1881	buf[0] = '\0';
1882	while ((dirp = readdir(dp)) != NULL) {
1883	FILE *f;
1884
1885	/* Don't accidentally read from the current and parent directories */
1886	if (strcmp(dirp->d_name, ".") == 0 \|\| strcmp(dirp->d_name, "..") == 0) {
1887	continue;
1888	}
1889
1890	snprintf(buf, buf_len, "%s%s/clock-frequency", PROC_DEVTREE_CPU,
1891	dirp->d_name);
1892	f = fopen(buf, "r");
1893	if (f) {
1894	snprintf(buf, buf_len, "%s%s", PROC_DEVTREE_CPU, dirp->d_name);
1895	fclose(f);
1896	break;
1897	}
1898	buf[0] = '\0';
1899	}
1900	closedir(dp);
1901	if (buf[0] == '\0') {
1902	printf("Unknown host!\n");
1903	return -1;
1904	}
1905
1906	return 0;
1907	}
1908
1909	static uint64_t kvmppc_read_int_dt(const char *filename)
1910	{
1911	union {
1912	uint32_t v32;
1913	uint64_t v64;
1914	} u;
1915	FILE *f;
1916	int len;
1917
1918	f = fopen(filename, "rb");
1919	if (!f) {
1920	return -1;
1921	}
1922
1923	len = fread(&u, 1, sizeof(u), f);
1924	fclose(f);
1925	switch (len) {
1926	case 4:
1927	/* property is a 32-bit quantity */
1928	return be32_to_cpu(u.v32);
1929	case 8:
1930	return be64_to_cpu(u.v64);
1931	}
1932
1933	return 0;
1934	}
1935
1936	/*
1937	* Read a CPU node property from the host device tree that's a single
1938	* integer (32-bit or 64-bit). Returns 0 if anything goes wrong
1939	* (can't find or open the property, or doesn't understand the format)
1940	*/
1941	static uint64_t kvmppc_read_int_cpu_dt(const char *propname)
1942	{
1943	char buf[PATH_MAX], *tmp;
1944	uint64_t val;
1945
1946	if (kvmppc_find_cpu_dt(buf, sizeof(buf))) {
1947	return -1;
1948	}
1949
1950	tmp = g_strdup_printf("%s/%s", buf, propname);
1951	val = kvmppc_read_int_dt(tmp);
1952	g_free(tmp);
1953
1954	return val;
1955	}
1956
1957	uint64_t kvmppc_get_clockfreq(void)
1958	{
1959	return kvmppc_read_int_cpu_dt("clock-frequency");
1960	}
1961
1962	static int kvmppc_get_dec_bits(void)
1963	{
1964	int nr_bits = kvmppc_read_int_cpu_dt("ibm,dec-bits");
1965
1966	if (nr_bits > 0) {
1967	return nr_bits;
1968	}
1969	return 0;
1970	}
1971
1972	static int kvmppc_get_pvinfo(CPUPPCState env, struct kvm_ppc_pvinfo pvinfo)
1973	{
1974	CPUState *cs = env_cpu(env);
1975
1976	if (kvm_vm_check_extension(cs->kvm_state, KVM_CAP_PPC_GET_PVINFO) &&
1977	!kvm_vm_ioctl(cs->kvm_state, KVM_PPC_GET_PVINFO, pvinfo)) {
1978	return 0;
1979	}
1980
1981	return 1;
1982	}
1983
1984	int kvmppc_get_hasidle(CPUPPCState *env)
1985	{
1986	struct kvm_ppc_pvinfo pvinfo;
1987
1988	if (!kvmppc_get_pvinfo(env, &pvinfo) &&
1989	(pvinfo.flags & KVM_PPC_PVINFO_FLAGS_EV_IDLE)) {
1990	return 1;
1991	}
1992
1993	return 0;
1994	}
1995
1996	int kvmppc_get_hypercall(CPUPPCState env, uint8_t buf, int buf_len)
1997	{
1998	uint32_t hc = (uint32_t )buf;
1999	struct kvm_ppc_pvinfo pvinfo;
2000
2001	if (!kvmppc_get_pvinfo(env, &pvinfo)) {
2002	memcpy(buf, pvinfo.hcall, buf_len);
2003	return 0;
2004	}
2005
2006	/*
2007	* Fallback to always fail hypercalls regardless of endianness:
2008	*
2009	* tdi 0,r0,72 (becomes b .+8 in wrong endian, nop in good endian)
2010	* li r3, -1
2011	* b .+8 (becomes nop in wrong endian)
2012	* bswap32(li r3, -1)
2013	*/
2014
2015	hc[0] = cpu_to_be32(0x08000048);
2016	hc[1] = cpu_to_be32(0x3860ffff);
2017	hc[2] = cpu_to_be32(0x48000008);
2018	hc[3] = cpu_to_be32(bswap32(0x3860ffff));
2019
2020	return 1;
2021	}
2022
2023	static inline int kvmppc_enable_hcall(KVMState *s, target_ulong hcall)
2024	{
2025	return kvm_vm_enable_cap(s, KVM_CAP_PPC_ENABLE_HCALL, 0, hcall, 1);
2026	}
2027
2028	void kvmppc_enable_logical_ci_hcalls(void)
2029	{
2030	/*
2031	* FIXME: it would be nice if we could detect the cases where
2032	* we're using a device which requires the in kernel
2033	* implementation of these hcalls, but the kernel lacks them and
2034	* produce a warning.
2035	*/
2036	kvmppc_enable_hcall(kvm_state, H_LOGICAL_CI_LOAD);
2037	kvmppc_enable_hcall(kvm_state, H_LOGICAL_CI_STORE);
2038	}
2039
2040	void kvmppc_enable_set_mode_hcall(void)
2041	{
2042	kvmppc_enable_hcall(kvm_state, H_SET_MODE);
2043	}
2044
2045	void kvmppc_enable_clear_ref_mod_hcalls(void)
2046	{
2047	kvmppc_enable_hcall(kvm_state, H_CLEAR_REF);
2048	kvmppc_enable_hcall(kvm_state, H_CLEAR_MOD);
2049	}
2050
2051	void kvmppc_enable_h_page_init(void)
2052	{
2053	kvmppc_enable_hcall(kvm_state, H_PAGE_INIT);
2054	}
2055
2056	void kvmppc_enable_h_rpt_invalidate(void)
2057	{
2058	kvmppc_enable_hcall(kvm_state, H_RPT_INVALIDATE);
2059	}
2060
2061	#ifdef CONFIG_PSERIES
2062	void kvmppc_set_papr(PowerPCCPU *cpu)
2063	{
2064	CPUState *cs = CPU(cpu);
2065	int ret;
2066
2067	if (!kvm_enabled()) {
2068	return;
2069	}
2070
2071	ret = kvm_vcpu_enable_cap(cs, KVM_CAP_PPC_PAPR, 0);
2072	if (ret) {
2073	error_report("This vCPU type or KVM version does not support PAPR");
2074	exit(1);
2075	}
2076
2077	/*
2078	* Update the capability flag so we sync the right information
2079	* with kvm
2080	*/
2081	cap_papr = 1;
2082	}
2083	#endif
2084
2085	int kvmppc_set_compat(PowerPCCPU *cpu, uint32_t compat_pvr)
2086	{
2087	return kvm_set_one_reg(CPU(cpu), KVM_REG_PPC_ARCH_COMPAT, &compat_pvr);
2088	}
2089
2090	void kvmppc_set_mpic_proxy(PowerPCCPU *cpu, int mpic_proxy)
2091	{
2092	CPUState *cs = CPU(cpu);
2093	int ret;
2094
2095	ret = kvm_vcpu_enable_cap(cs, KVM_CAP_PPC_EPR, 0, mpic_proxy);
2096	if (ret && mpic_proxy) {
2097	error_report("This KVM version does not support EPR");
2098	exit(1);
2099	}
2100	}
2101
2102	bool kvmppc_get_fwnmi(void)
2103	{
2104	return cap_fwnmi;
2105	}
2106
2107	int kvmppc_set_fwnmi(PowerPCCPU *cpu)
2108	{
2109	CPUState *cs = CPU(cpu);
2110
2111	return kvm_vcpu_enable_cap(cs, KVM_CAP_PPC_FWNMI, 0);
2112	}
2113
2114	bool kvmppc_has_cap_dawr1(void)
2115	{
2116	return !!cap_dawr1;
2117	}
2118
2119	int kvmppc_set_cap_dawr1(int enable)
2120	{
2121	return kvm_vm_enable_cap(kvm_state, KVM_CAP_PPC_DAWR1, 0, enable);
2122	}
2123
2124	int kvmppc_smt_threads(void)
2125	{
2126	return cap_ppc_smt ? cap_ppc_smt : 1;
2127	}
2128
2129	int kvmppc_set_smt_threads(int smt)
2130	{
2131	int ret;
2132
2133	ret = kvm_vm_enable_cap(kvm_state, KVM_CAP_PPC_SMT, 0, smt, 0);
2134	if (!ret) {
2135	cap_ppc_smt = smt;
2136	}
2137	return ret;
2138	}
2139
2140	void kvmppc_error_append_smt_possible_hint(Error const errp)
2141	{
2142	int i;
2143	GString *g;
2144	char *s;
2145
2146	assert(kvm_enabled());
2147	if (cap_ppc_smt_possible) {
2148	g = g_string_new("Available VSMT modes:");
2149	for (i = 63; i >= 0; i--) {
2150	if ((1UL << i) & cap_ppc_smt_possible) {
2151	g_string_append_printf(g, " %lu", (1UL << i));
2152	}
2153	}
2154	s = g_string_free(g, false);
2155	error_append_hint(errp, "%s.\n", s);
2156	g_free(s);
2157	} else {
2158	error_append_hint(errp,
2159	"This KVM seems to be too old to support VSMT.\n");
2160	}
2161	}
2162
2163
2164	#ifdef TARGET_PPC64
2165	uint64_t kvmppc_vrma_limit(unsigned int hash_shift)
2166	{
2167	struct kvm_ppc_smmu_info info;
2168	long rampagesize, best_page_shift;
2169	int i;
2170
2171	/*
2172	* Find the largest hardware supported page size that's less than
2173	* or equal to the (logical) backing page size of guest RAM
2174	*/
2175	kvm_get_smmu_info(&info, &error_fatal);
2176	rampagesize = qemu_minrampagesize();
2177	best_page_shift = 0;
2178
2179	for (i = 0; i < KVM_PPC_PAGE_SIZES_MAX_SZ; i++) {
2180	struct kvm_ppc_one_seg_page_size *sps = &info.sps[i];
2181
2182	if (!sps->page_shift) {
2183	continue;
2184	}
2185
2186	if ((sps->page_shift > best_page_shift)
2187	&& ((1UL << sps->page_shift) <= rampagesize)) {
2188	best_page_shift = sps->page_shift;
2189	}
2190	}
2191
2192	return 1ULL << (best_page_shift + hash_shift - 7);
2193	}
2194	#endif
2195
2196	bool kvmppc_spapr_use_multitce(void)
2197	{
2198	return cap_spapr_multitce;
2199	}
2200
2201	int kvmppc_spapr_enable_inkernel_multitce(void)
2202	{
2203	int ret;
2204
2205	ret = kvm_vm_enable_cap(kvm_state, KVM_CAP_PPC_ENABLE_HCALL, 0,
2206	H_PUT_TCE_INDIRECT, 1);
2207	if (!ret) {
2208	ret = kvm_vm_enable_cap(kvm_state, KVM_CAP_PPC_ENABLE_HCALL, 0,
2209	H_STUFF_TCE, 1);
2210	}
2211
2212	return ret;
2213	}
2214
2215	void *kvmppc_create_spapr_tce(uint32_t liobn, uint32_t page_shift,
2216	uint64_t bus_offset, uint32_t nb_table,
2217	int *pfd, bool need_vfio)
2218	{
2219	long len;
2220	int fd;
2221	void *table;
2222
2223	/*
2224	* Must set fd to -1 so we don't try to munmap when called for
2225	* destroying the table, which the upper layers -will- do
2226	*/
2227	*pfd = -1;
2228	if (!cap_spapr_tce \|\| (need_vfio && !cap_spapr_vfio)) {
2229	return NULL;
2230	}
2231
2232	if (cap_spapr_tce_64) {
2233	struct kvm_create_spapr_tce_64 args = {
2234	.liobn = liobn,
2235	.page_shift = page_shift,
2236	.offset = bus_offset >> page_shift,
2237	.size = nb_table,
2238	.flags = 0
2239	};
2240	fd = kvm_vm_ioctl(kvm_state, KVM_CREATE_SPAPR_TCE_64, &args);
2241	if (fd < 0) {
2242	fprintf(stderr,
2243	"KVM: Failed to create TCE64 table for liobn 0x%x\n",
2244	liobn);
2245	return NULL;
2246	}
2247	} else if (cap_spapr_tce) {
2248	uint64_t window_size = (uint64_t) nb_table << page_shift;
2249	struct kvm_create_spapr_tce args = {
2250	.liobn = liobn,
2251	.window_size = window_size,
2252	};
2253	if ((window_size != args.window_size) \|\| bus_offset) {
2254	return NULL;
2255	}
2256	fd = kvm_vm_ioctl(kvm_state, KVM_CREATE_SPAPR_TCE, &args);
2257	if (fd < 0) {
2258	fprintf(stderr, "KVM: Failed to create TCE table for liobn 0x%x\n",
2259	liobn);
2260	return NULL;
2261	}
2262	} else {
2263	return NULL;
2264	}
2265
2266	len = nb_table * sizeof(uint64_t);
2267	/* FIXME: round this up to page size */
2268
2269	table = mmap(NULL, len, PROT_READ \| PROT_WRITE, MAP_SHARED, fd, 0);
2270	if (table == MAP_FAILED) {
2271	fprintf(stderr, "KVM: Failed to map TCE table for liobn 0x%x\n",
2272	liobn);
2273	close(fd);
2274	return NULL;
2275	}
2276
2277	*pfd = fd;
2278	return table;
2279	}
2280
2281	int kvmppc_remove_spapr_tce(void *table, int fd, uint32_t nb_table)
2282	{
2283	long len;
2284
2285	if (fd < 0) {
2286	return -1;
2287	}
2288
2289	len = nb_table * sizeof(uint64_t);
2290	if ((munmap(table, len) < 0) \|\|
2291	(close(fd) < 0)) {
2292	fprintf(stderr, "KVM: Unexpected error removing TCE table: %s",
2293	strerror(errno));
2294	/* Leak the table */
2295	}
2296
2297	return 0;
2298	}
2299
2300	int kvmppc_reset_htab(int shift_hint)
2301	{
2302	uint32_t shift = shift_hint;
2303
2304	if (!kvm_enabled()) {
2305	/* Full emulation, tell caller to allocate htab itself */
2306	return 0;
2307	}
2308	if (kvm_vm_check_extension(kvm_state, KVM_CAP_PPC_ALLOC_HTAB)) {
2309	int ret;
2310	ret = kvm_vm_ioctl(kvm_state, KVM_PPC_ALLOCATE_HTAB, &shift);
2311	if (ret == -ENOTTY) {
2312	/*
2313	* At least some versions of PR KVM advertise the
2314	* capability, but don't implement the ioctl(). Oops.
2315	* Return 0 so that we allocate the htab in qemu, as is
2316	* correct for PR.
2317	*/
2318	return 0;
2319	} else if (ret < 0) {
2320	return ret;
2321	}
2322	return shift;
2323	}
2324
2325	/*
2326	* We have a kernel that predates the htab reset calls. For PR
2327	* KVM, we need to allocate the htab ourselves, for an HV KVM of
2328	* this era, it has allocated a 16MB fixed size hash table
2329	* already.
2330	*/
2331	if (kvmppc_is_pr(kvm_state)) {
2332	/* PR - tell caller to allocate htab */
2333	return 0;
2334	} else {
2335	/* HV - assume 16MB kernel allocated htab */
2336	return 24;
2337	}
2338	}
2339
2340	static inline uint32_t mfpvr(void)
2341	{
2342	uint32_t pvr;
2343
2344	asm ("mfpvr %0"
2345	: "=r"(pvr));
2346	return pvr;
2347	}
2348
2349	static void alter_insns(uint64_t *word, uint64_t flags, bool on)
2350	{
2351	if (on) {
2352	*word \|= flags;
2353	} else {
2354	*word &= ~flags;
2355	}
2356	}
2357
2358	static bool kvmppc_cpu_realize(CPUState cs, Error *errp)
2359	{
2360	int ret;
2361	const char *vcpu_str = (cs->parent_obj.hotplugged == true) ?
2362	"hotplug" : "create";
2363	cs->cpu_index = cpu_get_free_index();
2364
2365	POWERPC_CPU(cs)->vcpu_id = cs->cpu_index;
2366
2367	/* create and park to fail gracefully in case vcpu hotplug fails */
2368	ret = kvm_create_and_park_vcpu(cs);
2369	if (ret) {
2370	/*
2371	* This causes QEMU to terminate if initial CPU creation
2372	* fails, and only CPU hotplug failure if the error happens
2373	* there.
2374	*/
2375	error_setg(errp, "%s: vcpu %s failed with %d",
2376	__func__, vcpu_str, ret);
2377	return false;
2378	}
2379	return true;
2380	}
2381
2382	static void kvmppc_host_cpu_class_init(ObjectClass oc, const void data)
2383	{
2384	PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2385	uint32_t dcache_size = kvmppc_read_int_cpu_dt("d-cache-size");
2386	uint32_t icache_size = kvmppc_read_int_cpu_dt("i-cache-size");
2387
2388	/* Now fix up the class with information we can query from the host */
2389	pcc->pvr = mfpvr();
2390
2391	alter_insns(&pcc->insns_flags, PPC_ALTIVEC,
2392	qemu_getauxval(AT_HWCAP) & PPC_FEATURE_HAS_ALTIVEC);
2393	alter_insns(&pcc->insns_flags2, PPC2_VSX,
2394	qemu_getauxval(AT_HWCAP) & PPC_FEATURE_HAS_VSX);
2395	alter_insns(&pcc->insns_flags2, PPC2_DFP,
2396	qemu_getauxval(AT_HWCAP) & PPC_FEATURE_HAS_DFP);
2397
2398	if (dcache_size != -1) {
2399	pcc->l1_dcache_size = dcache_size;
2400	}
2401
2402	if (icache_size != -1) {
2403	pcc->l1_icache_size = icache_size;
2404	}
2405
2406	#if defined(TARGET_PPC64)
2407	pcc->radix_page_info = kvmppc_get_radix_page_info();
2408	#endif /* defined(TARGET_PPC64) */
2409	}
2410
2411	bool kvmppc_has_cap_epr(void)
2412	{
2413	return cap_epr;
2414	}
2415
2416	bool kvmppc_has_cap_fixup_hcalls(void)
2417	{
2418	return cap_fixup_hcalls;
2419	}
2420
2421	bool kvmppc_has_cap_htm(void)
2422	{
2423	return cap_htm;
2424	}
2425
2426	bool kvmppc_has_cap_mmu_radix(void)
2427	{
2428	return cap_mmu_radix;
2429	}
2430
2431	bool kvmppc_has_cap_mmu_hash_v3(void)
2432	{
2433	return cap_mmu_hash_v3;
2434	}
2435
2436	static bool kvmppc_power8_host(void)
2437	{
2438	bool ret = false;
2439	#ifdef TARGET_PPC64
2440	{
2441	uint32_t base_pvr = CPU_POWERPC_POWER_SERVER_MASK & mfpvr();
2442	ret = (base_pvr == CPU_POWERPC_POWER8_BASE);
2443	}
2444	#endif /* TARGET_PPC64 */
2445	return ret;
2446	}
2447
2448	static int parse_cap_ppc_safe_cache(struct kvm_ppc_cpu_char c)
2449	{
2450	bool l1d_thread_priv_req = !kvmppc_power8_host();
2451
2452	if (~c.behaviour & c.behaviour_mask & H_CPU_BEHAV_L1D_FLUSH_PR) {
2453	return SPAPR_CAP_FIXED;
2454	} else if ((!l1d_thread_priv_req \|\|
2455	c.character & c.character_mask & H_CPU_CHAR_L1D_THREAD_PRIV) &&
2456	(c.character & c.character_mask
2457	& (H_CPU_CHAR_L1D_FLUSH_ORI30 \| H_CPU_CHAR_L1D_FLUSH_TRIG2))) {
2458	return SPAPR_CAP_WORKAROUND;
2459	}
2460
2461	return SPAPR_CAP_BROKEN;
2462	}
2463
2464	static int parse_cap_ppc_safe_bounds_check(struct kvm_ppc_cpu_char c)
2465	{
2466	if (~c.behaviour & c.behaviour_mask & H_CPU_BEHAV_BNDS_CHK_SPEC_BAR) {
2467	return SPAPR_CAP_FIXED;
2468	} else if (c.character & c.character_mask & H_CPU_CHAR_SPEC_BAR_ORI31) {
2469	return SPAPR_CAP_WORKAROUND;
2470	}
2471
2472	return SPAPR_CAP_BROKEN;
2473	}
2474
2475	static int parse_cap_ppc_safe_indirect_branch(struct kvm_ppc_cpu_char c)
2476	{
2477	if ((~c.behaviour & c.behaviour_mask & H_CPU_BEHAV_FLUSH_COUNT_CACHE) &&
2478	(~c.character & c.character_mask & H_CPU_CHAR_CACHE_COUNT_DIS) &&
2479	(~c.character & c.character_mask & H_CPU_CHAR_BCCTRL_SERIALISED)) {
2480	return SPAPR_CAP_FIXED_NA;
2481	} else if (c.behaviour & c.behaviour_mask & H_CPU_BEHAV_FLUSH_COUNT_CACHE) {
2482	return SPAPR_CAP_WORKAROUND;
2483	} else if (c.character & c.character_mask & H_CPU_CHAR_CACHE_COUNT_DIS) {
2484	return SPAPR_CAP_FIXED_CCD;
2485	} else if (c.character & c.character_mask & H_CPU_CHAR_BCCTRL_SERIALISED) {
2486	return SPAPR_CAP_FIXED_IBS;
2487	}
2488
2489	return SPAPR_CAP_BROKEN;
2490	}
2491
2492	static int parse_cap_ppc_count_cache_flush_assist(struct kvm_ppc_cpu_char c)
2493	{
2494	if (c.character & c.character_mask & H_CPU_CHAR_BCCTR_FLUSH_ASSIST) {
2495	return SPAPR_CAP_WORKAROUND;
2496	}
2497	return SPAPR_CAP_BROKEN;
2498	}
2499
2500	bool kvmppc_has_cap_xive(void)
2501	{
2502	return cap_xive;
2503	}
2504
2505	static void kvmppc_get_cpu_characteristics(KVMState *s)
2506	{
2507	struct kvm_ppc_cpu_char c;
2508	int ret;
2509
2510	/* Assume broken */
2511	cap_ppc_safe_cache = 0;
2512	cap_ppc_safe_bounds_check = 0;
2513	cap_ppc_safe_indirect_branch = 0;
2514
2515	ret = kvm_vm_check_extension(s, KVM_CAP_PPC_GET_CPU_CHAR);
2516	if (!ret) {
2517	return;
2518	}
2519	ret = kvm_vm_ioctl(s, KVM_PPC_GET_CPU_CHAR, &c);
2520	if (ret < 0) {
2521	return;
2522	}
2523
2524	cap_ppc_safe_cache = parse_cap_ppc_safe_cache(c);
2525	cap_ppc_safe_bounds_check = parse_cap_ppc_safe_bounds_check(c);
2526	cap_ppc_safe_indirect_branch = parse_cap_ppc_safe_indirect_branch(c);
2527	cap_ppc_count_cache_flush_assist =
2528	parse_cap_ppc_count_cache_flush_assist(c);
2529	}
2530
2531	int kvmppc_get_cap_safe_cache(void)
2532	{
2533	return cap_ppc_safe_cache;
2534	}
2535
2536	int kvmppc_get_cap_safe_bounds_check(void)
2537	{
2538	return cap_ppc_safe_bounds_check;
2539	}
2540
2541	int kvmppc_get_cap_safe_indirect_branch(void)
2542	{
2543	return cap_ppc_safe_indirect_branch;
2544	}
2545
2546	int kvmppc_get_cap_count_cache_flush_assist(void)
2547	{
2548	return cap_ppc_count_cache_flush_assist;
2549	}
2550
2551	bool kvmppc_has_cap_nested_kvm_hv(void)
2552	{
2553	return !!cap_ppc_nested_kvm_hv;
2554	}
2555
2556	int kvmppc_set_cap_nested_kvm_hv(int enable)
2557	{
2558	return kvm_vm_enable_cap(kvm_state, KVM_CAP_PPC_NESTED_HV, 0, enable);
2559	}
2560
2561	bool kvmppc_has_cap_spapr_vfio(void)
2562	{
2563	return cap_spapr_vfio;
2564	}
2565
2566	int kvmppc_get_cap_large_decr(void)
2567	{
2568	return cap_large_decr;
2569	}
2570
2571	int kvmppc_enable_cap_large_decr(PowerPCCPU *cpu, int enable)
2572	{
2573	CPUState *cs = CPU(cpu);
2574	uint64_t lpcr = 0;
2575
2576	kvm_get_one_reg(cs, KVM_REG_PPC_LPCR_64, &lpcr);
2577	/* Do we need to modify the LPCR? */
2578	if (!!(lpcr & LPCR_LD) != !!enable) {
2579	if (enable) {
2580	lpcr \|= LPCR_LD;
2581	} else {
2582	lpcr &= ~LPCR_LD;
2583	}
2584	kvm_set_one_reg(cs, KVM_REG_PPC_LPCR_64, &lpcr);
2585	kvm_get_one_reg(cs, KVM_REG_PPC_LPCR_64, &lpcr);
2586
2587	if (!!(lpcr & LPCR_LD) != !!enable) {
2588	return -1;
2589	}
2590	}
2591
2592	return 0;
2593	}
2594
2595	int kvmppc_has_cap_rpt_invalidate(void)
2596	{
2597	return cap_rpt_invalidate;
2598	}
2599
2600	bool kvmppc_supports_ail_3(void)
2601	{
2602	return cap_ail_mode_3;
2603	}
2604
2605	#if defined(TARGET_PPC64)
2606	static target_ulong kvmppc_get_compat_caps(void)
2607	{
2608	struct kvm_ppc_compat_caps host_compat;
2609	int ret;
2610
2611	if (!kvm_check_extension(kvm_state, KVM_CAP_PPC_COMPAT_CAPS)) {
2612	return 0;
2613	}
2614
2615	/*
2616	* Set size to sizeof(struct kvm_ppc_compat_caps) so the kernel applies
2617	* copy_struct_from/to_user() versioning. size must be >= VER0.
2618	*/
2619	memset(&host_compat, 0, sizeof(host_compat));
2620	host_compat.size = sizeof(host_compat);
2621
2622	ret = kvm_vm_ioctl(kvm_state, KVM_PPC_GET_COMPAT_CAPS, &host_compat);
2623	if (ret == -E2BIG && host_compat.size >= KVM_PPC_COMPAT_CAPS_SIZE_VER0) {
2624	/*
2625	* Kernel is older and knows only a smaller struct version. It
2626	* wrote back its ksize into host_compat.size. Retry with that
2627	* size so the kernel accepts the call.
2628	*
2629	* When a VER1 struct is introduced, add a check here:
2630	* if (host_compat.size >= KVM_PPC_COMPAT_CAPS_SIZE_VER1) { ... }
2631	*/
2632	uint64_t ksize = host_compat.size;
2633	memset(&host_compat, 0, sizeof(host_compat));
2634	host_compat.size = ksize;
2635	ret = kvm_vm_ioctl(kvm_state, KVM_PPC_GET_COMPAT_CAPS, &host_compat);
2636	}
2637
2638	if (ret < 0) {
2639	error_report("KVM: failed to get host CPU compat capabilities: %s",
2640	strerror(-ret));
2641	return 0;
2642	}
2643
2644	return host_compat.compat_capabilities & KVM_PPC_COMPAT_BITMASK;
2645	}
2646
2647	/*
2648	* Return the effective host PVR based on the CPU compatibility mode
2649	* reported by KVM. Returns 0 if no compat mode is active or the
2650	* capability is not supported, in which case the caller falls back
2651	* to the raw hardware PVR.
2652	*/
2653	uint32_t kvm_ppc_host_compat_pvr(void)
2654	{
2655	uint32_t compat_host_pvr = 0;
2656	uint64_t cap_idx = 0;
2657	target_ulong host_caps = kvmppc_get_compat_caps();
2658
2659	if (host_caps) {
2660	cap_idx = 1ULL << ctz64(host_caps);
2661	switch (cap_idx) {
2662	case KVM_PPC_COMPAT_CAP_POWER9:
2663	compat_host_pvr = CPU_POWERPC_POWER9_DD22;
2664	break;
2665	case KVM_PPC_COMPAT_CAP_POWER10:
2666	compat_host_pvr = CPU_POWERPC_POWER10_DD20;
2667	break;
2668	case KVM_PPC_COMPAT_CAP_POWER11:
2669	compat_host_pvr = CPU_POWERPC_POWER11_DD20;
2670	break;
2671	default:
2672	break;
2673	}
2674	}
2675
2676	return compat_host_pvr;
2677	}
2678	#endif /* TARGET_PPC64 */
2679
2680	PowerPCCPUClass *kvm_ppc_get_host_cpu_class(void)
2681	{
2682	uint32_t host_pvr = mfpvr();
2683	PowerPCCPUClass *pvr_pcc;
2684
2685	#if defined(TARGET_PPC64)
2686	uint32_t compat_host_pvr;
2687
2688	compat_host_pvr = kvm_ppc_host_compat_pvr();
2689	if (compat_host_pvr) {
2690	host_pvr = compat_host_pvr;
2691	}
2692	#endif /* TARGET_PPC64 */
2693
2694	pvr_pcc = ppc_cpu_class_by_pvr(host_pvr);
2695	if (pvr_pcc == NULL) {
2696	pvr_pcc = ppc_cpu_class_by_pvr_mask(host_pvr);
2697	}
2698
2699	return pvr_pcc;
2700	}
2701
2702	static void pseries_machine_class_fixup(ObjectClass oc, void opaque)
2703	{
2704	MachineClass *mc = MACHINE_CLASS(oc);
2705
2706	mc->default_cpu_type = TYPE_HOST_POWERPC_CPU;
2707	}
2708
2709	static int kvm_ppc_register_host_cpu_type(void)
2710	{
2711	TypeInfo type_info = {
2712	.name = TYPE_HOST_POWERPC_CPU,
2713	.class_init = kvmppc_host_cpu_class_init,
2714	};
2715	PowerPCCPUClass *pvr_pcc;
2716	ObjectClass *oc;
2717	DeviceClass *dc;
2718	int i;
2719
2720	pvr_pcc = kvm_ppc_get_host_cpu_class();
2721	if (pvr_pcc == NULL) {
2722	return -1;
2723	}
2724	type_info.parent = object_class_get_name(OBJECT_CLASS(pvr_pcc));
2725	type_register_static(&type_info);
2726	/* override TCG default cpu type with 'host' cpu model */
2727	object_class_foreach(pseries_machine_class_fixup, TYPE_SPAPR_MACHINE,
2728	false, NULL);
2729
2730	oc = object_class_by_name(type_info.name);
2731	g_assert(oc);
2732
2733	/*
2734	* Update generic CPU family class alias (e.g. on a POWER8NVL host,
2735	* we want "POWER8" to be a "family" alias that points to the current
2736	* host CPU type, too)
2737	*/
2738	dc = DEVICE_CLASS(ppc_cpu_get_family_class(pvr_pcc));
2739	for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
2740	if (g_ascii_strcasecmp(ppc_cpu_aliases[i].alias, dc->desc) == 0) {
2741	const gchar suffix, cname = object_class_get_name(oc);
2742
2743	suffix = g_strstr_len(cname, -1, POWERPC_CPU_TYPE_SUFFIX);
2744	ppc_cpu_aliases[i].model = suffix ?
2745	g_strndup(cname, (gsize)(suffix - cname)) : g_strdup(cname);
2746
2747	break;
2748	}
2749	}
2750
2751	return 0;
2752	}
2753
2754	int kvmppc_define_rtas_kernel_token(uint32_t token, const char *function)
2755	{
2756	struct kvm_rtas_token_args args = {
2757	.token = token,
2758	};
2759
2760	if (!kvm_check_extension(kvm_state, KVM_CAP_PPC_RTAS)) {
2761	return -ENOENT;
2762	}
2763
2764	strncpy(args.name, function, sizeof(args.name) - 1);
2765
2766	return kvm_vm_ioctl(kvm_state, KVM_PPC_RTAS_DEFINE_TOKEN, &args);
2767	}
2768
2769	int kvmppc_get_htab_fd(bool write, uint64_t index, Error **errp)
2770	{
2771	struct kvm_get_htab_fd s = {
2772	.flags = write ? KVM_GET_HTAB_WRITE : 0,
2773	.start_index = index,
2774	};
2775	int ret;
2776
2777	if (!cap_htab_fd) {
2778	error_setg(errp, "KVM version doesn't support %s the HPT",
2779	write ? "writing" : "reading");
2780	return -ENOTSUP;
2781	}
2782
2783	ret = kvm_vm_ioctl(kvm_state, KVM_PPC_GET_HTAB_FD, &s);
2784	if (ret < 0) {
2785	error_setg_errno(errp, errno, "Unable to open fd for %s HPT %s KVM",
2786	write ? "writing" : "reading", write ? "to" : "from");
2787	return -errno;
2788	}
2789
2790	return ret;
2791	}
2792
2793	int kvmppc_save_htab(QEMUFile *f, int fd, size_t bufsize, int64_t max_ns)
2794	{
2795	int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
2796	g_autofree uint8_t *buf = g_malloc(bufsize);
2797	ssize_t rc;
2798
2799	do {
2800	rc = read(fd, buf, bufsize);
2801	if (rc < 0) {
2802	fprintf(stderr, "Error reading data from KVM HTAB fd: %s\n",
2803	strerror(errno));
2804	return rc;
2805	} else if (rc) {
2806	uint8_t *buffer = buf;
2807	ssize_t n = rc;
2808	while (n) {
2809	struct kvm_get_htab_header *head =
2810	(struct kvm_get_htab_header *) buffer;
2811	size_t chunksize = sizeof(*head) +
2812	HASH_PTE_SIZE_64 * head->n_valid;
2813
2814	qemu_put_be32(f, head->index);
2815	qemu_put_be16(f, head->n_valid);
2816	qemu_put_be16(f, head->n_invalid);
2817	qemu_put_buffer(f, (void *)(head + 1),
2818	HASH_PTE_SIZE_64 * head->n_valid);
2819
2820	buffer += chunksize;
2821	n -= chunksize;
2822	}
2823	}
2824	} while ((rc != 0)
2825	&& ((max_ns < 0) \|\|
2826	((qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) < max_ns)));
2827
2828	return (rc == 0) ? 1 : 0;
2829	}
2830
2831	int kvmppc_load_htab_chunk(QEMUFile *f, int fd, uint32_t index,
2832	uint16_t n_valid, uint16_t n_invalid, Error **errp)
2833	{
2834	size_t chunksize = sizeof(struct kvm_get_htab_header)
2835	+ n_valid * HASH_PTE_SIZE_64;
2836	g_autofree struct kvm_get_htab_header *buf = g_malloc(chunksize);
2837	ssize_t rc;
2838
2839	buf->index = index;
2840	buf->n_valid = n_valid;
2841	buf->n_invalid = n_invalid;
2842
2843	qemu_get_buffer(f, (void )(buf + 1), HASH_PTE_SIZE_64 n_valid);
2844
2845	rc = write(fd, buf, chunksize);
2846	if (rc < 0) {
2847	error_setg_errno(errp, errno, "Error writing the KVM hash table");
2848	return -errno;
2849	}
2850	if (rc != chunksize) {
2851	/* We should never get a short write on a single chunk */
2852	error_setg(errp, "Short write while restoring the KVM hash table");
2853	return -ENOSPC;
2854	}
2855	return 0;
2856	}
2857
2858	bool kvm_arch_stop_on_emulation_error(CPUState *cpu)
2859	{
2860	return true;
2861	}
2862
2863	void kvm_arch_init_irq_routing(KVMState *s)
2864	{
2865	}
2866
2867	void kvmppc_read_hptes(ppc_hash_pte64_t *hptes, hwaddr ptex, int n)
2868	{
2869	int fd, rc;
2870	int i;
2871
2872	fd = kvmppc_get_htab_fd(false, ptex, &error_abort);
2873
2874	i = 0;
2875	while (i < n) {
2876	struct kvm_get_htab_header *hdr;
2877	int m = n < HPTES_PER_GROUP ? n : HPTES_PER_GROUP;
2878	char buf[sizeof(hdr) + HPTES_PER_GROUP HASH_PTE_SIZE_64];
2879
2880	rc = read(fd, buf, sizeof(hdr) + m HASH_PTE_SIZE_64);
2881	if (rc < 0) {
2882	hw_error("kvmppc_read_hptes: Unable to read HPTEs");
2883	}
2884
2885	hdr = (struct kvm_get_htab_header *)buf;
2886	while ((i < n) && ((char *)hdr < (buf + rc))) {
2887	int invalid = hdr->n_invalid, valid = hdr->n_valid;
2888
2889	if (hdr->index != (ptex + i)) {
2890	hw_error("kvmppc_read_hptes: Unexpected HPTE index %"PRIu32
2891	" != (%"HWADDR_PRIu" + %d", hdr->index, ptex, i);
2892	}
2893
2894	if (n - i < valid) {
2895	valid = n - i;
2896	}
2897	memcpy(hptes + i, hdr + 1, HASH_PTE_SIZE_64 * valid);
2898	i += valid;
2899
2900	if ((n - i) < invalid) {
2901	invalid = n - i;
2902	}
2903	memset(hptes + i, 0, invalid * HASH_PTE_SIZE_64);
2904	i += invalid;
2905
2906	hdr = (struct kvm_get_htab_header *)
2907	((char )(hdr + 1) + HASH_PTE_SIZE_64 hdr->n_valid);
2908	}
2909	}
2910
2911	close(fd);
2912	}
2913
2914	void kvmppc_write_hpte(hwaddr ptex, uint64_t pte0, uint64_t pte1)
2915	{
2916	int fd, rc;
2917	struct {
2918	struct kvm_get_htab_header hdr;
2919	uint64_t pte0;
2920	uint64_t pte1;
2921	} buf;
2922
2923	fd = kvmppc_get_htab_fd(true, 0 /* Ignored */, &error_abort);
2924
2925	buf.hdr.n_valid = 1;
2926	buf.hdr.n_invalid = 0;
2927	buf.hdr.index = ptex;
2928	buf.pte0 = cpu_to_be64(pte0);
2929	buf.pte1 = cpu_to_be64(pte1);
2930
2931	rc = write(fd, &buf, sizeof(buf));
2932	if (rc != sizeof(buf)) {
2933	hw_error("kvmppc_write_hpte: Unable to update KVM HPT");
2934	}
2935	close(fd);
2936	}
2937
2938	int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
2939	uint64_t address, uint32_t data, PCIDevice *dev)
2940	{
2941	return 0;
2942	}
2943
2944	int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route,
2945	int vector, PCIDevice *dev)
2946	{
2947	return 0;
2948	}
2949
2950	int kvm_arch_release_virq_post(int virq)
2951	{
2952	return 0;
2953	}
2954
2955	int kvm_arch_msi_data_to_gsi(uint32_t data)
2956	{
2957	return data & 0xffff;
2958	}
2959
2960	#if defined(CONFIG_PSERIES)
2961	int kvm_handle_nmi(PowerPCCPU cpu, struct kvm_run run)
2962	{
2963	uint16_t flags = run->flags & KVM_RUN_PPC_NMI_DISP_MASK;
2964
2965	cpu_synchronize_state(CPU(cpu));
2966
2967	spapr_mce_req_event(cpu, flags == KVM_RUN_PPC_NMI_DISP_FULLY_RECOV);
2968
2969	return 0;
2970	}
2971	#endif
2972
2973	int kvmppc_enable_hwrng(void)
2974	{
2975	if (!kvm_enabled() \|\| !kvm_check_extension(kvm_state, KVM_CAP_PPC_HWRNG)) {
2976	return -1;
2977	}
2978
2979	return kvmppc_enable_hcall(kvm_state, H_RANDOM);
2980	}
2981
2982	void kvmppc_check_papr_resize_hpt(Error **errp)
2983	{
2984	if (!kvm_enabled()) {
2985	return; /* No KVM, we're good */
2986	}
2987
2988	if (cap_resize_hpt) {
2989	return; /* Kernel has explicit support, we're good */
2990	}
2991
2992	/* Otherwise fallback on looking for PR KVM */
2993	if (kvmppc_is_pr(kvm_state)) {
2994	return;
2995	}
2996
2997	error_setg(errp,
2998	"Hash page table resizing not available with this KVM version");
2999	}
3000
3001	int kvmppc_resize_hpt_prepare(PowerPCCPU *cpu, target_ulong flags, int shift)
3002	{
3003	CPUState *cs = CPU(cpu);
3004	struct kvm_ppc_resize_hpt rhpt = {
3005	.flags = flags,
3006	.shift = shift,
3007	};
3008
3009	if (!cap_resize_hpt) {
3010	return -ENOSYS;
3011	}
3012
3013	return kvm_vm_ioctl(cs->kvm_state, KVM_PPC_RESIZE_HPT_PREPARE, &rhpt);
3014	}
3015
3016	int kvmppc_resize_hpt_commit(PowerPCCPU *cpu, target_ulong flags, int shift)
3017	{
3018	CPUState *cs = CPU(cpu);
3019	struct kvm_ppc_resize_hpt rhpt = {
3020	.flags = flags,
3021	.shift = shift,
3022	};
3023
3024	if (!cap_resize_hpt) {
3025	return -ENOSYS;
3026	}
3027
3028	return kvm_vm_ioctl(cs->kvm_state, KVM_PPC_RESIZE_HPT_COMMIT, &rhpt);
3029	}
3030
3031	/*
3032	* This is a helper function to detect a post migration scenario
3033	* in which a guest, running as KVM-HV, freezes in cpu_post_load because
3034	* the guest kernel can't handle a PVR value other than the actual host
3035	* PVR in KVM_SET_SREGS, even if pvr_match() returns true.
3036	*
3037	* If we don't have cap_ppc_pvr_compat and we're not running in PR
3038	* (so, we're HV), return true. The workaround itself is done in
3039	* cpu_post_load.
3040	*
3041	* The order here is important: we'll only check for KVM PR as a
3042	* fallback if the guest kernel can't handle the situation itself.
3043	* We need to avoid as much as possible querying the running KVM type
3044	* in QEMU level.
3045	*/
3046	bool kvmppc_pvr_workaround_required(PowerPCCPU *cpu)
3047	{
3048	CPUState *cs = CPU(cpu);
3049
3050	if (!kvm_enabled()) {
3051	return false;
3052	}
3053
3054	if (cap_ppc_pvr_compat) {
3055	return false;
3056	}
3057
3058	return !kvmppc_is_pr(cs->kvm_state);
3059	}
3060
3061	void kvmppc_set_reg_ppc_online(PowerPCCPU *cpu, unsigned int online)
3062	{
3063	CPUState *cs = CPU(cpu);
3064
3065	if (kvm_enabled()) {
3066	kvm_set_one_reg(cs, KVM_REG_PPC_ONLINE, &online);
3067	}
3068	}
3069
3070	void kvmppc_set_reg_tb_offset(PowerPCCPU *cpu, int64_t tb_offset)
3071	{
3072	CPUState *cs = CPU(cpu);
3073
3074	if (kvm_enabled()) {
3075	kvm_set_one_reg(cs, KVM_REG_PPC_TB_OFFSET, &tb_offset);
3076	}
3077	}
3078
3079	void kvm_arch_accel_class_init(ObjectClass *oc)
3080	{
3081	}
3082
3083	static void kvm_cpu_accel_class_init(ObjectClass oc, const void data)
3084	{
3085	AccelCPUClass *acc = ACCEL_CPU_CLASS(oc);
3086
3087	acc->cpu_target_realize = kvmppc_cpu_realize;
3088	}
3089
3090	static const TypeInfo kvm_cpu_accel_type_info = {
3091	.name = ACCEL_CPU_NAME("kvm"),
3092
3093	.parent = TYPE_ACCEL_CPU,
3094	.class_init = kvm_cpu_accel_class_init,
3095	.abstract = true,
3096	};
3097	static void kvm_cpu_accel_register_types(void)
3098	{
3099	type_register_static(&kvm_cpu_accel_type_info);
3100	}
3101	type_init(kvm_cpu_accel_register_types);