| 1 | #include "qemu/osdep.h" |
| 2 | #include "cpu.h" |
| 3 | #include "system/kvm.h" |
| 4 | #include "system/tcg.h" |
| 5 | #include "helper_regs.h" |
| 6 | #include "mmu-hash64.h" |
| 7 | #include "migration/cpu.h" |
| 8 | #include "migration/qemu-file-types.h" |
| 9 | #include "qapi/error.h" |
| 10 | #include "kvm_ppc.h" |
| 11 | #include "power8-pmu.h" |
| 12 | #include "system/replay.h" |
| 13 | |
| 14 | static void post_load_update_msr(CPUPPCState *env) |
| 15 | { |
| 16 | target_ulong msr = env->msr; |
| 17 | |
| 18 | /* |
| 19 | * Invalidate all supported msr bits except MSR_TGPR/MSR_HVB |
| 20 | * before restoring. Note that this recomputes hflags. |
| 21 | */ |
| 22 | env->msr ^= env->msr_mask & ~((1ULL << MSR_TGPR) | MSR_HVB); |
| 23 | ppc_store_msr(env, msr); |
| 24 | } |
| 25 | |
| 26 | static int get_avr(QEMUFile *f, void *pv, size_t size, |
| 27 | const VMStateField *field) |
| 28 | { |
| 29 | ppc_avr_t *v = pv; |
| 30 | |
| 31 | v->u64[0] = qemu_get_be64(f); |
| 32 | v->u64[1] = qemu_get_be64(f); |
| 33 | |
| 34 | return 0; |
| 35 | } |
| 36 | |
| 37 | static int put_avr(QEMUFile *f, void *pv, size_t size, |
| 38 | const VMStateField *field, JSONWriter *vmdesc) |
| 39 | { |
| 40 | ppc_avr_t *v = pv; |
| 41 | |
| 42 | qemu_put_be64(f, v->u64[0]); |
| 43 | qemu_put_be64(f, v->u64[1]); |
| 44 | return 0; |
| 45 | } |
| 46 | |
| 47 | static const VMStateInfo vmstate_info_avr = { |
| 48 | .name = "avr", |
| 49 | .get = get_avr, |
| 50 | .put = put_avr, |
| 51 | }; |
| 52 | |
| 53 | #define VMSTATE_AVR_ARRAY_V(_f, _s, _n, _v) \ |
| 54 | VMSTATE_SUB_ARRAY(_f, _s, 32, _n, _v, vmstate_info_avr, ppc_avr_t) |
| 55 | |
| 56 | #define VMSTATE_AVR_ARRAY(_f, _s, _n) \ |
| 57 | VMSTATE_AVR_ARRAY_V(_f, _s, _n, 0) |
| 58 | |
| 59 | static int get_fpr(QEMUFile *f, void *pv, size_t size, |
| 60 | const VMStateField *field) |
| 61 | { |
| 62 | ppc_vsr_t *v = pv; |
| 63 | |
| 64 | v->VsrD(0) = qemu_get_be64(f); |
| 65 | |
| 66 | return 0; |
| 67 | } |
| 68 | |
| 69 | static int put_fpr(QEMUFile *f, void *pv, size_t size, |
| 70 | const VMStateField *field, JSONWriter *vmdesc) |
| 71 | { |
| 72 | ppc_vsr_t *v = pv; |
| 73 | |
| 74 | qemu_put_be64(f, v->VsrD(0)); |
| 75 | return 0; |
| 76 | } |
| 77 | |
| 78 | static const VMStateInfo vmstate_info_fpr = { |
| 79 | .name = "fpr", |
| 80 | .get = get_fpr, |
| 81 | .put = put_fpr, |
| 82 | }; |
| 83 | |
| 84 | #define VMSTATE_FPR_ARRAY_V(_f, _s, _n, _v) \ |
| 85 | VMSTATE_SUB_ARRAY(_f, _s, 0, _n, _v, vmstate_info_fpr, ppc_vsr_t) |
| 86 | |
| 87 | #define VMSTATE_FPR_ARRAY(_f, _s, _n) \ |
| 88 | VMSTATE_FPR_ARRAY_V(_f, _s, _n, 0) |
| 89 | |
| 90 | static int get_vsr(QEMUFile *f, void *pv, size_t size, |
| 91 | const VMStateField *field) |
| 92 | { |
| 93 | ppc_vsr_t *v = pv; |
| 94 | |
| 95 | v->VsrD(1) = qemu_get_be64(f); |
| 96 | |
| 97 | return 0; |
| 98 | } |
| 99 | |
| 100 | static int put_vsr(QEMUFile *f, void *pv, size_t size, |
| 101 | const VMStateField *field, JSONWriter *vmdesc) |
| 102 | { |
| 103 | ppc_vsr_t *v = pv; |
| 104 | |
| 105 | qemu_put_be64(f, v->VsrD(1)); |
| 106 | return 0; |
| 107 | } |
| 108 | |
| 109 | static const VMStateInfo vmstate_info_vsr = { |
| 110 | .name = "vsr", |
| 111 | .get = get_vsr, |
| 112 | .put = put_vsr, |
| 113 | }; |
| 114 | |
| 115 | #define VMSTATE_VSR_ARRAY_V(_f, _s, _n, _v) \ |
| 116 | VMSTATE_SUB_ARRAY(_f, _s, 0, _n, _v, vmstate_info_vsr, ppc_vsr_t) |
| 117 | |
| 118 | #define VMSTATE_VSR_ARRAY(_f, _s, _n) \ |
| 119 | VMSTATE_VSR_ARRAY_V(_f, _s, _n, 0) |
| 120 | |
| 121 | static int cpu_pre_save(void *opaque) |
| 122 | { |
| 123 | PowerPCCPU *cpu = opaque; |
| 124 | CPUPPCState *env = &cpu->env; |
| 125 | int i; |
| 126 | |
| 127 | env->spr[SPR_LR] = env->lr; |
| 128 | env->spr[SPR_CTR] = env->ctr; |
| 129 | env->spr[SPR_XER] = cpu_read_xer(env); |
| 130 | #if defined(TARGET_PPC64) |
| 131 | env->spr[SPR_CFAR] = env->cfar; |
| 132 | #endif |
| 133 | env->spr[SPR_BOOKE_SPEFSCR] = env->spe_fscr; |
| 134 | |
| 135 | for (i = 0; (i < 4) && (i < env->nb_BATs); i++) { |
| 136 | env->spr[SPR_DBAT0U + 2 * i] = env->DBAT[0][i]; |
| 137 | env->spr[SPR_DBAT0U + 2 * i + 1] = env->DBAT[1][i]; |
| 138 | env->spr[SPR_IBAT0U + 2 * i] = env->IBAT[0][i]; |
| 139 | env->spr[SPR_IBAT0U + 2 * i + 1] = env->IBAT[1][i]; |
| 140 | } |
| 141 | for (i = 0; (i < 4) && ((i + 4) < env->nb_BATs); i++) { |
| 142 | env->spr[SPR_DBAT4U + 2 * i] = env->DBAT[0][i + 4]; |
| 143 | env->spr[SPR_DBAT4U + 2 * i + 1] = env->DBAT[1][i + 4]; |
| 144 | env->spr[SPR_IBAT4U + 2 * i] = env->IBAT[0][i + 4]; |
| 145 | env->spr[SPR_IBAT4U + 2 * i + 1] = env->IBAT[1][i + 4]; |
| 146 | } |
| 147 | |
| 148 | /* Used to retain migration compatibility for pre 6.0 for 601 machines. */ |
| 149 | env->hflags_compat_nmsr = 0; |
| 150 | |
| 151 | if (tcg_enabled()) { |
| 152 | /* |
| 153 | * TCG does not maintain the DECR spr (unlike KVM) so have to save |
| 154 | * it here. |
| 155 | */ |
| 156 | env->spr[SPR_DECR] = cpu_ppc_load_decr(env); |
| 157 | } |
| 158 | |
| 159 | return 0; |
| 160 | } |
| 161 | |
| 162 | /* |
| 163 | * Determine if a given PVR is a "close enough" match to the CPU |
| 164 | * object. For TCG and KVM PR it would probably be sufficient to |
| 165 | * require an exact PVR match. However for KVM HV the user is |
| 166 | * restricted to a PVR exactly matching the host CPU. The correct way |
| 167 | * to handle this is to put the guest into an architected |
| 168 | * compatibility mode. However, to allow a more forgiving transition |
| 169 | * and migration from before this was widely done, we allow migration |
| 170 | * between sufficiently similar PVRs, as determined by the CPU class's |
| 171 | * pvr_match() hook. |
| 172 | */ |
| 173 | static bool pvr_match(PowerPCCPU *cpu, uint32_t pvr) |
| 174 | { |
| 175 | PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); |
| 176 | |
| 177 | if (pvr == pcc->pvr) { |
| 178 | return true; |
| 179 | } |
| 180 | return pcc->pvr_match(pcc, pvr, true); |
| 181 | } |
| 182 | |
| 183 | static int cpu_post_load(void *opaque, int version_id) |
| 184 | { |
| 185 | PowerPCCPU *cpu = opaque; |
| 186 | CPUPPCState *env = &cpu->env; |
| 187 | int i; |
| 188 | |
| 189 | /* |
| 190 | * If we're operating in compat mode, we should be ok as long as |
| 191 | * the destination supports the same compatibility mode. |
| 192 | * |
| 193 | * Otherwise, however, we require that the destination has exactly |
| 194 | * the same CPU model as the source. |
| 195 | */ |
| 196 | |
| 197 | #if defined(TARGET_PPC64) |
| 198 | if (cpu->compat_pvr) { |
| 199 | uint32_t compat_pvr = cpu->compat_pvr; |
| 200 | Error *local_err = NULL; |
| 201 | int ret; |
| 202 | |
| 203 | cpu->compat_pvr = 0; |
| 204 | ret = ppc_set_compat(cpu, compat_pvr, &local_err); |
| 205 | if (ret < 0) { |
| 206 | error_report_err(local_err); |
| 207 | return ret; |
| 208 | } |
| 209 | } else |
| 210 | #endif |
| 211 | { |
| 212 | if (!pvr_match(cpu, env->spr[SPR_PVR])) { |
| 213 | return -EINVAL; |
| 214 | } |
| 215 | } |
| 216 | |
| 217 | /* |
| 218 | * If we're running with KVM HV, there is a chance that the guest |
| 219 | * is running with KVM HV and its kernel does not have the |
| 220 | * capability of dealing with a different PVR other than this |
| 221 | * exact host PVR in KVM_SET_SREGS. If that happens, the |
| 222 | * guest freezes after migration. |
| 223 | * |
| 224 | * The function kvmppc_pvr_workaround_required does this verification |
| 225 | * by first checking if the kernel has the cap, returning true immediately |
| 226 | * if that is the case. Otherwise, it checks if we're running in KVM PR. |
| 227 | * If the guest kernel does not have the cap and we're not running KVM-PR |
| 228 | * (so, it is running KVM-HV), we need to ensure that KVM_SET_SREGS will |
| 229 | * receive the PVR it expects as a workaround. |
| 230 | * |
| 231 | */ |
| 232 | if (kvmppc_pvr_workaround_required(cpu)) { |
| 233 | env->spr[SPR_PVR] = env->spr_cb[SPR_PVR].default_value; |
| 234 | } |
| 235 | |
| 236 | env->lr = env->spr[SPR_LR]; |
| 237 | env->ctr = env->spr[SPR_CTR]; |
| 238 | cpu_write_xer(env, env->spr[SPR_XER]); |
| 239 | #if defined(TARGET_PPC64) |
| 240 | env->cfar = env->spr[SPR_CFAR]; |
| 241 | #endif |
| 242 | env->spe_fscr = env->spr[SPR_BOOKE_SPEFSCR]; |
| 243 | |
| 244 | for (i = 0; (i < 4) && (i < env->nb_BATs); i++) { |
| 245 | env->DBAT[0][i] = env->spr[SPR_DBAT0U + 2 * i]; |
| 246 | env->DBAT[1][i] = env->spr[SPR_DBAT0U + 2 * i + 1]; |
| 247 | env->IBAT[0][i] = env->spr[SPR_IBAT0U + 2 * i]; |
| 248 | env->IBAT[1][i] = env->spr[SPR_IBAT0U + 2 * i + 1]; |
| 249 | } |
| 250 | for (i = 0; (i < 4) && ((i + 4) < env->nb_BATs); i++) { |
| 251 | env->DBAT[0][i + 4] = env->spr[SPR_DBAT4U + 2 * i]; |
| 252 | env->DBAT[1][i + 4] = env->spr[SPR_DBAT4U + 2 * i + 1]; |
| 253 | env->IBAT[0][i + 4] = env->spr[SPR_IBAT4U + 2 * i]; |
| 254 | env->IBAT[1][i + 4] = env->spr[SPR_IBAT4U + 2 * i + 1]; |
| 255 | } |
| 256 | |
| 257 | if (!cpu->vhyp) { |
| 258 | ppc_store_sdr1(env, env->spr[SPR_SDR1]); |
| 259 | } |
| 260 | |
| 261 | if (!cpu->rtas_stopped_state) { |
| 262 | /* |
| 263 | * The source QEMU doesn't have fb802acdc8 and still uses halt + |
| 264 | * PM bits in LPCR to implement RTAS stopped state. The new (this) |
| 265 | * QEMU will have put the secondary vcpus in stopped state, |
| 266 | * waiting for the start-cpu RTAS call. That call will never come |
| 267 | * if the source cpus were already running. Try to infer the cpus |
| 268 | * state and set env->quiesced accordingly. |
| 269 | * |
| 270 | * env->quiesced = true ==> the cpu is waiting to start |
| 271 | * env->quiesced = false ==> the cpu is running (unless halted) |
| 272 | */ |
| 273 | |
| 274 | /* |
| 275 | * Halted _could_ mean quiesced, but it could also be cede, |
| 276 | * confer_self, power management, etc. |
| 277 | */ |
| 278 | if (CPU(cpu)->halted) { |
| 279 | PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); |
| 280 | /* |
| 281 | * Both the PSSCR_EC bit and LPCR PM bits set at cpu reset |
| 282 | * and rtas_stop and cleared at rtas_start, it's a good |
| 283 | * heuristic. |
| 284 | */ |
| 285 | if ((env->spr[SPR_PSSCR] & PSSCR_EC) && |
| 286 | (env->spr[SPR_LPCR] & pcc->lpcr_pm)) { |
| 287 | env->quiesced = true; |
| 288 | } else { |
| 289 | env->quiesced = false; |
| 290 | } |
| 291 | } else { |
| 292 | /* |
| 293 | * Old QEMU sets halted during rtas_stop_self. Not halted, |
| 294 | * therefore definitely not quiesced. |
| 295 | */ |
| 296 | env->quiesced = false; |
| 297 | } |
| 298 | } |
| 299 | |
| 300 | post_load_update_msr(env); |
| 301 | |
| 302 | if (tcg_enabled()) { |
| 303 | /* Re-set breaks based on regs */ |
| 304 | #if defined(TARGET_PPC64) |
| 305 | ppc_update_ciabr(env); |
| 306 | ppc_update_daw(env, 0); |
| 307 | ppc_update_daw(env, 1); |
| 308 | #endif |
| 309 | /* |
| 310 | * TCG needs to re-start the decrementer timer and/or raise the |
| 311 | * interrupt. This works for level-triggered decrementer. Edge |
| 312 | * triggered types (including HDEC) would need to carry more state. |
| 313 | */ |
| 314 | cpu_ppc_store_decr(env, env->spr[SPR_DECR]); |
| 315 | pmu_mmcr01a_updated(env); |
| 316 | } |
| 317 | |
| 318 | return 0; |
| 319 | } |
| 320 | |
| 321 | static bool fpu_needed(void *opaque) |
| 322 | { |
| 323 | PowerPCCPU *cpu = opaque; |
| 324 | |
| 325 | return cpu->env.insns_flags & PPC_FLOAT; |
| 326 | } |
| 327 | |
| 328 | static const VMStateDescription vmstate_fpu = { |
| 329 | .name = "cpu/fpu", |
| 330 | .version_id = 1, |
| 331 | .minimum_version_id = 1, |
| 332 | .needed = fpu_needed, |
| 333 | .fields = (const VMStateField[]) { |
| 334 | VMSTATE_FPR_ARRAY(env.vsr, PowerPCCPU, 32), |
| 335 | VMSTATE_UINTTL(env.fpscr, PowerPCCPU), |
| 336 | VMSTATE_END_OF_LIST() |
| 337 | }, |
| 338 | }; |
| 339 | |
| 340 | static bool altivec_needed(void *opaque) |
| 341 | { |
| 342 | PowerPCCPU *cpu = opaque; |
| 343 | |
| 344 | return cpu->env.insns_flags & PPC_ALTIVEC; |
| 345 | } |
| 346 | |
| 347 | static int get_vscr(QEMUFile *f, void *opaque, size_t size, |
| 348 | const VMStateField *field) |
| 349 | { |
| 350 | PowerPCCPU *cpu = opaque; |
| 351 | ppc_store_vscr(&cpu->env, qemu_get_be32(f)); |
| 352 | return 0; |
| 353 | } |
| 354 | |
| 355 | static int put_vscr(QEMUFile *f, void *opaque, size_t size, |
| 356 | const VMStateField *field, JSONWriter *vmdesc) |
| 357 | { |
| 358 | PowerPCCPU *cpu = opaque; |
| 359 | qemu_put_be32(f, ppc_get_vscr(&cpu->env)); |
| 360 | return 0; |
| 361 | } |
| 362 | |
| 363 | static const VMStateInfo vmstate_vscr = { |
| 364 | .name = "cpu/altivec/vscr", |
| 365 | .get = get_vscr, |
| 366 | .put = put_vscr, |
| 367 | }; |
| 368 | |
| 369 | static const VMStateDescription vmstate_altivec = { |
| 370 | .name = "cpu/altivec", |
| 371 | .version_id = 1, |
| 372 | .minimum_version_id = 1, |
| 373 | .needed = altivec_needed, |
| 374 | .fields = (const VMStateField[]) { |
| 375 | VMSTATE_AVR_ARRAY(env.vsr, PowerPCCPU, 32), |
| 376 | /* |
| 377 | * Save the architecture value of the vscr, not the internally |
| 378 | * expanded version. Since this architecture value does not |
| 379 | * exist in memory to be stored, this requires a but of hoop |
| 380 | * jumping. We want OFFSET=0 so that we effectively pass CPU |
| 381 | * to the helper functions. |
| 382 | */ |
| 383 | { |
| 384 | .name = "vscr", |
| 385 | .version_id = 0, |
| 386 | .size = sizeof(uint32_t), |
| 387 | .info = &vmstate_vscr, |
| 388 | .flags = VMS_SINGLE, |
| 389 | .offset = 0 |
| 390 | }, |
| 391 | VMSTATE_END_OF_LIST() |
| 392 | }, |
| 393 | }; |
| 394 | |
| 395 | static bool vsx_needed(void *opaque) |
| 396 | { |
| 397 | PowerPCCPU *cpu = opaque; |
| 398 | |
| 399 | return cpu->env.insns_flags2 & PPC2_VSX; |
| 400 | } |
| 401 | |
| 402 | static const VMStateDescription vmstate_vsx = { |
| 403 | .name = "cpu/vsx", |
| 404 | .version_id = 1, |
| 405 | .minimum_version_id = 1, |
| 406 | .needed = vsx_needed, |
| 407 | .fields = (const VMStateField[]) { |
| 408 | VMSTATE_VSR_ARRAY(env.vsr, PowerPCCPU, 32), |
| 409 | VMSTATE_END_OF_LIST() |
| 410 | }, |
| 411 | }; |
| 412 | |
| 413 | #ifdef TARGET_PPC64 |
| 414 | /* Transactional memory state */ |
| 415 | static bool tm_needed(void *opaque) |
| 416 | { |
| 417 | PowerPCCPU *cpu = opaque; |
| 418 | CPUPPCState *env = &cpu->env; |
| 419 | return FIELD_EX64(env->msr, MSR, TS); |
| 420 | } |
| 421 | |
| 422 | static const VMStateDescription vmstate_tm = { |
| 423 | .name = "cpu/tm", |
| 424 | .version_id = 1, |
| 425 | .minimum_version_id = 1, |
| 426 | .needed = tm_needed, |
| 427 | .fields = (const VMStateField []) { |
| 428 | VMSTATE_UINTTL_ARRAY(env.tm_gpr, PowerPCCPU, 32), |
| 429 | VMSTATE_AVR_ARRAY(env.tm_vsr, PowerPCCPU, 64), |
| 430 | VMSTATE_UINT64(env.tm_cr, PowerPCCPU), |
| 431 | VMSTATE_UINT64(env.tm_lr, PowerPCCPU), |
| 432 | VMSTATE_UINT64(env.tm_ctr, PowerPCCPU), |
| 433 | VMSTATE_UINT64(env.tm_fpscr, PowerPCCPU), |
| 434 | VMSTATE_UINT64(env.tm_amr, PowerPCCPU), |
| 435 | VMSTATE_UINT64(env.tm_ppr, PowerPCCPU), |
| 436 | VMSTATE_UINT64(env.tm_vrsave, PowerPCCPU), |
| 437 | VMSTATE_UINT32(env.tm_vscr, PowerPCCPU), |
| 438 | VMSTATE_UINT64(env.tm_dscr, PowerPCCPU), |
| 439 | VMSTATE_UINT64(env.tm_tar, PowerPCCPU), |
| 440 | VMSTATE_END_OF_LIST() |
| 441 | }, |
| 442 | }; |
| 443 | #endif |
| 444 | |
| 445 | static bool sr_needed(void *opaque) |
| 446 | { |
| 447 | #ifdef TARGET_PPC64 |
| 448 | PowerPCCPU *cpu = opaque; |
| 449 | |
| 450 | return !mmu_is_64bit(cpu->env.mmu_model); |
| 451 | #else |
| 452 | return true; |
| 453 | #endif |
| 454 | } |
| 455 | |
| 456 | static const VMStateDescription vmstate_sr = { |
| 457 | .name = "cpu/sr", |
| 458 | .version_id = 1, |
| 459 | .minimum_version_id = 1, |
| 460 | .needed = sr_needed, |
| 461 | .fields = (const VMStateField[]) { |
| 462 | VMSTATE_UINTTL_ARRAY(env.sr, PowerPCCPU, 32), |
| 463 | VMSTATE_END_OF_LIST() |
| 464 | }, |
| 465 | }; |
| 466 | |
| 467 | #ifdef TARGET_PPC64 |
| 468 | static int get_slbe(QEMUFile *f, void *pv, size_t size, |
| 469 | const VMStateField *field) |
| 470 | { |
| 471 | ppc_slb_t *v = pv; |
| 472 | |
| 473 | v->esid = qemu_get_be64(f); |
| 474 | v->vsid = qemu_get_be64(f); |
| 475 | |
| 476 | return 0; |
| 477 | } |
| 478 | |
| 479 | static int put_slbe(QEMUFile *f, void *pv, size_t size, |
| 480 | const VMStateField *field, JSONWriter *vmdesc) |
| 481 | { |
| 482 | ppc_slb_t *v = pv; |
| 483 | |
| 484 | qemu_put_be64(f, v->esid); |
| 485 | qemu_put_be64(f, v->vsid); |
| 486 | return 0; |
| 487 | } |
| 488 | |
| 489 | static const VMStateInfo vmstate_info_slbe = { |
| 490 | .name = "slbe", |
| 491 | .get = get_slbe, |
| 492 | .put = put_slbe, |
| 493 | }; |
| 494 | |
| 495 | #define VMSTATE_SLB_ARRAY_V(_f, _s, _n, _v) \ |
| 496 | VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_slbe, ppc_slb_t) |
| 497 | |
| 498 | #define VMSTATE_SLB_ARRAY(_f, _s, _n) \ |
| 499 | VMSTATE_SLB_ARRAY_V(_f, _s, _n, 0) |
| 500 | |
| 501 | static bool slb_needed(void *opaque) |
| 502 | { |
| 503 | PowerPCCPU *cpu = opaque; |
| 504 | |
| 505 | /* We don't support any of the old segment table based 64-bit CPUs */ |
| 506 | return mmu_is_64bit(cpu->env.mmu_model); |
| 507 | } |
| 508 | |
| 509 | static int slb_post_load(void *opaque, int version_id) |
| 510 | { |
| 511 | PowerPCCPU *cpu = opaque; |
| 512 | CPUPPCState *env = &cpu->env; |
| 513 | int i; |
| 514 | |
| 515 | /* |
| 516 | * We've pulled in the raw esid and vsid values from the migration |
| 517 | * stream, but we need to recompute the page size pointers |
| 518 | */ |
| 519 | for (i = 0; i < cpu->hash64_opts->slb_size; i++) { |
| 520 | if (ppc_store_slb(cpu, i, env->slb[i].esid, env->slb[i].vsid) < 0) { |
| 521 | /* Migration source had bad values in its SLB */ |
| 522 | return -1; |
| 523 | } |
| 524 | } |
| 525 | |
| 526 | return 0; |
| 527 | } |
| 528 | |
| 529 | static const VMStateDescription vmstate_slb = { |
| 530 | .name = "cpu/slb", |
| 531 | .version_id = 2, |
| 532 | .minimum_version_id = 1, |
| 533 | .needed = slb_needed, |
| 534 | .post_load = slb_post_load, |
| 535 | .fields = (const VMStateField[]) { |
| 536 | VMSTATE_SLB_ARRAY(env.slb, PowerPCCPU, MAX_SLB_ENTRIES), |
| 537 | VMSTATE_END_OF_LIST() |
| 538 | } |
| 539 | }; |
| 540 | #endif /* TARGET_PPC64 */ |
| 541 | |
| 542 | static const VMStateDescription vmstate_tlb6xx_entry = { |
| 543 | .name = "cpu/tlb6xx_entry", |
| 544 | .version_id = 1, |
| 545 | .minimum_version_id = 1, |
| 546 | .fields = (const VMStateField[]) { |
| 547 | VMSTATE_UINTTL(pte0, ppc6xx_tlb_t), |
| 548 | VMSTATE_UINTTL(pte1, ppc6xx_tlb_t), |
| 549 | VMSTATE_UINTTL(EPN, ppc6xx_tlb_t), |
| 550 | VMSTATE_END_OF_LIST() |
| 551 | }, |
| 552 | }; |
| 553 | |
| 554 | static bool tlb6xx_needed(void *opaque) |
| 555 | { |
| 556 | PowerPCCPU *cpu = opaque; |
| 557 | CPUPPCState *env = &cpu->env; |
| 558 | |
| 559 | return env->nb_tlb && (env->tlb_type == TLB_6XX); |
| 560 | } |
| 561 | |
| 562 | static const VMStateDescription vmstate_tlb6xx = { |
| 563 | .name = "cpu/tlb6xx", |
| 564 | .version_id = 1, |
| 565 | .minimum_version_id = 1, |
| 566 | .needed = tlb6xx_needed, |
| 567 | .fields = (const VMStateField[]) { |
| 568 | VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU), |
| 569 | VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlb6, PowerPCCPU, |
| 570 | env.nb_tlb, |
| 571 | vmstate_tlb6xx_entry, |
| 572 | ppc6xx_tlb_t), |
| 573 | VMSTATE_UINTTL_ARRAY(env.tgpr, PowerPCCPU, 4), |
| 574 | VMSTATE_END_OF_LIST() |
| 575 | } |
| 576 | }; |
| 577 | |
| 578 | static const VMStateDescription vmstate_tlbemb_entry = { |
| 579 | .name = "cpu/tlbemb_entry", |
| 580 | .version_id = 1, |
| 581 | .minimum_version_id = 1, |
| 582 | .fields = (const VMStateField[]) { |
| 583 | VMSTATE_UINT64(RPN, ppcemb_tlb_t), |
| 584 | VMSTATE_UINTTL(EPN, ppcemb_tlb_t), |
| 585 | VMSTATE_UINTTL(PID, ppcemb_tlb_t), |
| 586 | VMSTATE_UINTTL(size, ppcemb_tlb_t), |
| 587 | VMSTATE_UINT32(prot, ppcemb_tlb_t), |
| 588 | VMSTATE_UINT32(attr, ppcemb_tlb_t), |
| 589 | VMSTATE_END_OF_LIST() |
| 590 | }, |
| 591 | }; |
| 592 | |
| 593 | static bool tlbemb_needed(void *opaque) |
| 594 | { |
| 595 | PowerPCCPU *cpu = opaque; |
| 596 | CPUPPCState *env = &cpu->env; |
| 597 | |
| 598 | return env->nb_tlb && (env->tlb_type == TLB_EMB); |
| 599 | } |
| 600 | |
| 601 | static const VMStateDescription vmstate_tlbemb = { |
| 602 | .name = "cpu/tlbemb", |
| 603 | .version_id = 1, |
| 604 | .minimum_version_id = 1, |
| 605 | .needed = tlbemb_needed, |
| 606 | .fields = (const VMStateField[]) { |
| 607 | VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU), |
| 608 | VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlbe, PowerPCCPU, |
| 609 | env.nb_tlb, |
| 610 | vmstate_tlbemb_entry, |
| 611 | ppcemb_tlb_t), |
| 612 | VMSTATE_END_OF_LIST() |
| 613 | }, |
| 614 | }; |
| 615 | |
| 616 | static const VMStateDescription vmstate_tlbmas_entry = { |
| 617 | .name = "cpu/tlbmas_entry", |
| 618 | .version_id = 1, |
| 619 | .minimum_version_id = 1, |
| 620 | .fields = (const VMStateField[]) { |
| 621 | VMSTATE_UINT32(mas8, ppcmas_tlb_t), |
| 622 | VMSTATE_UINT32(mas1, ppcmas_tlb_t), |
| 623 | VMSTATE_UINT64(mas2, ppcmas_tlb_t), |
| 624 | VMSTATE_UINT64(mas7_3, ppcmas_tlb_t), |
| 625 | VMSTATE_END_OF_LIST() |
| 626 | }, |
| 627 | }; |
| 628 | |
| 629 | static bool tlbmas_needed(void *opaque) |
| 630 | { |
| 631 | PowerPCCPU *cpu = opaque; |
| 632 | CPUPPCState *env = &cpu->env; |
| 633 | |
| 634 | return env->nb_tlb && (env->tlb_type == TLB_MAS); |
| 635 | } |
| 636 | |
| 637 | static const VMStateDescription vmstate_tlbmas = { |
| 638 | .name = "cpu/tlbmas", |
| 639 | .version_id = 1, |
| 640 | .minimum_version_id = 1, |
| 641 | .needed = tlbmas_needed, |
| 642 | .fields = (const VMStateField[]) { |
| 643 | VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU), |
| 644 | VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlbm, PowerPCCPU, |
| 645 | env.nb_tlb, |
| 646 | vmstate_tlbmas_entry, |
| 647 | ppcmas_tlb_t), |
| 648 | VMSTATE_END_OF_LIST() |
| 649 | } |
| 650 | }; |
| 651 | |
| 652 | static bool compat_needed(void *opaque) |
| 653 | { |
| 654 | PowerPCCPU *cpu = opaque; |
| 655 | |
| 656 | assert(!(cpu->compat_pvr && !cpu->vhyp)); |
| 657 | return cpu->compat_pvr != 0; |
| 658 | } |
| 659 | |
| 660 | static const VMStateDescription vmstate_compat = { |
| 661 | .name = "cpu/compat", |
| 662 | .version_id = 1, |
| 663 | .minimum_version_id = 1, |
| 664 | .needed = compat_needed, |
| 665 | .fields = (const VMStateField[]) { |
| 666 | VMSTATE_UINT32(compat_pvr, PowerPCCPU), |
| 667 | VMSTATE_END_OF_LIST() |
| 668 | } |
| 669 | }; |
| 670 | |
| 671 | static bool reservation_needed(void *opaque) |
| 672 | { |
| 673 | return (replay_mode != REPLAY_MODE_NONE); |
| 674 | } |
| 675 | |
| 676 | static const VMStateDescription vmstate_reservation = { |
| 677 | .name = "cpu/reservation", |
| 678 | .version_id = 1, |
| 679 | .minimum_version_id = 1, |
| 680 | .needed = reservation_needed, |
| 681 | .fields = (const VMStateField[]) { |
| 682 | VMSTATE_UINTTL(env.reserve_addr, PowerPCCPU), |
| 683 | VMSTATE_UINTTL(env.reserve_length, PowerPCCPU), |
| 684 | VMSTATE_UINTTL(env.reserve_val, PowerPCCPU), |
| 685 | #if defined(TARGET_PPC64) |
| 686 | VMSTATE_UINTTL(env.reserve_val2, PowerPCCPU), |
| 687 | #endif |
| 688 | VMSTATE_END_OF_LIST() |
| 689 | } |
| 690 | }; |
| 691 | |
| 692 | static bool rtas_stopped_needed(void *opaque) |
| 693 | { |
| 694 | PowerPCCPU *cpu = opaque; |
| 695 | |
| 696 | return cpu->rtas_stopped_state; |
| 697 | } |
| 698 | |
| 699 | static const VMStateDescription vmstate_rtas_stopped = { |
| 700 | .name = "cpu/rtas_stopped", |
| 701 | .version_id = 1, |
| 702 | .minimum_version_id = 1, |
| 703 | .needed = rtas_stopped_needed, |
| 704 | .fields = (const VMStateField[]) { |
| 705 | /* |
| 706 | * "RTAS stopped" state, independent of halted state. For QEMU |
| 707 | * < 10.0, this is taken from cpu->halted at cpu_post_load() |
| 708 | */ |
| 709 | VMSTATE_BOOL(env.quiesced, PowerPCCPU), |
| 710 | VMSTATE_END_OF_LIST() |
| 711 | } |
| 712 | }; |
| 713 | |
| 714 | #ifdef TARGET_PPC64 |
| 715 | static bool bhrb_needed(void *opaque) |
| 716 | { |
| 717 | PowerPCCPU *cpu = opaque; |
| 718 | return (cpu->env.flags & POWERPC_FLAG_BHRB) != 0; |
| 719 | } |
| 720 | |
| 721 | static const VMStateDescription vmstate_bhrb = { |
| 722 | .name = "cpu/bhrb", |
| 723 | .version_id = 1, |
| 724 | .minimum_version_id = 1, |
| 725 | .needed = bhrb_needed, |
| 726 | .fields = (VMStateField[]) { |
| 727 | VMSTATE_UINTTL(env.bhrb_offset, PowerPCCPU), |
| 728 | VMSTATE_UINT64_ARRAY(env.bhrb, PowerPCCPU, BHRB_MAX_NUM_ENTRIES), |
| 729 | VMSTATE_END_OF_LIST() |
| 730 | } |
| 731 | }; |
| 732 | #endif |
| 733 | |
| 734 | const VMStateDescription vmstate_ppc_cpu = { |
| 735 | .name = "cpu", |
| 736 | .version_id = 5, |
| 737 | .minimum_version_id = 5, |
| 738 | .pre_save = cpu_pre_save, |
| 739 | .post_load = cpu_post_load, |
| 740 | .fields = (const VMStateField[]) { |
| 741 | VMSTATE_UNUSED(sizeof(target_ulong)), /* was _EQUAL(env.spr[SPR_PVR]) */ |
| 742 | |
| 743 | /* User mode architected state */ |
| 744 | VMSTATE_UINTTL_ARRAY(env.gpr, PowerPCCPU, 32), |
| 745 | #if !defined(TARGET_PPC64) |
| 746 | VMSTATE_UINTTL_ARRAY(env.gprh, PowerPCCPU, 32), |
| 747 | #endif |
| 748 | VMSTATE_UINT32_ARRAY(env.crf, PowerPCCPU, 8), |
| 749 | VMSTATE_UINTTL(env.nip, PowerPCCPU), |
| 750 | |
| 751 | /* SPRs */ |
| 752 | VMSTATE_UINTTL_ARRAY(env.spr, PowerPCCPU, 1024), |
| 753 | VMSTATE_UINT64(env.spe_acc, PowerPCCPU), |
| 754 | |
| 755 | VMSTATE_UNUSED(sizeof(target_ulong)), /* was env.reserve_addr */ |
| 756 | |
| 757 | /* Supervisor mode architected state */ |
| 758 | VMSTATE_UINTTL(env.msr, PowerPCCPU), |
| 759 | |
| 760 | /* Backward compatible internal state */ |
| 761 | VMSTATE_UINTTL(env.hflags_compat_nmsr, PowerPCCPU), |
| 762 | |
| 763 | VMSTATE_END_OF_LIST() |
| 764 | }, |
| 765 | .subsections = (const VMStateDescription * const []) { |
| 766 | &vmstate_fpu, |
| 767 | &vmstate_altivec, |
| 768 | &vmstate_vsx, |
| 769 | &vmstate_sr, |
| 770 | #ifdef TARGET_PPC64 |
| 771 | &vmstate_tm, |
| 772 | &vmstate_slb, |
| 773 | &vmstate_bhrb, |
| 774 | #endif /* TARGET_PPC64 */ |
| 775 | &vmstate_tlb6xx, |
| 776 | &vmstate_tlbemb, |
| 777 | &vmstate_tlbmas, |
| 778 | &vmstate_compat, |
| 779 | &vmstate_reservation, |
| 780 | &vmstate_rtas_stopped, |
| 781 | NULL |
| 782 | } |
| 783 | }; |