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1 #ifndef MMU_HASH32_H
2 #define MMU_HASH32_H
3
4 #ifndef CONFIG_USER_ONLY
5
6 #include "exec/page-protection.h"
7 #include "system/memory.h"
8
9 bool ppc_hash32_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_type,
10 hwaddr *raddrp, int *psizep, int *protp, int mmu_idx,
11 bool guest_visible);
12
13 /*
14 * Segment register definitions
15 */
16
17 #define SR32_T 0x80000000
18 #define SR32_KS 0x40000000
19 #define SR32_KP 0x20000000
20 #define SR32_NX 0x10000000
21 #define SR32_VSID 0x00ffffff
22
23 /*
24 * Block Address Translation (BAT) definitions
25 */
26
27 #define BATU32_BEPIU 0xf0000000
28 #define BATU32_BEPIL 0x0ffe0000
29 #define BATU32_BEPI 0xfffe0000
30 #define BATU32_BL 0x00001ffc
31 #define BATU32_VS 0x00000002
32 #define BATU32_VP 0x00000001
33
34
35 #define BATL32_BRPN 0xfffe0000
36 #define BATL32_WIMG 0x00000078
37 #define BATL32_PP 0x00000003
38
39 /*
40 * Hash page table definitions
41 */
42 #define SDR_32_HTABORG 0xFFFF0000UL
43 #define SDR_32_HTABMASK 0x000001FFUL
44
45 #define HPTES_PER_GROUP 8
46 #define HASH_PTE_SIZE_32 8
47 #define HASH_PTEG_SIZE_32 (HASH_PTE_SIZE_32 * HPTES_PER_GROUP)
48
49 #define HPTE32_V_VALID 0x80000000
50 #define HPTE32_V_VSID 0x7fffff80
51 #define HPTE32_V_SECONDARY 0x00000040
52 #define HPTE32_V_API 0x0000003f
53 #define HPTE32_V_COMPARE(x, y) (!(((x) ^ (y)) & 0x7fffffbf))
54
55 #define HPTE32_R_RPN 0xfffff000
56 #define HPTE32_R_R 0x00000100
57 #define HPTE32_R_C 0x00000080
58 #define HPTE32_R_W 0x00000040
59 #define HPTE32_R_I 0x00000020
60 #define HPTE32_R_M 0x00000010
61 #define HPTE32_R_G 0x00000008
62 #define HPTE32_R_WIMG 0x00000078
63 #define HPTE32_R_PP 0x00000003
64
65 static inline hwaddr ppc_hash32_hpt_base(PowerPCCPU *cpu)
66 {
67 return cpu->env.spr[SPR_SDR1] & SDR_32_HTABORG;
68 }
69
70 static inline hwaddr ppc_hash32_hpt_mask(PowerPCCPU *cpu)
71 {
72 return ((cpu->env.spr[SPR_SDR1] & SDR_32_HTABMASK) << 16) | 0xFFFF;
73 }
74
75 static inline hwaddr get_pteg_offset32(PowerPCCPU *cpu, hwaddr hash)
76 {
77 return (hash * HASH_PTEG_SIZE_32) & ppc_hash32_hpt_mask(cpu);
78 }
79
80 static inline bool ppc_hash32_key(bool pr, target_ulong sr)
81 {
82 return pr ? (sr & SR32_KP) : (sr & SR32_KS);
83 }
84
85 static inline int ppc_hash32_prot(bool key, int pp, bool nx)
86 {
87 int prot;
88
89 if (key) {
90 switch (pp) {
91 case 0x0:
92 prot = 0;
93 break;
94 case 0x1:
95 case 0x3:
96 prot = PAGE_READ;
97 break;
98 case 0x2:
99 prot = PAGE_READ | PAGE_WRITE;
100 break;
101 default:
102 g_assert_not_reached();
103 }
104 } else {
105 switch (pp) {
106 case 0x0:
107 case 0x1:
108 case 0x2:
109 prot = PAGE_READ | PAGE_WRITE;
110 break;
111 case 0x3:
112 prot = PAGE_READ;
113 break;
114 default:
115 g_assert_not_reached();
116 }
117 }
118 return nx ? prot : prot | PAGE_EXEC;
119 }
120
121 static inline int ppc_hash32_bat_prot(target_ulong batu, target_ulong batl)
122 {
123 int prot = 0;
124 int pp = batl & BATL32_PP;
125
126 if (pp) {
127 prot = PAGE_READ | PAGE_EXEC;
128 if (pp == 0x2) {
129 prot |= PAGE_WRITE;
130 }
131 }
132 return prot;
133 }
134
135 typedef struct {
136 uint32_t pte0, pte1;
137 } ppc_hash_pte32_t;
138
139 #endif /* CONFIG_USER_ONLY */
140
141 #endif /* MMU_HASH32_H */