| 1 | /* |
| 2 | * PowerPC exception emulation helpers for QEMU (TCG specific) |
| 3 | * |
| 4 | * Copyright (c) 2003-2007 Jocelyn Mayer |
| 5 | * |
| 6 | * This library is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU Lesser General Public |
| 8 | * License as published by the Free Software Foundation; either |
| 9 | * version 2.1 of the License, or (at your option) any later version. |
| 10 | * |
| 11 | * This library is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 14 | * Lesser General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU Lesser General Public |
| 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
| 18 | */ |
| 19 | #include "qemu/osdep.h" |
| 20 | #include "qemu/main-loop.h" |
| 21 | #include "qemu/log.h" |
| 22 | #include "target/ppc/cpu.h" |
| 23 | #include "accel/tcg/cpu-ldst.h" |
| 24 | #include "accel/tcg/cpu-loop.h" |
| 25 | #include "exec/helper-proto.h" |
| 26 | #include "system/runstate.h" |
| 27 | |
| 28 | #include "helper_regs.h" |
| 29 | #include "hw/ppc/ppc.h" |
| 30 | #include "internal.h" |
| 31 | #include "cpu.h" |
| 32 | #include "trace.h" |
| 33 | |
| 34 | /*****************************************************************************/ |
| 35 | /* Exceptions processing helpers */ |
| 36 | |
| 37 | void raise_exception_err_ra(CPUPPCState *env, uint32_t exception, |
| 38 | uint32_t error_code, uintptr_t raddr) |
| 39 | { |
| 40 | CPUState *cs = env_cpu(env); |
| 41 | |
| 42 | cs->exception_index = exception; |
| 43 | env->error_code = error_code; |
| 44 | cpu_loop_exit_restore(cs, raddr); |
| 45 | } |
| 46 | |
| 47 | void helper_raise_exception_err(CPUPPCState *env, uint32_t exception, |
| 48 | uint32_t error_code) |
| 49 | { |
| 50 | raise_exception_err_ra(env, exception, error_code, 0); |
| 51 | } |
| 52 | |
| 53 | void helper_raise_exception(CPUPPCState *env, uint32_t exception) |
| 54 | { |
| 55 | raise_exception_err_ra(env, exception, 0, 0); |
| 56 | } |
| 57 | |
| 58 | #ifndef CONFIG_USER_ONLY |
| 59 | |
| 60 | static G_NORETURN void raise_exception_err(CPUPPCState *env, uint32_t exception, |
| 61 | uint32_t error_code) |
| 62 | { |
| 63 | raise_exception_err_ra(env, exception, error_code, 0); |
| 64 | } |
| 65 | |
| 66 | static G_NORETURN void raise_exception(CPUPPCState *env, uint32_t exception) |
| 67 | { |
| 68 | raise_exception_err_ra(env, exception, 0, 0); |
| 69 | } |
| 70 | |
| 71 | #endif /* !CONFIG_USER_ONLY */ |
| 72 | |
| 73 | void helper_TW(CPUPPCState *env, target_ulong arg1, target_ulong arg2, |
| 74 | uint32_t flags) |
| 75 | { |
| 76 | if (!likely(!(((int32_t)arg1 < (int32_t)arg2 && (flags & 0x10)) || |
| 77 | ((int32_t)arg1 > (int32_t)arg2 && (flags & 0x08)) || |
| 78 | ((int32_t)arg1 == (int32_t)arg2 && (flags & 0x04)) || |
| 79 | ((uint32_t)arg1 < (uint32_t)arg2 && (flags & 0x02)) || |
| 80 | ((uint32_t)arg1 > (uint32_t)arg2 && (flags & 0x01))))) { |
| 81 | raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM, |
| 82 | POWERPC_EXCP_TRAP, GETPC()); |
| 83 | } |
| 84 | } |
| 85 | |
| 86 | #ifdef TARGET_PPC64 |
| 87 | void helper_TD(CPUPPCState *env, target_ulong arg1, target_ulong arg2, |
| 88 | uint32_t flags) |
| 89 | { |
| 90 | if (!likely(!(((int64_t)arg1 < (int64_t)arg2 && (flags & 0x10)) || |
| 91 | ((int64_t)arg1 > (int64_t)arg2 && (flags & 0x08)) || |
| 92 | ((int64_t)arg1 == (int64_t)arg2 && (flags & 0x04)) || |
| 93 | ((uint64_t)arg1 < (uint64_t)arg2 && (flags & 0x02)) || |
| 94 | ((uint64_t)arg1 > (uint64_t)arg2 && (flags & 0x01))))) { |
| 95 | raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM, |
| 96 | POWERPC_EXCP_TRAP, GETPC()); |
| 97 | } |
| 98 | } |
| 99 | #endif /* TARGET_PPC64 */ |
| 100 | |
| 101 | static uint32_t helper_SIMON_LIKE_32_64(uint32_t x, uint64_t key, uint32_t lane) |
| 102 | { |
| 103 | const uint16_t c = 0xfffc; |
| 104 | const uint64_t z0 = 0xfa2561cdf44ac398ULL; |
| 105 | uint16_t z = 0, temp; |
| 106 | uint16_t k[32], eff_k[32], xleft[33], xright[33], fxleft[32]; |
| 107 | |
| 108 | for (int i = 3; i >= 0; i--) { |
| 109 | k[i] = key & 0xffff; |
| 110 | key >>= 16; |
| 111 | } |
| 112 | xleft[0] = x & 0xffff; |
| 113 | xright[0] = (x >> 16) & 0xffff; |
| 114 | |
| 115 | for (int i = 0; i < 28; i++) { |
| 116 | z = (z0 >> (63 - i)) & 1; |
| 117 | temp = ror16(k[i + 3], 3) ^ k[i + 1]; |
| 118 | k[i + 4] = c ^ z ^ k[i] ^ temp ^ ror16(temp, 1); |
| 119 | } |
| 120 | |
| 121 | for (int i = 0; i < 8; i++) { |
| 122 | eff_k[4 * i + 0] = k[4 * i + ((0 + lane) % 4)]; |
| 123 | eff_k[4 * i + 1] = k[4 * i + ((1 + lane) % 4)]; |
| 124 | eff_k[4 * i + 2] = k[4 * i + ((2 + lane) % 4)]; |
| 125 | eff_k[4 * i + 3] = k[4 * i + ((3 + lane) % 4)]; |
| 126 | } |
| 127 | |
| 128 | for (int i = 0; i < 32; i++) { |
| 129 | fxleft[i] = (rol16(xleft[i], 1) & |
| 130 | rol16(xleft[i], 8)) ^ rol16(xleft[i], 2); |
| 131 | xleft[i + 1] = xright[i] ^ fxleft[i] ^ eff_k[i]; |
| 132 | xright[i + 1] = xleft[i]; |
| 133 | } |
| 134 | |
| 135 | return (((uint32_t)xright[32]) << 16) | xleft[32]; |
| 136 | } |
| 137 | |
| 138 | static uint64_t hash_digest(uint64_t ra, uint64_t rb, uint64_t key) |
| 139 | { |
| 140 | uint64_t stage0_h = 0ULL, stage0_l = 0ULL; |
| 141 | uint64_t stage1_h, stage1_l; |
| 142 | |
| 143 | for (int i = 0; i < 4; i++) { |
| 144 | stage0_h |= ror64(rb & 0xff, 8 * (2 * i + 1)); |
| 145 | stage0_h |= ((ra >> 32) & 0xff) << (8 * 2 * i); |
| 146 | stage0_l |= ror64((rb >> 32) & 0xff, 8 * (2 * i + 1)); |
| 147 | stage0_l |= (ra & 0xff) << (8 * 2 * i); |
| 148 | rb >>= 8; |
| 149 | ra >>= 8; |
| 150 | } |
| 151 | |
| 152 | stage1_h = (uint64_t)helper_SIMON_LIKE_32_64(stage0_h >> 32, key, 0) << 32; |
| 153 | stage1_h |= helper_SIMON_LIKE_32_64(stage0_h, key, 1); |
| 154 | stage1_l = (uint64_t)helper_SIMON_LIKE_32_64(stage0_l >> 32, key, 2) << 32; |
| 155 | stage1_l |= helper_SIMON_LIKE_32_64(stage0_l, key, 3); |
| 156 | |
| 157 | return stage1_h ^ stage1_l; |
| 158 | } |
| 159 | |
| 160 | static void do_hash(CPUPPCState *env, target_ulong ea, target_ulong ra, |
| 161 | target_ulong rb, uint64_t key, bool store) |
| 162 | { |
| 163 | uint64_t calculated_hash = hash_digest(ra, rb, key), loaded_hash; |
| 164 | unsigned mmu_idx = cpu_mmu_index(env_cpu(env), false); |
| 165 | MemOp op = ppc_data_endian_env(env) | MO_UQ; |
| 166 | MemOpIdx oi = make_memop_idx(op, mmu_idx); |
| 167 | uintptr_t retaddr = GETPC(); |
| 168 | |
| 169 | if (store) { |
| 170 | cpu_stq_mmu(env, ea, calculated_hash, oi, retaddr); |
| 171 | } else { |
| 172 | loaded_hash = cpu_ldq_mmu(env, ea, oi, retaddr); |
| 173 | if (loaded_hash != calculated_hash) { |
| 174 | raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM, |
| 175 | POWERPC_EXCP_TRAP, retaddr); |
| 176 | } |
| 177 | } |
| 178 | } |
| 179 | |
| 180 | #include "qemu/guest-random.h" |
| 181 | |
| 182 | #ifdef TARGET_PPC64 |
| 183 | #define HELPER_HASH(op, key, store, dexcr_aspect) \ |
| 184 | void helper_##op(CPUPPCState *env, target_ulong ea, target_ulong ra, \ |
| 185 | target_ulong rb) \ |
| 186 | { \ |
| 187 | if (env->msr & R_MSR_PR_MASK) { \ |
| 188 | if (!(env->spr[SPR_DEXCR] & R_DEXCR_PRO_##dexcr_aspect##_MASK || \ |
| 189 | env->spr[SPR_HDEXCR] & R_HDEXCR_ENF_##dexcr_aspect##_MASK)) \ |
| 190 | return; \ |
| 191 | } else if (!(env->msr & R_MSR_HV_MASK)) { \ |
| 192 | if (!(env->spr[SPR_DEXCR] & R_DEXCR_PNH_##dexcr_aspect##_MASK || \ |
| 193 | env->spr[SPR_HDEXCR] & R_HDEXCR_ENF_##dexcr_aspect##_MASK)) \ |
| 194 | return; \ |
| 195 | } else if (!(env->msr & R_MSR_S_MASK)) { \ |
| 196 | if (!(env->spr[SPR_HDEXCR] & R_HDEXCR_HNU_##dexcr_aspect##_MASK)) \ |
| 197 | return; \ |
| 198 | } \ |
| 199 | \ |
| 200 | do_hash(env, ea, ra, rb, key, store); \ |
| 201 | } |
| 202 | #else |
| 203 | #define HELPER_HASH(op, key, store, dexcr_aspect) \ |
| 204 | void helper_##op(CPUPPCState *env, target_ulong ea, target_ulong ra, \ |
| 205 | target_ulong rb) \ |
| 206 | { \ |
| 207 | do_hash(env, ea, ra, rb, key, store); \ |
| 208 | } |
| 209 | #endif /* TARGET_PPC64 */ |
| 210 | |
| 211 | HELPER_HASH(HASHST, env->spr[SPR_HASHKEYR], true, NPHIE) |
| 212 | HELPER_HASH(HASHCHK, env->spr[SPR_HASHKEYR], false, NPHIE) |
| 213 | HELPER_HASH(HASHSTP, env->spr[SPR_HASHPKEYR], true, PHIE) |
| 214 | HELPER_HASH(HASHCHKP, env->spr[SPR_HASHPKEYR], false, PHIE) |
| 215 | |
| 216 | #ifndef CONFIG_USER_ONLY |
| 217 | |
| 218 | void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, |
| 219 | MMUAccessType access_type, |
| 220 | int mmu_idx, uintptr_t retaddr) |
| 221 | { |
| 222 | CPUPPCState *env = cpu_env(cs); |
| 223 | uint32_t insn; |
| 224 | |
| 225 | /* Restore state and reload the insn we executed, for filling in DSISR. */ |
| 226 | cpu_restore_state(cs, retaddr); |
| 227 | insn = ppc_ldl_code(env, env->nip); |
| 228 | |
| 229 | switch (env->mmu_model) { |
| 230 | case POWERPC_MMU_SOFT_4xx: |
| 231 | env->spr[SPR_40x_DEAR] = vaddr; |
| 232 | break; |
| 233 | case POWERPC_MMU_BOOKE: |
| 234 | case POWERPC_MMU_BOOKE206: |
| 235 | env->spr[SPR_BOOKE_DEAR] = vaddr; |
| 236 | break; |
| 237 | case POWERPC_MMU_REAL: |
| 238 | if (env->flags & POWERPC_FLAG_PPE42) { |
| 239 | env->spr[SPR_PPE42_EDR] = vaddr; |
| 240 | if (access_type == MMU_DATA_STORE) { |
| 241 | env->spr[SPR_PPE42_ISR] |= PPE42_ISR_ST; |
| 242 | } else { |
| 243 | env->spr[SPR_PPE42_ISR] &= ~PPE42_ISR_ST; |
| 244 | } |
| 245 | } else { |
| 246 | env->spr[SPR_DAR] = vaddr; |
| 247 | } |
| 248 | break; |
| 249 | default: |
| 250 | env->spr[SPR_DAR] = vaddr; |
| 251 | break; |
| 252 | } |
| 253 | |
| 254 | cs->exception_index = POWERPC_EXCP_ALIGN; |
| 255 | env->error_code = insn & 0x03FF0000; |
| 256 | cpu_loop_exit(cs); |
| 257 | } |
| 258 | |
| 259 | void ppc_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, |
| 260 | vaddr vaddr, unsigned size, |
| 261 | MMUAccessType access_type, |
| 262 | int mmu_idx, MemTxAttrs attrs, |
| 263 | MemTxResult response, uintptr_t retaddr) |
| 264 | { |
| 265 | CPUPPCState *env = cpu_env(cs); |
| 266 | |
| 267 | switch (env->excp_model) { |
| 268 | #if defined(TARGET_PPC64) |
| 269 | case POWERPC_EXCP_POWER8: |
| 270 | case POWERPC_EXCP_POWER9: |
| 271 | case POWERPC_EXCP_POWER10: |
| 272 | case POWERPC_EXCP_POWER11: |
| 273 | /* |
| 274 | * Machine check codes can be found in processor User Manual or |
| 275 | * Linux or skiboot source. |
| 276 | */ |
| 277 | if (access_type == MMU_DATA_LOAD) { |
| 278 | env->spr[SPR_DAR] = vaddr; |
| 279 | env->spr[SPR_DSISR] = PPC_BIT(57); |
| 280 | env->error_code = PPC_BIT(42); |
| 281 | |
| 282 | } else if (access_type == MMU_DATA_STORE) { |
| 283 | /* |
| 284 | * MCE for stores in POWER is asynchronous so hardware does |
| 285 | * not set DAR, but QEMU can do better. |
| 286 | */ |
| 287 | env->spr[SPR_DAR] = vaddr; |
| 288 | env->error_code = PPC_BIT(36) | PPC_BIT(43) | PPC_BIT(45); |
| 289 | env->error_code |= PPC_BIT(42); |
| 290 | |
| 291 | } else { /* Fetch */ |
| 292 | /* |
| 293 | * is_prefix_insn_excp() tests !PPC_BIT(42) to avoid fetching |
| 294 | * the instruction, so that must always be clear for fetches. |
| 295 | */ |
| 296 | env->error_code = PPC_BIT(36) | PPC_BIT(44) | PPC_BIT(45); |
| 297 | } |
| 298 | break; |
| 299 | #endif |
| 300 | default: |
| 301 | /* |
| 302 | * TODO: Check behaviour for other CPUs, for now do nothing. |
| 303 | * Could add a basic MCE even if real hardware ignores. |
| 304 | */ |
| 305 | return; |
| 306 | } |
| 307 | |
| 308 | cs->exception_index = POWERPC_EXCP_MCHECK; |
| 309 | cpu_loop_exit_restore(cs, retaddr); |
| 310 | } |
| 311 | |
| 312 | void ppc_cpu_debug_excp_handler(CPUState *cs) |
| 313 | { |
| 314 | #if defined(TARGET_PPC64) |
| 315 | CPUPPCState *env = cpu_env(cs); |
| 316 | |
| 317 | if (env->insns_flags2 & PPC2_ISA207) { |
| 318 | if (cs->watchpoint_hit) { |
| 319 | if (cs->watchpoint_hit->flags & BP_CPU) { |
| 320 | env->spr[SPR_DAR] = cs->watchpoint_hit->hitaddr; |
| 321 | env->spr[SPR_DSISR] = PPC_BIT(41); |
| 322 | cs->watchpoint_hit = NULL; |
| 323 | raise_exception(env, POWERPC_EXCP_DSI); |
| 324 | } |
| 325 | cs->watchpoint_hit = NULL; |
| 326 | } else if (cpu_breakpoint_test(cs, env->nip, BP_CPU)) { |
| 327 | raise_exception_err(env, POWERPC_EXCP_TRACE, |
| 328 | PPC_BIT(33) | PPC_BIT(43)); |
| 329 | } |
| 330 | } |
| 331 | #endif |
| 332 | } |
| 333 | |
| 334 | bool ppc_cpu_debug_check_breakpoint(CPUState *cs) |
| 335 | { |
| 336 | #if defined(TARGET_PPC64) |
| 337 | CPUPPCState *env = cpu_env(cs); |
| 338 | |
| 339 | if (env->insns_flags2 & PPC2_ISA207) { |
| 340 | target_ulong priv; |
| 341 | |
| 342 | priv = env->spr[SPR_CIABR] & PPC_BITMASK(62, 63); |
| 343 | switch (priv) { |
| 344 | case 0x1: /* problem */ |
| 345 | return env->msr & ((target_ulong)1 << MSR_PR); |
| 346 | case 0x2: /* supervisor */ |
| 347 | return (!(env->msr & ((target_ulong)1 << MSR_PR)) && |
| 348 | !(env->msr & ((target_ulong)1 << MSR_HV))); |
| 349 | case 0x3: /* hypervisor */ |
| 350 | return (!(env->msr & ((target_ulong)1 << MSR_PR)) && |
| 351 | (env->msr & ((target_ulong)1 << MSR_HV))); |
| 352 | default: |
| 353 | g_assert_not_reached(); |
| 354 | } |
| 355 | } |
| 356 | #endif |
| 357 | |
| 358 | return false; |
| 359 | } |
| 360 | |
| 361 | bool ppc_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp) |
| 362 | { |
| 363 | #if defined(TARGET_PPC64) |
| 364 | CPUPPCState *env = cpu_env(cs); |
| 365 | bool wt, wti, hv, sv, pr; |
| 366 | uint32_t dawrx; |
| 367 | |
| 368 | if ((env->insns_flags2 & PPC2_ISA207) && |
| 369 | (wp == env->dawr_watchpoint[0])) { |
| 370 | dawrx = env->spr[SPR_DAWRX0]; |
| 371 | } else if ((env->insns_flags2 & PPC2_ISA310) && |
| 372 | (wp == env->dawr_watchpoint[1])) { |
| 373 | dawrx = env->spr[SPR_DAWRX1]; |
| 374 | } else { |
| 375 | return false; |
| 376 | } |
| 377 | |
| 378 | wt = extract32(dawrx, PPC_BIT_NR(59), 1); |
| 379 | wti = extract32(dawrx, PPC_BIT_NR(60), 1); |
| 380 | hv = extract32(dawrx, PPC_BIT_NR(61), 1); |
| 381 | sv = extract32(dawrx, PPC_BIT_NR(62), 1); |
| 382 | pr = extract32(dawrx, PPC_BIT_NR(62), 1); |
| 383 | |
| 384 | if ((env->msr & ((target_ulong)1 << MSR_PR)) && !pr) { |
| 385 | return false; |
| 386 | } else if ((env->msr & ((target_ulong)1 << MSR_HV)) && !hv) { |
| 387 | return false; |
| 388 | } else if (!sv) { |
| 389 | return false; |
| 390 | } |
| 391 | |
| 392 | if (!wti) { |
| 393 | if (env->msr & ((target_ulong)1 << MSR_DR)) { |
| 394 | return wt; |
| 395 | } else { |
| 396 | return !wt; |
| 397 | } |
| 398 | } |
| 399 | |
| 400 | return true; |
| 401 | #endif |
| 402 | |
| 403 | return false; |
| 404 | } |
| 405 | |
| 406 | /* |
| 407 | * This stops the machine and logs CPU state without killing QEMU (like |
| 408 | * cpu_abort()) because it is often a guest error as opposed to a QEMU error, |
| 409 | * so the machine can still be debugged. |
| 410 | */ |
| 411 | G_NORETURN void powerpc_checkstop(CPUPPCState *env, const char *reason) |
| 412 | { |
| 413 | CPUState *cs = env_cpu(env); |
| 414 | FILE *f; |
| 415 | |
| 416 | f = qemu_log_trylock(); |
| 417 | if (f) { |
| 418 | fprintf(f, "Entering checkstop state: %s\n", reason); |
| 419 | cpu_dump_state(cs, f, CPU_DUMP_FPU | CPU_DUMP_CCOP); |
| 420 | qemu_log_unlock(f); |
| 421 | } |
| 422 | |
| 423 | /* |
| 424 | * This stops the machine and logs CPU state without killing QEMU |
| 425 | * (like cpu_abort()) so the machine can still be debugged (because |
| 426 | * it is often a guest error). |
| 427 | */ |
| 428 | qemu_system_guest_panicked(NULL); |
| 429 | cpu_loop_exit_noexc(cs); |
| 430 | } |
| 431 | |
| 432 | uint32_t ppc_ldl_code(CPUArchState *env, target_ulong addr) |
| 433 | { |
| 434 | CPUState *cs = env_cpu(env); |
| 435 | MemOp op_end = ppc_data_endian_env(env); |
| 436 | MemOpIdx oi = make_memop_idx(MO_UL | op_end, cpu_mmu_index(cs, true)); |
| 437 | |
| 438 | return cpu_ldl_code_mmu(env, addr, oi, 0); |
| 439 | } |
| 440 | |
| 441 | #if defined(TARGET_PPC64) |
| 442 | void helper_attn(CPUPPCState *env) |
| 443 | { |
| 444 | /* POWER attn is unprivileged when enabled by HID, otherwise illegal */ |
| 445 | if ((*env->check_attn)(env)) { |
| 446 | powerpc_checkstop(env, "host executed attn"); |
| 447 | } else { |
| 448 | raise_exception_err(env, POWERPC_EXCP_HV_EMU, |
| 449 | POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL); |
| 450 | } |
| 451 | } |
| 452 | |
| 453 | void helper_scv(CPUPPCState *env, uint32_t lev) |
| 454 | { |
| 455 | if (env->spr[SPR_FSCR] & (1ull << FSCR_SCV)) { |
| 456 | raise_exception_err(env, POWERPC_EXCP_SYSCALL_VECTORED, lev); |
| 457 | } else { |
| 458 | raise_exception_err(env, POWERPC_EXCP_FU, FSCR_IC_SCV); |
| 459 | } |
| 460 | } |
| 461 | |
| 462 | void helper_PMINSN(CPUPPCState *env, uint32_t insn) |
| 463 | { |
| 464 | CPUState *cs = env_cpu(env); |
| 465 | |
| 466 | cs->halted = 1; |
| 467 | |
| 468 | /* Condition for waking up at 0x100 */ |
| 469 | env->resume_as_sreset = (insn != PPC_PM_STOP) || |
| 470 | (env->spr[SPR_PSSCR] & PSSCR_EC); |
| 471 | |
| 472 | /* HDECR is not to wake from PM state, it may have already fired */ |
| 473 | if (env->resume_as_sreset) { |
| 474 | PowerPCCPU *cpu = env_archcpu(env); |
| 475 | ppc_set_irq(cpu, PPC_INTERRUPT_HDECR, 0); |
| 476 | } |
| 477 | |
| 478 | ppc_maybe_interrupt(env); |
| 479 | } |
| 480 | |
| 481 | #endif /* TARGET_PPC64 */ |
| 482 | void helper_store_msr(CPUPPCState *env, target_ulong val) |
| 483 | { |
| 484 | uint32_t excp = hreg_store_msr(env, val, 0); |
| 485 | |
| 486 | if (excp != 0) { |
| 487 | cpu_interrupt_exittb(env_cpu(env)); |
| 488 | raise_exception(env, excp); |
| 489 | } |
| 490 | } |
| 491 | |
| 492 | void helper_ppc_maybe_interrupt(CPUPPCState *env) |
| 493 | { |
| 494 | ppc_maybe_interrupt(env); |
| 495 | } |
| 496 | |
| 497 | static void do_rfi(CPUPPCState *env, target_ulong nip, target_ulong msr) |
| 498 | { |
| 499 | /* MSR:POW cannot be set by any form of rfi */ |
| 500 | msr &= ~(1ULL << MSR_POW); |
| 501 | |
| 502 | /* MSR:TGPR cannot be set by any form of rfi */ |
| 503 | if (env->flags & POWERPC_FLAG_TGPR) { |
| 504 | msr &= ~(1ULL << MSR_TGPR); |
| 505 | } |
| 506 | |
| 507 | #ifdef TARGET_PPC64 |
| 508 | /* Switching to 32-bit ? Crop the nip */ |
| 509 | if (!msr_is_64bit(env, msr)) { |
| 510 | nip = (uint32_t)nip; |
| 511 | } |
| 512 | #else |
| 513 | nip = (uint32_t)nip; |
| 514 | #endif |
| 515 | /* XXX: beware: this is false if VLE is supported */ |
| 516 | env->nip = nip & ~((target_ulong)0x00000003); |
| 517 | hreg_store_msr(env, msr, 1); |
| 518 | trace_ppc_excp_rfi(env->nip, env->msr); |
| 519 | /* |
| 520 | * No need to raise an exception here, as rfi is always the last |
| 521 | * insn of a TB |
| 522 | */ |
| 523 | cpu_interrupt_exittb(env_cpu(env)); |
| 524 | /* Reset the reservation */ |
| 525 | env->reserve_addr = -1; |
| 526 | |
| 527 | /* Context synchronizing: check if TCG TLB needs flush */ |
| 528 | check_tlb_flush(env, false); |
| 529 | } |
| 530 | |
| 531 | void helper_RFI(CPUPPCState *env) |
| 532 | { |
| 533 | do_rfi(env, env->spr[SPR_SRR0], env->spr[SPR_SRR1] & 0xfffffffful); |
| 534 | } |
| 535 | |
| 536 | #ifdef TARGET_PPC64 |
| 537 | void helper_RFID(CPUPPCState *env) |
| 538 | { |
| 539 | /* |
| 540 | * The architecture defines a number of rules for which bits can |
| 541 | * change but in practice, we handle this in hreg_store_msr() |
| 542 | * which will be called by do_rfi(), so there is no need to filter |
| 543 | * here |
| 544 | */ |
| 545 | do_rfi(env, env->spr[SPR_SRR0], env->spr[SPR_SRR1]); |
| 546 | } |
| 547 | |
| 548 | void helper_RFSCV(CPUPPCState *env) |
| 549 | { |
| 550 | do_rfi(env, env->lr, env->ctr); |
| 551 | } |
| 552 | |
| 553 | void helper_HRFID(CPUPPCState *env) |
| 554 | { |
| 555 | do_rfi(env, env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]); |
| 556 | } |
| 557 | |
| 558 | void helper_rfebb(CPUPPCState *env, target_ulong s) |
| 559 | { |
| 560 | target_ulong msr = env->msr; |
| 561 | |
| 562 | /* |
| 563 | * Handling of BESCR bits 32:33 according to PowerISA v3.1: |
| 564 | * |
| 565 | * "If BESCR 32:33 != 0b00 the instruction is treated as if |
| 566 | * the instruction form were invalid." |
| 567 | */ |
| 568 | if (env->spr[SPR_BESCR] & BESCR_INVALID) { |
| 569 | raise_exception_err(env, POWERPC_EXCP_PROGRAM, |
| 570 | POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL); |
| 571 | } |
| 572 | |
| 573 | env->nip = env->spr[SPR_EBBRR]; |
| 574 | |
| 575 | /* Switching to 32-bit ? Crop the nip */ |
| 576 | if (!msr_is_64bit(env, msr)) { |
| 577 | env->nip = (uint32_t)env->spr[SPR_EBBRR]; |
| 578 | } |
| 579 | |
| 580 | if (s) { |
| 581 | env->spr[SPR_BESCR] |= BESCR_GE; |
| 582 | } else { |
| 583 | env->spr[SPR_BESCR] &= ~BESCR_GE; |
| 584 | } |
| 585 | } |
| 586 | |
| 587 | /* |
| 588 | * Triggers or queues an 'ebb_excp' EBB exception. All checks |
| 589 | * but FSCR, HFSCR and msr_pr must be done beforehand. |
| 590 | * |
| 591 | * PowerISA v3.1 isn't clear about whether an EBB should be |
| 592 | * postponed or cancelled if the EBB facility is unavailable. |
| 593 | * Our assumption here is that the EBB is cancelled if both |
| 594 | * FSCR and HFSCR EBB facilities aren't available. |
| 595 | */ |
| 596 | static void do_ebb(CPUPPCState *env, int ebb_excp) |
| 597 | { |
| 598 | PowerPCCPU *cpu = env_archcpu(env); |
| 599 | |
| 600 | /* |
| 601 | * FSCR_EBB and FSCR_IC_EBB are the same bits used with |
| 602 | * HFSCR. |
| 603 | */ |
| 604 | helper_fscr_facility_check(env, FSCR_EBB, 0, FSCR_IC_EBB); |
| 605 | helper_hfscr_facility_check(env, FSCR_EBB, "EBB", FSCR_IC_EBB); |
| 606 | |
| 607 | if (ebb_excp == POWERPC_EXCP_PERFM_EBB) { |
| 608 | env->spr[SPR_BESCR] |= BESCR_PMEO; |
| 609 | } else if (ebb_excp == POWERPC_EXCP_EXTERNAL_EBB) { |
| 610 | env->spr[SPR_BESCR] |= BESCR_EEO; |
| 611 | } |
| 612 | |
| 613 | if (FIELD_EX64(env->msr, MSR, PR)) { |
| 614 | powerpc_excp(cpu, ebb_excp); |
| 615 | } else { |
| 616 | ppc_set_irq(cpu, PPC_INTERRUPT_EBB, 1); |
| 617 | } |
| 618 | } |
| 619 | |
| 620 | void raise_ebb_perfm_exception(CPUPPCState *env) |
| 621 | { |
| 622 | bool perfm_ebb_enabled = env->spr[SPR_POWER_MMCR0] & MMCR0_EBE && |
| 623 | env->spr[SPR_BESCR] & BESCR_PME && |
| 624 | env->spr[SPR_BESCR] & BESCR_GE; |
| 625 | |
| 626 | if (!perfm_ebb_enabled) { |
| 627 | return; |
| 628 | } |
| 629 | |
| 630 | do_ebb(env, POWERPC_EXCP_PERFM_EBB); |
| 631 | } |
| 632 | #endif /* TARGET_PPC64 */ |
| 633 | |
| 634 | /*****************************************************************************/ |
| 635 | /* Embedded PowerPC specific helpers */ |
| 636 | void helper_40x_rfci(CPUPPCState *env) |
| 637 | { |
| 638 | do_rfi(env, env->spr[SPR_40x_SRR2], env->spr[SPR_40x_SRR3]); |
| 639 | } |
| 640 | |
| 641 | void helper_rfci(CPUPPCState *env) |
| 642 | { |
| 643 | do_rfi(env, env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1]); |
| 644 | } |
| 645 | |
| 646 | void helper_rfdi(CPUPPCState *env) |
| 647 | { |
| 648 | /* FIXME: choose CSRR1 or DSRR1 based on cpu type */ |
| 649 | do_rfi(env, env->spr[SPR_BOOKE_DSRR0], env->spr[SPR_BOOKE_DSRR1]); |
| 650 | } |
| 651 | |
| 652 | void helper_rfmci(CPUPPCState *env) |
| 653 | { |
| 654 | /* FIXME: choose CSRR1 or MCSRR1 based on cpu type */ |
| 655 | do_rfi(env, env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]); |
| 656 | } |
| 657 | |
| 658 | /* Embedded.Processor Control */ |
| 659 | static int dbell2irq(target_ulong rb) |
| 660 | { |
| 661 | int msg = rb & DBELL_TYPE_MASK; |
| 662 | int irq = -1; |
| 663 | |
| 664 | switch (msg) { |
| 665 | case DBELL_TYPE_DBELL: |
| 666 | irq = PPC_INTERRUPT_DOORBELL; |
| 667 | break; |
| 668 | case DBELL_TYPE_DBELL_CRIT: |
| 669 | irq = PPC_INTERRUPT_CDOORBELL; |
| 670 | break; |
| 671 | case DBELL_TYPE_G_DBELL: |
| 672 | case DBELL_TYPE_G_DBELL_CRIT: |
| 673 | case DBELL_TYPE_G_DBELL_MC: |
| 674 | /* XXX implement */ |
| 675 | default: |
| 676 | break; |
| 677 | } |
| 678 | |
| 679 | return irq; |
| 680 | } |
| 681 | |
| 682 | void helper_msgclr(CPUPPCState *env, target_ulong rb) |
| 683 | { |
| 684 | int irq = dbell2irq(rb); |
| 685 | |
| 686 | if (irq < 0) { |
| 687 | return; |
| 688 | } |
| 689 | |
| 690 | ppc_set_irq(env_archcpu(env), irq, 0); |
| 691 | } |
| 692 | |
| 693 | void helper_msgsnd(target_ulong rb) |
| 694 | { |
| 695 | int irq = dbell2irq(rb); |
| 696 | int pir = rb & DBELL_PIRTAG_MASK; |
| 697 | CPUState *cs; |
| 698 | |
| 699 | if (irq < 0) { |
| 700 | return; |
| 701 | } |
| 702 | |
| 703 | bql_lock(); |
| 704 | CPU_FOREACH(cs) { |
| 705 | PowerPCCPU *cpu = POWERPC_CPU(cs); |
| 706 | CPUPPCState *cenv = &cpu->env; |
| 707 | |
| 708 | if ((rb & DBELL_BRDCAST_MASK) || (cenv->spr[SPR_BOOKE_PIR] == pir)) { |
| 709 | ppc_set_irq(cpu, irq, 1); |
| 710 | } |
| 711 | } |
| 712 | bql_unlock(); |
| 713 | } |
| 714 | |
| 715 | /* Server Processor Control */ |
| 716 | |
| 717 | static bool dbell_type_server(target_ulong rb) |
| 718 | { |
| 719 | /* |
| 720 | * A Directed Hypervisor Doorbell message is sent only if the |
| 721 | * message type is 5. All other types are reserved and the |
| 722 | * instruction is a no-op |
| 723 | */ |
| 724 | return (rb & DBELL_TYPE_MASK) == DBELL_TYPE_DBELL_SERVER; |
| 725 | } |
| 726 | |
| 727 | static inline bool dbell_bcast_core(target_ulong rb) |
| 728 | { |
| 729 | return (rb & DBELL_BRDCAST_MASK) == DBELL_BRDCAST_CORE; |
| 730 | } |
| 731 | |
| 732 | static inline bool dbell_bcast_subproc(target_ulong rb) |
| 733 | { |
| 734 | return (rb & DBELL_BRDCAST_MASK) == DBELL_BRDCAST_SUBPROC; |
| 735 | } |
| 736 | |
| 737 | /* |
| 738 | * Send an interrupt to a thread in the same core as env). |
| 739 | */ |
| 740 | static void msgsnd_core_tir(CPUPPCState *env, uint32_t target_tir, int irq) |
| 741 | { |
| 742 | PowerPCCPU *cpu = env_archcpu(env); |
| 743 | CPUState *cs = env_cpu(env); |
| 744 | |
| 745 | if (ppc_cpu_lpar_single_threaded(cs)) { |
| 746 | if (target_tir == 0) { |
| 747 | ppc_set_irq(cpu, irq, 1); |
| 748 | } |
| 749 | } else { |
| 750 | CPUState *ccs; |
| 751 | |
| 752 | /* Does iothread need to be locked for walking CPU list? */ |
| 753 | bql_lock(); |
| 754 | THREAD_SIBLING_FOREACH(cs, ccs) { |
| 755 | PowerPCCPU *ccpu = POWERPC_CPU(ccs); |
| 756 | if (target_tir == ppc_cpu_tir(ccpu)) { |
| 757 | ppc_set_irq(ccpu, irq, 1); |
| 758 | break; |
| 759 | } |
| 760 | } |
| 761 | bql_unlock(); |
| 762 | } |
| 763 | } |
| 764 | |
| 765 | void helper_book3s_msgclr(CPUPPCState *env, target_ulong rb) |
| 766 | { |
| 767 | if (!dbell_type_server(rb)) { |
| 768 | return; |
| 769 | } |
| 770 | |
| 771 | ppc_set_irq(env_archcpu(env), PPC_INTERRUPT_HDOORBELL, 0); |
| 772 | } |
| 773 | |
| 774 | void helper_book3s_msgsnd(CPUPPCState *env, target_ulong rb) |
| 775 | { |
| 776 | int pir = rb & DBELL_PROCIDTAG_MASK; |
| 777 | bool brdcast = false; |
| 778 | CPUState *cs, *ccs; |
| 779 | PowerPCCPU *cpu; |
| 780 | |
| 781 | if (!dbell_type_server(rb)) { |
| 782 | return; |
| 783 | } |
| 784 | |
| 785 | /* POWER8 msgsnd is like msgsndp (targets a thread within core) */ |
| 786 | if (!(env->insns_flags2 & PPC2_ISA300)) { |
| 787 | msgsnd_core_tir(env, rb & PPC_BITMASK(57, 63), PPC_INTERRUPT_HDOORBELL); |
| 788 | return; |
| 789 | } |
| 790 | |
| 791 | /* POWER9 and later msgsnd is a global (targets any thread) */ |
| 792 | cpu = ppc_get_vcpu_by_pir(pir); |
| 793 | if (!cpu) { |
| 794 | return; |
| 795 | } |
| 796 | cs = CPU(cpu); |
| 797 | |
| 798 | if (dbell_bcast_core(rb) || (dbell_bcast_subproc(rb) && |
| 799 | (env->flags & POWERPC_FLAG_SMT_1LPAR))) { |
| 800 | brdcast = true; |
| 801 | } |
| 802 | |
| 803 | if (ppc_cpu_core_single_threaded(cs) || !brdcast) { |
| 804 | ppc_set_irq(cpu, PPC_INTERRUPT_HDOORBELL, 1); |
| 805 | return; |
| 806 | } |
| 807 | |
| 808 | /* |
| 809 | * Why is bql needed for walking CPU list? Answer seems to be because ppc |
| 810 | * irq handling needs it, but ppc_set_irq takes the lock itself if needed, |
| 811 | * so could this be removed? |
| 812 | */ |
| 813 | bql_lock(); |
| 814 | THREAD_SIBLING_FOREACH(cs, ccs) { |
| 815 | ppc_set_irq(POWERPC_CPU(ccs), PPC_INTERRUPT_HDOORBELL, 1); |
| 816 | } |
| 817 | bql_unlock(); |
| 818 | } |
| 819 | |
| 820 | #ifdef TARGET_PPC64 |
| 821 | void helper_book3s_msgclrp(CPUPPCState *env, target_ulong rb) |
| 822 | { |
| 823 | helper_hfscr_facility_check(env, HFSCR_MSGP, "msgclrp", HFSCR_IC_MSGP); |
| 824 | |
| 825 | if (!dbell_type_server(rb)) { |
| 826 | return; |
| 827 | } |
| 828 | |
| 829 | ppc_set_irq(env_archcpu(env), PPC_INTERRUPT_DOORBELL, 0); |
| 830 | } |
| 831 | |
| 832 | /* |
| 833 | * sends a message to another thread on the same |
| 834 | * multi-threaded processor |
| 835 | */ |
| 836 | void helper_book3s_msgsndp(CPUPPCState *env, target_ulong rb) |
| 837 | { |
| 838 | helper_hfscr_facility_check(env, HFSCR_MSGP, "msgsndp", HFSCR_IC_MSGP); |
| 839 | |
| 840 | if (!dbell_type_server(rb)) { |
| 841 | return; |
| 842 | } |
| 843 | |
| 844 | msgsnd_core_tir(env, rb & PPC_BITMASK(57, 63), PPC_INTERRUPT_DOORBELL); |
| 845 | } |
| 846 | #endif /* TARGET_PPC64 */ |
| 847 | |
| 848 | /* Single-step tracing */ |
| 849 | void helper_book3s_trace(CPUPPCState *env, target_ulong prev_ip) |
| 850 | { |
| 851 | uint32_t error_code = 0; |
| 852 | if (env->insns_flags2 & PPC2_ISA207) { |
| 853 | /* Load/store reporting, SRR1[35, 36] and SDAR, are not implemented. */ |
| 854 | env->spr[SPR_POWER_SIAR] = prev_ip; |
| 855 | error_code = PPC_BIT(33); |
| 856 | } |
| 857 | raise_exception_err(env, POWERPC_EXCP_TRACE, error_code); |
| 858 | } |
| 859 | #endif /* !CONFIG_USER_ONLY */ |