@samitouri / QOSamiQemu
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1 /*
2 * Power ISA decode for Storage Control instructions
3 *
4 * Copyright (c) 2022 Instituto de Pesquisas Eldorado (eldorado.org.br)
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 /*
21 * Processor Control Instructions
22 */
23
24 static bool trans_MSGCLR(DisasContext *ctx, arg_X_rb *a)
25 {
26 if (!(ctx->insns_flags2 & PPC2_ISA207)) {
27 /*
28 * Before Power ISA 2.07, processor control instructions were only
29 * implemented in the "Embedded.Processor Control" category.
30 */
31 REQUIRE_INSNS_FLAGS2(ctx, PRCNTL);
32 }
33
34 REQUIRE_HV(ctx);
35
36 #if !defined(CONFIG_USER_ONLY)
37 if (is_book3s_arch2x(ctx)) {
38 gen_helper_book3s_msgclr(tcg_env, cpu_gpr[a->rb]);
39 } else {
40 gen_helper_msgclr(tcg_env, cpu_gpr[a->rb]);
41 }
42 #else
43 qemu_build_not_reached();
44 #endif
45 return true;
46 }
47
48 static bool trans_MSGSND(DisasContext *ctx, arg_X_rb *a)
49 {
50 if (!(ctx->insns_flags2 & PPC2_ISA207)) {
51 /*
52 * Before Power ISA 2.07, processor control instructions were only
53 * implemented in the "Embedded.Processor Control" category.
54 */
55 REQUIRE_INSNS_FLAGS2(ctx, PRCNTL);
56 }
57
58 REQUIRE_HV(ctx);
59
60 #if !defined(CONFIG_USER_ONLY)
61 if (is_book3s_arch2x(ctx)) {
62 gen_helper_book3s_msgsnd(tcg_env, cpu_gpr[a->rb]);
63 } else {
64 gen_helper_msgsnd(cpu_gpr[a->rb]);
65 }
66 #else
67 qemu_build_not_reached();
68 #endif
69 return true;
70 }
71
72 static bool trans_MSGCLRP(DisasContext *ctx, arg_X_rb *a)
73 {
74 REQUIRE_64BIT(ctx);
75 REQUIRE_INSNS_FLAGS2(ctx, ISA207);
76 REQUIRE_SV(ctx);
77 #if !defined(CONFIG_USER_ONLY) && defined(TARGET_PPC64)
78 gen_helper_book3s_msgclrp(tcg_env, cpu_gpr[a->rb]);
79 #else
80 qemu_build_not_reached();
81 #endif
82 return true;
83 }
84
85 static bool trans_MSGSNDP(DisasContext *ctx, arg_X_rb *a)
86 {
87 REQUIRE_64BIT(ctx);
88 REQUIRE_INSNS_FLAGS2(ctx, ISA207);
89 REQUIRE_SV(ctx);
90 #if !defined(CONFIG_USER_ONLY) && defined(TARGET_PPC64)
91 gen_helper_book3s_msgsndp(tcg_env, cpu_gpr[a->rb]);
92 #else
93 qemu_build_not_reached();
94 #endif
95 return true;
96 }
97
98 static bool trans_MSGSYNC(DisasContext *ctx, arg_MSGSYNC *a)
99 {
100 REQUIRE_INSNS_FLAGS2(ctx, ISA300);
101 REQUIRE_HV(ctx);
102
103 /* interpreted as no-op */
104 return true;
105 }
106
107 /*
108 * Helper to handle DOZE, NAP, SLEEP, RVWINKLE & STOP. Since none of them use
109 * any arguments just use a placeholder arg_SLEEP.
110 */
111 static bool do_sleep(DisasContext *ctx, arg_SLEEP *a, powerpc_pm_insn_t type)
112 {
113 REQUIRE_64BIT(ctx);
114
115 #if defined(CONFIG_USER_ONLY)
116 gen_priv_opc(ctx);
117 #elif defined(TARGET_PPC64)
118 TCGv_i32 t;
119
120 REQUIRE_HV(ctx);
121 translator_io_start(&ctx->base);
122 t = tcg_constant_i32(type);
123 gen_helper_PMINSN(tcg_env, t);
124 /* Stop translation, as the CPU is supposed to sleep from now */
125 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
126 #else
127 qemu_build_not_reached();
128 #endif
129 return true;
130 }
131
132 TRANS_FLAGS2(PM_ISA206, DOZE, do_sleep, PPC_PM_DOZE);
133 TRANS_FLAGS2(PM_ISA206, NAP, do_sleep, PPC_PM_NAP);
134 TRANS_FLAGS2(PM_ISA206, SLEEP, do_sleep, PPC_PM_SLEEP);
135 TRANS_FLAGS2(PM_ISA206, RVWINKLE, do_sleep, PPC_PM_RVWINKLE);
136 TRANS_FLAGS2(ISA300, STOP, do_sleep, PPC_PM_STOP);