| 1 | /* |
| 2 | * Target-specific parts of semihosting/arm-compat-semi.c. |
| 3 | * |
| 4 | * Copyright (c) 2005, 2007 CodeSourcery. |
| 5 | * Copyright (c) 2019, 2022 Linaro |
| 6 | * Copyright © 2020 by Keith Packard <keithp@keithp.com> |
| 7 | * |
| 8 | * SPDX-License-Identifier: GPL-2.0-or-later |
| 9 | */ |
| 10 | |
| 11 | #include "qemu/osdep.h" |
| 12 | #include "cpu.h" |
| 13 | #include "semihosting/common-semi.h" |
| 14 | |
| 15 | uint64_t common_semi_arg(CPUState *cs, int argno) |
| 16 | { |
| 17 | RISCVCPU *cpu = RISCV_CPU(cs); |
| 18 | CPURISCVState *env = &cpu->env; |
| 19 | return env->gpr[xA0 + argno]; |
| 20 | } |
| 21 | |
| 22 | void common_semi_set_ret(CPUState *cs, uint64_t ret) |
| 23 | { |
| 24 | RISCVCPU *cpu = RISCV_CPU(cs); |
| 25 | CPURISCVState *env = &cpu->env; |
| 26 | env->gpr[xA0] = ret; |
| 27 | } |
| 28 | |
| 29 | bool is_64bit_semihosting(CPUArchState *env) |
| 30 | { |
| 31 | return riscv_cpu_mxl(env) != MXL_RV32; |
| 32 | } |
| 33 | |
| 34 | bool common_semi_sys_exit_is_extended(CPUState *cs) |
| 35 | { |
| 36 | return is_64bit_semihosting(cpu_env(cs)); |
| 37 | } |
| 38 | |
| 39 | uint64_t common_semi_stack_bottom(CPUState *cs) |
| 40 | { |
| 41 | RISCVCPU *cpu = RISCV_CPU(cs); |
| 42 | CPURISCVState *env = &cpu->env; |
| 43 | return env->gpr[xSP]; |
| 44 | } |
| 45 | |
| 46 | bool common_semi_has_synccache(CPUArchState *env) |
| 47 | { |
| 48 | return true; |
| 49 | } |