| 1 | /* |
| 2 | * RISC-V cpu parameters for qemu. |
| 3 | * |
| 4 | * Copyright (c) 2017-2018 SiFive, Inc. |
| 5 | * SPDX-License-Identifier: GPL-2.0-or-later |
| 6 | */ |
| 7 | |
| 8 | #ifndef RISCV_CPU_PARAM_H |
| 9 | #define RISCV_CPU_PARAM_H |
| 10 | |
| 11 | #if defined(TARGET_RISCV64) |
| 12 | # define TARGET_VIRT_ADDR_SPACE_BITS 48 /* sv48 */ |
| 13 | #elif defined(TARGET_RISCV32) |
| 14 | # define TARGET_VIRT_ADDR_SPACE_BITS 32 /* sv32 */ |
| 15 | #endif |
| 16 | #define TARGET_PAGE_BITS 12 /* 4 KiB Pages */ |
| 17 | |
| 18 | /* |
| 19 | * The current MMU Modes are: |
| 20 | * - U mode 0b000 |
| 21 | * - S mode 0b001 |
| 22 | * - M mode 0b011 |
| 23 | * - U mode HLV/HLVX/HSV 0b100 |
| 24 | * - S mode HLV/HLVX/HSV 0b101 |
| 25 | * - M mode HLV/HLVX/HSV 0b111 |
| 26 | */ |
| 27 | |
| 28 | #endif |