| 1 | /* |
| 2 | * QEMU RISC-V CPU QOM header (target agnostic) |
| 3 | * |
| 4 | * Copyright (c) 2023 Ventana Micro Systems Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify it |
| 7 | * under the terms and conditions of the GNU General Public License, |
| 8 | * version 2 or later, as published by the Free Software Foundation. |
| 9 | * |
| 10 | * This program is distributed in the hope it will be useful, but WITHOUT |
| 11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 13 | * more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License along with |
| 16 | * this program. If not, see <http://www.gnu.org/licenses/>. |
| 17 | */ |
| 18 | |
| 19 | #ifndef RISCV_CPU_QOM_H |
| 20 | #define RISCV_CPU_QOM_H |
| 21 | |
| 22 | #include "hw/core/cpu.h" |
| 23 | |
| 24 | #define TYPE_RISCV_CPU "riscv-cpu" |
| 25 | #define TYPE_RISCV_DYNAMIC_CPU "riscv-dynamic-cpu" |
| 26 | #define TYPE_RISCV_VENDOR_CPU "riscv-vendor-cpu" |
| 27 | #define TYPE_RISCV_BARE_CPU "riscv-bare-cpu" |
| 28 | |
| 29 | #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU |
| 30 | #define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX) |
| 31 | |
| 32 | #define TYPE_RISCV_CPU_MAX RISCV_CPU_TYPE_NAME("max") |
| 33 | #define TYPE_RISCV_CPU_MAX32 RISCV_CPU_TYPE_NAME("max32") |
| 34 | #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32") |
| 35 | #define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64") |
| 36 | #define TYPE_RISCV_CPU_BASE128 RISCV_CPU_TYPE_NAME("x-rv128") |
| 37 | #define TYPE_RISCV_CPU_RV32I RISCV_CPU_TYPE_NAME("rv32i") |
| 38 | #define TYPE_RISCV_CPU_RV32E RISCV_CPU_TYPE_NAME("rv32e") |
| 39 | #define TYPE_RISCV_CPU_RV64I RISCV_CPU_TYPE_NAME("rv64i") |
| 40 | #define TYPE_RISCV_CPU_RV64E RISCV_CPU_TYPE_NAME("rv64e") |
| 41 | #define TYPE_RISCV_CPU_RVA22U64 RISCV_CPU_TYPE_NAME("rva22u64") |
| 42 | #define TYPE_RISCV_CPU_RVA22S64 RISCV_CPU_TYPE_NAME("rva22s64") |
| 43 | #define TYPE_RISCV_CPU_RVA23U64 RISCV_CPU_TYPE_NAME("rva23u64") |
| 44 | #define TYPE_RISCV_CPU_RVA23S64 RISCV_CPU_TYPE_NAME("rva23s64") |
| 45 | #define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex") |
| 46 | #define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c") |
| 47 | #define TYPE_RISCV_CPU_SIFIVE_E RISCV_CPU_TYPE_NAME("sifive-e") |
| 48 | #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31") |
| 49 | #define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34") |
| 50 | #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51") |
| 51 | #define TYPE_RISCV_CPU_SIFIVE_U RISCV_CPU_TYPE_NAME("sifive-u") |
| 52 | #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") |
| 53 | #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") |
| 54 | #define TYPE_RISCV_CPU_THEAD_C906 RISCV_CPU_TYPE_NAME("thead-c906") |
| 55 | #define TYPE_RISCV_CPU_THEAD_C908 RISCV_CPU_TYPE_NAME("thead-c908") |
| 56 | #define TYPE_RISCV_CPU_THEAD_C908V RISCV_CPU_TYPE_NAME("thead-c908v") |
| 57 | #define TYPE_RISCV_CPU_VEYRON_V1 RISCV_CPU_TYPE_NAME("veyron-v1") |
| 58 | #define TYPE_RISCV_CPU_TT_ASCALON RISCV_CPU_TYPE_NAME("tt-ascalon") |
| 59 | #define TYPE_RISCV_CPU_XIANGSHAN_NANHU RISCV_CPU_TYPE_NAME("xiangshan-nanhu") |
| 60 | #define TYPE_RISCV_CPU_XIANGSHAN_KMH RISCV_CPU_TYPE_NAME("xiangshan-kunminghu") |
| 61 | #define TYPE_RISCV_CPU_MIPS_P8700 RISCV_CPU_TYPE_NAME("mips-p8700") |
| 62 | #define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host") |
| 63 | |
| 64 | OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU) |
| 65 | |
| 66 | #endif /* RISCV_CPU_QOM_H */ |