| 1 | /* |
| 2 | * QEMU RISC-V CPU |
| 3 | * |
| 4 | * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu |
| 5 | * Copyright (c) 2017-2018 SiFive, Inc. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify it |
| 8 | * under the terms and conditions of the GNU General Public License, |
| 9 | * version 2 or later, as published by the Free Software Foundation. |
| 10 | * |
| 11 | * This program is distributed in the hope it will be useful, but WITHOUT |
| 12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 14 | * more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License along with |
| 17 | * this program. If not, see <http://www.gnu.org/licenses/>. |
| 18 | */ |
| 19 | |
| 20 | #ifndef RISCV_CPU_H |
| 21 | #define RISCV_CPU_H |
| 22 | |
| 23 | #include "hw/core/cpu.h" |
| 24 | #include "hw/core/registerfields.h" |
| 25 | #include "hw/core/qdev-properties.h" |
| 26 | #include "exec/cpu-common.h" |
| 27 | #include "exec/cpu-interrupt.h" |
| 28 | #include "exec/gdbstub.h" |
| 29 | #include "exec/target_long.h" |
| 30 | #include "qemu/cpu-float.h" |
| 31 | #include "qom/object.h" |
| 32 | #include "qemu/int128.h" |
| 33 | #include "cpu_bits.h" |
| 34 | #include "cpu_cfg.h" |
| 35 | #include "qapi/qapi-types-common.h" |
| 36 | #include "cpu-qom.h" |
| 37 | |
| 38 | typedef struct CPUArchState CPURISCVState; |
| 39 | |
| 40 | #define CPU_RESOLVING_TYPE TYPE_RISCV_CPU |
| 41 | |
| 42 | #if defined(TARGET_RISCV32) |
| 43 | # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32 |
| 44 | #elif defined(TARGET_RISCV64) |
| 45 | # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64 |
| 46 | #endif |
| 47 | |
| 48 | /* |
| 49 | * b0: Whether a instruction always raise a store AMO or not. |
| 50 | */ |
| 51 | #define RISCV_UW2_ALWAYS_STORE_AMO 1 |
| 52 | |
| 53 | #define RV(x) BIT(x - 'A') |
| 54 | |
| 55 | /* |
| 56 | * Update misa_bits[], misa_ext_info_arr[] and misa_ext_cfgs[] |
| 57 | * when adding new MISA bits here. |
| 58 | */ |
| 59 | #define RVI RV('I') |
| 60 | #define RVE RV('E') /* E and I are mutually exclusive */ |
| 61 | #define RVM RV('M') |
| 62 | #define RVA RV('A') |
| 63 | #define RVF RV('F') |
| 64 | #define RVD RV('D') |
| 65 | #define RVV RV('V') |
| 66 | #define RVC RV('C') |
| 67 | #define RVS RV('S') |
| 68 | #define RVU RV('U') |
| 69 | #define RVH RV('H') |
| 70 | #define RVG RV('G') |
| 71 | #define RVB RV('B') |
| 72 | #define RVX RV('X') |
| 73 | |
| 74 | extern const uint32_t misa_bits[]; |
| 75 | const char *riscv_get_misa_ext_name(uint32_t bit); |
| 76 | const char *riscv_get_misa_ext_description(uint32_t bit); |
| 77 | |
| 78 | #define CPU_CFG_OFFSET(_prop) offsetof(struct RISCVCPUConfig, _prop) |
| 79 | #define ENV_CSR_OFFSET(_csr) offsetof(CPURISCVState, _csr) |
| 80 | |
| 81 | typedef struct riscv_cpu_profile { |
| 82 | struct riscv_cpu_profile *u_parent; |
| 83 | struct riscv_cpu_profile *s_parent; |
| 84 | const char *name; |
| 85 | uint32_t misa_ext; |
| 86 | /* |
| 87 | * The profile is enabled/disabled via command line or |
| 88 | * via cpu_init(). Enabling a profile will add all its |
| 89 | * mandatory extensions in the CPU during init(). |
| 90 | */ |
| 91 | bool enabled; |
| 92 | /* |
| 93 | * The profile is present in the CPU, i.e. the current set of |
| 94 | * CPU extensions complies with it. A profile can be enabled |
| 95 | * and not present (e.g. the user disabled a mandatory extension) |
| 96 | * and the other way around (e.g. all mandatory extensions are |
| 97 | * present in a non-profile CPU). |
| 98 | * |
| 99 | * QMP uses this flag. |
| 100 | */ |
| 101 | bool present; |
| 102 | bool user_set; |
| 103 | int priv_spec; |
| 104 | int satp_mode; |
| 105 | const int32_t ext_offsets[]; |
| 106 | } RISCVCPUProfile; |
| 107 | |
| 108 | #define RISCV_PROFILE_EXT_LIST_END -1 |
| 109 | #define RISCV_PROFILE_ATTR_UNUSED -1 |
| 110 | |
| 111 | extern RISCVCPUProfile *riscv_profiles[]; |
| 112 | |
| 113 | /* |
| 114 | * Type large enough to hold all PRV_* fields, update CPUArchState::priv |
| 115 | * migration field if changing this type. |
| 116 | */ |
| 117 | typedef uint8_t privilege_mode_t; |
| 118 | |
| 119 | /* Privileged specification version */ |
| 120 | #define PRIV_VER_1_10_0_STR "v1.10.0" |
| 121 | #define PRIV_VER_1_11_0_STR "v1.11.0" |
| 122 | #define PRIV_VER_1_12_0_STR "v1.12.0" |
| 123 | #define PRIV_VER_1_13_0_STR "v1.13.0" |
| 124 | enum { |
| 125 | PRIV_VERSION_1_10_0 = 0, |
| 126 | PRIV_VERSION_1_11_0, |
| 127 | PRIV_VERSION_1_12_0, |
| 128 | PRIV_VERSION_1_13_0, |
| 129 | |
| 130 | PRIV_VERSION_LATEST = PRIV_VERSION_1_13_0, |
| 131 | }; |
| 132 | |
| 133 | #define VEXT_VERSION_1_00_0 0x00010000 |
| 134 | #define VEXT_VER_1_00_0_STR "v1.0" |
| 135 | |
| 136 | enum { |
| 137 | TRANSLATE_SUCCESS, |
| 138 | TRANSLATE_FAIL, |
| 139 | TRANSLATE_PMP_FAIL, |
| 140 | TRANSLATE_G_STAGE_FAIL, |
| 141 | TRANSLATE_PMA_FAIL, |
| 142 | }; |
| 143 | |
| 144 | /* Extension context status */ |
| 145 | typedef enum { |
| 146 | EXT_STATUS_DISABLED = 0, |
| 147 | EXT_STATUS_INITIAL, |
| 148 | EXT_STATUS_CLEAN, |
| 149 | EXT_STATUS_DIRTY, |
| 150 | } RISCVExtStatus; |
| 151 | |
| 152 | /* Enum holds PMM field values for Zjpm v1.0 extension */ |
| 153 | typedef enum { |
| 154 | PMM_FIELD_DISABLED = 0, |
| 155 | PMM_FIELD_RESERVED = 1, |
| 156 | PMM_FIELD_PMLEN7 = 2, |
| 157 | PMM_FIELD_PMLEN16 = 3, |
| 158 | } RISCVPmPmm; |
| 159 | |
| 160 | typedef struct riscv_cpu_implied_exts_rule { |
| 161 | #ifndef CONFIG_USER_ONLY |
| 162 | /* |
| 163 | * Bitmask indicates the rule enabled status for the harts. |
| 164 | * This enhancement is only available in system-mode QEMU, |
| 165 | * as we don't have a good way (e.g. mhartid) to distinguish |
| 166 | * the SMP cores in user-mode QEMU. |
| 167 | */ |
| 168 | unsigned long *enabled; |
| 169 | #endif |
| 170 | /* True if this is a MISA implied rule. */ |
| 171 | bool is_misa; |
| 172 | /* ext is MISA bit if is_misa flag is true, else multi extension offset. */ |
| 173 | const uint32_t ext; |
| 174 | const uint32_t implied_misa_exts; |
| 175 | const uint32_t implied_multi_exts[]; |
| 176 | } RISCVCPUImpliedExtsRule; |
| 177 | |
| 178 | extern RISCVCPUImpliedExtsRule *riscv_misa_ext_implied_rules[]; |
| 179 | extern RISCVCPUImpliedExtsRule *riscv_multi_ext_implied_rules[]; |
| 180 | |
| 181 | #define RISCV_IMPLIED_EXTS_RULE_END -1 |
| 182 | |
| 183 | #define MMU_USER_IDX 3 |
| 184 | |
| 185 | #if !defined(CONFIG_USER_ONLY) |
| 186 | #include "tcg/pmp.h" |
| 187 | #endif |
| 188 | |
| 189 | #define RV_VLEN_MAX 1024 |
| 190 | #define RV_MAX_MHPMEVENTS 32 |
| 191 | #define RV_MAX_MHPMCOUNTERS 32 |
| 192 | |
| 193 | /* |
| 194 | * The Debug 1.0 spec allows a humongous amount of triggers. Section |
| 195 | * "Enumeration" says: "The above algorithm reads back tselect so that |
| 196 | * implementations which have 2^n triggers only need to implement n |
| 197 | * bits of tselect.". tselect can have up to XLEN bits, so the max |
| 198 | * theoretical RV_MAX_TRIGGERS value is 2^XLEN. |
| 199 | * |
| 200 | * Allowing 2^XLEN triggers per hart is silly so we'll set a max to a |
| 201 | * modest 1024 triggers, which is way more than what we see current |
| 202 | * hardware use (most chips uses 2-4 triggers per hart, RISC-V Server |
| 203 | * Ref requires at least 11). With a 1024 max per hart we'll be set |
| 204 | * for a long time ... hopefully. |
| 205 | */ |
| 206 | #define RV_MAX_TRIGGERS 1024 |
| 207 | #define RV_DEFAULT_NUM_TRIGGERS 2 |
| 208 | |
| 209 | FIELD(VTYPE, VLMUL, 0, 3) |
| 210 | FIELD(VTYPE, VSEW, 3, 3) |
| 211 | FIELD(VTYPE, VTA, 6, 1) |
| 212 | FIELD(VTYPE, VMA, 7, 1) |
| 213 | FIELD(VTYPE, ALTFMT, 8, 1) |
| 214 | FIELD(VTYPE, RESERVED, 9, sizeof(uint64_t) * 8 - 10) |
| 215 | |
| 216 | #ifndef CONFIG_USER_ONLY |
| 217 | /* machine specific AIA ireg read-modify-write callback */ |
| 218 | #define AIA_MAKE_IREG(__isel, __priv, __virt, __vgein, __xlen) \ |
| 219 | ((uint32_t)((((__xlen) & 0xff) << 24) | \ |
| 220 | (((__vgein) & 0x3f) << 20) | \ |
| 221 | (((__virt) & 0x1) << 18) | \ |
| 222 | (((__priv) & 0x3) << 16) | \ |
| 223 | (__isel & 0xffff))) |
| 224 | #define AIA_IREG_ISEL(__ireg) ((__ireg) & 0xffff) |
| 225 | #define AIA_IREG_PRIV(__ireg) (((__ireg) >> 16) & 0x3) |
| 226 | #define AIA_IREG_VIRT(__ireg) (((__ireg) >> 18) & 0x1) |
| 227 | #define AIA_IREG_VGEIN(__ireg) (((__ireg) >> 20) & 0x3f) |
| 228 | #define AIA_IREG_XLEN(__ireg) (((__ireg) >> 24) & 0xff) |
| 229 | |
| 230 | typedef int (*aia_ireg_rmw_fn)(void *arg, uint32_t reg, uint64_t *val, |
| 231 | uint64_t new_val, uint64_t write_mask); |
| 232 | #endif |
| 233 | |
| 234 | typedef struct PMUCTRState { |
| 235 | /* Current value of a counter */ |
| 236 | uint64_t mhpmcounter_val; |
| 237 | /* Snapshot value of a counter */ |
| 238 | uint64_t mhpmcounter_prev; |
| 239 | /* Value beyond INT64_MAX before overflow interrupt trigger */ |
| 240 | uint64_t irq_overflow_left; |
| 241 | } PMUCTRState; |
| 242 | |
| 243 | typedef struct PMUFixedCtrState { |
| 244 | /* Track cycle and icount for each privilege mode */ |
| 245 | uint64_t counter[4]; |
| 246 | uint64_t counter_prev[4]; |
| 247 | /* Track cycle and icount for each privilege mode when V = 1*/ |
| 248 | uint64_t counter_virt[2]; |
| 249 | uint64_t counter_virt_prev[2]; |
| 250 | } PMUFixedCtrState; |
| 251 | |
| 252 | struct CPUArchState { |
| 253 | uint64_t gpr[32]; |
| 254 | uint64_t gprh[32]; /* 64 top bits of the 128-bit registers */ |
| 255 | |
| 256 | /* vector coprocessor state. */ |
| 257 | uint64_t vreg[32 * RV_VLEN_MAX / 64] QEMU_ALIGNED(16); |
| 258 | uint64_t vtype; |
| 259 | uint32_t vl; |
| 260 | uint32_t vstart; |
| 261 | uint8_t vxrm; |
| 262 | uint8_t vxsat; |
| 263 | bool vill; |
| 264 | |
| 265 | uint64_t pc; |
| 266 | uint64_t load_res; |
| 267 | uint64_t load_val; |
| 268 | |
| 269 | /* Floating-Point state */ |
| 270 | uint64_t fpr[32]; /* assume both F and D extensions */ |
| 271 | uint8_t frm; |
| 272 | float_status fp_status; |
| 273 | |
| 274 | uint64_t badaddr; |
| 275 | uint64_t bins; |
| 276 | |
| 277 | uint64_t guest_phys_fault_addr; |
| 278 | |
| 279 | uint32_t priv_ver; |
| 280 | uint32_t vext_ver; |
| 281 | |
| 282 | /* RISCVMXL, but uint32_t for vmstate migration */ |
| 283 | uint32_t misa_mxl; /* current mxl */ |
| 284 | uint32_t misa_ext; /* current extensions */ |
| 285 | uint32_t misa_ext_mask; /* max ext for this cpu */ |
| 286 | uint32_t xl; /* current xlen */ |
| 287 | |
| 288 | /* 128-bit helpers upper part return value */ |
| 289 | uint64_t retxh; |
| 290 | |
| 291 | uint64_t jvt; |
| 292 | |
| 293 | /* elp state for zicfilp extension */ |
| 294 | bool elp; |
| 295 | /* shadow stack register for zicfiss extension */ |
| 296 | uint64_t ssp; |
| 297 | /* env place holder for extra word 2 during unwind */ |
| 298 | uint64_t excp_uw2; |
| 299 | /* sw check code for sw check exception */ |
| 300 | uint8_t sw_check_code; |
| 301 | #ifdef CONFIG_USER_ONLY |
| 302 | uint32_t elf_flags; |
| 303 | #endif |
| 304 | |
| 305 | privilege_mode_t priv; |
| 306 | /* CSRs for execution environment configuration */ |
| 307 | uint64_t menvcfg; |
| 308 | uint64_t senvcfg; |
| 309 | |
| 310 | #ifndef CONFIG_USER_ONLY |
| 311 | /* This contains QEMU specific information about the virt state. */ |
| 312 | bool virt_enabled; |
| 313 | uint8_t geilen; |
| 314 | uint64_t resetvec; |
| 315 | |
| 316 | uint64_t mhartid; |
| 317 | /* |
| 318 | * For RV32 this is 32-bit mstatus and 32-bit mstatush. |
| 319 | * For RV64 this is a 64-bit mstatus. |
| 320 | */ |
| 321 | uint64_t mstatus; |
| 322 | |
| 323 | uint64_t mip; |
| 324 | /* |
| 325 | * MIP contains the software writable version of SEIP ORed with the |
| 326 | * external interrupt value. The MIP register is always up-to-date. |
| 327 | * To keep track of the current source, we also save booleans of the values |
| 328 | * here. |
| 329 | */ |
| 330 | bool external_seip; |
| 331 | bool software_seip; |
| 332 | |
| 333 | uint64_t miclaim; |
| 334 | |
| 335 | uint64_t mie; |
| 336 | uint64_t mideleg; |
| 337 | |
| 338 | /* |
| 339 | * When mideleg[i]=0 and mvien[i]=1, sie[i] is no more |
| 340 | * alias of mie[i] and needs to be maintained separately. |
| 341 | */ |
| 342 | uint64_t sie; |
| 343 | |
| 344 | /* |
| 345 | * When hideleg[i]=0 and hvien[i]=1, vsie[i] is no more |
| 346 | * alias of sie[i] (mie[i]) and needs to be maintained separately. |
| 347 | */ |
| 348 | uint64_t vsie; |
| 349 | |
| 350 | uint64_t satp; /* since: priv-1.10.0 */ |
| 351 | uint64_t stval; |
| 352 | uint64_t medeleg; |
| 353 | |
| 354 | uint64_t stvec; |
| 355 | uint64_t sepc; |
| 356 | uint64_t scause; |
| 357 | |
| 358 | uint64_t mtvec; |
| 359 | uint64_t mepc; |
| 360 | uint64_t mcause; |
| 361 | uint64_t mtval; /* since: priv-1.10.0 */ |
| 362 | |
| 363 | uint64_t mctrctl; |
| 364 | uint32_t sctrdepth; |
| 365 | uint32_t sctrstatus; |
| 366 | uint64_t vsctrctl; |
| 367 | |
| 368 | uint64_t ctr_src[16 << SCTRDEPTH_MAX]; |
| 369 | uint64_t ctr_dst[16 << SCTRDEPTH_MAX]; |
| 370 | uint64_t ctr_data[16 << SCTRDEPTH_MAX]; |
| 371 | |
| 372 | /* Machine and Supervisor interrupt priorities */ |
| 373 | uint8_t miprio[64]; |
| 374 | uint8_t siprio[64]; |
| 375 | |
| 376 | /* AIA CSRs */ |
| 377 | uint16_t miselect; |
| 378 | uint16_t siselect; |
| 379 | uint64_t mvien; |
| 380 | uint64_t mvip; |
| 381 | |
| 382 | /* Hypervisor CSRs */ |
| 383 | uint64_t hstatus; |
| 384 | uint64_t hedeleg; |
| 385 | uint64_t hideleg; |
| 386 | uint32_t hcounteren; |
| 387 | uint64_t htval; |
| 388 | uint64_t htinst; |
| 389 | uint64_t hgatp; |
| 390 | uint64_t hgeie; |
| 391 | uint64_t hgeip; |
| 392 | uint64_t htimedelta; |
| 393 | uint64_t hvien; |
| 394 | |
| 395 | /* |
| 396 | * Bits VSSIP, VSTIP and VSEIP in hvip are maintained in mip. Other bits |
| 397 | * from 0:12 are reserved. Bits 13:63 are not aliased and must be separately |
| 398 | * maintain in hvip. |
| 399 | */ |
| 400 | uint64_t hvip; |
| 401 | |
| 402 | /* Hypervisor controlled virtual interrupt priorities */ |
| 403 | uint32_t hvictl; |
| 404 | uint8_t hviprio[64]; |
| 405 | |
| 406 | /* Upper 64-bits of 128-bit CSRs */ |
| 407 | uint64_t mscratchh; |
| 408 | uint64_t sscratchh; |
| 409 | |
| 410 | /* Virtual CSRs */ |
| 411 | /* |
| 412 | * For RV32 this is 32-bit vsstatus and 32-bit vsstatush. |
| 413 | * For RV64 this is a 64-bit vsstatus. |
| 414 | */ |
| 415 | uint64_t vsstatus; |
| 416 | uint64_t vstvec; |
| 417 | uint64_t vsscratch; |
| 418 | uint64_t vsepc; |
| 419 | uint64_t vscause; |
| 420 | uint64_t vstval; |
| 421 | uint64_t vsatp; |
| 422 | |
| 423 | /* AIA VS-mode CSRs */ |
| 424 | uint16_t vsiselect; |
| 425 | |
| 426 | uint64_t mtval2; |
| 427 | uint64_t mtinst; |
| 428 | |
| 429 | /* HS Backup CSRs */ |
| 430 | uint64_t stvec_hs; |
| 431 | uint64_t sscratch_hs; |
| 432 | uint64_t sepc_hs; |
| 433 | uint64_t scause_hs; |
| 434 | uint64_t stval_hs; |
| 435 | uint64_t satp_hs; |
| 436 | uint64_t mstatus_hs; |
| 437 | |
| 438 | /* |
| 439 | * Signals whether the current exception occurred with two-stage address |
| 440 | * translation active. |
| 441 | */ |
| 442 | bool two_stage_lookup; |
| 443 | /* |
| 444 | * Signals whether the current exception occurred while doing two-stage |
| 445 | * address translation for the VS-stage page table walk. |
| 446 | */ |
| 447 | bool two_stage_indirect_lookup; |
| 448 | |
| 449 | uint32_t scounteren; |
| 450 | uint32_t mcounteren; |
| 451 | |
| 452 | uint32_t scountinhibit; |
| 453 | uint32_t mcountinhibit; |
| 454 | |
| 455 | /* PMU cycle & instret privilege mode filtering */ |
| 456 | uint64_t mcyclecfg; |
| 457 | uint64_t minstretcfg; |
| 458 | |
| 459 | /* PMU counter state */ |
| 460 | PMUCTRState pmu_ctrs[RV_MAX_MHPMCOUNTERS]; |
| 461 | |
| 462 | /* |
| 463 | * PMU event selector configured values. First three are unused. |
| 464 | * For RV32 top 32 bits are accessed via the mhpmeventh CSR. |
| 465 | */ |
| 466 | uint64_t mhpmevent_val[RV_MAX_MHPMEVENTS]; |
| 467 | |
| 468 | PMUFixedCtrState pmu_fixed_ctrs[2]; |
| 469 | |
| 470 | uint64_t sscratch; |
| 471 | uint64_t mscratch; |
| 472 | |
| 473 | /* Sstc CSRs */ |
| 474 | uint64_t stimecmp; |
| 475 | |
| 476 | uint64_t vstimecmp; |
| 477 | |
| 478 | /* physical memory protection */ |
| 479 | pmp_table_t pmp_state; |
| 480 | uint64_t mseccfg; |
| 481 | |
| 482 | /* trigger module */ |
| 483 | uint16_t mcontext; |
| 484 | uint8_t trigger_cur; |
| 485 | /* |
| 486 | * num_triggers is the length of tdata1, tdata2, tdata3, |
| 487 | * cpu_breakpoint, cpu_watchpoint and itrigger_timer |
| 488 | * arrays. |
| 489 | */ |
| 490 | uint32_t num_triggers; |
| 491 | uint64_t *tdata1; |
| 492 | uint64_t *tdata2; |
| 493 | uint64_t *tdata3; |
| 494 | struct CPUBreakpoint **cpu_breakpoint; |
| 495 | struct CPUWatchpoint **cpu_watchpoint; |
| 496 | QEMUTimer **itrigger_timer; |
| 497 | int64_t last_icount; |
| 498 | bool itrigger_enabled; |
| 499 | |
| 500 | /* machine specific rdtime callback */ |
| 501 | uint64_t (*rdtime_fn)(void *); |
| 502 | void *rdtime_fn_arg; |
| 503 | |
| 504 | /* machine specific AIA ireg read-modify-write callback */ |
| 505 | aia_ireg_rmw_fn aia_ireg_rmw_cb[4]; |
| 506 | void *aia_ireg_rmw_cb_arg[4]; |
| 507 | |
| 508 | /* True if in debugger mode. */ |
| 509 | bool debugger; |
| 510 | |
| 511 | uint64_t mstateen[SMSTATEEN_MAX_COUNT]; |
| 512 | uint64_t hstateen[SMSTATEEN_MAX_COUNT]; |
| 513 | uint64_t sstateen[SMSTATEEN_MAX_COUNT]; |
| 514 | uint64_t henvcfg; |
| 515 | |
| 516 | /* RNMI */ |
| 517 | uint64_t mnscratch; |
| 518 | uint64_t mnepc; |
| 519 | uint64_t mncause; /* mncause without bit XLEN-1 set to 1 */ |
| 520 | uint64_t mnstatus; |
| 521 | uint64_t rnmip; |
| 522 | uint64_t rnmi_irqvec; |
| 523 | uint64_t rnmi_excpvec; |
| 524 | #endif |
| 525 | |
| 526 | /* Fields from here on are preserved across CPU reset. */ |
| 527 | QEMUTimer *stimer; /* Internal timer for S-mode interrupt */ |
| 528 | QEMUTimer *vstimer; /* Internal timer for VS-mode interrupt */ |
| 529 | bool vstime_irq; |
| 530 | |
| 531 | hwaddr kernel_addr; |
| 532 | hwaddr fdt_addr; |
| 533 | |
| 534 | #ifdef CONFIG_KVM |
| 535 | /* kvm timer */ |
| 536 | bool kvm_timer_dirty; |
| 537 | uint64_t kvm_timer_time; |
| 538 | uint64_t kvm_timer_compare; |
| 539 | uint64_t kvm_timer_state; |
| 540 | uint64_t kvm_timer_frequency; |
| 541 | |
| 542 | /* KVM multiprocessor state */ |
| 543 | uint32_t kvm_mp_state; |
| 544 | bool kvm_mp_state_loaded; |
| 545 | #endif /* CONFIG_KVM */ |
| 546 | }; |
| 547 | |
| 548 | /* |
| 549 | * map is a 16-bit bitmap: the most significant set bit in map is the maximum |
| 550 | * satp mode that is supported. It may be chosen by the user and must respect |
| 551 | * what qemu implements (valid_1_10_32/64) and what the hw is capable of |
| 552 | * (supported bitmap below). |
| 553 | * |
| 554 | * init is a 16-bit bitmap used to make sure the user selected a correct |
| 555 | * configuration as per the specification. |
| 556 | */ |
| 557 | typedef struct { |
| 558 | uint16_t map, init; |
| 559 | } RISCVSATPModes; |
| 560 | |
| 561 | /* |
| 562 | * RISCVCPU: |
| 563 | * @env: #CPURISCVState |
| 564 | * |
| 565 | * A RISCV CPU. |
| 566 | */ |
| 567 | struct ArchCPU { |
| 568 | CPUState parent_obj; |
| 569 | |
| 570 | CPURISCVState env; |
| 571 | |
| 572 | GDBFeature dyn_csr_feature; |
| 573 | GDBFeature dyn_vreg_feature; |
| 574 | |
| 575 | /* Configuration Settings */ |
| 576 | RISCVCPUConfig cfg; |
| 577 | RISCVSATPModes satp_modes; |
| 578 | |
| 579 | QEMUTimer *pmu_timer; |
| 580 | /* A bitmask of Available programmable counters */ |
| 581 | uint32_t pmu_avail_ctrs; |
| 582 | /* Mapping of events to counters */ |
| 583 | GHashTable *pmu_event_ctr_map; |
| 584 | GHashTable *user_options; |
| 585 | const GPtrArray *decoders; |
| 586 | }; |
| 587 | |
| 588 | typedef struct RISCVCSR RISCVCSR; |
| 589 | |
| 590 | typedef struct RISCVCPUDef { |
| 591 | RISCVMXL misa_mxl_max; /* max mxl for this cpu */ |
| 592 | RISCVCPUProfile *profile; |
| 593 | uint32_t misa_ext; |
| 594 | int priv_spec; |
| 595 | int32_t vext_spec; |
| 596 | RISCVCPUConfig cfg; |
| 597 | bool bare; |
| 598 | #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) |
| 599 | const RISCVCSR *custom_csrs; |
| 600 | #endif |
| 601 | /* This is just a setter for env->num_triggers. */ |
| 602 | uint32_t num_triggers; |
| 603 | } RISCVCPUDef; |
| 604 | |
| 605 | /** |
| 606 | * RISCVCPUClass: |
| 607 | * @parent_realize: The parent class' realize handler. |
| 608 | * @parent_unrealize: The parent class' unrealize handler. |
| 609 | * @parent_phases: The parent class' reset phase handlers. |
| 610 | * |
| 611 | * A RISCV CPU model. |
| 612 | */ |
| 613 | struct RISCVCPUClass { |
| 614 | CPUClass parent_class; |
| 615 | |
| 616 | DeviceRealize parent_realize; |
| 617 | DeviceUnrealize parent_unrealize; |
| 618 | ResettablePhases parent_phases; |
| 619 | RISCVCPUDef *def; |
| 620 | }; |
| 621 | |
| 622 | static inline bool riscv_has_ext(const CPURISCVState *env, uint32_t ext) |
| 623 | { |
| 624 | return (env->misa_ext & ext) != 0; |
| 625 | } |
| 626 | |
| 627 | #include "cpu_user.h" |
| 628 | |
| 629 | extern const char * const riscv_int_regnames[]; |
| 630 | extern const char * const riscv_int_regnamesh[]; |
| 631 | extern const char * const riscv_fpr_regnames[]; |
| 632 | extern const char * const riscv_rvv_regnames[]; |
| 633 | |
| 634 | const char *riscv_cpu_get_trap_name(uint64_t cause, bool async); |
| 635 | int riscv_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, |
| 636 | int cpuid, DumpState *s); |
| 637 | int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, |
| 638 | int cpuid, DumpState *s); |
| 639 | int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); |
| 640 | int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); |
| 641 | int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int *out_rdzero); |
| 642 | uint8_t riscv_cpu_default_priority(int irq); |
| 643 | uint64_t riscv_cpu_all_pending(CPURISCVState *env); |
| 644 | int riscv_cpu_mirq_pending(CPURISCVState *env); |
| 645 | int riscv_cpu_sirq_pending(CPURISCVState *env); |
| 646 | int riscv_cpu_vsirq_pending(CPURISCVState *env); |
| 647 | int riscv_cpu_pending_to_irq(CPURISCVState *env, |
| 648 | int extirq, unsigned int extirq_def_prio, |
| 649 | uint64_t pending, uint8_t *iprio); |
| 650 | |
| 651 | |
| 652 | bool riscv_cpu_fp_enabled(CPURISCVState *env); |
| 653 | bool riscv_cpu_vector_enabled(CPURISCVState *env); |
| 654 | void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); |
| 655 | int riscv_env_mmu_index(CPURISCVState *env, bool ifetch); |
| 656 | bool cpu_get_fcfien(CPURISCVState *env); |
| 657 | bool cpu_get_bcfien(CPURISCVState *env); |
| 658 | bool riscv_env_smode_dbltrp_enabled(CPURISCVState *env, bool virt); |
| 659 | G_NORETURN void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, |
| 660 | MMUAccessType access_type, |
| 661 | int mmu_idx, uintptr_t retaddr); |
| 662 | bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, |
| 663 | MMUAccessType access_type, int mmu_idx, |
| 664 | bool probe, uintptr_t retaddr); |
| 665 | char *riscv_isa_string(RISCVCPU *cpu); |
| 666 | int riscv_cpu_max_xlen(RISCVCPUClass *mcc); |
| 667 | bool riscv_cpu_option_set(RISCVCPU *cpu, const char *optname); |
| 668 | |
| 669 | #ifndef CONFIG_USER_ONLY |
| 670 | void riscv_cpu_do_interrupt(CPUState *cpu); |
| 671 | void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, char *nodename); |
| 672 | void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, |
| 673 | vaddr addr, unsigned size, |
| 674 | MMUAccessType access_type, |
| 675 | int mmu_idx, MemTxAttrs attrs, |
| 676 | MemTxResult response, uintptr_t retaddr); |
| 677 | bool riscv_cpu_translate_for_debug(CPUState *cs, vaddr addr, |
| 678 | TranslateForDebugResult *result); |
| 679 | bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); |
| 680 | void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env); |
| 681 | int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts); |
| 682 | uint64_t riscv_cpu_update_mip(CPURISCVState *env, uint64_t mask, |
| 683 | uint64_t value); |
| 684 | void riscv_cpu_set_rnmi(RISCVCPU *cpu, uint32_t irq, bool level); |
| 685 | void riscv_cpu_interrupt(CPURISCVState *env); |
| 686 | #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */ |
| 687 | |
| 688 | RISCVException smstateen_acc_ok(CPURISCVState *env, int index, uint64_t bit); |
| 689 | #endif /* !CONFIG_USER_ONLY */ |
| 690 | |
| 691 | void riscv_cpu_set_mode(CPURISCVState *env, privilege_mode_t newpriv, |
| 692 | bool virt_en); |
| 693 | |
| 694 | void riscv_ctr_add_entry(CPURISCVState *env, uint64_t src, uint64_t dst, |
| 695 | enum CTRType type, privilege_mode_t prev_priv, |
| 696 | bool prev_virt); |
| 697 | void riscv_ctr_clear(CPURISCVState *env); |
| 698 | |
| 699 | void riscv_translate_init(void); |
| 700 | void riscv_translate_code(CPUState *cs, TranslationBlock *tb, |
| 701 | int *max_insns, vaddr pc, void *host_pc); |
| 702 | |
| 703 | G_NORETURN void riscv_raise_exception(CPURISCVState *env, |
| 704 | RISCVException exception, |
| 705 | uintptr_t pc); |
| 706 | |
| 707 | uint8_t riscv_cpu_get_fflags(CPURISCVState *env); |
| 708 | void riscv_cpu_set_fflags(CPURISCVState *env, uint8_t); |
| 709 | void riscv_cpu_check_fflags(CPURISCVState *env, FloatExceptionFlags); |
| 710 | |
| 711 | #ifndef CONFIG_USER_ONLY |
| 712 | void cpu_set_exception_base(int vp_index, uint64_t address); |
| 713 | #endif |
| 714 | |
| 715 | FIELD(TB_FLAGS, MEM_IDX, 0, 3) |
| 716 | FIELD(TB_FLAGS, FS, 3, 2) |
| 717 | /* Vector flags */ |
| 718 | FIELD(TB_FLAGS, VS, 5, 2) |
| 719 | FIELD(TB_FLAGS, LMUL, 7, 3) |
| 720 | FIELD(TB_FLAGS, SEW, 10, 3) |
| 721 | FIELD(TB_FLAGS, VL_EQ_VLMAX, 13, 1) |
| 722 | FIELD(TB_FLAGS, VILL, 14, 1) |
| 723 | FIELD(TB_FLAGS, VSTART_EQ_ZERO, 15, 1) |
| 724 | /* The combination of MXL/SXL/UXL that applies to the current cpu mode. */ |
| 725 | FIELD(TB_FLAGS, XL, 16, 2) |
| 726 | /* If PointerMasking should be applied */ |
| 727 | FIELD(TB_FLAGS, PM_MASK_ENABLED, 18, 1) |
| 728 | FIELD(TB_FLAGS, PM_BASE_ENABLED, 19, 1) |
| 729 | FIELD(TB_FLAGS, VTA, 18, 1) |
| 730 | FIELD(TB_FLAGS, VMA, 19, 1) |
| 731 | /* Native debug itrigger */ |
| 732 | FIELD(TB_FLAGS, ITRIGGER, 20, 1) |
| 733 | /* Virtual mode enabled */ |
| 734 | FIELD(TB_FLAGS, VIRT_ENABLED, 21, 1) |
| 735 | FIELD(TB_FLAGS, PRIV, 22, 2) |
| 736 | FIELD(TB_FLAGS, AXL, 24, 2) |
| 737 | /* zicfilp needs a TB flag to track indirect branches */ |
| 738 | FIELD(TB_FLAGS, FCFI_ENABLED, 26, 1) |
| 739 | FIELD(TB_FLAGS, FCFI_LP_EXPECTED, 27, 1) |
| 740 | /* zicfiss needs a TB flag so that correct TB is located based on tb flags */ |
| 741 | FIELD(TB_FLAGS, BCFI_ENABLED, 28, 1) |
| 742 | /* If pointer masking should be applied and address sign extended */ |
| 743 | FIELD(TB_FLAGS, PM_PMM, 29, 2) |
| 744 | FIELD(TB_FLAGS, PM_SIGNEXTEND, 31, 1) |
| 745 | |
| 746 | FIELD(EXT_TB_FLAGS, MISA_EXT, 0, 32) |
| 747 | FIELD(EXT_TB_FLAGS, ALTFMT, 32, 1) |
| 748 | FIELD(EXT_TB_FLAGS, BIG_ENDIAN, 33, 1) |
| 749 | |
| 750 | #ifdef TARGET_RISCV32 |
| 751 | #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) |
| 752 | #else |
| 753 | static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env) |
| 754 | { |
| 755 | return env->misa_mxl; |
| 756 | } |
| 757 | #endif |
| 758 | #define riscv_cpu_mxl_bits(env) (1UL << (4 + riscv_cpu_mxl(env))) |
| 759 | |
| 760 | static inline const RISCVCPUConfig *riscv_cpu_cfg(CPURISCVState *env) |
| 761 | { |
| 762 | return &env_archcpu(env)->cfg; |
| 763 | } |
| 764 | |
| 765 | #if !defined(CONFIG_USER_ONLY) |
| 766 | static inline privilege_mode_t cpu_address_mode(CPURISCVState *env) |
| 767 | { |
| 768 | privilege_mode_t mode = env->priv; |
| 769 | |
| 770 | if (mode == PRV_M && get_field(env->mstatus, MSTATUS_MPRV)) { |
| 771 | mode = get_field(env->mstatus, MSTATUS_MPP); |
| 772 | } |
| 773 | return mode; |
| 774 | } |
| 775 | |
| 776 | static inline RISCVMXL cpu_get_xl(CPURISCVState *env, privilege_mode_t mode) |
| 777 | { |
| 778 | RISCVMXL xl = env->misa_mxl; |
| 779 | /* |
| 780 | * When emulating a 32-bit-only cpu, use RV32. |
| 781 | * When emulating a 64-bit cpu, and MXL has been reduced to RV32, |
| 782 | * MSTATUSH doesn't have UXL/SXL, therefore XLEN cannot be widened |
| 783 | * back to RV64 for lower privs. |
| 784 | */ |
| 785 | if (xl != MXL_RV32) { |
| 786 | switch (mode) { |
| 787 | case PRV_M: |
| 788 | break; |
| 789 | case PRV_U: |
| 790 | xl = get_field(env->mstatus, MSTATUS64_UXL); |
| 791 | break; |
| 792 | default: /* PRV_S */ |
| 793 | xl = get_field(env->mstatus, MSTATUS64_SXL); |
| 794 | break; |
| 795 | } |
| 796 | } |
| 797 | return xl; |
| 798 | } |
| 799 | #endif |
| 800 | |
| 801 | #if defined(TARGET_RISCV32) |
| 802 | #define cpu_recompute_xl(env) ((void)(env), MXL_RV32) |
| 803 | #else |
| 804 | static inline RISCVMXL cpu_recompute_xl(CPURISCVState *env) |
| 805 | { |
| 806 | #if !defined(CONFIG_USER_ONLY) |
| 807 | return cpu_get_xl(env, env->priv); |
| 808 | #else |
| 809 | return env->misa_mxl; |
| 810 | #endif |
| 811 | } |
| 812 | #endif |
| 813 | |
| 814 | #if defined(TARGET_RISCV32) |
| 815 | #define cpu_address_xl(env) ((void)(env), MXL_RV32) |
| 816 | #else |
| 817 | static inline RISCVMXL cpu_address_xl(CPURISCVState *env) |
| 818 | { |
| 819 | #ifdef CONFIG_USER_ONLY |
| 820 | return env->xl; |
| 821 | #else |
| 822 | privilege_mode_t mode = cpu_address_mode(env); |
| 823 | |
| 824 | return cpu_get_xl(env, mode); |
| 825 | #endif |
| 826 | } |
| 827 | #endif |
| 828 | |
| 829 | static inline uint16_t riscv_cpu_xlen(CPURISCVState *env) |
| 830 | { |
| 831 | return 16 << env->xl; |
| 832 | } |
| 833 | |
| 834 | #ifdef TARGET_RISCV32 |
| 835 | #define riscv_cpu_sxl(env) ((void)(env), MXL_RV32) |
| 836 | #else |
| 837 | static inline RISCVMXL riscv_cpu_sxl(CPURISCVState *env) |
| 838 | { |
| 839 | #ifdef CONFIG_USER_ONLY |
| 840 | return env->misa_mxl; |
| 841 | #else |
| 842 | if (env->misa_mxl != MXL_RV32) { |
| 843 | return get_field(env->mstatus, MSTATUS64_SXL); |
| 844 | } |
| 845 | #endif |
| 846 | return MXL_RV32; |
| 847 | } |
| 848 | #endif |
| 849 | |
| 850 | /* |
| 851 | * Returns the current effective privilege mode. |
| 852 | * |
| 853 | * @env: CPURISCVState |
| 854 | * @priv: The returned effective privilege mode. |
| 855 | * @virt: The returned effective virtualization mode. |
| 856 | * |
| 857 | * Returns true if the effective privilege mode is modified. |
| 858 | */ |
| 859 | static inline QEMU_ALWAYS_INLINE |
| 860 | bool riscv_cpu_eff_priv(CPURISCVState *env, privilege_mode_t *priv, bool *virt) |
| 861 | { |
| 862 | privilege_mode_t mode = env->priv; |
| 863 | bool virt_enabled = false; |
| 864 | bool mode_modified = false; |
| 865 | |
| 866 | #ifndef CONFIG_USER_ONLY |
| 867 | if (mode == PRV_M && get_field(env->mstatus, MSTATUS_MPRV)) { |
| 868 | mode = get_field(env->mstatus, MSTATUS_MPP); |
| 869 | virt_enabled = get_field(env->mstatus, MSTATUS_MPV) && (mode != PRV_M); |
| 870 | mode_modified = true; |
| 871 | } else { |
| 872 | virt_enabled = env->virt_enabled; |
| 873 | } |
| 874 | #endif |
| 875 | |
| 876 | if (priv) { |
| 877 | *priv = mode; |
| 878 | } |
| 879 | |
| 880 | if (virt) { |
| 881 | *virt = virt_enabled; |
| 882 | } |
| 883 | |
| 884 | return mode_modified; |
| 885 | } |
| 886 | |
| 887 | static inline bool riscv_cpu_allow_16bit_insn(const RISCVCPUConfig *cfg, |
| 888 | uint32_t priv_ver, |
| 889 | uint32_t misa_ext) |
| 890 | { |
| 891 | /* In priv spec version 1.12 or newer, C always implies Zca */ |
| 892 | if (priv_ver >= PRIV_VERSION_1_12_0) { |
| 893 | return cfg->ext_zca; |
| 894 | } else { |
| 895 | return misa_ext & RVC; |
| 896 | } |
| 897 | } |
| 898 | |
| 899 | /* |
| 900 | * Encode LMUL to lmul as follows: |
| 901 | * LMUL vlmul lmul |
| 902 | * 1 000 0 |
| 903 | * 2 001 1 |
| 904 | * 4 010 2 |
| 905 | * 8 011 3 |
| 906 | * - 100 - |
| 907 | * 1/8 101 -3 |
| 908 | * 1/4 110 -2 |
| 909 | * 1/2 111 -1 |
| 910 | * |
| 911 | * then, we can calculate VLMAX = vlen >> (vsew + 3 - lmul) |
| 912 | * e.g. vlen = 256 bits, SEW = 16, LMUL = 1/8 |
| 913 | * => VLMAX = vlen >> (1 + 3 - (-3)) |
| 914 | * = 256 >> 7 |
| 915 | * = 2 |
| 916 | */ |
| 917 | static inline uint32_t vext_get_vlmax(uint32_t vlenb, uint32_t vsew, |
| 918 | int8_t lmul) |
| 919 | { |
| 920 | uint32_t vlen = vlenb << 3; |
| 921 | |
| 922 | /* |
| 923 | * We need to use 'vlen' instead of 'vlenb' to |
| 924 | * preserve the '+ 3' in the formula. Otherwise |
| 925 | * we risk a negative shift if vsew < lmul. |
| 926 | */ |
| 927 | return vlen >> (vsew + 3 - lmul); |
| 928 | } |
| 929 | |
| 930 | bool riscv_cpu_is_32bit(RISCVCPU *cpu); |
| 931 | |
| 932 | bool riscv_cpu_virt_mem_enabled(CPURISCVState *env, bool is_vm_ldst); |
| 933 | RISCVPmPmm riscv_pm_get_pmm(CPURISCVState *env); |
| 934 | RISCVPmPmm riscv_pm_get_vm_ldst_pmm(CPURISCVState *env); |
| 935 | uint32_t riscv_pm_get_pmlen(RISCVPmPmm pmm); |
| 936 | |
| 937 | /* |
| 938 | * Externally facing CSR access functions, wrappers around riscv_csr*(). |
| 939 | */ |
| 940 | |
| 941 | RISCVException riscv_csr_write_i64(CPURISCVState *env, int csrno, uint64_t val); |
| 942 | RISCVException riscv_csr_read_i64(CPURISCVState *env, int csrn, uint64_t *res); |
| 943 | |
| 944 | /* |
| 945 | * The event id are encoded based on the encoding specified in the |
| 946 | * SBI specification v0.3 |
| 947 | */ |
| 948 | |
| 949 | enum riscv_pmu_event_idx { |
| 950 | RISCV_PMU_EVENT_HW_CPU_CYCLES = 0x01, |
| 951 | RISCV_PMU_EVENT_HW_INSTRUCTIONS = 0x02, |
| 952 | RISCV_PMU_EVENT_CACHE_DTLB_READ_MISS = 0x10019, |
| 953 | RISCV_PMU_EVENT_CACHE_DTLB_WRITE_MISS = 0x1001B, |
| 954 | RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS = 0x10021, |
| 955 | }; |
| 956 | |
| 957 | /* used by tcg/tcg-cpu.c*/ |
| 958 | void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool en); |
| 959 | bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset); |
| 960 | void riscv_cpu_set_misa_ext(CPURISCVState *env, uint32_t ext); |
| 961 | bool riscv_cpu_is_vendor(Object *cpu_obj); |
| 962 | |
| 963 | typedef struct isa_ext_data { |
| 964 | const char *name; |
| 965 | const char *prop_name; |
| 966 | int min_version; |
| 967 | int ext_enable_offset; |
| 968 | } RISCVIsaExtData; |
| 969 | extern const RISCVIsaExtData isa_edata_arr[]; |
| 970 | char *riscv_cpu_get_name(RISCVCPU *cpu); |
| 971 | |
| 972 | void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp); |
| 973 | void riscv_add_satp_mode_properties(Object *obj); |
| 974 | bool riscv_cpu_accelerator_compatible(RISCVCPU *cpu); |
| 975 | |
| 976 | void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); |
| 977 | target_ulong riscv_new_csr_seed(target_ulong new_value, |
| 978 | target_ulong write_mask); |
| 979 | const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit); |
| 980 | |
| 981 | const char *priv_spec_to_str(int priv_version); |
| 982 | #endif /* RISCV_CPU_H */ |