| 1 | /* RISC-V ISA constants */ |
| 2 | |
| 3 | #ifndef TARGET_RISCV_CPU_BITS_H |
| 4 | #define TARGET_RISCV_CPU_BITS_H |
| 5 | |
| 6 | #define get_field(reg, mask) (((reg) & \ |
| 7 | (uint64_t)(mask)) / ((mask) & ~((mask) << 1))) |
| 8 | #define set_field(reg, mask, val) (((reg) & ~(uint64_t)(mask)) | \ |
| 9 | (((uint64_t)(val) * ((mask) & ~((mask) << 1))) & \ |
| 10 | (uint64_t)(mask))) |
| 11 | |
| 12 | /* Extension context status mask */ |
| 13 | #define EXT_STATUS_MASK 0x3ULL |
| 14 | |
| 15 | /* Floating point round mode */ |
| 16 | #define FSR_RD_SHIFT 5 |
| 17 | #define FSR_RD (0x7 << FSR_RD_SHIFT) |
| 18 | |
| 19 | /* Floating point accrued exception flags */ |
| 20 | #define FPEXC_NX 0x01 |
| 21 | #define FPEXC_UF 0x02 |
| 22 | #define FPEXC_OF 0x04 |
| 23 | #define FPEXC_DZ 0x08 |
| 24 | #define FPEXC_NV 0x10 |
| 25 | |
| 26 | /* Floating point status register bits */ |
| 27 | #define FSR_AEXC_SHIFT 0 |
| 28 | #define FSR_NVA (FPEXC_NV << FSR_AEXC_SHIFT) |
| 29 | #define FSR_OFA (FPEXC_OF << FSR_AEXC_SHIFT) |
| 30 | #define FSR_UFA (FPEXC_UF << FSR_AEXC_SHIFT) |
| 31 | #define FSR_DZA (FPEXC_DZ << FSR_AEXC_SHIFT) |
| 32 | #define FSR_NXA (FPEXC_NX << FSR_AEXC_SHIFT) |
| 33 | #define FSR_AEXC (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA) |
| 34 | |
| 35 | /* Control and Status Registers */ |
| 36 | |
| 37 | /* zicfiss user ssp csr */ |
| 38 | #define CSR_SSP 0x011 |
| 39 | |
| 40 | /* User Trap Setup */ |
| 41 | #define CSR_USTATUS 0x000 |
| 42 | #define CSR_UIE 0x004 |
| 43 | #define CSR_UTVEC 0x005 |
| 44 | |
| 45 | /* User Trap Handling */ |
| 46 | #define CSR_USCRATCH 0x040 |
| 47 | #define CSR_UEPC 0x041 |
| 48 | #define CSR_UCAUSE 0x042 |
| 49 | #define CSR_UTVAL 0x043 |
| 50 | #define CSR_UIP 0x044 |
| 51 | |
| 52 | /* User Floating-Point CSRs */ |
| 53 | #define CSR_FFLAGS 0x001 |
| 54 | #define CSR_FRM 0x002 |
| 55 | #define CSR_FCSR 0x003 |
| 56 | |
| 57 | /* User Vector CSRs */ |
| 58 | #define CSR_VSTART 0x008 |
| 59 | #define CSR_VXSAT 0x009 |
| 60 | #define CSR_VXRM 0x00a |
| 61 | #define CSR_VCSR 0x00f |
| 62 | #define CSR_VL 0xc20 |
| 63 | #define CSR_VTYPE 0xc21 |
| 64 | #define CSR_VLENB 0xc22 |
| 65 | |
| 66 | /* VCSR fields */ |
| 67 | #define VCSR_VXSAT_SHIFT 0 |
| 68 | #define VCSR_VXSAT (0x1 << VCSR_VXSAT_SHIFT) |
| 69 | #define VCSR_VXRM_SHIFT 1 |
| 70 | #define VCSR_VXRM (0x3 << VCSR_VXRM_SHIFT) |
| 71 | |
| 72 | /* User Timers and Counters */ |
| 73 | #define CSR_CYCLE 0xc00 |
| 74 | #define CSR_TIME 0xc01 |
| 75 | #define CSR_INSTRET 0xc02 |
| 76 | #define CSR_HPMCOUNTER3 0xc03 |
| 77 | #define CSR_HPMCOUNTER4 0xc04 |
| 78 | #define CSR_HPMCOUNTER5 0xc05 |
| 79 | #define CSR_HPMCOUNTER6 0xc06 |
| 80 | #define CSR_HPMCOUNTER7 0xc07 |
| 81 | #define CSR_HPMCOUNTER8 0xc08 |
| 82 | #define CSR_HPMCOUNTER9 0xc09 |
| 83 | #define CSR_HPMCOUNTER10 0xc0a |
| 84 | #define CSR_HPMCOUNTER11 0xc0b |
| 85 | #define CSR_HPMCOUNTER12 0xc0c |
| 86 | #define CSR_HPMCOUNTER13 0xc0d |
| 87 | #define CSR_HPMCOUNTER14 0xc0e |
| 88 | #define CSR_HPMCOUNTER15 0xc0f |
| 89 | #define CSR_HPMCOUNTER16 0xc10 |
| 90 | #define CSR_HPMCOUNTER17 0xc11 |
| 91 | #define CSR_HPMCOUNTER18 0xc12 |
| 92 | #define CSR_HPMCOUNTER19 0xc13 |
| 93 | #define CSR_HPMCOUNTER20 0xc14 |
| 94 | #define CSR_HPMCOUNTER21 0xc15 |
| 95 | #define CSR_HPMCOUNTER22 0xc16 |
| 96 | #define CSR_HPMCOUNTER23 0xc17 |
| 97 | #define CSR_HPMCOUNTER24 0xc18 |
| 98 | #define CSR_HPMCOUNTER25 0xc19 |
| 99 | #define CSR_HPMCOUNTER26 0xc1a |
| 100 | #define CSR_HPMCOUNTER27 0xc1b |
| 101 | #define CSR_HPMCOUNTER28 0xc1c |
| 102 | #define CSR_HPMCOUNTER29 0xc1d |
| 103 | #define CSR_HPMCOUNTER30 0xc1e |
| 104 | #define CSR_HPMCOUNTER31 0xc1f |
| 105 | #define CSR_CYCLEH 0xc80 |
| 106 | #define CSR_TIMEH 0xc81 |
| 107 | #define CSR_INSTRETH 0xc82 |
| 108 | #define CSR_HPMCOUNTER3H 0xc83 |
| 109 | #define CSR_HPMCOUNTER4H 0xc84 |
| 110 | #define CSR_HPMCOUNTER5H 0xc85 |
| 111 | #define CSR_HPMCOUNTER6H 0xc86 |
| 112 | #define CSR_HPMCOUNTER7H 0xc87 |
| 113 | #define CSR_HPMCOUNTER8H 0xc88 |
| 114 | #define CSR_HPMCOUNTER9H 0xc89 |
| 115 | #define CSR_HPMCOUNTER10H 0xc8a |
| 116 | #define CSR_HPMCOUNTER11H 0xc8b |
| 117 | #define CSR_HPMCOUNTER12H 0xc8c |
| 118 | #define CSR_HPMCOUNTER13H 0xc8d |
| 119 | #define CSR_HPMCOUNTER14H 0xc8e |
| 120 | #define CSR_HPMCOUNTER15H 0xc8f |
| 121 | #define CSR_HPMCOUNTER16H 0xc90 |
| 122 | #define CSR_HPMCOUNTER17H 0xc91 |
| 123 | #define CSR_HPMCOUNTER18H 0xc92 |
| 124 | #define CSR_HPMCOUNTER19H 0xc93 |
| 125 | #define CSR_HPMCOUNTER20H 0xc94 |
| 126 | #define CSR_HPMCOUNTER21H 0xc95 |
| 127 | #define CSR_HPMCOUNTER22H 0xc96 |
| 128 | #define CSR_HPMCOUNTER23H 0xc97 |
| 129 | #define CSR_HPMCOUNTER24H 0xc98 |
| 130 | #define CSR_HPMCOUNTER25H 0xc99 |
| 131 | #define CSR_HPMCOUNTER26H 0xc9a |
| 132 | #define CSR_HPMCOUNTER27H 0xc9b |
| 133 | #define CSR_HPMCOUNTER28H 0xc9c |
| 134 | #define CSR_HPMCOUNTER29H 0xc9d |
| 135 | #define CSR_HPMCOUNTER30H 0xc9e |
| 136 | #define CSR_HPMCOUNTER31H 0xc9f |
| 137 | |
| 138 | /* Machine Timers and Counters */ |
| 139 | #define CSR_MCYCLE 0xb00 |
| 140 | #define CSR_MINSTRET 0xb02 |
| 141 | #define CSR_MCYCLEH 0xb80 |
| 142 | #define CSR_MINSTRETH 0xb82 |
| 143 | |
| 144 | /* Machine Information Registers */ |
| 145 | #define CSR_MVENDORID 0xf11 |
| 146 | #define CSR_MARCHID 0xf12 |
| 147 | #define CSR_MIMPID 0xf13 |
| 148 | #define CSR_MHARTID 0xf14 |
| 149 | #define CSR_MCONFIGPTR 0xf15 |
| 150 | |
| 151 | /* Machine Trap Setup */ |
| 152 | #define CSR_MSTATUS 0x300 |
| 153 | #define CSR_MISA 0x301 |
| 154 | #define CSR_MEDELEG 0x302 |
| 155 | #define CSR_MIDELEG 0x303 |
| 156 | #define CSR_MIE 0x304 |
| 157 | #define CSR_MTVEC 0x305 |
| 158 | #define CSR_MCOUNTEREN 0x306 |
| 159 | |
| 160 | /* 32-bit only */ |
| 161 | #define CSR_MSTATUSH 0x310 |
| 162 | #define CSR_MEDELEGH 0x312 |
| 163 | #define CSR_HEDELEGH 0x612 |
| 164 | |
| 165 | /* Machine Trap Handling */ |
| 166 | #define CSR_MSCRATCH 0x340 |
| 167 | #define CSR_MEPC 0x341 |
| 168 | #define CSR_MCAUSE 0x342 |
| 169 | #define CSR_MTVAL 0x343 |
| 170 | #define CSR_MIP 0x344 |
| 171 | |
| 172 | /* Machine-Level Window to Indirectly Accessed Registers (AIA) */ |
| 173 | #define CSR_MISELECT 0x350 |
| 174 | #define CSR_MIREG 0x351 |
| 175 | |
| 176 | /* Machine Indirect Register Alias */ |
| 177 | #define CSR_MIREG2 0x352 |
| 178 | #define CSR_MIREG3 0x353 |
| 179 | #define CSR_MIREG4 0x355 |
| 180 | #define CSR_MIREG5 0x356 |
| 181 | #define CSR_MIREG6 0x357 |
| 182 | |
| 183 | /* Machine-Level Interrupts (AIA) */ |
| 184 | #define CSR_MTOPEI 0x35c |
| 185 | #define CSR_MTOPI 0xfb0 |
| 186 | |
| 187 | /* Virtual Interrupts for Supervisor Level (AIA) */ |
| 188 | #define CSR_MVIEN 0x308 |
| 189 | #define CSR_MVIP 0x309 |
| 190 | |
| 191 | /* Machine-Level High-Half CSRs (AIA) */ |
| 192 | #define CSR_MIDELEGH 0x313 |
| 193 | #define CSR_MIEH 0x314 |
| 194 | #define CSR_MVIENH 0x318 |
| 195 | #define CSR_MVIPH 0x319 |
| 196 | #define CSR_MIPH 0x354 |
| 197 | |
| 198 | /* Supervisor Trap Setup */ |
| 199 | #define CSR_SSTATUS 0x100 |
| 200 | #define CSR_SIE 0x104 |
| 201 | #define CSR_STVEC 0x105 |
| 202 | #define CSR_SCOUNTEREN 0x106 |
| 203 | |
| 204 | /* Supervisor Configuration CSRs */ |
| 205 | #define CSR_SENVCFG 0x10A |
| 206 | |
| 207 | /* Supervisor state CSRs */ |
| 208 | #define CSR_SSTATEEN0 0x10C |
| 209 | #define CSR_SSTATEEN1 0x10D |
| 210 | #define CSR_SSTATEEN2 0x10E |
| 211 | #define CSR_SSTATEEN3 0x10F |
| 212 | |
| 213 | /* Supervisor Counter Delegation */ |
| 214 | #define CSR_SCOUNTINHIBIT 0x120 |
| 215 | |
| 216 | /* Supervisor Trap Handling */ |
| 217 | #define CSR_SSCRATCH 0x140 |
| 218 | #define CSR_SEPC 0x141 |
| 219 | #define CSR_SCAUSE 0x142 |
| 220 | #define CSR_STVAL 0x143 |
| 221 | #define CSR_SIP 0x144 |
| 222 | |
| 223 | /* Sstc supervisor CSRs */ |
| 224 | #define CSR_STIMECMP 0x14D |
| 225 | #define CSR_STIMECMPH 0x15D |
| 226 | |
| 227 | /* Supervisor Protection and Translation */ |
| 228 | #define CSR_SPTBR 0x180 |
| 229 | #define CSR_SATP 0x180 |
| 230 | |
| 231 | /* Supervisor-Level Window to Indirectly Accessed Registers (AIA) */ |
| 232 | #define CSR_SISELECT 0x150 |
| 233 | #define CSR_SIREG 0x151 |
| 234 | |
| 235 | /* Supervisor Indirect Register Alias */ |
| 236 | #define CSR_SIREG2 0x152 |
| 237 | #define CSR_SIREG3 0x153 |
| 238 | #define CSR_SIREG4 0x155 |
| 239 | #define CSR_SIREG5 0x156 |
| 240 | #define CSR_SIREG6 0x157 |
| 241 | |
| 242 | /* Supervisor-Level Interrupts (AIA) */ |
| 243 | #define CSR_STOPEI 0x15c |
| 244 | #define CSR_STOPI 0xdb0 |
| 245 | |
| 246 | /* Supervisor-Level High-Half CSRs (AIA) */ |
| 247 | #define CSR_SIEH 0x114 |
| 248 | #define CSR_SIPH 0x154 |
| 249 | |
| 250 | /* Machine-Level Control transfer records CSRs */ |
| 251 | #define CSR_MCTRCTL 0x34e |
| 252 | |
| 253 | /* Supervisor-Level Control transfer records CSRs */ |
| 254 | #define CSR_SCTRCTL 0x14e |
| 255 | #define CSR_SCTRSTATUS 0x14f |
| 256 | #define CSR_SCTRDEPTH 0x15f |
| 257 | |
| 258 | /* VS-Level Control transfer records CSRs */ |
| 259 | #define CSR_VSCTRCTL 0x24e |
| 260 | |
| 261 | /* Hpervisor CSRs */ |
| 262 | #define CSR_HSTATUS 0x600 |
| 263 | #define CSR_HEDELEG 0x602 |
| 264 | #define CSR_HIDELEG 0x603 |
| 265 | #define CSR_HIE 0x604 |
| 266 | #define CSR_HCOUNTEREN 0x606 |
| 267 | #define CSR_HGEIE 0x607 |
| 268 | #define CSR_HTVAL 0x643 |
| 269 | #define CSR_HVIP 0x645 |
| 270 | #define CSR_HIP 0x644 |
| 271 | #define CSR_HTINST 0x64A |
| 272 | #define CSR_HGEIP 0xE12 |
| 273 | #define CSR_HGATP 0x680 |
| 274 | #define CSR_HTIMEDELTA 0x605 |
| 275 | #define CSR_HTIMEDELTAH 0x615 |
| 276 | |
| 277 | /* Hypervisor Configuration CSRs */ |
| 278 | #define CSR_HENVCFG 0x60A |
| 279 | #define CSR_HENVCFGH 0x61A |
| 280 | |
| 281 | /* Hypervisor state CSRs */ |
| 282 | #define CSR_HSTATEEN0 0x60C |
| 283 | #define CSR_HSTATEEN0H 0x61C |
| 284 | #define CSR_HSTATEEN1 0x60D |
| 285 | #define CSR_HSTATEEN1H 0x61D |
| 286 | #define CSR_HSTATEEN2 0x60E |
| 287 | #define CSR_HSTATEEN2H 0x61E |
| 288 | #define CSR_HSTATEEN3 0x60F |
| 289 | #define CSR_HSTATEEN3H 0x61F |
| 290 | |
| 291 | /* Virtual CSRs */ |
| 292 | #define CSR_VSSTATUS 0x200 |
| 293 | #define CSR_VSIE 0x204 |
| 294 | #define CSR_VSTVEC 0x205 |
| 295 | #define CSR_VSSCRATCH 0x240 |
| 296 | #define CSR_VSEPC 0x241 |
| 297 | #define CSR_VSCAUSE 0x242 |
| 298 | #define CSR_VSTVAL 0x243 |
| 299 | #define CSR_VSIP 0x244 |
| 300 | #define CSR_VSATP 0x280 |
| 301 | |
| 302 | /* Sstc virtual CSRs */ |
| 303 | #define CSR_VSTIMECMP 0x24D |
| 304 | #define CSR_VSTIMECMPH 0x25D |
| 305 | |
| 306 | #define CSR_MTINST 0x34a |
| 307 | #define CSR_MTVAL2 0x34b |
| 308 | |
| 309 | /* Virtual Interrupts and Interrupt Priorities (H-extension with AIA) */ |
| 310 | #define CSR_HVIEN 0x608 |
| 311 | #define CSR_HVICTL 0x609 |
| 312 | #define CSR_HVIPRIO1 0x646 |
| 313 | #define CSR_HVIPRIO2 0x647 |
| 314 | |
| 315 | /* VS-Level Window to Indirectly Accessed Registers (H-extension with AIA) */ |
| 316 | #define CSR_VSISELECT 0x250 |
| 317 | #define CSR_VSIREG 0x251 |
| 318 | |
| 319 | /* Virtual Supervisor Indirect Alias */ |
| 320 | #define CSR_VSIREG2 0x252 |
| 321 | #define CSR_VSIREG3 0x253 |
| 322 | #define CSR_VSIREG4 0x255 |
| 323 | #define CSR_VSIREG5 0x256 |
| 324 | #define CSR_VSIREG6 0x257 |
| 325 | |
| 326 | /* VS-Level Interrupts (H-extension with AIA) */ |
| 327 | #define CSR_VSTOPEI 0x25c |
| 328 | #define CSR_VSTOPI 0xeb0 |
| 329 | |
| 330 | /* Hypervisor and VS-Level High-Half CSRs (H-extension with AIA) */ |
| 331 | #define CSR_HIDELEGH 0x613 |
| 332 | #define CSR_HVIENH 0x618 |
| 333 | #define CSR_HVIPH 0x655 |
| 334 | #define CSR_HVIPRIO1H 0x656 |
| 335 | #define CSR_HVIPRIO2H 0x657 |
| 336 | #define CSR_VSIEH 0x214 |
| 337 | #define CSR_VSIPH 0x254 |
| 338 | |
| 339 | /* Machine Configuration CSRs */ |
| 340 | #define CSR_MENVCFG 0x30A |
| 341 | #define CSR_MENVCFGH 0x31A |
| 342 | |
| 343 | /* Machine state CSRs */ |
| 344 | #define CSR_MSTATEEN0 0x30C |
| 345 | #define CSR_MSTATEEN0H 0x31C |
| 346 | #define CSR_MSTATEEN1 0x30D |
| 347 | #define CSR_MSTATEEN1H 0x31D |
| 348 | #define CSR_MSTATEEN2 0x30E |
| 349 | #define CSR_MSTATEEN2H 0x31E |
| 350 | #define CSR_MSTATEEN3 0x30F |
| 351 | #define CSR_MSTATEEN3H 0x31F |
| 352 | |
| 353 | /* Common defines for all smstateen */ |
| 354 | #define SMSTATEEN_MAX_COUNT 4 |
| 355 | #define SMSTATEEN0_CS (1ULL << 0) |
| 356 | #define SMSTATEEN0_FCSR (1ULL << 1) |
| 357 | #define SMSTATEEN0_JVT (1ULL << 2) |
| 358 | #define SMSTATEEN0_CTR (1ULL << 54) |
| 359 | #define SMSTATEEN0_P1P13 (1ULL << 56) |
| 360 | #define SMSTATEEN0_HSCONTXT (1ULL << 57) |
| 361 | #define SMSTATEEN0_IMSIC (1ULL << 58) |
| 362 | #define SMSTATEEN0_AIA (1ULL << 59) |
| 363 | #define SMSTATEEN0_SVSLCT (1ULL << 60) |
| 364 | #define SMSTATEEN0_HSENVCFG (1ULL << 62) |
| 365 | #define SMSTATEEN_STATEEN (1ULL << 63) |
| 366 | |
| 367 | /* Enhanced Physical Memory Protection (ePMP) */ |
| 368 | #define CSR_MSECCFG 0x747 |
| 369 | #define CSR_MSECCFGH 0x757 |
| 370 | /* Physical Memory Protection */ |
| 371 | #define CSR_PMPCFG0 0x3a0 |
| 372 | #define CSR_PMPCFG1 0x3a1 |
| 373 | #define CSR_PMPCFG2 0x3a2 |
| 374 | #define CSR_PMPCFG3 0x3a3 |
| 375 | #define CSR_PMPCFG4 0x3a4 |
| 376 | #define CSR_PMPCFG5 0x3a5 |
| 377 | #define CSR_PMPCFG6 0x3a6 |
| 378 | #define CSR_PMPCFG7 0x3a7 |
| 379 | #define CSR_PMPCFG8 0x3a8 |
| 380 | #define CSR_PMPCFG9 0x3a9 |
| 381 | #define CSR_PMPCFG10 0x3aa |
| 382 | #define CSR_PMPCFG11 0x3ab |
| 383 | #define CSR_PMPCFG12 0x3ac |
| 384 | #define CSR_PMPCFG13 0x3ad |
| 385 | #define CSR_PMPCFG14 0x3ae |
| 386 | #define CSR_PMPCFG15 0x3af |
| 387 | #define CSR_PMPADDR0 0x3b0 |
| 388 | #define CSR_PMPADDR1 0x3b1 |
| 389 | #define CSR_PMPADDR2 0x3b2 |
| 390 | #define CSR_PMPADDR3 0x3b3 |
| 391 | #define CSR_PMPADDR4 0x3b4 |
| 392 | #define CSR_PMPADDR5 0x3b5 |
| 393 | #define CSR_PMPADDR6 0x3b6 |
| 394 | #define CSR_PMPADDR7 0x3b7 |
| 395 | #define CSR_PMPADDR8 0x3b8 |
| 396 | #define CSR_PMPADDR9 0x3b9 |
| 397 | #define CSR_PMPADDR10 0x3ba |
| 398 | #define CSR_PMPADDR11 0x3bb |
| 399 | #define CSR_PMPADDR12 0x3bc |
| 400 | #define CSR_PMPADDR13 0x3bd |
| 401 | #define CSR_PMPADDR14 0x3be |
| 402 | #define CSR_PMPADDR15 0x3bf |
| 403 | #define CSR_PMPADDR16 0x3c0 |
| 404 | #define CSR_PMPADDR17 0x3c1 |
| 405 | #define CSR_PMPADDR18 0x3c2 |
| 406 | #define CSR_PMPADDR19 0x3c3 |
| 407 | #define CSR_PMPADDR20 0x3c4 |
| 408 | #define CSR_PMPADDR21 0x3c5 |
| 409 | #define CSR_PMPADDR22 0x3c6 |
| 410 | #define CSR_PMPADDR23 0x3c7 |
| 411 | #define CSR_PMPADDR24 0x3c8 |
| 412 | #define CSR_PMPADDR25 0x3c9 |
| 413 | #define CSR_PMPADDR26 0x3ca |
| 414 | #define CSR_PMPADDR27 0x3cb |
| 415 | #define CSR_PMPADDR28 0x3cc |
| 416 | #define CSR_PMPADDR29 0x3cd |
| 417 | #define CSR_PMPADDR30 0x3ce |
| 418 | #define CSR_PMPADDR31 0x3cf |
| 419 | #define CSR_PMPADDR32 0x3d0 |
| 420 | #define CSR_PMPADDR33 0x3d1 |
| 421 | #define CSR_PMPADDR34 0x3d2 |
| 422 | #define CSR_PMPADDR35 0x3d3 |
| 423 | #define CSR_PMPADDR36 0x3d4 |
| 424 | #define CSR_PMPADDR37 0x3d5 |
| 425 | #define CSR_PMPADDR38 0x3d6 |
| 426 | #define CSR_PMPADDR39 0x3d7 |
| 427 | #define CSR_PMPADDR40 0x3d8 |
| 428 | #define CSR_PMPADDR41 0x3d9 |
| 429 | #define CSR_PMPADDR42 0x3da |
| 430 | #define CSR_PMPADDR43 0x3db |
| 431 | #define CSR_PMPADDR44 0x3dc |
| 432 | #define CSR_PMPADDR45 0x3dd |
| 433 | #define CSR_PMPADDR46 0x3de |
| 434 | #define CSR_PMPADDR47 0x3df |
| 435 | #define CSR_PMPADDR48 0x3e0 |
| 436 | #define CSR_PMPADDR49 0x3e1 |
| 437 | #define CSR_PMPADDR50 0x3e2 |
| 438 | #define CSR_PMPADDR51 0x3e3 |
| 439 | #define CSR_PMPADDR52 0x3e4 |
| 440 | #define CSR_PMPADDR53 0x3e5 |
| 441 | #define CSR_PMPADDR54 0x3e6 |
| 442 | #define CSR_PMPADDR55 0x3e7 |
| 443 | #define CSR_PMPADDR56 0x3e8 |
| 444 | #define CSR_PMPADDR57 0x3e9 |
| 445 | #define CSR_PMPADDR58 0x3ea |
| 446 | #define CSR_PMPADDR59 0x3eb |
| 447 | #define CSR_PMPADDR60 0x3ec |
| 448 | #define CSR_PMPADDR61 0x3ed |
| 449 | #define CSR_PMPADDR62 0x3ee |
| 450 | #define CSR_PMPADDR63 0x3ef |
| 451 | |
| 452 | /* RNMI */ |
| 453 | #define CSR_MNSCRATCH 0x740 |
| 454 | #define CSR_MNEPC 0x741 |
| 455 | #define CSR_MNCAUSE 0x742 |
| 456 | #define CSR_MNSTATUS 0x744 |
| 457 | |
| 458 | /* Debug/Trace Registers (shared with Debug Mode) */ |
| 459 | #define CSR_TSELECT 0x7a0 |
| 460 | #define CSR_TDATA1 0x7a1 |
| 461 | #define CSR_TDATA2 0x7a2 |
| 462 | #define CSR_TDATA3 0x7a3 |
| 463 | #define CSR_TINFO 0x7a4 |
| 464 | #define CSR_MCONTEXT 0x7a8 |
| 465 | |
| 466 | /* Debug Mode Registers */ |
| 467 | #define CSR_DCSR 0x7b0 |
| 468 | #define CSR_DPC 0x7b1 |
| 469 | #define CSR_DSCRATCH 0x7b2 |
| 470 | |
| 471 | /* Performance Counters */ |
| 472 | #define CSR_MHPMCOUNTER3 0xb03 |
| 473 | #define CSR_MHPMCOUNTER4 0xb04 |
| 474 | #define CSR_MHPMCOUNTER5 0xb05 |
| 475 | #define CSR_MHPMCOUNTER6 0xb06 |
| 476 | #define CSR_MHPMCOUNTER7 0xb07 |
| 477 | #define CSR_MHPMCOUNTER8 0xb08 |
| 478 | #define CSR_MHPMCOUNTER9 0xb09 |
| 479 | #define CSR_MHPMCOUNTER10 0xb0a |
| 480 | #define CSR_MHPMCOUNTER11 0xb0b |
| 481 | #define CSR_MHPMCOUNTER12 0xb0c |
| 482 | #define CSR_MHPMCOUNTER13 0xb0d |
| 483 | #define CSR_MHPMCOUNTER14 0xb0e |
| 484 | #define CSR_MHPMCOUNTER15 0xb0f |
| 485 | #define CSR_MHPMCOUNTER16 0xb10 |
| 486 | #define CSR_MHPMCOUNTER17 0xb11 |
| 487 | #define CSR_MHPMCOUNTER18 0xb12 |
| 488 | #define CSR_MHPMCOUNTER19 0xb13 |
| 489 | #define CSR_MHPMCOUNTER20 0xb14 |
| 490 | #define CSR_MHPMCOUNTER21 0xb15 |
| 491 | #define CSR_MHPMCOUNTER22 0xb16 |
| 492 | #define CSR_MHPMCOUNTER23 0xb17 |
| 493 | #define CSR_MHPMCOUNTER24 0xb18 |
| 494 | #define CSR_MHPMCOUNTER25 0xb19 |
| 495 | #define CSR_MHPMCOUNTER26 0xb1a |
| 496 | #define CSR_MHPMCOUNTER27 0xb1b |
| 497 | #define CSR_MHPMCOUNTER28 0xb1c |
| 498 | #define CSR_MHPMCOUNTER29 0xb1d |
| 499 | #define CSR_MHPMCOUNTER30 0xb1e |
| 500 | #define CSR_MHPMCOUNTER31 0xb1f |
| 501 | |
| 502 | /* Machine counter-inhibit register */ |
| 503 | #define CSR_MCOUNTINHIBIT 0x320 |
| 504 | |
| 505 | /* Machine counter configuration registers */ |
| 506 | #define CSR_MCYCLECFG 0x321 |
| 507 | #define CSR_MINSTRETCFG 0x322 |
| 508 | |
| 509 | #define CSR_MHPMEVENT3 0x323 |
| 510 | #define CSR_MHPMEVENT4 0x324 |
| 511 | #define CSR_MHPMEVENT5 0x325 |
| 512 | #define CSR_MHPMEVENT6 0x326 |
| 513 | #define CSR_MHPMEVENT7 0x327 |
| 514 | #define CSR_MHPMEVENT8 0x328 |
| 515 | #define CSR_MHPMEVENT9 0x329 |
| 516 | #define CSR_MHPMEVENT10 0x32a |
| 517 | #define CSR_MHPMEVENT11 0x32b |
| 518 | #define CSR_MHPMEVENT12 0x32c |
| 519 | #define CSR_MHPMEVENT13 0x32d |
| 520 | #define CSR_MHPMEVENT14 0x32e |
| 521 | #define CSR_MHPMEVENT15 0x32f |
| 522 | #define CSR_MHPMEVENT16 0x330 |
| 523 | #define CSR_MHPMEVENT17 0x331 |
| 524 | #define CSR_MHPMEVENT18 0x332 |
| 525 | #define CSR_MHPMEVENT19 0x333 |
| 526 | #define CSR_MHPMEVENT20 0x334 |
| 527 | #define CSR_MHPMEVENT21 0x335 |
| 528 | #define CSR_MHPMEVENT22 0x336 |
| 529 | #define CSR_MHPMEVENT23 0x337 |
| 530 | #define CSR_MHPMEVENT24 0x338 |
| 531 | #define CSR_MHPMEVENT25 0x339 |
| 532 | #define CSR_MHPMEVENT26 0x33a |
| 533 | #define CSR_MHPMEVENT27 0x33b |
| 534 | #define CSR_MHPMEVENT28 0x33c |
| 535 | #define CSR_MHPMEVENT29 0x33d |
| 536 | #define CSR_MHPMEVENT30 0x33e |
| 537 | #define CSR_MHPMEVENT31 0x33f |
| 538 | |
| 539 | #define CSR_MCYCLECFGH 0x721 |
| 540 | #define CSR_MINSTRETCFGH 0x722 |
| 541 | |
| 542 | #define CSR_MHPMEVENT3H 0x723 |
| 543 | #define CSR_MHPMEVENT4H 0x724 |
| 544 | #define CSR_MHPMEVENT5H 0x725 |
| 545 | #define CSR_MHPMEVENT6H 0x726 |
| 546 | #define CSR_MHPMEVENT7H 0x727 |
| 547 | #define CSR_MHPMEVENT8H 0x728 |
| 548 | #define CSR_MHPMEVENT9H 0x729 |
| 549 | #define CSR_MHPMEVENT10H 0x72a |
| 550 | #define CSR_MHPMEVENT11H 0x72b |
| 551 | #define CSR_MHPMEVENT12H 0x72c |
| 552 | #define CSR_MHPMEVENT13H 0x72d |
| 553 | #define CSR_MHPMEVENT14H 0x72e |
| 554 | #define CSR_MHPMEVENT15H 0x72f |
| 555 | #define CSR_MHPMEVENT16H 0x730 |
| 556 | #define CSR_MHPMEVENT17H 0x731 |
| 557 | #define CSR_MHPMEVENT18H 0x732 |
| 558 | #define CSR_MHPMEVENT19H 0x733 |
| 559 | #define CSR_MHPMEVENT20H 0x734 |
| 560 | #define CSR_MHPMEVENT21H 0x735 |
| 561 | #define CSR_MHPMEVENT22H 0x736 |
| 562 | #define CSR_MHPMEVENT23H 0x737 |
| 563 | #define CSR_MHPMEVENT24H 0x738 |
| 564 | #define CSR_MHPMEVENT25H 0x739 |
| 565 | #define CSR_MHPMEVENT26H 0x73a |
| 566 | #define CSR_MHPMEVENT27H 0x73b |
| 567 | #define CSR_MHPMEVENT28H 0x73c |
| 568 | #define CSR_MHPMEVENT29H 0x73d |
| 569 | #define CSR_MHPMEVENT30H 0x73e |
| 570 | #define CSR_MHPMEVENT31H 0x73f |
| 571 | |
| 572 | #define CSR_MHPMCOUNTER3H 0xb83 |
| 573 | #define CSR_MHPMCOUNTER4H 0xb84 |
| 574 | #define CSR_MHPMCOUNTER5H 0xb85 |
| 575 | #define CSR_MHPMCOUNTER6H 0xb86 |
| 576 | #define CSR_MHPMCOUNTER7H 0xb87 |
| 577 | #define CSR_MHPMCOUNTER8H 0xb88 |
| 578 | #define CSR_MHPMCOUNTER9H 0xb89 |
| 579 | #define CSR_MHPMCOUNTER10H 0xb8a |
| 580 | #define CSR_MHPMCOUNTER11H 0xb8b |
| 581 | #define CSR_MHPMCOUNTER12H 0xb8c |
| 582 | #define CSR_MHPMCOUNTER13H 0xb8d |
| 583 | #define CSR_MHPMCOUNTER14H 0xb8e |
| 584 | #define CSR_MHPMCOUNTER15H 0xb8f |
| 585 | #define CSR_MHPMCOUNTER16H 0xb90 |
| 586 | #define CSR_MHPMCOUNTER17H 0xb91 |
| 587 | #define CSR_MHPMCOUNTER18H 0xb92 |
| 588 | #define CSR_MHPMCOUNTER19H 0xb93 |
| 589 | #define CSR_MHPMCOUNTER20H 0xb94 |
| 590 | #define CSR_MHPMCOUNTER21H 0xb95 |
| 591 | #define CSR_MHPMCOUNTER22H 0xb96 |
| 592 | #define CSR_MHPMCOUNTER23H 0xb97 |
| 593 | #define CSR_MHPMCOUNTER24H 0xb98 |
| 594 | #define CSR_MHPMCOUNTER25H 0xb99 |
| 595 | #define CSR_MHPMCOUNTER26H 0xb9a |
| 596 | #define CSR_MHPMCOUNTER27H 0xb9b |
| 597 | #define CSR_MHPMCOUNTER28H 0xb9c |
| 598 | #define CSR_MHPMCOUNTER29H 0xb9d |
| 599 | #define CSR_MHPMCOUNTER30H 0xb9e |
| 600 | #define CSR_MHPMCOUNTER31H 0xb9f |
| 601 | |
| 602 | #define CSR_SCOUNTOVF 0xda0 |
| 603 | |
| 604 | /* Crypto Extension */ |
| 605 | #define CSR_SEED 0x015 |
| 606 | |
| 607 | /* Zcmt Extension */ |
| 608 | #define CSR_JVT 0x017 |
| 609 | |
| 610 | /* mstatus CSR bits */ |
| 611 | #define MSTATUS_UIE 0x00000001 |
| 612 | #define MSTATUS_SIE 0x00000002 |
| 613 | #define MSTATUS_MIE 0x00000008 |
| 614 | #define MSTATUS_UPIE 0x00000010 |
| 615 | #define MSTATUS_SPIE 0x00000020 |
| 616 | #define MSTATUS_UBE 0x00000040 |
| 617 | #define MSTATUS_MPIE 0x00000080 |
| 618 | #define MSTATUS_SPP 0x00000100 |
| 619 | #define MSTATUS_VS 0x00000600 |
| 620 | #define MSTATUS_MPP 0x00001800 |
| 621 | #define MSTATUS_FS 0x00006000 |
| 622 | #define MSTATUS_XS 0x00018000 |
| 623 | #define MSTATUS_MPRV 0x00020000 |
| 624 | #define MSTATUS_SUM 0x00040000 /* since: priv-1.10 */ |
| 625 | #define MSTATUS_MXR 0x00080000 |
| 626 | #define MSTATUS_TVM 0x00100000 /* since: priv-1.10 */ |
| 627 | #define MSTATUS_TW 0x00200000 /* since: priv-1.10 */ |
| 628 | #define MSTATUS_TSR 0x00400000 /* since: priv-1.10 */ |
| 629 | #define MSTATUS_SPELP 0x00800000 /* zicfilp */ |
| 630 | #define MSTATUS_SDT 0x01000000 |
| 631 | #define MSTATUS_MPELP 0x020000000000 /* zicfilp */ |
| 632 | #define MSTATUS_SBE 0x1000000000ULL |
| 633 | #define MSTATUS_MBE 0x2000000000ULL |
| 634 | #define MSTATUS_GVA 0x4000000000ULL |
| 635 | #define MSTATUS_MPV 0x8000000000ULL |
| 636 | #define MSTATUS_MDT 0x40000000000ULL /* Smdbltrp extension */ |
| 637 | |
| 638 | #define MSTATUS64_UXL 0x0000000300000000ULL |
| 639 | #define MSTATUS64_SXL 0x0000000C00000000ULL |
| 640 | |
| 641 | #define MSTATUS32_SD 0x80000000 |
| 642 | #define MSTATUS64_SD 0x8000000000000000ULL |
| 643 | #define MSTATUSH128_SD 0x8000000000000000ULL |
| 644 | |
| 645 | #define MISA32_MXL 0xC0000000 |
| 646 | #define MISA64_MXL 0xC000000000000000ULL |
| 647 | |
| 648 | typedef enum { |
| 649 | MXL_RV32 = 1, |
| 650 | MXL_RV64 = 2, |
| 651 | MXL_RV128 = 3, |
| 652 | } RISCVMXL; |
| 653 | |
| 654 | /* sstatus CSR bits */ |
| 655 | #define SSTATUS_UIE 0x00000001 |
| 656 | #define SSTATUS_SIE 0x00000002 |
| 657 | #define SSTATUS_UPIE 0x00000010 |
| 658 | #define SSTATUS_SPIE 0x00000020 |
| 659 | #define SSTATUS_SPP 0x00000100 |
| 660 | #define SSTATUS_VS 0x00000600 |
| 661 | #define SSTATUS_FS 0x00006000 |
| 662 | #define SSTATUS_XS 0x00018000 |
| 663 | #define SSTATUS_SUM 0x00040000 /* since: priv-1.10 */ |
| 664 | #define SSTATUS_MXR 0x00080000 |
| 665 | #define SSTATUS_SPELP MSTATUS_SPELP /* zicfilp */ |
| 666 | #define SSTATUS_SDT MSTATUS_SDT |
| 667 | |
| 668 | #define SSTATUS64_UXL 0x0000000300000000ULL |
| 669 | |
| 670 | #define SSTATUS32_SD 0x80000000 |
| 671 | #define SSTATUS64_SD 0x8000000000000000ULL |
| 672 | |
| 673 | /* hstatus CSR bits */ |
| 674 | #define HSTATUS_VSBE 0x00000020 |
| 675 | #define HSTATUS_GVA 0x00000040 |
| 676 | #define HSTATUS_SPV 0x00000080 |
| 677 | #define HSTATUS_SPVP 0x00000100 |
| 678 | #define HSTATUS_HU 0x00000200 |
| 679 | #define HSTATUS_VGEIN 0x0003F000 |
| 680 | #define HSTATUS_VTVM 0x00100000 |
| 681 | #define HSTATUS_VTW 0x00200000 |
| 682 | #define HSTATUS_VTSR 0x00400000 |
| 683 | #define HSTATUS_HUKTE 0x01000000 |
| 684 | #define HSTATUS_VSXL 0x300000000 |
| 685 | #define HSTATUS_HUPMM 0x3000000000000 |
| 686 | |
| 687 | #define HSTATUS32_WPRI 0xFF8FF87E |
| 688 | #define HSTATUS64_WPRI 0xFFFFFFFFFF8FF87EULL |
| 689 | |
| 690 | #define COUNTEREN_CY (1 << 0) |
| 691 | #define COUNTEREN_TM (1 << 1) |
| 692 | #define COUNTEREN_IR (1 << 2) |
| 693 | #define COUNTEREN_HPM3 (1 << 3) |
| 694 | |
| 695 | /* vsstatus CSR bits */ |
| 696 | #define VSSTATUS64_UXL 0x0000000300000000ULL |
| 697 | |
| 698 | /* Privilege modes */ |
| 699 | #define PRV_U 0 |
| 700 | #define PRV_S 1 |
| 701 | #define PRV_RESERVED 2 |
| 702 | #define PRV_M 3 |
| 703 | |
| 704 | /* RV32 satp CSR field masks */ |
| 705 | #define SATP32_MODE 0x80000000 |
| 706 | #define SATP32_ASID 0x7fc00000 |
| 707 | #define SATP32_PPN 0x003fffff |
| 708 | |
| 709 | /* RV64 satp CSR field masks */ |
| 710 | #define SATP64_MODE 0xF000000000000000ULL |
| 711 | #define SATP64_ASID 0x0FFFF00000000000ULL |
| 712 | #define SATP64_PPN 0x00000FFFFFFFFFFFULL |
| 713 | |
| 714 | /* RNMI mnstatus CSR mask */ |
| 715 | #define MNSTATUS_NMIE 0x00000008 |
| 716 | #define MNSTATUS_MNPV 0x00000080 |
| 717 | #define MNSTATUS_MNPELP 0x00000200 |
| 718 | #define MNSTATUS_MNPP 0x00001800 |
| 719 | |
| 720 | /* VM modes (satp.mode) privileged ISA 1.10 */ |
| 721 | #define VM_1_10_MBARE 0 |
| 722 | #define VM_1_10_SV32 1 |
| 723 | #define VM_1_10_SV39 8 |
| 724 | #define VM_1_10_SV48 9 |
| 725 | #define VM_1_10_SV57 10 |
| 726 | #define VM_1_10_SV64 11 |
| 727 | |
| 728 | /* Page table entry (PTE) fields */ |
| 729 | #define PTE_V 0x001 /* Valid */ |
| 730 | #define PTE_R 0x002 /* Read */ |
| 731 | #define PTE_W 0x004 /* Write */ |
| 732 | #define PTE_X 0x008 /* Execute */ |
| 733 | #define PTE_U 0x010 /* User */ |
| 734 | #define PTE_G 0x020 /* Global */ |
| 735 | #define PTE_A 0x040 /* Accessed */ |
| 736 | #define PTE_D 0x080 /* Dirty */ |
| 737 | #define PTE_SOFT 0x300 /* Reserved for Software */ |
| 738 | #define PTE_PBMT 0x6000000000000000ULL /* Page-based memory types */ |
| 739 | #define PTE_N 0x8000000000000000ULL /* NAPOT translation */ |
| 740 | #define PTE_RESERVED(svrsw60t59b) \ |
| 741 | (svrsw60t59b ? 0x07C0000000000000ULL : 0x1FC0000000000000ULL) /* Reserved bits */ |
| 742 | #define PTE_ATTR (PTE_N | PTE_PBMT) /* All attributes bits */ |
| 743 | |
| 744 | /* Page table PPN shift amount */ |
| 745 | #define PTE_PPN_SHIFT 10 |
| 746 | |
| 747 | /* Page table PPN mask */ |
| 748 | #define PTE_PPN_MASK 0x3FFFFFFFFFFC00ULL |
| 749 | |
| 750 | /* Leaf page shift amount */ |
| 751 | #define PGSHIFT 12 |
| 752 | |
| 753 | /* Default Reset Vector address */ |
| 754 | #define DEFAULT_RSTVEC 0x1000 |
| 755 | |
| 756 | /* Default RNMI Interrupt Vector address */ |
| 757 | #define DEFAULT_RNMI_IRQVEC 0x0 |
| 758 | |
| 759 | /* Default RNMI Exception Vector address */ |
| 760 | #define DEFAULT_RNMI_EXCPVEC 0x0 |
| 761 | |
| 762 | /* Exception causes */ |
| 763 | typedef enum RISCVException { |
| 764 | RISCV_EXCP_NONE = -1, /* sentinel value */ |
| 765 | RISCV_EXCP_INST_ADDR_MIS = 0x0, |
| 766 | RISCV_EXCP_INST_ACCESS_FAULT = 0x1, |
| 767 | RISCV_EXCP_ILLEGAL_INST = 0x2, |
| 768 | RISCV_EXCP_BREAKPOINT = 0x3, |
| 769 | RISCV_EXCP_LOAD_ADDR_MIS = 0x4, |
| 770 | RISCV_EXCP_LOAD_ACCESS_FAULT = 0x5, |
| 771 | RISCV_EXCP_STORE_AMO_ADDR_MIS = 0x6, |
| 772 | RISCV_EXCP_STORE_AMO_ACCESS_FAULT = 0x7, |
| 773 | RISCV_EXCP_U_ECALL = 0x8, |
| 774 | RISCV_EXCP_S_ECALL = 0x9, |
| 775 | RISCV_EXCP_VS_ECALL = 0xa, |
| 776 | RISCV_EXCP_M_ECALL = 0xb, |
| 777 | RISCV_EXCP_INST_PAGE_FAULT = 0xc, /* since: priv-1.10.0 */ |
| 778 | RISCV_EXCP_LOAD_PAGE_FAULT = 0xd, /* since: priv-1.10.0 */ |
| 779 | RISCV_EXCP_STORE_PAGE_FAULT = 0xf, /* since: priv-1.10.0 */ |
| 780 | RISCV_EXCP_DOUBLE_TRAP = 0x10, |
| 781 | RISCV_EXCP_SW_CHECK = 0x12, /* since: priv-1.13.0 */ |
| 782 | RISCV_EXCP_HW_ERR = 0x13, /* since: priv-1.13.0 */ |
| 783 | RISCV_EXCP_INST_GUEST_PAGE_FAULT = 0x14, |
| 784 | RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT = 0x15, |
| 785 | RISCV_EXCP_VIRT_INSTRUCTION_FAULT = 0x16, |
| 786 | RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT = 0x17, |
| 787 | RISCV_EXCP_SEMIHOST = 0x3f, |
| 788 | } RISCVException; |
| 789 | |
| 790 | /* zicfilp defines lp violation results in sw check with tval = 2*/ |
| 791 | #define RISCV_EXCP_SW_CHECK_FCFI_TVAL 2 |
| 792 | /* zicfiss defines ss violation results in sw check with tval = 3*/ |
| 793 | #define RISCV_EXCP_SW_CHECK_BCFI_TVAL 3 |
| 794 | |
| 795 | #define RISCV_EXCP_INT_FLAG 0x80000000 |
| 796 | #define RISCV_EXCP_INT_MASK 0x7fffffff |
| 797 | |
| 798 | /* Interrupt causes */ |
| 799 | #define IRQ_U_SOFT 0 |
| 800 | #define IRQ_S_SOFT 1 |
| 801 | #define IRQ_VS_SOFT 2 |
| 802 | #define IRQ_M_SOFT 3 |
| 803 | #define IRQ_U_TIMER 4 |
| 804 | #define IRQ_S_TIMER 5 |
| 805 | #define IRQ_VS_TIMER 6 |
| 806 | #define IRQ_M_TIMER 7 |
| 807 | #define IRQ_U_EXT 8 |
| 808 | #define IRQ_S_EXT 9 |
| 809 | #define IRQ_VS_EXT 10 |
| 810 | #define IRQ_M_EXT 11 |
| 811 | #define IRQ_S_GEXT 12 |
| 812 | #define IRQ_PMU_OVF 13 |
| 813 | #define IRQ_LOCAL_MAX 64 |
| 814 | /* -1 is due to bit zero of hgeip and hgeie being ROZ. */ |
| 815 | #define IRQ_LOCAL_GUEST_MAX (TARGET_LONG_BITS - 1) |
| 816 | |
| 817 | /* RNMI causes */ |
| 818 | #define RNMI_MAX 16 |
| 819 | |
| 820 | /* mip masks */ |
| 821 | #define MIP_USIP (1 << IRQ_U_SOFT) |
| 822 | #define MIP_SSIP (1 << IRQ_S_SOFT) |
| 823 | #define MIP_VSSIP (1 << IRQ_VS_SOFT) |
| 824 | #define MIP_MSIP (1 << IRQ_M_SOFT) |
| 825 | #define MIP_UTIP (1 << IRQ_U_TIMER) |
| 826 | #define MIP_STIP (1 << IRQ_S_TIMER) |
| 827 | #define MIP_VSTIP (1 << IRQ_VS_TIMER) |
| 828 | #define MIP_MTIP (1 << IRQ_M_TIMER) |
| 829 | #define MIP_UEIP (1 << IRQ_U_EXT) |
| 830 | #define MIP_SEIP (1 << IRQ_S_EXT) |
| 831 | #define MIP_VSEIP (1 << IRQ_VS_EXT) |
| 832 | #define MIP_MEIP (1 << IRQ_M_EXT) |
| 833 | #define MIP_SGEIP (1 << IRQ_S_GEXT) |
| 834 | #define MIP_LCOFIP (1 << IRQ_PMU_OVF) |
| 835 | |
| 836 | /* sip masks */ |
| 837 | #define SIP_SSIP MIP_SSIP |
| 838 | #define SIP_STIP MIP_STIP |
| 839 | #define SIP_SEIP MIP_SEIP |
| 840 | #define SIP_LCOFIP MIP_LCOFIP |
| 841 | |
| 842 | /* MIE masks */ |
| 843 | #define MIE_SEIE (1 << IRQ_S_EXT) |
| 844 | #define MIE_UEIE (1 << IRQ_U_EXT) |
| 845 | #define MIE_STIE (1 << IRQ_S_TIMER) |
| 846 | #define MIE_UTIE (1 << IRQ_U_TIMER) |
| 847 | #define MIE_SSIE (1 << IRQ_S_SOFT) |
| 848 | #define MIE_USIE (1 << IRQ_U_SOFT) |
| 849 | |
| 850 | /* Machine constants */ |
| 851 | #define M_MODE_INTERRUPTS ((uint64_t)(MIP_MSIP | MIP_MTIP | MIP_MEIP)) |
| 852 | #define S_MODE_INTERRUPTS ((uint64_t)(MIP_SSIP | MIP_STIP | MIP_SEIP)) |
| 853 | #define VS_MODE_INTERRUPTS ((uint64_t)(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)) |
| 854 | #define HS_MODE_INTERRUPTS ((uint64_t)(MIP_SGEIP | VS_MODE_INTERRUPTS)) |
| 855 | |
| 856 | /* Execution environment configuration bits */ |
| 857 | #define MENVCFG_FIOM BIT(0) |
| 858 | #define MENVCFG_LPE BIT(2) /* zicfilp */ |
| 859 | #define MENVCFG_SSE BIT(3) /* zicfiss */ |
| 860 | #define MENVCFG_CBIE (3UL << 4) |
| 861 | #define MENVCFG_CBCFE BIT(6) |
| 862 | #define MENVCFG_CBZE BIT(7) |
| 863 | #define MENVCFG_PMM (3ULL << 32) |
| 864 | #define MENVCFG_DTE (1ULL << 59) |
| 865 | #define MENVCFG_CDE (1ULL << 60) |
| 866 | #define MENVCFG_ADUE (1ULL << 61) |
| 867 | #define MENVCFG_PBMTE (1ULL << 62) |
| 868 | #define MENVCFG_STCE (1ULL << 63) |
| 869 | |
| 870 | /* For RV32 */ |
| 871 | #define MENVCFGH_DTE BIT(27) |
| 872 | #define MENVCFGH_ADUE BIT(29) |
| 873 | #define MENVCFGH_PBMTE BIT(30) |
| 874 | #define MENVCFGH_STCE BIT(31) |
| 875 | |
| 876 | #define SENVCFG_FIOM MENVCFG_FIOM |
| 877 | #define SENVCFG_LPE MENVCFG_LPE |
| 878 | #define SENVCFG_SSE MENVCFG_SSE |
| 879 | #define SENVCFG_CBIE MENVCFG_CBIE |
| 880 | #define SENVCFG_CBCFE MENVCFG_CBCFE |
| 881 | #define SENVCFG_CBZE MENVCFG_CBZE |
| 882 | #define SENVCFG_UKTE BIT(8) |
| 883 | #define SENVCFG_PMM MENVCFG_PMM |
| 884 | |
| 885 | #define HENVCFG_FIOM MENVCFG_FIOM |
| 886 | #define HENVCFG_LPE MENVCFG_LPE |
| 887 | #define HENVCFG_SSE MENVCFG_SSE |
| 888 | #define HENVCFG_CBIE MENVCFG_CBIE |
| 889 | #define HENVCFG_CBCFE MENVCFG_CBCFE |
| 890 | #define HENVCFG_CBZE MENVCFG_CBZE |
| 891 | #define HENVCFG_PMM MENVCFG_PMM |
| 892 | #define HENVCFG_DTE MENVCFG_DTE |
| 893 | #define HENVCFG_ADUE MENVCFG_ADUE |
| 894 | #define HENVCFG_PBMTE MENVCFG_PBMTE |
| 895 | #define HENVCFG_STCE MENVCFG_STCE |
| 896 | |
| 897 | /* For RV32 */ |
| 898 | #define HENVCFGH_DTE MENVCFGH_DTE |
| 899 | #define HENVCFGH_ADUE MENVCFGH_ADUE |
| 900 | #define HENVCFGH_PBMTE MENVCFGH_PBMTE |
| 901 | #define HENVCFGH_STCE MENVCFGH_STCE |
| 902 | |
| 903 | /* Offsets for every pair of control bits per each priv level */ |
| 904 | #define XS_OFFSET 0ULL |
| 905 | #define U_OFFSET 2ULL |
| 906 | #define S_OFFSET 5ULL |
| 907 | #define M_OFFSET 8ULL |
| 908 | |
| 909 | #define PM_XS_BITS (EXT_STATUS_MASK << XS_OFFSET) |
| 910 | #define U_PM_ENABLE (PM_ENABLE << U_OFFSET) |
| 911 | #define U_PM_CURRENT (PM_CURRENT << U_OFFSET) |
| 912 | #define U_PM_INSN (PM_INSN << U_OFFSET) |
| 913 | #define S_PM_ENABLE (PM_ENABLE << S_OFFSET) |
| 914 | #define S_PM_CURRENT (PM_CURRENT << S_OFFSET) |
| 915 | #define S_PM_INSN (PM_INSN << S_OFFSET) |
| 916 | #define M_PM_ENABLE (PM_ENABLE << M_OFFSET) |
| 917 | #define M_PM_CURRENT (PM_CURRENT << M_OFFSET) |
| 918 | #define M_PM_INSN (PM_INSN << M_OFFSET) |
| 919 | |
| 920 | /* mmte CSR bits */ |
| 921 | #define MMTE_PM_XS_BITS PM_XS_BITS |
| 922 | #define MMTE_U_PM_ENABLE U_PM_ENABLE |
| 923 | #define MMTE_U_PM_CURRENT U_PM_CURRENT |
| 924 | #define MMTE_U_PM_INSN U_PM_INSN |
| 925 | #define MMTE_S_PM_ENABLE S_PM_ENABLE |
| 926 | #define MMTE_S_PM_CURRENT S_PM_CURRENT |
| 927 | #define MMTE_S_PM_INSN S_PM_INSN |
| 928 | #define MMTE_M_PM_ENABLE M_PM_ENABLE |
| 929 | #define MMTE_M_PM_CURRENT M_PM_CURRENT |
| 930 | #define MMTE_M_PM_INSN M_PM_INSN |
| 931 | #define MMTE_MASK (MMTE_U_PM_ENABLE | MMTE_U_PM_CURRENT | MMTE_U_PM_INSN | \ |
| 932 | MMTE_S_PM_ENABLE | MMTE_S_PM_CURRENT | MMTE_S_PM_INSN | \ |
| 933 | MMTE_M_PM_ENABLE | MMTE_M_PM_CURRENT | MMTE_M_PM_INSN | \ |
| 934 | MMTE_PM_XS_BITS) |
| 935 | |
| 936 | /* (v)smte CSR bits */ |
| 937 | #define SMTE_PM_XS_BITS PM_XS_BITS |
| 938 | #define SMTE_U_PM_ENABLE U_PM_ENABLE |
| 939 | #define SMTE_U_PM_CURRENT U_PM_CURRENT |
| 940 | #define SMTE_U_PM_INSN U_PM_INSN |
| 941 | #define SMTE_S_PM_ENABLE S_PM_ENABLE |
| 942 | #define SMTE_S_PM_CURRENT S_PM_CURRENT |
| 943 | #define SMTE_S_PM_INSN S_PM_INSN |
| 944 | #define SMTE_MASK (SMTE_U_PM_ENABLE | SMTE_U_PM_CURRENT | SMTE_U_PM_INSN | \ |
| 945 | SMTE_S_PM_ENABLE | SMTE_S_PM_CURRENT | SMTE_S_PM_INSN | \ |
| 946 | SMTE_PM_XS_BITS) |
| 947 | |
| 948 | /* umte CSR bits */ |
| 949 | #define UMTE_U_PM_ENABLE U_PM_ENABLE |
| 950 | #define UMTE_U_PM_CURRENT U_PM_CURRENT |
| 951 | #define UMTE_U_PM_INSN U_PM_INSN |
| 952 | #define UMTE_MASK (UMTE_U_PM_ENABLE | MMTE_U_PM_CURRENT | UMTE_U_PM_INSN) |
| 953 | |
| 954 | /* CTR control register commom fields */ |
| 955 | #define XCTRCTL_U BIT_ULL(0) |
| 956 | #define XCTRCTL_S BIT_ULL(1) |
| 957 | #define XCTRCTL_RASEMU BIT_ULL(7) |
| 958 | #define XCTRCTL_STE BIT_ULL(8) |
| 959 | #define XCTRCTL_BPFRZ BIT_ULL(11) |
| 960 | #define XCTRCTL_LCOFIFRZ BIT_ULL(12) |
| 961 | #define XCTRCTL_EXCINH BIT_ULL(33) |
| 962 | #define XCTRCTL_INTRINH BIT_ULL(34) |
| 963 | #define XCTRCTL_TRETINH BIT_ULL(35) |
| 964 | #define XCTRCTL_NTBREN BIT_ULL(36) |
| 965 | #define XCTRCTL_TKBRINH BIT_ULL(37) |
| 966 | #define XCTRCTL_INDCALLINH BIT_ULL(40) |
| 967 | #define XCTRCTL_DIRCALLINH BIT_ULL(41) |
| 968 | #define XCTRCTL_INDJMPINH BIT_ULL(42) |
| 969 | #define XCTRCTL_DIRJMPINH BIT_ULL(43) |
| 970 | #define XCTRCTL_CORSWAPINH BIT_ULL(44) |
| 971 | #define XCTRCTL_RETINH BIT_ULL(45) |
| 972 | #define XCTRCTL_INDLJMPINH BIT_ULL(46) |
| 973 | #define XCTRCTL_DIRLJMPINH BIT_ULL(47) |
| 974 | |
| 975 | #define XCTRCTL_MASK (XCTRCTL_U | XCTRCTL_S | XCTRCTL_RASEMU | \ |
| 976 | XCTRCTL_STE | XCTRCTL_BPFRZ | XCTRCTL_LCOFIFRZ | \ |
| 977 | XCTRCTL_EXCINH | XCTRCTL_INTRINH | XCTRCTL_TRETINH | \ |
| 978 | XCTRCTL_NTBREN | XCTRCTL_TKBRINH | XCTRCTL_INDCALLINH | \ |
| 979 | XCTRCTL_DIRCALLINH | XCTRCTL_INDJMPINH | \ |
| 980 | XCTRCTL_DIRJMPINH | XCTRCTL_CORSWAPINH | \ |
| 981 | XCTRCTL_RETINH | XCTRCTL_INDLJMPINH | XCTRCTL_DIRLJMPINH) |
| 982 | |
| 983 | #define XCTRCTL_INH_START 32U |
| 984 | |
| 985 | /* CTR mctrctl bits */ |
| 986 | #define MCTRCTL_M BIT_ULL(2) |
| 987 | #define MCTRCTL_MTE BIT_ULL(9) |
| 988 | |
| 989 | #define MCTRCTL_MASK (XCTRCTL_MASK | MCTRCTL_M | MCTRCTL_MTE) |
| 990 | #define SCTRCTL_MASK XCTRCTL_MASK |
| 991 | #define VSCTRCTL_MASK XCTRCTL_MASK |
| 992 | |
| 993 | /* sctrstatus CSR bits. */ |
| 994 | #define SCTRSTATUS_WRPTR_MASK 0xFF |
| 995 | #define SCTRSTATUS_FROZEN BIT(31) |
| 996 | #define SCTRSTATUS_MASK (SCTRSTATUS_WRPTR_MASK | SCTRSTATUS_FROZEN) |
| 997 | |
| 998 | /* sctrdepth CSR bits. */ |
| 999 | #define SCTRDEPTH_MASK 0x7 |
| 1000 | #define SCTRDEPTH_MIN 0U /* 16 Entries. */ |
| 1001 | #define SCTRDEPTH_MAX 4U /* 256 Entries. */ |
| 1002 | |
| 1003 | #define CTR_ENTRIES_FIRST 0x200 |
| 1004 | #define CTR_ENTRIES_LAST 0x2ff |
| 1005 | |
| 1006 | #define CTRSOURCE_VALID BIT(0) |
| 1007 | #define CTRTARGET_MISP BIT(0) |
| 1008 | |
| 1009 | #define CTRDATA_TYPE_MASK 0xF |
| 1010 | #define CTRDATA_CCV BIT(15) |
| 1011 | #define CTRDATA_CCM_MASK 0xFFF0000 |
| 1012 | #define CTRDATA_CCE_MASK 0xF0000000 |
| 1013 | |
| 1014 | #define CTRDATA_MASK (CTRDATA_TYPE_MASK | CTRDATA_CCV | \ |
| 1015 | CTRDATA_CCM_MASK | CTRDATA_CCE_MASK) |
| 1016 | |
| 1017 | typedef enum CTRType { |
| 1018 | CTRDATA_TYPE_NONE = 0, |
| 1019 | CTRDATA_TYPE_EXCEPTION = 1, |
| 1020 | CTRDATA_TYPE_INTERRUPT = 2, |
| 1021 | CTRDATA_TYPE_EXCEP_INT_RET = 3, |
| 1022 | CTRDATA_TYPE_NONTAKEN_BRANCH = 4, |
| 1023 | CTRDATA_TYPE_TAKEN_BRANCH = 5, |
| 1024 | CTRDATA_TYPE_RESERVED_0 = 6, |
| 1025 | CTRDATA_TYPE_RESERVED_1 = 7, |
| 1026 | CTRDATA_TYPE_INDIRECT_CALL = 8, |
| 1027 | CTRDATA_TYPE_DIRECT_CALL = 9, |
| 1028 | CTRDATA_TYPE_INDIRECT_JUMP = 10, |
| 1029 | CTRDATA_TYPE_DIRECT_JUMP = 11, |
| 1030 | CTRDATA_TYPE_CO_ROUTINE_SWAP = 12, |
| 1031 | CTRDATA_TYPE_RETURN = 13, |
| 1032 | CTRDATA_TYPE_OTHER_INDIRECT_JUMP = 14, |
| 1033 | CTRDATA_TYPE_OTHER_DIRECT_JUMP = 15, |
| 1034 | } CTRType; |
| 1035 | |
| 1036 | /* MISELECT, SISELECT, and VSISELECT bits (AIA) */ |
| 1037 | #define ISELECT_IPRIO0 0x30 |
| 1038 | #define ISELECT_IPRIO15 0x3f |
| 1039 | #define ISELECT_IMSIC_EIDELIVERY 0x70 |
| 1040 | #define ISELECT_IMSIC_EITHRESHOLD 0x72 |
| 1041 | #define ISELECT_IMSIC_EIP0 0x80 |
| 1042 | #define ISELECT_IMSIC_EIP63 0xbf |
| 1043 | #define ISELECT_IMSIC_EIE0 0xc0 |
| 1044 | #define ISELECT_IMSIC_EIE63 0xff |
| 1045 | #define ISELECT_IMSIC_FIRST ISELECT_IMSIC_EIDELIVERY |
| 1046 | #define ISELECT_IMSIC_LAST ISELECT_IMSIC_EIE63 |
| 1047 | #define ISELECT_MASK_AIA 0x1ff |
| 1048 | |
| 1049 | /* [M|S|VS]SELCT value for Indirect CSR Access Extension */ |
| 1050 | #define ISELECT_CD_FIRST 0x40 |
| 1051 | #define ISELECT_CD_LAST 0x5f |
| 1052 | #define ISELECT_MASK_SXCSRIND 0xfff |
| 1053 | |
| 1054 | /* Dummy [M|S|VS]ISELECT value for emulating [M|S|VS]TOPEI CSRs */ |
| 1055 | #define ISELECT_IMSIC_TOPEI (ISELECT_MASK_AIA + 1) |
| 1056 | |
| 1057 | /* IMSIC bits (AIA) */ |
| 1058 | #define IMSIC_TOPEI_IID_SHIFT 16 |
| 1059 | #define IMSIC_TOPEI_IID_MASK 0x7ff |
| 1060 | #define IMSIC_TOPEI_IPRIO_MASK 0x7ff |
| 1061 | #define IMSIC_EIPx_BITS 32 |
| 1062 | #define IMSIC_EIEx_BITS 32 |
| 1063 | |
| 1064 | /* MTOPI and STOPI bits (AIA) */ |
| 1065 | #define TOPI_IID_SHIFT 16 |
| 1066 | #define TOPI_IID_MASK 0xfff |
| 1067 | #define TOPI_IPRIO_MASK 0xff |
| 1068 | |
| 1069 | /* Interrupt priority bits (AIA) */ |
| 1070 | #define IPRIO_IRQ_BITS 8 |
| 1071 | #define IPRIO_MMAXIPRIO 255 |
| 1072 | #define IPRIO_DEFAULT_UPPER 4 |
| 1073 | #define IPRIO_DEFAULT_MIDDLE (IPRIO_DEFAULT_UPPER + 12) |
| 1074 | #define IPRIO_DEFAULT_M IPRIO_DEFAULT_MIDDLE |
| 1075 | #define IPRIO_DEFAULT_S (IPRIO_DEFAULT_M + 3) |
| 1076 | #define IPRIO_DEFAULT_SGEXT (IPRIO_DEFAULT_S + 3) |
| 1077 | #define IPRIO_DEFAULT_VS (IPRIO_DEFAULT_SGEXT + 1) |
| 1078 | #define IPRIO_DEFAULT_LOWER (IPRIO_DEFAULT_VS + 3) |
| 1079 | |
| 1080 | /* HVICTL bits (AIA) */ |
| 1081 | #define HVICTL_VTI 0x40000000 |
| 1082 | #define HVICTL_IID 0x0fff0000 |
| 1083 | #define HVICTL_IPRIOM 0x00000100 |
| 1084 | #define HVICTL_IPRIO 0x000000ff |
| 1085 | #define HVICTL_VALID_MASK \ |
| 1086 | (HVICTL_VTI | HVICTL_IID | HVICTL_IPRIOM | HVICTL_IPRIO) |
| 1087 | |
| 1088 | /* seed CSR bits */ |
| 1089 | #define SEED_OPST (0b11U << 30) |
| 1090 | #define SEED_OPST_BIST (0b00U << 30) |
| 1091 | #define SEED_OPST_WAIT (0b01U << 30) |
| 1092 | #define SEED_OPST_ES16 (0b10U << 30) |
| 1093 | #define SEED_OPST_DEAD (0b11U << 30) |
| 1094 | /* PMU related bits */ |
| 1095 | #define MIE_LCOFIE (1 << IRQ_PMU_OVF) |
| 1096 | |
| 1097 | #define MCYCLECFG_BIT_MINH BIT_ULL(62) |
| 1098 | #define MCYCLECFGH_BIT_MINH BIT(30) |
| 1099 | #define MCYCLECFG_BIT_SINH BIT_ULL(61) |
| 1100 | #define MCYCLECFGH_BIT_SINH BIT(29) |
| 1101 | #define MCYCLECFG_BIT_UINH BIT_ULL(60) |
| 1102 | #define MCYCLECFGH_BIT_UINH BIT(28) |
| 1103 | #define MCYCLECFG_BIT_VSINH BIT_ULL(59) |
| 1104 | #define MCYCLECFGH_BIT_VSINH BIT(27) |
| 1105 | #define MCYCLECFG_BIT_VUINH BIT_ULL(58) |
| 1106 | #define MCYCLECFGH_BIT_VUINH BIT(26) |
| 1107 | |
| 1108 | #define MINSTRETCFG_BIT_MINH BIT_ULL(62) |
| 1109 | #define MINSTRETCFGH_BIT_MINH BIT(30) |
| 1110 | #define MINSTRETCFG_BIT_SINH BIT_ULL(61) |
| 1111 | #define MINSTRETCFGH_BIT_SINH BIT(29) |
| 1112 | #define MINSTRETCFG_BIT_UINH BIT_ULL(60) |
| 1113 | #define MINSTRETCFGH_BIT_UINH BIT(28) |
| 1114 | #define MINSTRETCFG_BIT_VSINH BIT_ULL(59) |
| 1115 | #define MINSTRETCFGH_BIT_VSINH BIT(27) |
| 1116 | #define MINSTRETCFG_BIT_VUINH BIT_ULL(58) |
| 1117 | #define MINSTRETCFGH_BIT_VUINH BIT(26) |
| 1118 | |
| 1119 | #define MHPMEVENT_BIT_OF BIT_ULL(63) |
| 1120 | #define MHPMEVENTH_BIT_OF BIT(31) |
| 1121 | #define MHPMEVENT_BIT_MINH BIT_ULL(62) |
| 1122 | #define MHPMEVENTH_BIT_MINH BIT(30) |
| 1123 | #define MHPMEVENT_BIT_SINH BIT_ULL(61) |
| 1124 | #define MHPMEVENTH_BIT_SINH BIT(29) |
| 1125 | #define MHPMEVENT_BIT_UINH BIT_ULL(60) |
| 1126 | #define MHPMEVENTH_BIT_UINH BIT(28) |
| 1127 | #define MHPMEVENT_BIT_VSINH BIT_ULL(59) |
| 1128 | #define MHPMEVENTH_BIT_VSINH BIT(27) |
| 1129 | #define MHPMEVENT_BIT_VUINH BIT_ULL(58) |
| 1130 | #define MHPMEVENTH_BIT_VUINH BIT(26) |
| 1131 | |
| 1132 | #define MHPMEVENT_FILTER_MASK (MHPMEVENT_BIT_MINH | \ |
| 1133 | MHPMEVENT_BIT_SINH | \ |
| 1134 | MHPMEVENT_BIT_UINH | \ |
| 1135 | MHPMEVENT_BIT_VSINH | \ |
| 1136 | MHPMEVENT_BIT_VUINH) |
| 1137 | |
| 1138 | #define MHPMEVENTH_FILTER_MASK (MHPMEVENTH_BIT_MINH | \ |
| 1139 | MHPMEVENTH_BIT_SINH | \ |
| 1140 | MHPMEVENTH_BIT_UINH | \ |
| 1141 | MHPMEVENTH_BIT_VSINH | \ |
| 1142 | MHPMEVENTH_BIT_VUINH) |
| 1143 | |
| 1144 | #define MHPMEVENT_SSCOF_MASK MAKE_64BIT_MASK(63, 56) |
| 1145 | #define MHPMEVENT_IDX_MASK (~MHPMEVENT_SSCOF_MASK) |
| 1146 | |
| 1147 | /* RISC-V-specific interrupt pending bits. */ |
| 1148 | #define CPU_INTERRUPT_RNMI CPU_INTERRUPT_TGT_EXT_0 |
| 1149 | |
| 1150 | /* JVT CSR bits */ |
| 1151 | #define JVT_MODE 0x3F |
| 1152 | #define JVT_BASE (~0x3F) |
| 1153 | |
| 1154 | /* Debug Sdtrig CSR masks */ |
| 1155 | #define TEXTRA32_MHVALUE 0xFC000000 |
| 1156 | #define TEXTRA32_MHSELECT 0x03800000 |
| 1157 | #define TEXTRA32_SBYTEMASK 0x000C0000 |
| 1158 | #define TEXTRA32_SVALUE 0x0003FFFC |
| 1159 | #define TEXTRA32_SSELECT 0x00000003 |
| 1160 | #define TEXTRA64_MHVALUE 0xFFF8000000000000ULL |
| 1161 | #define TEXTRA64_MHSELECT 0x0007000000000000ULL |
| 1162 | #define TEXTRA64_SBYTEMASK 0x000000F000000000ULL |
| 1163 | #define TEXTRA64_SVALUE 0x00000003FFFFFFFCULL |
| 1164 | #define TEXTRA64_SSELECT 0x0000000000000003ULL |
| 1165 | #define MCONTEXT32 0x0000003F |
| 1166 | #define MCONTEXT64 0x0000000000001FFFULL |
| 1167 | #define MCONTEXT32_HCONTEXT 0x0000007F |
| 1168 | #define MCONTEXT64_HCONTEXT 0x0000000000003FFFULL |
| 1169 | #endif |