| 1 | # |
| 2 | # RISC-V translation routines for the RVXI Base Integer Instruction Set. |
| 3 | # |
| 4 | # Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de |
| 5 | # Bastian Koppelmann, kbastian@mail.uni-paderborn.de |
| 6 | # |
| 7 | # This program is free software; you can redistribute it and/or modify it |
| 8 | # under the terms and conditions of the GNU General Public License, |
| 9 | # version 2 or later, as published by the Free Software Foundation. |
| 10 | # |
| 11 | # This program is distributed in the hope it will be useful, but WITHOUT |
| 12 | # ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 13 | # FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 14 | # more details. |
| 15 | # |
| 16 | # You should have received a copy of the GNU General Public License along with |
| 17 | # this program. If not, see <http://www.gnu.org/licenses/>. |
| 18 | |
| 19 | # Fields: |
| 20 | %rd 7:5 |
| 21 | %rs1_3 7:3 !function=ex_rvc_register |
| 22 | %rs2_3 2:3 !function=ex_rvc_register |
| 23 | %rs2_5 2:5 |
| 24 | %r1s 7:3 !function=ex_sreg_register |
| 25 | %r2s 2:3 !function=ex_sreg_register |
| 26 | |
| 27 | # Immediates: |
| 28 | %imm_ci 12:s1 2:5 |
| 29 | %nzuimm_ciw 7:4 11:2 5:1 6:1 !function=ex_shift_2 |
| 30 | %uimm_cl_q 10:1 5:2 11:2 !function=ex_shift_4 |
| 31 | %uimm_cl_d 5:2 10:3 !function=ex_shift_3 |
| 32 | %uimm_cl_w 5:1 10:3 6:1 !function=ex_shift_2 |
| 33 | %imm_cb 12:s1 5:2 2:1 10:2 3:2 !function=ex_shift_1 |
| 34 | %imm_cj 12:s1 8:1 9:2 6:1 7:1 2:1 11:1 3:3 !function=ex_shift_1 |
| 35 | |
| 36 | %shlimm_6bit 12:1 2:5 !function=ex_rvc_shiftli |
| 37 | %shrimm_6bit 12:1 2:5 !function=ex_rvc_shiftri |
| 38 | %uimm_6bit_lq 2:4 12:1 6:1 !function=ex_shift_4 |
| 39 | %uimm_6bit_ld 2:3 12:1 5:2 !function=ex_shift_3 |
| 40 | %uimm_6bit_lw 2:2 12:1 4:3 !function=ex_shift_2 |
| 41 | %uimm_6bit_sq 7:4 11:2 !function=ex_shift_4 |
| 42 | %uimm_6bit_sd 7:3 10:3 !function=ex_shift_3 |
| 43 | %uimm_6bit_sw 7:2 9:4 !function=ex_shift_2 |
| 44 | |
| 45 | %imm_addi16sp 12:s1 3:2 5:1 2:1 6:1 !function=ex_shift_4 |
| 46 | %imm_lui 12:s1 2:5 !function=ex_shift_12 |
| 47 | |
| 48 | %uimm_cl_b 5:1 6:1 |
| 49 | %uimm_cl_h 5:1 !function=ex_shift_1 |
| 50 | %spimm 2:2 !function=ex_shift_4 |
| 51 | %urlist 4:4 |
| 52 | %index 2:8 |
| 53 | |
| 54 | # Argument sets imported from insn32.decode: |
| 55 | &empty !extern |
| 56 | &r rd rs1 rs2 !extern |
| 57 | &i imm rs1 rd !extern |
| 58 | &s imm rs1 rs2 !extern |
| 59 | &j imm rd !extern |
| 60 | &b imm rs2 rs1 !extern |
| 61 | &u imm rd !extern |
| 62 | &shift shamt rs1 rd !extern |
| 63 | &r2 rd rs1 !extern |
| 64 | &r2_s rs1 rs2 !extern |
| 65 | |
| 66 | &cmpp urlist spimm |
| 67 | &cmjt index |
| 68 | |
| 69 | # Formats 16: |
| 70 | @cr .... ..... ..... .. &r rs2=%rs2_5 rs1=%rd %rd |
| 71 | @ci ... . ..... ..... .. &i imm=%imm_ci rs1=%rd %rd |
| 72 | @cl_q ... . ..... ..... .. &i imm=%uimm_cl_q rs1=%rs1_3 rd=%rs2_3 |
| 73 | @cl_d ... ... ... .. ... .. &i imm=%uimm_cl_d rs1=%rs1_3 rd=%rs2_3 |
| 74 | @cl_w ... ... ... .. ... .. &i imm=%uimm_cl_w rs1=%rs1_3 rd=%rs2_3 |
| 75 | @cs_2 ... ... ... .. ... .. &r rs2=%rs2_3 rs1=%rs1_3 rd=%rs1_3 |
| 76 | @cs_q ... ... ... .. ... .. &s imm=%uimm_cl_q rs1=%rs1_3 rs2=%rs2_3 |
| 77 | @cs_d ... ... ... .. ... .. &s imm=%uimm_cl_d rs1=%rs1_3 rs2=%rs2_3 |
| 78 | @cs_w ... ... ... .. ... .. &s imm=%uimm_cl_w rs1=%rs1_3 rs2=%rs2_3 |
| 79 | @cj ... ........... .. &j imm=%imm_cj |
| 80 | @cb_z ... ... ... .. ... .. &b imm=%imm_cb rs1=%rs1_3 rs2=0 |
| 81 | |
| 82 | @c_lqsp ... . ..... ..... .. &i imm=%uimm_6bit_lq rs1=2 %rd |
| 83 | @c_ldsp ... . ..... ..... .. &i imm=%uimm_6bit_ld rs1=2 %rd |
| 84 | @c_lwsp ... . ..... ..... .. &i imm=%uimm_6bit_lw rs1=2 %rd |
| 85 | @c_sqsp ... . ..... ..... .. &s imm=%uimm_6bit_sq rs1=2 rs2=%rs2_5 |
| 86 | @c_sdsp ... . ..... ..... .. &s imm=%uimm_6bit_sd rs1=2 rs2=%rs2_5 |
| 87 | @c_swsp ... . ..... ..... .. &s imm=%uimm_6bit_sw rs1=2 rs2=%rs2_5 |
| 88 | @c_li ... . ..... ..... .. &i imm=%imm_ci rs1=0 %rd |
| 89 | @c_lui ... . ..... ..... .. &u imm=%imm_lui %rd |
| 90 | @c_jalr ... . ..... ..... .. &i imm=0 rs1=%rd |
| 91 | @c_mv ... . ..... ..... .. &i imm=0 rs1=%rs2_5 %rd |
| 92 | |
| 93 | @c_addi4spn ... . ..... ..... .. &i imm=%nzuimm_ciw rs1=2 rd=%rs2_3 |
| 94 | @c_addi16sp ... . ..... ..... .. &i imm=%imm_addi16sp rs1=2 rd=2 |
| 95 | |
| 96 | @c_shift ... . .. ... ..... .. \ |
| 97 | &shift rd=%rs1_3 rs1=%rs1_3 shamt=%shrimm_6bit |
| 98 | @c_shift2 ... . .. ... ..... .. \ |
| 99 | &shift rd=%rd rs1=%rd shamt=%shlimm_6bit |
| 100 | |
| 101 | @c_andi ... . .. ... ..... .. &i imm=%imm_ci rs1=%rs1_3 rd=%rs1_3 |
| 102 | |
| 103 | @cu ... ... ... .. ... .. &r2 rs1=%rs1_3 rd=%rs1_3 |
| 104 | @cl_b ... . .. ... .. ... .. &i imm=%uimm_cl_b rs1=%rs1_3 rd=%rs2_3 |
| 105 | @cl_h ... . .. ... .. ... .. &i imm=%uimm_cl_h rs1=%rs1_3 rd=%rs2_3 |
| 106 | @cs_b ... . .. ... .. ... .. &s imm=%uimm_cl_b rs1=%rs1_3 rs2=%rs2_3 |
| 107 | @cs_h ... . .. ... .. ... .. &s imm=%uimm_cl_h rs1=%rs1_3 rs2=%rs2_3 |
| 108 | @cm_pp ... ... ........ .. &cmpp %urlist %spimm |
| 109 | @cm_mv ... ... ... .. ... .. &r2_s rs2=%r2s rs1=%r1s |
| 110 | @cm_jt ... ... ........ .. &cmjt %index |
| 111 | |
| 112 | # *** RV32/64C Standard Extension (Quadrant 0) *** |
| 113 | { |
| 114 | # Opcode of all zeros is illegal; rd != 0, nzuimm == 0 is reserved. |
| 115 | illegal 000 000 000 00 --- 00 |
| 116 | addi 000 ... ... .. ... 00 @c_addi4spn |
| 117 | } |
| 118 | { |
| 119 | lq 001 ... ... .. ... 00 @cl_q |
| 120 | c_fld 001 ... ... .. ... 00 @cl_d |
| 121 | } |
| 122 | lw 010 ... ... .. ... 00 @cl_w |
| 123 | { |
| 124 | sq 101 ... ... .. ... 00 @cs_q |
| 125 | c_fsd 101 ... ... .. ... 00 @cs_d |
| 126 | } |
| 127 | sw 110 ... ... .. ... 00 @cs_w |
| 128 | |
| 129 | # *** RV32C and RV64C specific Standard Extension (Quadrant 0) *** |
| 130 | { |
| 131 | ld 011 ... ... .. ... 00 @cl_d |
| 132 | c_flw 011 ... ... .. ... 00 @cl_w |
| 133 | # *** Zclsd Extension *** |
| 134 | zclsd_ld 011 ... ... .. ... 00 @cl_d |
| 135 | } |
| 136 | { |
| 137 | sd 111 ... ... .. ... 00 @cs_d |
| 138 | c_fsw 111 ... ... .. ... 00 @cs_w |
| 139 | # *** Zclsd Extension *** |
| 140 | zclsd_sd 111 ... ... .. ... 00 @cs_d |
| 141 | } |
| 142 | |
| 143 | # *** RV32/64C Standard Extension (Quadrant 1) *** |
| 144 | addi 000 . ..... ..... 01 @ci |
| 145 | addi 010 . ..... ..... 01 @c_li |
| 146 | { |
| 147 | # c.sspush x1 carving out of zcmops |
| 148 | sspush 011 0 00001 00000 01 &r2_s rs2=1 rs1=0 |
| 149 | # c.sspopchk x5 carving out of zcmops |
| 150 | sspopchk 011 0 00101 00000 01 &r2 rs1=5 rd=0 |
| 151 | c_mop_n 011 0 0 n:3 1 00000 01 |
| 152 | illegal 011 0 ----- 00000 01 # c.addi16sp and c.lui, RES nzimm=0 |
| 153 | addi 011 . 00010 ..... 01 @c_addi16sp |
| 154 | lui 011 . ..... ..... 01 @c_lui |
| 155 | } |
| 156 | srli 100 . 00 ... ..... 01 @c_shift |
| 157 | srai 100 . 01 ... ..... 01 @c_shift |
| 158 | andi 100 . 10 ... ..... 01 @c_andi |
| 159 | sub 100 0 11 ... 00 ... 01 @cs_2 |
| 160 | xor 100 0 11 ... 01 ... 01 @cs_2 |
| 161 | or 100 0 11 ... 10 ... 01 @cs_2 |
| 162 | and 100 0 11 ... 11 ... 01 @cs_2 |
| 163 | jal 101 ........... 01 @cj rd=0 # C.J |
| 164 | beq 110 ... ... ..... 01 @cb_z |
| 165 | bne 111 ... ... ..... 01 @cb_z |
| 166 | |
| 167 | # *** RV64C and RV32C specific Standard Extension (Quadrant 1) *** |
| 168 | { |
| 169 | c64_illegal 001 - 00000 ----- 01 # c.addiw, RES rd=0 |
| 170 | addiw 001 . ..... ..... 01 @ci |
| 171 | jal 001 ........... 01 @cj rd=1 # C.JAL |
| 172 | } |
| 173 | subw 100 1 11 ... 00 ... 01 @cs_2 |
| 174 | addw 100 1 11 ... 01 ... 01 @cs_2 |
| 175 | |
| 176 | # *** RV32/64C Standard Extension (Quadrant 2) *** |
| 177 | slli 000 . ..... ..... 10 @c_shift2 |
| 178 | { |
| 179 | lq 001 ... ... .. ... 10 @c_lqsp |
| 180 | c_fld 001 . ..... ..... 10 @c_ldsp |
| 181 | } |
| 182 | { |
| 183 | illegal 010 - 00000 ----- 10 # c.lwsp, RES rd=0 |
| 184 | lw 010 . ..... ..... 10 @c_lwsp |
| 185 | } |
| 186 | { |
| 187 | illegal 100 0 00000 00000 10 # c.jr, RES rs1=0 |
| 188 | jalr 100 0 ..... 00000 10 @c_jalr rd=0 # C.JR |
| 189 | addi 100 0 ..... ..... 10 @c_mv |
| 190 | } |
| 191 | { |
| 192 | ebreak 100 1 00000 00000 10 |
| 193 | jalr 100 1 ..... 00000 10 @c_jalr rd=1 # C.JALR |
| 194 | add 100 1 ..... ..... 10 @cr |
| 195 | } |
| 196 | { |
| 197 | sq 101 ... ... .. ... 10 @c_sqsp |
| 198 | c_fsd 101 ...... ..... 10 @c_sdsp |
| 199 | |
| 200 | # *** RV64 and RV32 Zcmp/Zcmt Extension *** |
| 201 | [ |
| 202 | cm_push 101 11000 .... .. 10 @cm_pp |
| 203 | cm_pop 101 11010 .... .. 10 @cm_pp |
| 204 | cm_popret 101 11110 .... .. 10 @cm_pp |
| 205 | cm_popretz 101 11100 .... .. 10 @cm_pp |
| 206 | cm_mva01s 101 011 ... 11 ... 10 @cm_mv |
| 207 | cm_mvsa01 101 011 ... 01 ... 10 @cm_mv |
| 208 | |
| 209 | cm_jalt 101 000 ........ 10 @cm_jt |
| 210 | ] |
| 211 | } |
| 212 | sw 110 . ..... ..... 10 @c_swsp |
| 213 | |
| 214 | # *** RV32C and RV64C specific Standard Extension (Quadrant 2) *** |
| 215 | { |
| 216 | c64_illegal 011 - 00000 ----- 10 # c.ldsp, RES rd=0 |
| 217 | ld 011 . ..... ..... 10 @c_ldsp |
| 218 | c_flw 011 . ..... ..... 10 @c_lwsp |
| 219 | # *** Zclsd Extension *** |
| 220 | zclsd_ldsp 011 . ..... ..... 10 @c_ldsp |
| 221 | } |
| 222 | { |
| 223 | sd 111 . ..... ..... 10 @c_sdsp |
| 224 | c_fsw 111 . ..... ..... 10 @c_swsp |
| 225 | # *** Zclsd Extension *** |
| 226 | zclsd_sd 111 . ..... ..... 10 @c_sdsp |
| 227 | } |
| 228 | |
| 229 | # *** RV64 and RV32 Zcb Extension *** |
| 230 | c_zext_b 100 111 ... 11 000 01 @cu |
| 231 | c_sext_b 100 111 ... 11 001 01 @cu |
| 232 | c_zext_h 100 111 ... 11 010 01 @cu |
| 233 | c_sext_h 100 111 ... 11 011 01 @cu |
| 234 | c_zext_w 100 111 ... 11 100 01 @cu |
| 235 | c_not 100 111 ... 11 101 01 @cu |
| 236 | c_mul 100 111 ... 10 ... 01 @cs_2 |
| 237 | c_lbu 100 000 ... .. ... 00 @cl_b |
| 238 | c_lhu 100 001 ... 0. ... 00 @cl_h |
| 239 | c_lh 100 001 ... 1. ... 00 @cl_h |
| 240 | c_sb 100 010 ... .. ... 00 @cs_b |
| 241 | c_sh 100 011 ... 0. ... 00 @cs_h |