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1 #
2 # RISC-V translation routines for the RVXI Base Integer Instruction Set.
3 #
4 # Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
5 # Bastian Koppelmann, kbastian@mail.uni-paderborn.de
6 #
7 # This program is free software; you can redistribute it and/or modify it
8 # under the terms and conditions of the GNU General Public License,
9 # version 2 or later, as published by the Free Software Foundation.
10 #
11 # This program is distributed in the hope it will be useful, but WITHOUT
12 # ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 # FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 # more details.
15 #
16 # You should have received a copy of the GNU General Public License along with
17 # this program. If not, see <http://www.gnu.org/licenses/>.
18
19 # Fields:
20 %rs3 27:5
21 %rs2 20:5
22 %rs1 15:5
23 %rd 7:5
24 %sh5 20:5
25 %sh6 20:6
26
27 %sh7 20:7
28 %csr 20:12
29 %rm 12:3
30 %nf 29:3 !function=ex_plus_1
31
32 # immediates:
33 %imm_i 20:s12
34 %imm_s 25:s7 7:5
35 %imm_b 31:s1 7:1 25:6 8:4 !function=ex_shift_1
36 %imm_j 31:s1 12:8 20:1 21:10 !function=ex_shift_1
37 %imm_u 12:s20 !function=ex_shift_12
38 %imm_bs 30:2 !function=ex_shift_3
39 %imm_rnum 20:4
40 %imm_z6 26:1 15:5
41 %imm_mop5 30:1 26:2 20:2
42 %imm_mop3 30:1 26:2
43
44 # Argument sets:
45 &empty
46 &b imm rs2 rs1
47 &i imm rs1 rd
48 &j imm rd
49 &r rd rs1 rs2
50 &r2 rd rs1
51 &r2_s rs1 rs2
52 &s imm rs1 rs2
53 &u imm rd
54 &shift shamt rs1 rd
55 &atomic aq rl rs2 rs1 rd
56 &rmrr vm rd rs1 rs2
57 &rmr vm rd rs2
58 &r2nfvm vm rd rs1 nf
59 &rnfvm vm rd rs1 rs2 nf
60 &k_aes shamt rs2 rs1 rd
61 &mop5 imm rd rs1
62 &mop3 imm rd rs1 rs2
63
64 # Formats 32:
65 @r ....... ..... ..... ... ..... ....... &r %rs2 %rs1 %rd
66 @i ............ ..... ... ..... ....... &i imm=%imm_i %rs1 %rd
67 @b ....... ..... ..... ... ..... ....... &b imm=%imm_b %rs2 %rs1
68 @s ....... ..... ..... ... ..... ....... &s imm=%imm_s %rs2 %rs1
69 @u .................... ..... ....... &u imm=%imm_u %rd
70 @j .................... ..... ....... &j imm=%imm_j %rd
71
72 @sh ...... ...... ..... ... ..... ....... &shift shamt=%sh7 %rs1 %rd
73 @csr ............ ..... ... ..... ....... %csr %rs1 %rd
74
75 @atom_ld ..... aq:1 rl:1 ..... ........ ..... ....... &atomic rs2=0 %rs1 %rd
76 @atom_st ..... aq:1 rl:1 ..... ........ ..... ....... &atomic %rs2 %rs1 %rd
77
78 @r4_rm ..... .. ..... ..... ... ..... ....... %rs3 %rs2 %rs1 %rm %rd
79 @r_rm ....... ..... ..... ... ..... ....... %rs2 %rs1 %rm %rd
80 @r2_rm ....... ..... ..... ... ..... ....... %rs1 %rm %rd
81 @r2 ....... ..... ..... ... ..... ....... &r2 %rs1 %rd
82 @r2_vm_1 ...... . ..... ..... ... ..... ....... &rmr vm=1 %rs2 %rd
83 @r2_nfvm ... ... vm:1 ..... ..... ... ..... ....... &r2nfvm %nf %rs1 %rd
84 @r2_vm ...... vm:1 ..... ..... ... ..... ....... &rmr %rs2 %rd
85 @r1_vm ...... vm:1 ..... ..... ... ..... ....... %rd
86 @r_nfvm ... ... vm:1 ..... ..... ... ..... ....... &rnfvm %nf %rs2 %rs1 %rd
87 @r2rd ....... ..... ..... ... ..... ....... %rs2 %rd
88 @r_vm ...... vm:1 ..... ..... ... ..... ....... &rmrr %rs2 %rs1 %rd
89 @r_vm_1 ...... . ..... ..... ... ..... ....... &rmrr vm=1 %rs2 %rs1 %rd
90 @r_vm_0 ...... . ..... ..... ... ..... ....... &rmrr vm=0 %rs2 %rs1 %rd
91 @r2_zimm6 ..... . vm:1 ..... ..... ... ..... ....... &rmrr %rs2 rs1=%imm_z6 %rd
92 @r2_zimm11 . zimm:11 ..... ... ..... ....... %rs1 %rd
93 @r2_zimm10 .. zimm:10 ..... ... ..... ....... %rs1 %rd
94 @r2_s ....... ..... ..... ... ..... ....... %rs2 %rs1
95
96 @hfence_gvma ....... ..... ..... ... ..... ....... %rs2 %rs1
97 @hfence_vvma ....... ..... ..... ... ..... ....... %rs2 %rs1
98
99 @sfence_vma ....... ..... ..... ... ..... ....... %rs2 %rs1
100 @sfence_vm ....... ..... ..... ... ..... ....... %rs1
101
102 @k_aes .. ..... ..... ..... ... ..... ....... &k_aes shamt=%imm_bs %rs2 %rs1 %rd
103 @i_aes .. ..... ..... ..... ... ..... ....... &i imm=%imm_rnum %rs1 %rd
104
105 @mop5 . . .. .. .... .. ..... ... ..... ....... &mop5 imm=%imm_mop5 %rd %rs1
106 @mop3 . . .. .. . ..... ..... ... ..... ....... &mop3 imm=%imm_mop3 %rd %rs1 %rs2
107
108 # Formats 64:
109 @sh5 ....... ..... ..... ... ..... ....... &shift shamt=%sh5 %rs1 %rd
110
111 # Formats 128:
112 @sh6 ...... ...... ..... ... ..... ....... &shift shamt=%sh6 %rs1 %rd
113
114 # *** Privileged Instructions ***
115 ecall 000000000000 00000 000 00000 1110011
116 ebreak 000000000001 00000 000 00000 1110011
117 sctrclr 000100000100 00000 000 00000 1110011
118 uret 0000000 00010 00000 000 00000 1110011
119 sret 0001000 00010 00000 000 00000 1110011
120 mret 0011000 00010 00000 000 00000 1110011
121 wfi 0001000 00101 00000 000 00000 1110011
122 sfence_vma 0001001 ..... ..... 000 00000 1110011 @sfence_vma
123
124 # *** NMI ***
125 mnret 0111000 00010 00000 000 00000 1110011
126
127 # *** RV32I Base Instruction Set ***
128 lui .................... ..... 0110111 @u
129 {
130 lpad label:20 00000 0010111
131 auipc .................... ..... 0010111 @u
132 }
133 jal .................... ..... 1101111 @j
134 jalr ............ ..... 000 ..... 1100111 @i
135 beq ....... ..... ..... 000 ..... 1100011 @b
136 bne ....... ..... ..... 001 ..... 1100011 @b
137 blt ....... ..... ..... 100 ..... 1100011 @b
138 bge ....... ..... ..... 101 ..... 1100011 @b
139 bltu ....... ..... ..... 110 ..... 1100011 @b
140 bgeu ....... ..... ..... 111 ..... 1100011 @b
141 lb ............ ..... 000 ..... 0000011 @i
142 lh ............ ..... 001 ..... 0000011 @i
143 lw ............ ..... 010 ..... 0000011 @i
144 lbu ............ ..... 100 ..... 0000011 @i
145 lhu ............ ..... 101 ..... 0000011 @i
146 sb ....... ..... ..... 000 ..... 0100011 @s
147 sh ....... ..... ..... 001 ..... 0100011 @s
148 sw ....... ..... ..... 010 ..... 0100011 @s
149 addi ............ ..... 000 ..... 0010011 @i
150 slti ............ ..... 010 ..... 0010011 @i
151 sltiu ............ ..... 011 ..... 0010011 @i
152 xori ............ ..... 100 ..... 0010011 @i
153 # cbo.prefetch_{i,r,m} instructions are ori with rd=x0 and not decoded.
154 ori ............ ..... 110 ..... 0010011 @i
155 andi ............ ..... 111 ..... 0010011 @i
156 slli 00000. ...... ..... 001 ..... 0010011 @sh
157 srli 00000. ...... ..... 101 ..... 0010011 @sh
158 srai 01000. ...... ..... 101 ..... 0010011 @sh
159 add 0000000 ..... ..... 000 ..... 0110011 @r
160 sub 0100000 ..... ..... 000 ..... 0110011 @r
161 sll 0000000 ..... ..... 001 ..... 0110011 @r
162 slt 0000000 ..... ..... 010 ..... 0110011 @r
163 sltu 0000000 ..... ..... 011 ..... 0110011 @r
164 xor 0000000 ..... ..... 100 ..... 0110011 @r
165 srl 0000000 ..... ..... 101 ..... 0110011 @r
166 sra 0100000 ..... ..... 101 ..... 0110011 @r
167 or 0000000 ..... ..... 110 ..... 0110011 @r
168 and 0000000 ..... ..... 111 ..... 0110011 @r
169
170 {
171 pause 0000 0001 0000 00000 000 00000 0001111
172 fence ---- pred:4 succ:4 ----- 000 ----- 0001111
173 }
174
175 fence_i ---- ---- ---- ----- 001 ----- 0001111
176 csrrw ............ ..... 001 ..... 1110011 @csr
177 csrrs ............ ..... 010 ..... 1110011 @csr
178 csrrc ............ ..... 011 ..... 1110011 @csr
179 csrrwi ............ ..... 101 ..... 1110011 @csr
180 csrrsi ............ ..... 110 ..... 1110011 @csr
181 csrrci ............ ..... 111 ..... 1110011 @csr
182
183 # *** RV64I Base Instruction Set (in addition to RV32I) ***
184 lwu ............ ..... 110 ..... 0000011 @i
185 {
186 ld ............ ..... 011 ..... 0000011 @i
187 # *** Zilsd instructions ***
188 zilsd_ld ............ ..... 011 ..... 0000011 @i
189 }
190 {
191 sd ....... ..... ..... 011 ..... 0100011 @s
192 # *** Zilsd instructions ***
193 zilsd_sd ....... ..... ..... 011 ..... 0100011 @s
194 }
195 addiw ............ ..... 000 ..... 0011011 @i
196 slliw 0000000 ..... ..... 001 ..... 0011011 @sh5
197 srliw 0000000 ..... ..... 101 ..... 0011011 @sh5
198 sraiw 0100000 ..... ..... 101 ..... 0011011 @sh5
199 addw 0000000 ..... ..... 000 ..... 0111011 @r
200 subw 0100000 ..... ..... 000 ..... 0111011 @r
201 sllw 0000000 ..... ..... 001 ..... 0111011 @r
202 srlw 0000000 ..... ..... 101 ..... 0111011 @r
203 sraw 0100000 ..... ..... 101 ..... 0111011 @r
204
205 # *** RV128I Base Instruction Set (in addition to RV64I) ***
206 ldu ............ ..... 111 ..... 0000011 @i
207 {
208 [
209 # *** RV32 Zicbom Standard Extension ***
210 cbo_inval 0000000 00000 ..... 010 00000 0001111 @sfence_vm
211 cbo_clean 0000000 00001 ..... 010 00000 0001111 @sfence_vm
212 cbo_flush 0000000 00010 ..... 010 00000 0001111 @sfence_vm
213
214 # *** RV32 Zicboz Standard Extension ***
215 cbo_zero 0000000 00100 ..... 010 00000 0001111 @sfence_vm
216 ]
217
218 # *** RVI128 lq ***
219 lq ............ ..... 010 ..... 0001111 @i
220 }
221 sq ............ ..... 100 ..... 0100011 @s
222 addid ............ ..... 000 ..... 1011011 @i
223 sllid 000000 ...... ..... 001 ..... 1011011 @sh6
224 srlid 000000 ...... ..... 101 ..... 1011011 @sh6
225 sraid 010000 ...... ..... 101 ..... 1011011 @sh6
226 addd 0000000 ..... ..... 000 ..... 1111011 @r
227 subd 0100000 ..... ..... 000 ..... 1111011 @r
228 slld 0000000 ..... ..... 001 ..... 1111011 @r
229 srld 0000000 ..... ..... 101 ..... 1111011 @r
230 srad 0100000 ..... ..... 101 ..... 1111011 @r
231
232 # *** RV32M Standard Extension ***
233 mul 0000001 ..... ..... 000 ..... 0110011 @r
234 mulh 0000001 ..... ..... 001 ..... 0110011 @r
235 mulhsu 0000001 ..... ..... 010 ..... 0110011 @r
236 mulhu 0000001 ..... ..... 011 ..... 0110011 @r
237 div 0000001 ..... ..... 100 ..... 0110011 @r
238 divu 0000001 ..... ..... 101 ..... 0110011 @r
239 rem 0000001 ..... ..... 110 ..... 0110011 @r
240 remu 0000001 ..... ..... 111 ..... 0110011 @r
241
242 # *** RV64M Standard Extension (in addition to RV32M) ***
243 mulw 0000001 ..... ..... 000 ..... 0111011 @r
244 divw 0000001 ..... ..... 100 ..... 0111011 @r
245 divuw 0000001 ..... ..... 101 ..... 0111011 @r
246 remw 0000001 ..... ..... 110 ..... 0111011 @r
247 remuw 0000001 ..... ..... 111 ..... 0111011 @r
248
249 # *** RV128M Standard Extension (in addition to RV64M) ***
250 muld 0000001 ..... ..... 000 ..... 1111011 @r
251 divd 0000001 ..... ..... 100 ..... 1111011 @r
252 divud 0000001 ..... ..... 101 ..... 1111011 @r
253 remd 0000001 ..... ..... 110 ..... 1111011 @r
254 remud 0000001 ..... ..... 111 ..... 1111011 @r
255
256 # *** RV32A Standard Extension ***
257 lr_w 00010 . . 00000 ..... 010 ..... 0101111 @atom_ld
258 sc_w 00011 . . ..... ..... 010 ..... 0101111 @atom_st
259 amoswap_w 00001 . . ..... ..... 010 ..... 0101111 @atom_st
260 ssamoswap_w 01001 . . ..... ..... 010 ..... 0101111 @atom_st
261 amoadd_w 00000 . . ..... ..... 010 ..... 0101111 @atom_st
262 amoxor_w 00100 . . ..... ..... 010 ..... 0101111 @atom_st
263 amoand_w 01100 . . ..... ..... 010 ..... 0101111 @atom_st
264 amoor_w 01000 . . ..... ..... 010 ..... 0101111 @atom_st
265 amomin_w 10000 . . ..... ..... 010 ..... 0101111 @atom_st
266 amomax_w 10100 . . ..... ..... 010 ..... 0101111 @atom_st
267 amominu_w 11000 . . ..... ..... 010 ..... 0101111 @atom_st
268 amomaxu_w 11100 . . ..... ..... 010 ..... 0101111 @atom_st
269
270 # *** RV64A Standard Extension (in addition to RV32A) ***
271 lr_d 00010 . . 00000 ..... 011 ..... 0101111 @atom_ld
272 sc_d 00011 . . ..... ..... 011 ..... 0101111 @atom_st
273 amoswap_d 00001 . . ..... ..... 011 ..... 0101111 @atom_st
274 ssamoswap_d 01001 . . ..... ..... 011 ..... 0101111 @atom_st
275 amoadd_d 00000 . . ..... ..... 011 ..... 0101111 @atom_st
276 amoxor_d 00100 . . ..... ..... 011 ..... 0101111 @atom_st
277 amoand_d 01100 . . ..... ..... 011 ..... 0101111 @atom_st
278 amoor_d 01000 . . ..... ..... 011 ..... 0101111 @atom_st
279 amomin_d 10000 . . ..... ..... 011 ..... 0101111 @atom_st
280 amomax_d 10100 . . ..... ..... 011 ..... 0101111 @atom_st
281 amominu_d 11000 . . ..... ..... 011 ..... 0101111 @atom_st
282 amomaxu_d 11100 . . ..... ..... 011 ..... 0101111 @atom_st
283
284 # *** RV32F Standard Extension ***
285 flw ............ ..... 010 ..... 0000111 @i
286 fsw ....... ..... ..... 010 ..... 0100111 @s
287 fmadd_s ..... 00 ..... ..... ... ..... 1000011 @r4_rm
288 fmsub_s ..... 00 ..... ..... ... ..... 1000111 @r4_rm
289 fnmsub_s ..... 00 ..... ..... ... ..... 1001011 @r4_rm
290 fnmadd_s ..... 00 ..... ..... ... ..... 1001111 @r4_rm
291 fadd_s 0000000 ..... ..... ... ..... 1010011 @r_rm
292 fsub_s 0000100 ..... ..... ... ..... 1010011 @r_rm
293 fmul_s 0001000 ..... ..... ... ..... 1010011 @r_rm
294 fdiv_s 0001100 ..... ..... ... ..... 1010011 @r_rm
295 fsqrt_s 0101100 00000 ..... ... ..... 1010011 @r2_rm
296 fsgnj_s 0010000 ..... ..... 000 ..... 1010011 @r
297 fsgnjn_s 0010000 ..... ..... 001 ..... 1010011 @r
298 fsgnjx_s 0010000 ..... ..... 010 ..... 1010011 @r
299 fmin_s 0010100 ..... ..... 000 ..... 1010011 @r
300 fmax_s 0010100 ..... ..... 001 ..... 1010011 @r
301 fcvt_w_s 1100000 00000 ..... ... ..... 1010011 @r2_rm
302 fcvt_wu_s 1100000 00001 ..... ... ..... 1010011 @r2_rm
303 fmv_x_w 1110000 00000 ..... 000 ..... 1010011 @r2
304 feq_s 1010000 ..... ..... 010 ..... 1010011 @r
305 flt_s 1010000 ..... ..... 001 ..... 1010011 @r
306 fle_s 1010000 ..... ..... 000 ..... 1010011 @r
307 fclass_s 1110000 00000 ..... 001 ..... 1010011 @r2
308 fcvt_s_w 1101000 00000 ..... ... ..... 1010011 @r2_rm
309 fcvt_s_wu 1101000 00001 ..... ... ..... 1010011 @r2_rm
310 fmv_w_x 1111000 00000 ..... 000 ..... 1010011 @r2
311
312 # *** RV64F Standard Extension (in addition to RV32F) ***
313 fcvt_l_s 1100000 00010 ..... ... ..... 1010011 @r2_rm
314 fcvt_lu_s 1100000 00011 ..... ... ..... 1010011 @r2_rm
315 fcvt_s_l 1101000 00010 ..... ... ..... 1010011 @r2_rm
316 fcvt_s_lu 1101000 00011 ..... ... ..... 1010011 @r2_rm
317
318 # *** RV32D Standard Extension ***
319 fld ............ ..... 011 ..... 0000111 @i
320 fsd ....... ..... ..... 011 ..... 0100111 @s
321 fmadd_d ..... 01 ..... ..... ... ..... 1000011 @r4_rm
322 fmsub_d ..... 01 ..... ..... ... ..... 1000111 @r4_rm
323 fnmsub_d ..... 01 ..... ..... ... ..... 1001011 @r4_rm
324 fnmadd_d ..... 01 ..... ..... ... ..... 1001111 @r4_rm
325 fadd_d 0000001 ..... ..... ... ..... 1010011 @r_rm
326 fsub_d 0000101 ..... ..... ... ..... 1010011 @r_rm
327 fmul_d 0001001 ..... ..... ... ..... 1010011 @r_rm
328 fdiv_d 0001101 ..... ..... ... ..... 1010011 @r_rm
329 fsqrt_d 0101101 00000 ..... ... ..... 1010011 @r2_rm
330 fsgnj_d 0010001 ..... ..... 000 ..... 1010011 @r
331 fsgnjn_d 0010001 ..... ..... 001 ..... 1010011 @r
332 fsgnjx_d 0010001 ..... ..... 010 ..... 1010011 @r
333 fmin_d 0010101 ..... ..... 000 ..... 1010011 @r
334 fmax_d 0010101 ..... ..... 001 ..... 1010011 @r
335 fcvt_s_d 0100000 00001 ..... ... ..... 1010011 @r2_rm
336 fcvt_d_s 0100001 00000 ..... ... ..... 1010011 @r2_rm
337 feq_d 1010001 ..... ..... 010 ..... 1010011 @r
338 flt_d 1010001 ..... ..... 001 ..... 1010011 @r
339 fle_d 1010001 ..... ..... 000 ..... 1010011 @r
340 fclass_d 1110001 00000 ..... 001 ..... 1010011 @r2
341 fcvt_w_d 1100001 00000 ..... ... ..... 1010011 @r2_rm
342 fcvt_wu_d 1100001 00001 ..... ... ..... 1010011 @r2_rm
343 fcvt_d_w 1101001 00000 ..... ... ..... 1010011 @r2_rm
344 fcvt_d_wu 1101001 00001 ..... ... ..... 1010011 @r2_rm
345
346 # *** RV64D Standard Extension (in addition to RV32D) ***
347 fcvt_l_d 1100001 00010 ..... ... ..... 1010011 @r2_rm
348 fcvt_lu_d 1100001 00011 ..... ... ..... 1010011 @r2_rm
349 fmv_x_d 1110001 00000 ..... 000 ..... 1010011 @r2
350 fcvt_d_l 1101001 00010 ..... ... ..... 1010011 @r2_rm
351 fcvt_d_lu 1101001 00011 ..... ... ..... 1010011 @r2_rm
352 fmv_d_x 1111001 00000 ..... 000 ..... 1010011 @r2
353
354 # *** RV32H Base Instruction Set ***
355 hlv_b 0110000 00000 ..... 100 ..... 1110011 @r2
356 hlv_bu 0110000 00001 ..... 100 ..... 1110011 @r2
357 hlv_h 0110010 00000 ..... 100 ..... 1110011 @r2
358 hlv_hu 0110010 00001 ..... 100 ..... 1110011 @r2
359 hlvx_hu 0110010 00011 ..... 100 ..... 1110011 @r2
360 hlv_w 0110100 00000 ..... 100 ..... 1110011 @r2
361 hlvx_wu 0110100 00011 ..... 100 ..... 1110011 @r2
362 hsv_b 0110001 ..... ..... 100 00000 1110011 @r2_s
363 hsv_h 0110011 ..... ..... 100 00000 1110011 @r2_s
364 hsv_w 0110101 ..... ..... 100 00000 1110011 @r2_s
365 hfence_gvma 0110001 ..... ..... 000 00000 1110011 @hfence_gvma
366 hfence_vvma 0010001 ..... ..... 000 00000 1110011 @hfence_vvma
367
368 # *** RV64H Base Instruction Set ***
369 hlv_wu 0110100 00001 ..... 100 ..... 1110011 @r2
370 hlv_d 0110110 00000 ..... 100 ..... 1110011 @r2
371 hsv_d 0110111 ..... ..... 100 00000 1110011 @r2_s
372
373 # *** Vector loads and stores are encoded within LOADFP/STORE-FP ***
374 # Vector unit-stride load/store insns.
375 vle8_v ... 000 . 00000 ..... 000 ..... 0000111 @r2_nfvm
376 vle16_v ... 000 . 00000 ..... 101 ..... 0000111 @r2_nfvm
377 vle32_v ... 000 . 00000 ..... 110 ..... 0000111 @r2_nfvm
378 vle64_v ... 000 . 00000 ..... 111 ..... 0000111 @r2_nfvm
379 vse8_v ... 000 . 00000 ..... 000 ..... 0100111 @r2_nfvm
380 vse16_v ... 000 . 00000 ..... 101 ..... 0100111 @r2_nfvm
381 vse32_v ... 000 . 00000 ..... 110 ..... 0100111 @r2_nfvm
382 vse64_v ... 000 . 00000 ..... 111 ..... 0100111 @r2_nfvm
383
384 # Vector unit-stride mask load/store insns.
385 vlm_v 000 000 1 01011 ..... 000 ..... 0000111 @r2
386 vsm_v 000 000 1 01011 ..... 000 ..... 0100111 @r2
387
388 # Vector strided insns.
389 vlse8_v ... 010 . ..... ..... 000 ..... 0000111 @r_nfvm
390 vlse16_v ... 010 . ..... ..... 101 ..... 0000111 @r_nfvm
391 vlse32_v ... 010 . ..... ..... 110 ..... 0000111 @r_nfvm
392 vlse64_v ... 010 . ..... ..... 111 ..... 0000111 @r_nfvm
393 vsse8_v ... 010 . ..... ..... 000 ..... 0100111 @r_nfvm
394 vsse16_v ... 010 . ..... ..... 101 ..... 0100111 @r_nfvm
395 vsse32_v ... 010 . ..... ..... 110 ..... 0100111 @r_nfvm
396 vsse64_v ... 010 . ..... ..... 111 ..... 0100111 @r_nfvm
397
398 # Vector ordered-indexed and unordered-indexed load insns.
399 vlxei8_v ... 0-1 . ..... ..... 000 ..... 0000111 @r_nfvm
400 vlxei16_v ... 0-1 . ..... ..... 101 ..... 0000111 @r_nfvm
401 vlxei32_v ... 0-1 . ..... ..... 110 ..... 0000111 @r_nfvm
402 vlxei64_v ... 0-1 . ..... ..... 111 ..... 0000111 @r_nfvm
403
404 # Vector ordered-indexed and unordered-indexed store insns.
405 vsxei8_v ... 0-1 . ..... ..... 000 ..... 0100111 @r_nfvm
406 vsxei16_v ... 0-1 . ..... ..... 101 ..... 0100111 @r_nfvm
407 vsxei32_v ... 0-1 . ..... ..... 110 ..... 0100111 @r_nfvm
408 vsxei64_v ... 0-1 . ..... ..... 111 ..... 0100111 @r_nfvm
409
410 # Vector unit-stride fault-only-first load insns.
411 vle8ff_v ... 000 . 10000 ..... 000 ..... 0000111 @r2_nfvm
412 vle16ff_v ... 000 . 10000 ..... 101 ..... 0000111 @r2_nfvm
413 vle32ff_v ... 000 . 10000 ..... 110 ..... 0000111 @r2_nfvm
414 vle64ff_v ... 000 . 10000 ..... 111 ..... 0000111 @r2_nfvm
415
416 # Vector whole register insns
417 vl1re8_v 000 000 1 01000 ..... 000 ..... 0000111 @r2
418 vl1re16_v 000 000 1 01000 ..... 101 ..... 0000111 @r2
419 vl1re32_v 000 000 1 01000 ..... 110 ..... 0000111 @r2
420 vl1re64_v 000 000 1 01000 ..... 111 ..... 0000111 @r2
421 vl2re8_v 001 000 1 01000 ..... 000 ..... 0000111 @r2
422 vl2re16_v 001 000 1 01000 ..... 101 ..... 0000111 @r2
423 vl2re32_v 001 000 1 01000 ..... 110 ..... 0000111 @r2
424 vl2re64_v 001 000 1 01000 ..... 111 ..... 0000111 @r2
425 vl4re8_v 011 000 1 01000 ..... 000 ..... 0000111 @r2
426 vl4re16_v 011 000 1 01000 ..... 101 ..... 0000111 @r2
427 vl4re32_v 011 000 1 01000 ..... 110 ..... 0000111 @r2
428 vl4re64_v 011 000 1 01000 ..... 111 ..... 0000111 @r2
429 vl8re8_v 111 000 1 01000 ..... 000 ..... 0000111 @r2
430 vl8re16_v 111 000 1 01000 ..... 101 ..... 0000111 @r2
431 vl8re32_v 111 000 1 01000 ..... 110 ..... 0000111 @r2
432 vl8re64_v 111 000 1 01000 ..... 111 ..... 0000111 @r2
433 vs1r_v 000 000 1 01000 ..... 000 ..... 0100111 @r2
434 vs2r_v 001 000 1 01000 ..... 000 ..... 0100111 @r2
435 vs4r_v 011 000 1 01000 ..... 000 ..... 0100111 @r2
436 vs8r_v 111 000 1 01000 ..... 000 ..... 0100111 @r2
437
438 # *** new major opcode OP-V ***
439 vadd_vv 000000 . ..... ..... 000 ..... 1010111 @r_vm
440 vadd_vx 000000 . ..... ..... 100 ..... 1010111 @r_vm
441 vadd_vi 000000 . ..... ..... 011 ..... 1010111 @r_vm
442 vsub_vv 000010 . ..... ..... 000 ..... 1010111 @r_vm
443 vsub_vx 000010 . ..... ..... 100 ..... 1010111 @r_vm
444 vrsub_vx 000011 . ..... ..... 100 ..... 1010111 @r_vm
445 vrsub_vi 000011 . ..... ..... 011 ..... 1010111 @r_vm
446 vwaddu_vv 110000 . ..... ..... 010 ..... 1010111 @r_vm
447 vwaddu_vx 110000 . ..... ..... 110 ..... 1010111 @r_vm
448 vwadd_vv 110001 . ..... ..... 010 ..... 1010111 @r_vm
449 vwadd_vx 110001 . ..... ..... 110 ..... 1010111 @r_vm
450 vwsubu_vv 110010 . ..... ..... 010 ..... 1010111 @r_vm
451 vwsubu_vx 110010 . ..... ..... 110 ..... 1010111 @r_vm
452 vwsub_vv 110011 . ..... ..... 010 ..... 1010111 @r_vm
453 vwsub_vx 110011 . ..... ..... 110 ..... 1010111 @r_vm
454 vwaddu_wv 110100 . ..... ..... 010 ..... 1010111 @r_vm
455 vwaddu_wx 110100 . ..... ..... 110 ..... 1010111 @r_vm
456 vwadd_wv 110101 . ..... ..... 010 ..... 1010111 @r_vm
457 vwadd_wx 110101 . ..... ..... 110 ..... 1010111 @r_vm
458 vwsubu_wv 110110 . ..... ..... 010 ..... 1010111 @r_vm
459 vwsubu_wx 110110 . ..... ..... 110 ..... 1010111 @r_vm
460 vwsub_wv 110111 . ..... ..... 010 ..... 1010111 @r_vm
461 vwsub_wx 110111 . ..... ..... 110 ..... 1010111 @r_vm
462 vadc_vvm 010000 0 ..... ..... 000 ..... 1010111 @r_vm_1
463 vadc_vxm 010000 0 ..... ..... 100 ..... 1010111 @r_vm_1
464 vadc_vim 010000 0 ..... ..... 011 ..... 1010111 @r_vm_1
465 vmadc_vvm 010001 . ..... ..... 000 ..... 1010111 @r_vm
466 vmadc_vxm 010001 . ..... ..... 100 ..... 1010111 @r_vm
467 vmadc_vim 010001 . ..... ..... 011 ..... 1010111 @r_vm
468 vsbc_vvm 010010 0 ..... ..... 000 ..... 1010111 @r_vm_1
469 vsbc_vxm 010010 0 ..... ..... 100 ..... 1010111 @r_vm_1
470 vmsbc_vvm 010011 . ..... ..... 000 ..... 1010111 @r_vm
471 vmsbc_vxm 010011 . ..... ..... 100 ..... 1010111 @r_vm
472 vand_vv 001001 . ..... ..... 000 ..... 1010111 @r_vm
473 vand_vx 001001 . ..... ..... 100 ..... 1010111 @r_vm
474 vand_vi 001001 . ..... ..... 011 ..... 1010111 @r_vm
475 vor_vv 001010 . ..... ..... 000 ..... 1010111 @r_vm
476 vor_vx 001010 . ..... ..... 100 ..... 1010111 @r_vm
477 vor_vi 001010 . ..... ..... 011 ..... 1010111 @r_vm
478 vxor_vv 001011 . ..... ..... 000 ..... 1010111 @r_vm
479 vxor_vx 001011 . ..... ..... 100 ..... 1010111 @r_vm
480 vxor_vi 001011 . ..... ..... 011 ..... 1010111 @r_vm
481 vsll_vv 100101 . ..... ..... 000 ..... 1010111 @r_vm
482 vsll_vx 100101 . ..... ..... 100 ..... 1010111 @r_vm
483 vsll_vi 100101 . ..... ..... 011 ..... 1010111 @r_vm
484 vsrl_vv 101000 . ..... ..... 000 ..... 1010111 @r_vm
485 vsrl_vx 101000 . ..... ..... 100 ..... 1010111 @r_vm
486 vsrl_vi 101000 . ..... ..... 011 ..... 1010111 @r_vm
487 vsra_vv 101001 . ..... ..... 000 ..... 1010111 @r_vm
488 vsra_vx 101001 . ..... ..... 100 ..... 1010111 @r_vm
489 vsra_vi 101001 . ..... ..... 011 ..... 1010111 @r_vm
490 vnsrl_wv 101100 . ..... ..... 000 ..... 1010111 @r_vm
491 vnsrl_wx 101100 . ..... ..... 100 ..... 1010111 @r_vm
492 vnsrl_wi 101100 . ..... ..... 011 ..... 1010111 @r_vm
493 vnsra_wv 101101 . ..... ..... 000 ..... 1010111 @r_vm
494 vnsra_wx 101101 . ..... ..... 100 ..... 1010111 @r_vm
495 vnsra_wi 101101 . ..... ..... 011 ..... 1010111 @r_vm
496 vmseq_vv 011000 . ..... ..... 000 ..... 1010111 @r_vm
497 vmseq_vx 011000 . ..... ..... 100 ..... 1010111 @r_vm
498 vmseq_vi 011000 . ..... ..... 011 ..... 1010111 @r_vm
499 vmsne_vv 011001 . ..... ..... 000 ..... 1010111 @r_vm
500 vmsne_vx 011001 . ..... ..... 100 ..... 1010111 @r_vm
501 vmsne_vi 011001 . ..... ..... 011 ..... 1010111 @r_vm
502 vmsltu_vv 011010 . ..... ..... 000 ..... 1010111 @r_vm
503 vmsltu_vx 011010 . ..... ..... 100 ..... 1010111 @r_vm
504 vmslt_vv 011011 . ..... ..... 000 ..... 1010111 @r_vm
505 vmslt_vx 011011 . ..... ..... 100 ..... 1010111 @r_vm
506 vmsleu_vv 011100 . ..... ..... 000 ..... 1010111 @r_vm
507 vmsleu_vx 011100 . ..... ..... 100 ..... 1010111 @r_vm
508 vmsleu_vi 011100 . ..... ..... 011 ..... 1010111 @r_vm
509 vmsle_vv 011101 . ..... ..... 000 ..... 1010111 @r_vm
510 vmsle_vx 011101 . ..... ..... 100 ..... 1010111 @r_vm
511 vmsle_vi 011101 . ..... ..... 011 ..... 1010111 @r_vm
512 vmsgtu_vx 011110 . ..... ..... 100 ..... 1010111 @r_vm
513 vmsgtu_vi 011110 . ..... ..... 011 ..... 1010111 @r_vm
514 vmsgt_vx 011111 . ..... ..... 100 ..... 1010111 @r_vm
515 vmsgt_vi 011111 . ..... ..... 011 ..... 1010111 @r_vm
516 vminu_vv 000100 . ..... ..... 000 ..... 1010111 @r_vm
517 vminu_vx 000100 . ..... ..... 100 ..... 1010111 @r_vm
518 vmin_vv 000101 . ..... ..... 000 ..... 1010111 @r_vm
519 vmin_vx 000101 . ..... ..... 100 ..... 1010111 @r_vm
520 vmaxu_vv 000110 . ..... ..... 000 ..... 1010111 @r_vm
521 vmaxu_vx 000110 . ..... ..... 100 ..... 1010111 @r_vm
522 vmax_vv 000111 . ..... ..... 000 ..... 1010111 @r_vm
523 vmax_vx 000111 . ..... ..... 100 ..... 1010111 @r_vm
524 vmul_vv 100101 . ..... ..... 010 ..... 1010111 @r_vm
525 vmul_vx 100101 . ..... ..... 110 ..... 1010111 @r_vm
526 vmulh_vv 100111 . ..... ..... 010 ..... 1010111 @r_vm
527 vmulh_vx 100111 . ..... ..... 110 ..... 1010111 @r_vm
528 vmulhu_vv 100100 . ..... ..... 010 ..... 1010111 @r_vm
529 vmulhu_vx 100100 . ..... ..... 110 ..... 1010111 @r_vm
530 vmulhsu_vv 100110 . ..... ..... 010 ..... 1010111 @r_vm
531 vmulhsu_vx 100110 . ..... ..... 110 ..... 1010111 @r_vm
532 vdivu_vv 100000 . ..... ..... 010 ..... 1010111 @r_vm
533 vdivu_vx 100000 . ..... ..... 110 ..... 1010111 @r_vm
534 vdiv_vv 100001 . ..... ..... 010 ..... 1010111 @r_vm
535 vdiv_vx 100001 . ..... ..... 110 ..... 1010111 @r_vm
536 vremu_vv 100010 . ..... ..... 010 ..... 1010111 @r_vm
537 vremu_vx 100010 . ..... ..... 110 ..... 1010111 @r_vm
538 vrem_vv 100011 . ..... ..... 010 ..... 1010111 @r_vm
539 vrem_vx 100011 . ..... ..... 110 ..... 1010111 @r_vm
540 vwmulu_vv 111000 . ..... ..... 010 ..... 1010111 @r_vm
541 vwmulu_vx 111000 . ..... ..... 110 ..... 1010111 @r_vm
542 vwmulsu_vv 111010 . ..... ..... 010 ..... 1010111 @r_vm
543 vwmulsu_vx 111010 . ..... ..... 110 ..... 1010111 @r_vm
544 vwmul_vv 111011 . ..... ..... 010 ..... 1010111 @r_vm
545 vwmul_vx 111011 . ..... ..... 110 ..... 1010111 @r_vm
546 vmacc_vv 101101 . ..... ..... 010 ..... 1010111 @r_vm
547 vmacc_vx 101101 . ..... ..... 110 ..... 1010111 @r_vm
548 vnmsac_vv 101111 . ..... ..... 010 ..... 1010111 @r_vm
549 vnmsac_vx 101111 . ..... ..... 110 ..... 1010111 @r_vm
550 vmadd_vv 101001 . ..... ..... 010 ..... 1010111 @r_vm
551 vmadd_vx 101001 . ..... ..... 110 ..... 1010111 @r_vm
552 vnmsub_vv 101011 . ..... ..... 010 ..... 1010111 @r_vm
553 vnmsub_vx 101011 . ..... ..... 110 ..... 1010111 @r_vm
554 vwmaccu_vv 111100 . ..... ..... 010 ..... 1010111 @r_vm
555 vwmaccu_vx 111100 . ..... ..... 110 ..... 1010111 @r_vm
556 vwmacc_vv 111101 . ..... ..... 010 ..... 1010111 @r_vm
557 vwmacc_vx 111101 . ..... ..... 110 ..... 1010111 @r_vm
558 vwmaccsu_vv 111111 . ..... ..... 010 ..... 1010111 @r_vm
559 vwmaccsu_vx 111111 . ..... ..... 110 ..... 1010111 @r_vm
560 vwmaccus_vx 111110 . ..... ..... 110 ..... 1010111 @r_vm
561 vmv_v_v 010111 1 00000 ..... 000 ..... 1010111 @r2
562 vmv_v_x 010111 1 00000 ..... 100 ..... 1010111 @r2
563 vmv_v_i 010111 1 00000 ..... 011 ..... 1010111 @r2
564 vmerge_vvm 010111 0 ..... ..... 000 ..... 1010111 @r_vm_0
565 vmerge_vxm 010111 0 ..... ..... 100 ..... 1010111 @r_vm_0
566 vmerge_vim 010111 0 ..... ..... 011 ..... 1010111 @r_vm_0
567 vsaddu_vv 100000 . ..... ..... 000 ..... 1010111 @r_vm
568 vsaddu_vx 100000 . ..... ..... 100 ..... 1010111 @r_vm
569 vsaddu_vi 100000 . ..... ..... 011 ..... 1010111 @r_vm
570 vsadd_vv 100001 . ..... ..... 000 ..... 1010111 @r_vm
571 vsadd_vx 100001 . ..... ..... 100 ..... 1010111 @r_vm
572 vsadd_vi 100001 . ..... ..... 011 ..... 1010111 @r_vm
573 vssubu_vv 100010 . ..... ..... 000 ..... 1010111 @r_vm
574 vssubu_vx 100010 . ..... ..... 100 ..... 1010111 @r_vm
575 vssub_vv 100011 . ..... ..... 000 ..... 1010111 @r_vm
576 vssub_vx 100011 . ..... ..... 100 ..... 1010111 @r_vm
577 vaadd_vv 001001 . ..... ..... 010 ..... 1010111 @r_vm
578 vaadd_vx 001001 . ..... ..... 110 ..... 1010111 @r_vm
579 vaaddu_vv 001000 . ..... ..... 010 ..... 1010111 @r_vm
580 vaaddu_vx 001000 . ..... ..... 110 ..... 1010111 @r_vm
581 vasub_vv 001011 . ..... ..... 010 ..... 1010111 @r_vm
582 vasub_vx 001011 . ..... ..... 110 ..... 1010111 @r_vm
583 vasubu_vv 001010 . ..... ..... 010 ..... 1010111 @r_vm
584 vasubu_vx 001010 . ..... ..... 110 ..... 1010111 @r_vm
585 vsmul_vv 100111 . ..... ..... 000 ..... 1010111 @r_vm
586 vsmul_vx 100111 . ..... ..... 100 ..... 1010111 @r_vm
587 vssrl_vv 101010 . ..... ..... 000 ..... 1010111 @r_vm
588 vssrl_vx 101010 . ..... ..... 100 ..... 1010111 @r_vm
589 vssrl_vi 101010 . ..... ..... 011 ..... 1010111 @r_vm
590 vssra_vv 101011 . ..... ..... 000 ..... 1010111 @r_vm
591 vssra_vx 101011 . ..... ..... 100 ..... 1010111 @r_vm
592 vssra_vi 101011 . ..... ..... 011 ..... 1010111 @r_vm
593 vnclipu_wv 101110 . ..... ..... 000 ..... 1010111 @r_vm
594 vnclipu_wx 101110 . ..... ..... 100 ..... 1010111 @r_vm
595 vnclipu_wi 101110 . ..... ..... 011 ..... 1010111 @r_vm
596 vnclip_wv 101111 . ..... ..... 000 ..... 1010111 @r_vm
597 vnclip_wx 101111 . ..... ..... 100 ..... 1010111 @r_vm
598 vnclip_wi 101111 . ..... ..... 011 ..... 1010111 @r_vm
599 vfadd_vv 000000 . ..... ..... 001 ..... 1010111 @r_vm
600 vfadd_vf 000000 . ..... ..... 101 ..... 1010111 @r_vm
601 vfsub_vv 000010 . ..... ..... 001 ..... 1010111 @r_vm
602 vfsub_vf 000010 . ..... ..... 101 ..... 1010111 @r_vm
603 vfrsub_vf 100111 . ..... ..... 101 ..... 1010111 @r_vm
604 vfwadd_vv 110000 . ..... ..... 001 ..... 1010111 @r_vm
605 vfwadd_vf 110000 . ..... ..... 101 ..... 1010111 @r_vm
606 vfwadd_wv 110100 . ..... ..... 001 ..... 1010111 @r_vm
607 vfwadd_wf 110100 . ..... ..... 101 ..... 1010111 @r_vm
608 vfwsub_vv 110010 . ..... ..... 001 ..... 1010111 @r_vm
609 vfwsub_vf 110010 . ..... ..... 101 ..... 1010111 @r_vm
610 vfwsub_wv 110110 . ..... ..... 001 ..... 1010111 @r_vm
611 vfwsub_wf 110110 . ..... ..... 101 ..... 1010111 @r_vm
612 vfmul_vv 100100 . ..... ..... 001 ..... 1010111 @r_vm
613 vfmul_vf 100100 . ..... ..... 101 ..... 1010111 @r_vm
614 vfdiv_vv 100000 . ..... ..... 001 ..... 1010111 @r_vm
615 vfdiv_vf 100000 . ..... ..... 101 ..... 1010111 @r_vm
616 vfrdiv_vf 100001 . ..... ..... 101 ..... 1010111 @r_vm
617 vfwmul_vv 111000 . ..... ..... 001 ..... 1010111 @r_vm
618 vfwmul_vf 111000 . ..... ..... 101 ..... 1010111 @r_vm
619 vfmacc_vv 101100 . ..... ..... 001 ..... 1010111 @r_vm
620 vfnmacc_vv 101101 . ..... ..... 001 ..... 1010111 @r_vm
621 vfnmacc_vf 101101 . ..... ..... 101 ..... 1010111 @r_vm
622 vfmacc_vf 101100 . ..... ..... 101 ..... 1010111 @r_vm
623 vfmsac_vv 101110 . ..... ..... 001 ..... 1010111 @r_vm
624 vfmsac_vf 101110 . ..... ..... 101 ..... 1010111 @r_vm
625 vfnmsac_vv 101111 . ..... ..... 001 ..... 1010111 @r_vm
626 vfnmsac_vf 101111 . ..... ..... 101 ..... 1010111 @r_vm
627 vfmadd_vv 101000 . ..... ..... 001 ..... 1010111 @r_vm
628 vfmadd_vf 101000 . ..... ..... 101 ..... 1010111 @r_vm
629 vfnmadd_vv 101001 . ..... ..... 001 ..... 1010111 @r_vm
630 vfnmadd_vf 101001 . ..... ..... 101 ..... 1010111 @r_vm
631 vfmsub_vv 101010 . ..... ..... 001 ..... 1010111 @r_vm
632 vfmsub_vf 101010 . ..... ..... 101 ..... 1010111 @r_vm
633 vfnmsub_vv 101011 . ..... ..... 001 ..... 1010111 @r_vm
634 vfnmsub_vf 101011 . ..... ..... 101 ..... 1010111 @r_vm
635 vfwmacc_vv 111100 . ..... ..... 001 ..... 1010111 @r_vm
636 vfwmacc_vf 111100 . ..... ..... 101 ..... 1010111 @r_vm
637 vfwnmacc_vv 111101 . ..... ..... 001 ..... 1010111 @r_vm
638 vfwnmacc_vf 111101 . ..... ..... 101 ..... 1010111 @r_vm
639 vfwmsac_vv 111110 . ..... ..... 001 ..... 1010111 @r_vm
640 vfwmsac_vf 111110 . ..... ..... 101 ..... 1010111 @r_vm
641 vfwnmsac_vv 111111 . ..... ..... 001 ..... 1010111 @r_vm
642 vfwnmsac_vf 111111 . ..... ..... 101 ..... 1010111 @r_vm
643 vfsqrt_v 010011 . ..... 00000 001 ..... 1010111 @r2_vm
644 vfrsqrt7_v 010011 . ..... 00100 001 ..... 1010111 @r2_vm
645 vfrec7_v 010011 . ..... 00101 001 ..... 1010111 @r2_vm
646 vfmin_vv 000100 . ..... ..... 001 ..... 1010111 @r_vm
647 vfmin_vf 000100 . ..... ..... 101 ..... 1010111 @r_vm
648 vfmax_vv 000110 . ..... ..... 001 ..... 1010111 @r_vm
649 vfmax_vf 000110 . ..... ..... 101 ..... 1010111 @r_vm
650 vfsgnj_vv 001000 . ..... ..... 001 ..... 1010111 @r_vm
651 vfsgnj_vf 001000 . ..... ..... 101 ..... 1010111 @r_vm
652 vfsgnjn_vv 001001 . ..... ..... 001 ..... 1010111 @r_vm
653 vfsgnjn_vf 001001 . ..... ..... 101 ..... 1010111 @r_vm
654 vfsgnjx_vv 001010 . ..... ..... 001 ..... 1010111 @r_vm
655 vfsgnjx_vf 001010 . ..... ..... 101 ..... 1010111 @r_vm
656 vfslide1up_vf 001110 . ..... ..... 101 ..... 1010111 @r_vm
657 vfslide1down_vf 001111 . ..... ..... 101 ..... 1010111 @r_vm
658 vmfeq_vv 011000 . ..... ..... 001 ..... 1010111 @r_vm
659 vmfeq_vf 011000 . ..... ..... 101 ..... 1010111 @r_vm
660 vmfne_vv 011100 . ..... ..... 001 ..... 1010111 @r_vm
661 vmfne_vf 011100 . ..... ..... 101 ..... 1010111 @r_vm
662 vmflt_vv 011011 . ..... ..... 001 ..... 1010111 @r_vm
663 vmflt_vf 011011 . ..... ..... 101 ..... 1010111 @r_vm
664 vmfle_vv 011001 . ..... ..... 001 ..... 1010111 @r_vm
665 vmfle_vf 011001 . ..... ..... 101 ..... 1010111 @r_vm
666 vmfgt_vf 011101 . ..... ..... 101 ..... 1010111 @r_vm
667 vmfge_vf 011111 . ..... ..... 101 ..... 1010111 @r_vm
668 vfclass_v 010011 . ..... 10000 001 ..... 1010111 @r2_vm
669 vfmerge_vfm 010111 0 ..... ..... 101 ..... 1010111 @r_vm_0
670 vfmv_v_f 010111 1 00000 ..... 101 ..... 1010111 @r2
671
672 vfcvt_xu_f_v 010010 . ..... 00000 001 ..... 1010111 @r2_vm
673 vfcvt_x_f_v 010010 . ..... 00001 001 ..... 1010111 @r2_vm
674 vfcvt_f_xu_v 010010 . ..... 00010 001 ..... 1010111 @r2_vm
675 vfcvt_f_x_v 010010 . ..... 00011 001 ..... 1010111 @r2_vm
676 vfcvt_rtz_xu_f_v 010010 . ..... 00110 001 ..... 1010111 @r2_vm
677 vfcvt_rtz_x_f_v 010010 . ..... 00111 001 ..... 1010111 @r2_vm
678
679 vfwcvt_xu_f_v 010010 . ..... 01000 001 ..... 1010111 @r2_vm
680 vfwcvt_x_f_v 010010 . ..... 01001 001 ..... 1010111 @r2_vm
681 vfwcvt_f_xu_v 010010 . ..... 01010 001 ..... 1010111 @r2_vm
682 vfwcvt_f_x_v 010010 . ..... 01011 001 ..... 1010111 @r2_vm
683 vfwcvt_f_f_v 010010 . ..... 01100 001 ..... 1010111 @r2_vm
684 vfwcvt_rtz_xu_f_v 010010 . ..... 01110 001 ..... 1010111 @r2_vm
685 vfwcvt_rtz_x_f_v 010010 . ..... 01111 001 ..... 1010111 @r2_vm
686
687 vfncvt_xu_f_w 010010 . ..... 10000 001 ..... 1010111 @r2_vm
688 vfncvt_x_f_w 010010 . ..... 10001 001 ..... 1010111 @r2_vm
689 vfncvt_f_xu_w 010010 . ..... 10010 001 ..... 1010111 @r2_vm
690 vfncvt_f_x_w 010010 . ..... 10011 001 ..... 1010111 @r2_vm
691 vfncvt_f_f_w 010010 . ..... 10100 001 ..... 1010111 @r2_vm
692 vfncvt_rod_f_f_w 010010 . ..... 10101 001 ..... 1010111 @r2_vm
693 vfncvt_rtz_xu_f_w 010010 . ..... 10110 001 ..... 1010111 @r2_vm
694 vfncvt_rtz_x_f_w 010010 . ..... 10111 001 ..... 1010111 @r2_vm
695
696 vredsum_vs 000000 . ..... ..... 010 ..... 1010111 @r_vm
697 vredand_vs 000001 . ..... ..... 010 ..... 1010111 @r_vm
698 vredor_vs 000010 . ..... ..... 010 ..... 1010111 @r_vm
699 vredxor_vs 000011 . ..... ..... 010 ..... 1010111 @r_vm
700 vredminu_vs 000100 . ..... ..... 010 ..... 1010111 @r_vm
701 vredmin_vs 000101 . ..... ..... 010 ..... 1010111 @r_vm
702 vredmaxu_vs 000110 . ..... ..... 010 ..... 1010111 @r_vm
703 vredmax_vs 000111 . ..... ..... 010 ..... 1010111 @r_vm
704 vwredsumu_vs 110000 . ..... ..... 000 ..... 1010111 @r_vm
705 vwredsum_vs 110001 . ..... ..... 000 ..... 1010111 @r_vm
706 # Vector ordered and unordered reduction sum
707 vfredusum_vs 000001 . ..... ..... 001 ..... 1010111 @r_vm
708 vfredosum_vs 000011 . ..... ..... 001 ..... 1010111 @r_vm
709 vfredmin_vs 000101 . ..... ..... 001 ..... 1010111 @r_vm
710 vfredmax_vs 000111 . ..... ..... 001 ..... 1010111 @r_vm
711 # Vector widening ordered and unordered float reduction sum
712 vfwredusum_vs 110001 . ..... ..... 001 ..... 1010111 @r_vm
713 vfwredosum_vs 110011 . ..... ..... 001 ..... 1010111 @r_vm
714 vmand_mm 011001 1 ..... ..... 010 ..... 1010111 @r
715 vmnand_mm 011101 1 ..... ..... 010 ..... 1010111 @r
716 vmandn_mm 011000 1 ..... ..... 010 ..... 1010111 @r
717 vmxor_mm 011011 1 ..... ..... 010 ..... 1010111 @r
718 vmor_mm 011010 1 ..... ..... 010 ..... 1010111 @r
719 vmnor_mm 011110 1 ..... ..... 010 ..... 1010111 @r
720 vmorn_mm 011100 1 ..... ..... 010 ..... 1010111 @r
721 vmxnor_mm 011111 1 ..... ..... 010 ..... 1010111 @r
722 vcpop_m 010000 . ..... 10000 010 ..... 1010111 @r2_vm
723 vfirst_m 010000 . ..... 10001 010 ..... 1010111 @r2_vm
724 vmsbf_m 010100 . ..... 00001 010 ..... 1010111 @r2_vm
725 vmsif_m 010100 . ..... 00011 010 ..... 1010111 @r2_vm
726 vmsof_m 010100 . ..... 00010 010 ..... 1010111 @r2_vm
727 viota_m 010100 . ..... 10000 010 ..... 1010111 @r2_vm
728 vid_v 010100 . 00000 10001 010 ..... 1010111 @r1_vm
729 vmv_x_s 010000 1 ..... 00000 010 ..... 1010111 @r2rd
730 vmv_s_x 010000 1 00000 ..... 110 ..... 1010111 @r2
731 vfmv_f_s 010000 1 ..... 00000 001 ..... 1010111 @r2rd
732 vfmv_s_f 010000 1 00000 ..... 101 ..... 1010111 @r2
733 vslideup_vx 001110 . ..... ..... 100 ..... 1010111 @r_vm
734 vslideup_vi 001110 . ..... ..... 011 ..... 1010111 @r_vm
735 vslide1up_vx 001110 . ..... ..... 110 ..... 1010111 @r_vm
736 vslidedown_vx 001111 . ..... ..... 100 ..... 1010111 @r_vm
737 vslidedown_vi 001111 . ..... ..... 011 ..... 1010111 @r_vm
738 vslide1down_vx 001111 . ..... ..... 110 ..... 1010111 @r_vm
739 vrgather_vv 001100 . ..... ..... 000 ..... 1010111 @r_vm
740 vrgatherei16_vv 001110 . ..... ..... 000 ..... 1010111 @r_vm
741 vrgather_vx 001100 . ..... ..... 100 ..... 1010111 @r_vm
742 vrgather_vi 001100 . ..... ..... 011 ..... 1010111 @r_vm
743 vcompress_vm 010111 1 ..... ..... 010 ..... 1010111 @r
744 vmv1r_v 100111 1 ..... 00000 011 ..... 1010111 @r2rd
745 vmv2r_v 100111 1 ..... 00001 011 ..... 1010111 @r2rd
746 vmv4r_v 100111 1 ..... 00011 011 ..... 1010111 @r2rd
747 vmv8r_v 100111 1 ..... 00111 011 ..... 1010111 @r2rd
748
749 # Vector Integer Extension
750 vzext_vf2 010010 . ..... 00110 010 ..... 1010111 @r2_vm
751 vzext_vf4 010010 . ..... 00100 010 ..... 1010111 @r2_vm
752 vzext_vf8 010010 . ..... 00010 010 ..... 1010111 @r2_vm
753 vsext_vf2 010010 . ..... 00111 010 ..... 1010111 @r2_vm
754 vsext_vf4 010010 . ..... 00101 010 ..... 1010111 @r2_vm
755 vsext_vf8 010010 . ..... 00011 010 ..... 1010111 @r2_vm
756
757 vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm11
758 vsetivli 11 .......... ..... 111 ..... 1010111 @r2_zimm10
759 vsetvl 1000000 ..... ..... 111 ..... 1010111 @r
760
761 # *** Zawrs Standard Extension ***
762 wrs_nto 000000001101 00000 000 00000 1110011
763 wrs_sto 000000011101 00000 000 00000 1110011
764
765 # *** RV32 Zba Standard Extension ***
766 sh1add 0010000 .......... 010 ..... 0110011 @r
767 sh2add 0010000 .......... 100 ..... 0110011 @r
768 sh3add 0010000 .......... 110 ..... 0110011 @r
769
770 # *** RV64 Zba Standard Extension (in addition to RV32 Zba) ***
771 add_uw 0000100 .......... 000 ..... 0111011 @r
772 sh1add_uw 0010000 .......... 010 ..... 0111011 @r
773 sh2add_uw 0010000 .......... 100 ..... 0111011 @r
774 sh3add_uw 0010000 .......... 110 ..... 0111011 @r
775 slli_uw 00001 ............ 001 ..... 0011011 @sh
776
777 # *** RV32 Zbb/Zbkb Standard Extension ***
778 andn 0100000 .......... 111 ..... 0110011 @r
779 rol 0110000 .......... 001 ..... 0110011 @r
780 ror 0110000 .......... 101 ..... 0110011 @r
781 rori 01100 ............ 101 ..... 0010011 @sh
782 # The encoding for rev8 differs between RV32 and RV64.
783 # rev8_32 denotes the RV32 variant.
784 rev8_32 011010 011000 ..... 101 ..... 0010011 @r2
785 # The encoding for zext.h differs between RV32 and RV64.
786 # zext_h_32 denotes the RV32 variant.
787 {
788 zext_h_32 0000100 00000 ..... 100 ..... 0110011 @r2
789 pack 0000100 ..... ..... 100 ..... 0110011 @r
790 }
791 xnor 0100000 .......... 100 ..... 0110011 @r
792 # *** RV32 extra Zbb Standard Extension ***
793 clz 011000 000000 ..... 001 ..... 0010011 @r2
794 cpop 011000 000010 ..... 001 ..... 0010011 @r2
795 ctz 011000 000001 ..... 001 ..... 0010011 @r2
796 max 0000101 .......... 110 ..... 0110011 @r
797 maxu 0000101 .......... 111 ..... 0110011 @r
798 min 0000101 .......... 100 ..... 0110011 @r
799 minu 0000101 .......... 101 ..... 0110011 @r
800 orc_b 001010 000111 ..... 101 ..... 0010011 @r2
801 orn 0100000 .......... 110 ..... 0110011 @r
802 sext_b 011000 000100 ..... 001 ..... 0010011 @r2
803 sext_h 011000 000101 ..... 001 ..... 0010011 @r2
804 # *** RV32 extra Zbkb Standard Extension ***
805 brev8 0110100 00111 ..... 101 ..... 0010011 @r2 #grevi
806 packh 0000100 .......... 111 ..... 0110011 @r
807 unzip 0000100 01111 ..... 101 ..... 0010011 @r2 #unshfl
808 zip 0000100 01111 ..... 001 ..... 0010011 @r2 #shfl
809
810 # *** RV64 Zbb/Zbkb Standard Extension (in addition to RV32 Zbb/Zbkb) ***
811 # The encoding for rev8 differs between RV32 and RV64.
812 # When executing on RV64, the encoding used in RV32 is an illegal
813 # instruction, so we use different handler functions to differentiate.
814 rev8_64 011010 111000 ..... 101 ..... 0010011 @r2
815 rolw 0110000 .......... 001 ..... 0111011 @r
816 roriw 0110000 .......... 101 ..... 0011011 @sh5
817 rorw 0110000 .......... 101 ..... 0111011 @r
818 # The encoding for zext.h differs between RV32 and RV64.
819 # When executing on RV64, the encoding used in RV32 is an illegal
820 # instruction, so we use different handler functions to differentiate.
821 {
822 zext_h_64 0000100 00000 ..... 100 ..... 0111011 @r2
823 packw 0000100 ..... ..... 100 ..... 0111011 @r
824 }
825 # *** RV64 extra Zbb Standard Extension (in addition to RV32 Zbb) ***
826 clzw 0110000 00000 ..... 001 ..... 0011011 @r2
827 ctzw 0110000 00001 ..... 001 ..... 0011011 @r2
828 cpopw 0110000 00010 ..... 001 ..... 0011011 @r2
829
830 # *** RV32 Zbc/Zbkc Standard Extension ***
831 clmul 0000101 .......... 001 ..... 0110011 @r
832 clmulh 0000101 .......... 011 ..... 0110011 @r
833 # *** RV32 extra Zbc Standard Extension ***
834 clmulr 0000101 .......... 010 ..... 0110011 @r
835
836 # *** RV32 Zbkx Standard Extension ***
837 xperm4 0010100 .......... 010 ..... 0110011 @r
838 xperm8 0010100 .......... 100 ..... 0110011 @r
839
840 # *** RV32 Zbs Standard Extension ***
841 bclr 0100100 .......... 001 ..... 0110011 @r
842 bclri 01001. ........... 001 ..... 0010011 @sh
843 bext 0100100 .......... 101 ..... 0110011 @r
844 bexti 01001. ........... 101 ..... 0010011 @sh
845 binv 0110100 .......... 001 ..... 0110011 @r
846 binvi 01101. ........... 001 ..... 0010011 @sh
847 bset 0010100 .......... 001 ..... 0110011 @r
848 bseti 00101. ........... 001 ..... 0010011 @sh
849
850 # *** Zfa Standard Extension ***
851 fli_s 1111000 00001 ..... 000 ..... 1010011 @r2
852 fli_d 1111001 00001 ..... 000 ..... 1010011 @r2
853 fli_h 1111010 00001 ..... 000 ..... 1010011 @r2
854 fminm_s 0010100 ..... ..... 010 ..... 1010011 @r
855 fmaxm_s 0010100 ..... ..... 011 ..... 1010011 @r
856 fminm_d 0010101 ..... ..... 010 ..... 1010011 @r
857 fmaxm_d 0010101 ..... ..... 011 ..... 1010011 @r
858 fminm_h 0010110 ..... ..... 010 ..... 1010011 @r
859 fmaxm_h 0010110 ..... ..... 011 ..... 1010011 @r
860 fround_s 0100000 00100 ..... ... ..... 1010011 @r2_rm
861 froundnx_s 0100000 00101 ..... ... ..... 1010011 @r2_rm
862 fround_d 0100001 00100 ..... ... ..... 1010011 @r2_rm
863 froundnx_d 0100001 00101 ..... ... ..... 1010011 @r2_rm
864 fround_h 0100010 00100 ..... ... ..... 1010011 @r2_rm
865 froundnx_h 0100010 00101 ..... ... ..... 1010011 @r2_rm
866 fcvtmod_w_d 1100001 01000 ..... 001 ..... 1010011 @r2
867 fmvh_x_d 1110001 00001 ..... 000 ..... 1010011 @r2
868 fmvp_d_x 1011001 ..... ..... 000 ..... 1010011 @r
869 fleq_s 1010000 ..... ..... 100 ..... 1010011 @r
870 fltq_s 1010000 ..... ..... 101 ..... 1010011 @r
871 fleq_d 1010001 ..... ..... 100 ..... 1010011 @r
872 fltq_d 1010001 ..... ..... 101 ..... 1010011 @r
873 fleq_h 1010010 ..... ..... 100 ..... 1010011 @r
874 fltq_h 1010010 ..... ..... 101 ..... 1010011 @r
875
876 # *** RV32 Zfh Extension ***
877 flh ............ ..... 001 ..... 0000111 @i
878 fsh ....... ..... ..... 001 ..... 0100111 @s
879 fmadd_h ..... 10 ..... ..... ... ..... 1000011 @r4_rm
880 fmsub_h ..... 10 ..... ..... ... ..... 1000111 @r4_rm
881 fnmsub_h ..... 10 ..... ..... ... ..... 1001011 @r4_rm
882 fnmadd_h ..... 10 ..... ..... ... ..... 1001111 @r4_rm
883 fadd_h 0000010 ..... ..... ... ..... 1010011 @r_rm
884 fsub_h 0000110 ..... ..... ... ..... 1010011 @r_rm
885 fmul_h 0001010 ..... ..... ... ..... 1010011 @r_rm
886 fdiv_h 0001110 ..... ..... ... ..... 1010011 @r_rm
887 fsqrt_h 0101110 00000 ..... ... ..... 1010011 @r2_rm
888 fsgnj_h 0010010 ..... ..... 000 ..... 1010011 @r
889 fsgnjn_h 0010010 ..... ..... 001 ..... 1010011 @r
890 fsgnjx_h 0010010 ..... ..... 010 ..... 1010011 @r
891 fmin_h 0010110 ..... ..... 000 ..... 1010011 @r
892 fmax_h 0010110 ..... ..... 001 ..... 1010011 @r
893 fcvt_h_s 0100010 00000 ..... ... ..... 1010011 @r2_rm
894 fcvt_s_h 0100000 00010 ..... ... ..... 1010011 @r2_rm
895 fcvt_h_d 0100010 00001 ..... ... ..... 1010011 @r2_rm
896 fcvt_d_h 0100001 00010 ..... ... ..... 1010011 @r2_rm
897 fcvt_w_h 1100010 00000 ..... ... ..... 1010011 @r2_rm
898 fcvt_wu_h 1100010 00001 ..... ... ..... 1010011 @r2_rm
899 fmv_x_h 1110010 00000 ..... 000 ..... 1010011 @r2
900 feq_h 1010010 ..... ..... 010 ..... 1010011 @r
901 flt_h 1010010 ..... ..... 001 ..... 1010011 @r
902 fle_h 1010010 ..... ..... 000 ..... 1010011 @r
903 fclass_h 1110010 00000 ..... 001 ..... 1010011 @r2
904 fcvt_h_w 1101010 00000 ..... ... ..... 1010011 @r2_rm
905 fcvt_h_wu 1101010 00001 ..... ... ..... 1010011 @r2_rm
906 fmv_h_x 1111010 00000 ..... 000 ..... 1010011 @r2
907
908 # *** RV64 Zfh Extension (in addition to RV32 Zfh) ***
909 fcvt_l_h 1100010 00010 ..... ... ..... 1010011 @r2_rm
910 fcvt_lu_h 1100010 00011 ..... ... ..... 1010011 @r2_rm
911 fcvt_h_l 1101010 00010 ..... ... ..... 1010011 @r2_rm
912 fcvt_h_lu 1101010 00011 ..... ... ..... 1010011 @r2_rm
913
914 # *** Svinval Standard Extension ***
915 sinval_vma 0001011 ..... ..... 000 00000 1110011 @sfence_vma
916 sfence_w_inval 0001100 00000 00000 000 00000 1110011
917 sfence_inval_ir 0001100 00001 00000 000 00000 1110011
918 hinval_vvma 0010011 ..... ..... 000 00000 1110011 @hfence_vvma
919 hinval_gvma 0110011 ..... ..... 000 00000 1110011 @hfence_gvma
920
921 # *** RV32 Zknd Standard Extension ***
922 aes32dsmi .. 10111 ..... ..... 000 ..... 0110011 @k_aes
923 aes32dsi .. 10101 ..... ..... 000 ..... 0110011 @k_aes
924 # *** RV64 Zknd Standard Extension ***
925 aes64dsm 00 11111 ..... ..... 000 ..... 0110011 @r
926 aes64ds 00 11101 ..... ..... 000 ..... 0110011 @r
927 aes64im 00 11000 00000 ..... 001 ..... 0010011 @r2
928 # *** RV32 Zkne Standard Extension ***
929 aes32esmi .. 10011 ..... ..... 000 ..... 0110011 @k_aes
930 aes32esi .. 10001 ..... ..... 000 ..... 0110011 @k_aes
931 # *** RV64 Zkne Standard Extension ***
932 aes64es 00 11001 ..... ..... 000 ..... 0110011 @r
933 aes64esm 00 11011 ..... ..... 000 ..... 0110011 @r
934 # *** RV64 Zkne/zknd Standard Extension ***
935 aes64ks2 01 11111 ..... ..... 000 ..... 0110011 @r
936 aes64ks1i 00 11000 1.... ..... 001 ..... 0010011 @i_aes
937 # *** RV32 Zknh Standard Extension ***
938 sha256sig0 00 01000 00010 ..... 001 ..... 0010011 @r2
939 sha256sig1 00 01000 00011 ..... 001 ..... 0010011 @r2
940 sha256sum0 00 01000 00000 ..... 001 ..... 0010011 @r2
941 sha256sum1 00 01000 00001 ..... 001 ..... 0010011 @r2
942 sha512sum0r 01 01000 ..... ..... 000 ..... 0110011 @r
943 sha512sum1r 01 01001 ..... ..... 000 ..... 0110011 @r
944 sha512sig0l 01 01010 ..... ..... 000 ..... 0110011 @r
945 sha512sig0h 01 01110 ..... ..... 000 ..... 0110011 @r
946 sha512sig1l 01 01011 ..... ..... 000 ..... 0110011 @r
947 sha512sig1h 01 01111 ..... ..... 000 ..... 0110011 @r
948 # *** RV64 Zknh Standard Extension ***
949 sha512sig0 00 01000 00110 ..... 001 ..... 0010011 @r2
950 sha512sig1 00 01000 00111 ..... 001 ..... 0010011 @r2
951 sha512sum0 00 01000 00100 ..... 001 ..... 0010011 @r2
952 sha512sum1 00 01000 00101 ..... 001 ..... 0010011 @r2
953 # *** RV32 Zksh Standard Extension ***
954 sm3p0 00 01000 01000 ..... 001 ..... 0010011 @r2
955 sm3p1 00 01000 01001 ..... 001 ..... 0010011 @r2
956 # *** RV32 Zksed Standard Extension ***
957 sm4ed .. 11000 ..... ..... 000 ..... 0110011 @k_aes
958 sm4ks .. 11010 ..... ..... 000 ..... 0110011 @k_aes
959
960 # *** RV32 Zicond Standard Extension ***
961 czero_eqz 0000111 ..... ..... 101 ..... 0110011 @r
962 czero_nez 0000111 ..... ..... 111 ..... 0110011 @r
963
964 # *** Zfbfmin Standard Extension ***
965 fcvt_bf16_s 0100010 01000 ..... ... ..... 1010011 @r2_rm
966 fcvt_s_bf16 0100000 00110 ..... ... ..... 1010011 @r2_rm
967
968 # *** Zvfbfmin Standard Extension ***
969 vfncvtbf16_f_f_w 010010 . ..... 11101 001 ..... 1010111 @r2_vm
970 vfwcvtbf16_f_f_v 010010 . ..... 01101 001 ..... 1010111 @r2_vm
971
972 # *** Zvfbfwma Standard Extension ***
973 vfwmaccbf16_vv 111011 . ..... ..... 001 ..... 1010111 @r_vm
974 vfwmaccbf16_vf 111011 . ..... ..... 101 ..... 1010111 @r_vm
975
976 # *** Zvbc vector crypto extension ***
977 vclmul_vv 001100 . ..... ..... 010 ..... 1010111 @r_vm
978 vclmul_vx 001100 . ..... ..... 110 ..... 1010111 @r_vm
979 vclmulh_vv 001101 . ..... ..... 010 ..... 1010111 @r_vm
980 vclmulh_vx 001101 . ..... ..... 110 ..... 1010111 @r_vm
981
982 # *** Zvbb vector crypto extension ***
983 vrol_vv 010101 . ..... ..... 000 ..... 1010111 @r_vm
984 vrol_vx 010101 . ..... ..... 100 ..... 1010111 @r_vm
985 vror_vv 010100 . ..... ..... 000 ..... 1010111 @r_vm
986 vror_vx 010100 . ..... ..... 100 ..... 1010111 @r_vm
987 vror_vi 01010. . ..... ..... 011 ..... 1010111 @r2_zimm6
988 vbrev8_v 010010 . ..... 01000 010 ..... 1010111 @r2_vm
989 vrev8_v 010010 . ..... 01001 010 ..... 1010111 @r2_vm
990 vandn_vv 000001 . ..... ..... 000 ..... 1010111 @r_vm
991 vandn_vx 000001 . ..... ..... 100 ..... 1010111 @r_vm
992 vbrev_v 010010 . ..... 01010 010 ..... 1010111 @r2_vm
993 vclz_v 010010 . ..... 01100 010 ..... 1010111 @r2_vm
994 vctz_v 010010 . ..... 01101 010 ..... 1010111 @r2_vm
995 vcpop_v 010010 . ..... 01110 010 ..... 1010111 @r2_vm
996 vwsll_vv 110101 . ..... ..... 000 ..... 1010111 @r_vm
997 vwsll_vx 110101 . ..... ..... 100 ..... 1010111 @r_vm
998 vwsll_vi 110101 . ..... ..... 011 ..... 1010111 @r_vm
999
1000 # *** Zvkned vector crypto extension ***
1001 vaesef_vv 101000 1 ..... 00011 010 ..... 1110111 @r2_vm_1
1002 vaesef_vs 101001 1 ..... 00011 010 ..... 1110111 @r2_vm_1
1003 vaesdf_vv 101000 1 ..... 00001 010 ..... 1110111 @r2_vm_1
1004 vaesdf_vs 101001 1 ..... 00001 010 ..... 1110111 @r2_vm_1
1005 vaesem_vv 101000 1 ..... 00010 010 ..... 1110111 @r2_vm_1
1006 vaesem_vs 101001 1 ..... 00010 010 ..... 1110111 @r2_vm_1
1007 vaesdm_vv 101000 1 ..... 00000 010 ..... 1110111 @r2_vm_1
1008 vaesdm_vs 101001 1 ..... 00000 010 ..... 1110111 @r2_vm_1
1009 vaesz_vs 101001 1 ..... 00111 010 ..... 1110111 @r2_vm_1
1010 vaeskf1_vi 100010 1 ..... ..... 010 ..... 1110111 @r_vm_1
1011 vaeskf2_vi 101010 1 ..... ..... 010 ..... 1110111 @r_vm_1
1012
1013 # *** Zvknh vector crypto extension ***
1014 vsha2ms_vv 101101 1 ..... ..... 010 ..... 1110111 @r_vm_1
1015 vsha2ch_vv 101110 1 ..... ..... 010 ..... 1110111 @r_vm_1
1016 vsha2cl_vv 101111 1 ..... ..... 010 ..... 1110111 @r_vm_1
1017
1018 # *** Zvksh vector crypto extension ***
1019 vsm3me_vv 100000 1 ..... ..... 010 ..... 1110111 @r_vm_1
1020 vsm3c_vi 101011 1 ..... ..... 010 ..... 1110111 @r_vm_1
1021
1022 # *** Zvkg vector crypto extension ***
1023 vghsh_vv 101100 1 ..... ..... 010 ..... 1110111 @r_vm_1
1024 vgmul_vv 101000 1 ..... 10001 010 ..... 1110111 @r2_vm_1
1025
1026 # *** Zvksed vector crypto extension ***
1027 vsm4k_vi 100001 1 ..... ..... 010 ..... 1110111 @r_vm_1
1028 vsm4r_vv 101000 1 ..... 10000 010 ..... 1110111 @r2_vm_1
1029 vsm4r_vs 101001 1 ..... 10000 010 ..... 1110111 @r2_vm_1
1030
1031 # *** RV32 Zacas Standard Extension ***
1032 amocas_w 00101 . . ..... ..... 010 ..... 0101111 @atom_st
1033 amocas_d 00101 . . ..... ..... 011 ..... 0101111 @atom_st
1034 # *** RV64 Zacas Standard Extension ***
1035 amocas_q 00101 . . ..... ..... 100 ..... 0101111 @atom_st
1036
1037 # *** Zimop may-be-operation extension ***
1038 {
1039 # zicfiss instructions carved out of mop.r
1040 [
1041 ssrdp 1100110 11100 00000 100 rd:5 1110011
1042 sspopchk 1100110 11100 00001 100 00000 1110011 &r2 rs1=1 rd=0
1043 sspopchk 1100110 11100 00101 100 00000 1110011 &r2 rs1=5 rd=0
1044 ]
1045 mop_r_n 1 . 00 .. 0111 .. ..... 100 ..... 1110011 @mop5
1046 }
1047 {
1048 # zicfiss instruction carved out of mop.rr
1049 [
1050 sspush 1100111 00001 00000 100 00000 1110011 &r2_s rs2=1 rs1=0
1051 sspush 1100111 00101 00000 100 00000 1110011 &r2_s rs2=5 rs1=0
1052 ]
1053 mop_rr_n 1 . 00 .. 1 ..... ..... 100 ..... 1110011 @mop3
1054 }
1055
1056 # *** Zabhb Standard Extension ***
1057 amoswap_b 00001 . . ..... ..... 000 ..... 0101111 @atom_st
1058 amoadd_b 00000 . . ..... ..... 000 ..... 0101111 @atom_st
1059 amoxor_b 00100 . . ..... ..... 000 ..... 0101111 @atom_st
1060 amoand_b 01100 . . ..... ..... 000 ..... 0101111 @atom_st
1061 amoor_b 01000 . . ..... ..... 000 ..... 0101111 @atom_st
1062 amomin_b 10000 . . ..... ..... 000 ..... 0101111 @atom_st
1063 amomax_b 10100 . . ..... ..... 000 ..... 0101111 @atom_st
1064 amominu_b 11000 . . ..... ..... 000 ..... 0101111 @atom_st
1065 amomaxu_b 11100 . . ..... ..... 000 ..... 0101111 @atom_st
1066 amoswap_h 00001 . . ..... ..... 001 ..... 0101111 @atom_st
1067 amoadd_h 00000 . . ..... ..... 001 ..... 0101111 @atom_st
1068 amoxor_h 00100 . . ..... ..... 001 ..... 0101111 @atom_st
1069 amoand_h 01100 . . ..... ..... 001 ..... 0101111 @atom_st
1070 amoor_h 01000 . . ..... ..... 001 ..... 0101111 @atom_st
1071 amomin_h 10000 . . ..... ..... 001 ..... 0101111 @atom_st
1072 amomax_h 10100 . . ..... ..... 001 ..... 0101111 @atom_st
1073 amominu_h 11000 . . ..... ..... 001 ..... 0101111 @atom_st
1074 amomaxu_h 11100 . . ..... ..... 001 ..... 0101111 @atom_st
1075 amocas_b 00101 . . ..... ..... 000 ..... 0101111 @atom_st
1076 amocas_h 00101 . . ..... ..... 001 ..... 0101111 @atom_st
1077
1078 # *** Zalasr Standard Extension ***
1079 lb_aqrl 00110 . . ..... ..... 000 ..... 0101111 @atom_st
1080 lh_aqrl 00110 . . ..... ..... 001 ..... 0101111 @atom_st
1081 lw_aqrl 00110 . . ..... ..... 010 ..... 0101111 @atom_st
1082 ld_aqrl 00110 . . ..... ..... 011 ..... 0101111 @atom_st
1083 sb_aqrl 00111 . . ..... ..... 000 ..... 0101111 @atom_st
1084 sh_aqrl 00111 . . ..... ..... 001 ..... 0101111 @atom_st
1085 sw_aqrl 00111 . . ..... ..... 010 ..... 0101111 @atom_st
1086 sd_aqrl 00111 . . ..... ..... 011 ..... 0101111 @atom_st