| 1 | /* |
| 2 | * QEMU RISC-V CPU -- internal functions and types |
| 3 | * |
| 4 | * Copyright (c) 2020 T-Head Semiconductor Co., Ltd. All rights reserved. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify it |
| 7 | * under the terms and conditions of the GNU General Public License, |
| 8 | * version 2 or later, as published by the Free Software Foundation. |
| 9 | * |
| 10 | * This program is distributed in the hope it will be useful, but WITHOUT |
| 11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 13 | * more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License along with |
| 16 | * this program. If not, see <http://www.gnu.org/licenses/>. |
| 17 | */ |
| 18 | |
| 19 | #ifndef RISCV_CPU_INTERNALS_H |
| 20 | #define RISCV_CPU_INTERNALS_H |
| 21 | |
| 22 | #include "exec/cpu-common.h" |
| 23 | #include "hw/core/registerfields.h" |
| 24 | #include "fpu/softfloat-types.h" |
| 25 | #include "target/riscv/cpu_bits.h" |
| 26 | |
| 27 | /* |
| 28 | * The current MMU Modes are: |
| 29 | * - U 0b000 |
| 30 | * - S 0b001 |
| 31 | * - S+SUM 0b010 |
| 32 | * - M 0b011 |
| 33 | * - U+2STAGE 0b100 |
| 34 | * - S+2STAGE 0b101 |
| 35 | * - S+SUM+2STAGE 0b110 |
| 36 | * - Shadow stack+U 0b1000 |
| 37 | * - Shadow stack+S 0b1001 |
| 38 | */ |
| 39 | #define MMUIdx_U 0 |
| 40 | #define MMUIdx_S 1 |
| 41 | #define MMUIdx_S_SUM 2 |
| 42 | #define MMUIdx_M 3 |
| 43 | #define MMU_2STAGE_BIT (1 << 2) |
| 44 | #define MMU_IDX_SS_WRITE (1 << 3) |
| 45 | |
| 46 | static inline privilege_mode_t mmuidx_priv(int mmu_idx) |
| 47 | { |
| 48 | privilege_mode_t ret = mmu_idx & 3; |
| 49 | if (ret == MMUIdx_S_SUM) { |
| 50 | ret = PRV_S; |
| 51 | } |
| 52 | return ret; |
| 53 | } |
| 54 | |
| 55 | static inline bool mmuidx_sum(int mmu_idx) |
| 56 | { |
| 57 | return (mmu_idx & 3) == MMUIdx_S_SUM; |
| 58 | } |
| 59 | |
| 60 | static inline bool mmuidx_2stage(int mmu_idx) |
| 61 | { |
| 62 | return mmu_idx & MMU_2STAGE_BIT; |
| 63 | } |
| 64 | |
| 65 | /* |
| 66 | * Return the endianness for the current privilege |
| 67 | * level, based on the MSTATUS MBE/SBE/UBE bits. |
| 68 | */ |
| 69 | static inline MemOp mo_endian_env(CPURISCVState *env) |
| 70 | { |
| 71 | bool be = false; |
| 72 | #if !defined(CONFIG_USER_ONLY) |
| 73 | switch (env->priv) { |
| 74 | case PRV_M: |
| 75 | be = env->mstatus & MSTATUS_MBE; |
| 76 | break; |
| 77 | case PRV_S: |
| 78 | be = env->mstatus & MSTATUS_SBE; |
| 79 | break; |
| 80 | case PRV_U: |
| 81 | be = env->mstatus & MSTATUS_UBE; |
| 82 | break; |
| 83 | default: |
| 84 | g_assert_not_reached(); |
| 85 | } |
| 86 | #endif |
| 87 | return be ? MO_BE : MO_LE; |
| 88 | } |
| 89 | |
| 90 | /* share data between vector helpers and decode code */ |
| 91 | FIELD(VDATA, VM, 0, 1) |
| 92 | FIELD(VDATA, LMUL, 1, 3) |
| 93 | FIELD(VDATA, VTA, 4, 1) |
| 94 | FIELD(VDATA, VTA_ALL_1S, 5, 1) |
| 95 | FIELD(VDATA, VMA, 6, 1) |
| 96 | FIELD(VDATA, NF, 7, 4) |
| 97 | FIELD(VDATA, WD, 7, 1) |
| 98 | |
| 99 | /* float point classify helpers */ |
| 100 | target_ulong fclass_h_bf16(uint64_t frs1); |
| 101 | target_ulong fclass_h(uint64_t frs1); |
| 102 | target_ulong fclass_s(uint64_t frs1); |
| 103 | target_ulong fclass_d(uint64_t frs1); |
| 104 | |
| 105 | #ifndef CONFIG_USER_ONLY |
| 106 | extern const VMStateDescription vmstate_riscv_cpu; |
| 107 | #endif |
| 108 | |
| 109 | enum { |
| 110 | RISCV_FRM_RNE = 0, /* Round to Nearest, ties to Even */ |
| 111 | RISCV_FRM_RTZ = 1, /* Round towards Zero */ |
| 112 | RISCV_FRM_RDN = 2, /* Round Down */ |
| 113 | RISCV_FRM_RUP = 3, /* Round Up */ |
| 114 | RISCV_FRM_RMM = 4, /* Round to Nearest, ties to Max Magnitude */ |
| 115 | RISCV_FRM_DYN = 7, /* Dynamic rounding mode */ |
| 116 | RISCV_FRM_ROD = 8, /* Round to Odd */ |
| 117 | }; |
| 118 | |
| 119 | static inline uint64_t nanbox_s(CPURISCVState *env, float32 f) |
| 120 | { |
| 121 | /* the value is sign-extended instead of NaN-boxing for zfinx */ |
| 122 | if (env_archcpu(env)->cfg.ext_zfinx) { |
| 123 | return (int32_t)f; |
| 124 | } else { |
| 125 | return f | MAKE_64BIT_MASK(32, 32); |
| 126 | } |
| 127 | } |
| 128 | |
| 129 | static inline float32 check_nanbox_s(CPURISCVState *env, uint64_t f) |
| 130 | { |
| 131 | /* Disable NaN-boxing check when enable zfinx */ |
| 132 | if (env_archcpu(env)->cfg.ext_zfinx) { |
| 133 | return (uint32_t)f; |
| 134 | } |
| 135 | |
| 136 | uint64_t mask = MAKE_64BIT_MASK(32, 32); |
| 137 | |
| 138 | if (likely((f & mask) == mask)) { |
| 139 | return (uint32_t)f; |
| 140 | } else { |
| 141 | return 0x7fc00000u; /* default qnan */ |
| 142 | } |
| 143 | } |
| 144 | |
| 145 | static inline uint64_t nanbox_h(CPURISCVState *env, float16 f) |
| 146 | { |
| 147 | /* the value is sign-extended instead of NaN-boxing for zfinx */ |
| 148 | if (env_archcpu(env)->cfg.ext_zfinx) { |
| 149 | return (int16_t)f; |
| 150 | } else { |
| 151 | return f | MAKE_64BIT_MASK(16, 48); |
| 152 | } |
| 153 | } |
| 154 | |
| 155 | static inline float16 check_nanbox_h(CPURISCVState *env, uint64_t f) |
| 156 | { |
| 157 | /* Disable nanbox check when enable zfinx */ |
| 158 | if (env_archcpu(env)->cfg.ext_zfinx) { |
| 159 | return (uint16_t)f; |
| 160 | } |
| 161 | |
| 162 | uint64_t mask = MAKE_64BIT_MASK(16, 48); |
| 163 | |
| 164 | if (likely((f & mask) == mask)) { |
| 165 | return (uint16_t)f; |
| 166 | } else { |
| 167 | return 0x7E00u; /* default qnan */ |
| 168 | } |
| 169 | } |
| 170 | |
| 171 | static inline float16 check_nanbox_bf16(CPURISCVState *env, uint64_t f) |
| 172 | { |
| 173 | /* Disable nanbox check when enable zfinx */ |
| 174 | if (env_archcpu(env)->cfg.ext_zfinx) { |
| 175 | return (uint16_t)f; |
| 176 | } |
| 177 | |
| 178 | uint64_t mask = MAKE_64BIT_MASK(16, 48); |
| 179 | |
| 180 | if (likely((f & mask) == mask)) { |
| 181 | return (uint16_t)f; |
| 182 | } else { |
| 183 | return 0x7FC0u; /* default qnan */ |
| 184 | } |
| 185 | } |
| 186 | |
| 187 | static inline target_ulong get_xepc_mask(CPURISCVState *env) |
| 188 | { |
| 189 | RISCVCPU *cpu = env_archcpu(env); |
| 190 | |
| 191 | /* |
| 192 | * When IALIGN=32, both low bits must be zero. |
| 193 | * When IALIGN=16 (has C or Zc* extensions), only bit 0 must be zero. |
| 194 | */ |
| 195 | if (riscv_has_ext(env, RVC) || cpu->cfg.ext_zca || |
| 196 | cpu->cfg.ext_zcb || cpu->cfg.ext_zcd || cpu->cfg.ext_zce || |
| 197 | cpu->cfg.ext_zcf || cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt) { |
| 198 | return ~(target_ulong)1; |
| 199 | } else { |
| 200 | return ~(target_ulong)3; |
| 201 | } |
| 202 | } |
| 203 | |
| 204 | #ifndef CONFIG_USER_ONLY |
| 205 | /* Our implementation of SysemuCPUOps::has_work */ |
| 206 | bool riscv_cpu_has_work(CPUState *cs); |
| 207 | #endif |
| 208 | |
| 209 | /* Zjpm addr masking routine */ |
| 210 | static inline target_ulong adjust_addr_body(CPURISCVState *env, |
| 211 | target_ulong addr, |
| 212 | bool is_virt_addr) |
| 213 | { |
| 214 | RISCVPmPmm pmm = PMM_FIELD_DISABLED; |
| 215 | uint32_t pmlen = 0; |
| 216 | bool signext = false; |
| 217 | |
| 218 | /* do nothing for rv32 mode */ |
| 219 | if (riscv_cpu_mxl(env) == MXL_RV32) { |
| 220 | return addr; |
| 221 | } |
| 222 | |
| 223 | /* get pmm field depending on whether addr is */ |
| 224 | if (is_virt_addr) { |
| 225 | pmm = riscv_pm_get_vm_ldst_pmm(env); |
| 226 | } else { |
| 227 | pmm = riscv_pm_get_pmm(env); |
| 228 | } |
| 229 | |
| 230 | /* if pointer masking is disabled, return original addr */ |
| 231 | if (pmm == PMM_FIELD_DISABLED) { |
| 232 | return addr; |
| 233 | } |
| 234 | |
| 235 | signext = riscv_cpu_virt_mem_enabled(env, is_virt_addr); |
| 236 | pmlen = riscv_pm_get_pmlen(pmm); |
| 237 | addr = addr << pmlen; |
| 238 | |
| 239 | /* sign/zero extend masked address by N-1 bit */ |
| 240 | if (signext) { |
| 241 | addr = (target_long)addr >> pmlen; |
| 242 | } else { |
| 243 | addr = addr >> pmlen; |
| 244 | } |
| 245 | |
| 246 | return addr; |
| 247 | } |
| 248 | |
| 249 | static inline target_ulong adjust_addr(CPURISCVState *env, |
| 250 | target_ulong addr) |
| 251 | { |
| 252 | return adjust_addr_body(env, addr, false); |
| 253 | } |
| 254 | |
| 255 | static inline target_ulong adjust_addr_virt(CPURISCVState *env, |
| 256 | target_ulong addr) |
| 257 | { |
| 258 | return adjust_addr_body(env, addr, true); |
| 259 | } |
| 260 | |
| 261 | static inline int insn_len(uint16_t first_word) |
| 262 | { |
| 263 | return (first_word & 3) == 3 ? 4 : 2; |
| 264 | } |
| 265 | |
| 266 | int riscv_monitor_get_register_legacy(CPUState *cs, const char *name, |
| 267 | int64_t *pval); |
| 268 | |
| 269 | #endif |