| 1 | /* |
| 2 | * RISC-V implementation of KVM hooks |
| 3 | * |
| 4 | * Copyright (c) 2020 Huawei Technologies Co., Ltd |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify it |
| 7 | * under the terms and conditions of the GNU General Public License, |
| 8 | * version 2 or later, as published by the Free Software Foundation. |
| 9 | * |
| 10 | * This program is distributed in the hope it will be useful, but WITHOUT |
| 11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 13 | * more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License along with |
| 16 | * this program. If not, see <http://www.gnu.org/licenses/>. |
| 17 | */ |
| 18 | |
| 19 | #include "qemu/osdep.h" |
| 20 | #include <sys/ioctl.h> |
| 21 | #include <sys/prctl.h> |
| 22 | |
| 23 | #include <linux/kvm.h> |
| 24 | |
| 25 | #include "qemu/timer.h" |
| 26 | #include "qapi/error.h" |
| 27 | #include "qemu/error-report.h" |
| 28 | #include "qemu/main-loop.h" |
| 29 | #include "qapi/visitor.h" |
| 30 | #include "system/system.h" |
| 31 | #include "system/kvm.h" |
| 32 | #include "system/kvm_int.h" |
| 33 | #include "cpu.h" |
| 34 | #include "trace.h" |
| 35 | #include "accel/accel-cpu-target.h" |
| 36 | #include "hw/pci/pci.h" |
| 37 | #include "exec/memattrs.h" |
| 38 | #include "system/address-spaces.h" |
| 39 | #include "system/memory.h" |
| 40 | #include "hw/core/boards.h" |
| 41 | #include "hw/core/irq.h" |
| 42 | #include "hw/intc/riscv_imsic.h" |
| 43 | #include "qemu/log.h" |
| 44 | #include "hw/core/loader.h" |
| 45 | #include "kvm_riscv.h" |
| 46 | #include "sbi_ecall_interface.h" |
| 47 | #include "chardev/char-fe.h" |
| 48 | #include "migration/misc.h" |
| 49 | #include "system/runstate.h" |
| 50 | #include "hw/riscv/numa.h" |
| 51 | |
| 52 | #define PR_RISCV_V_SET_CONTROL 69 |
| 53 | #define PR_RISCV_V_VSTATE_CTRL_ON 2 |
| 54 | |
| 55 | void riscv_kvm_aplic_request(void *opaque, int irq, int level) |
| 56 | { |
| 57 | kvm_set_irq(kvm_state, irq, !!level); |
| 58 | } |
| 59 | |
| 60 | static bool cap_has_mp_state; |
| 61 | |
| 62 | #define KVM_RISCV_REG_ID_U32(type, idx) (KVM_REG_RISCV | KVM_REG_SIZE_U32 | \ |
| 63 | type | idx) |
| 64 | |
| 65 | #define KVM_RISCV_REG_ID_U64(type, idx) (KVM_REG_RISCV | KVM_REG_SIZE_U64 | \ |
| 66 | type | idx) |
| 67 | |
| 68 | #if defined(TARGET_RISCV64) |
| 69 | #define KVM_RISCV_REG_ID_ULONG(type, idx) KVM_RISCV_REG_ID_U64(type, idx) |
| 70 | #else |
| 71 | #define KVM_RISCV_REG_ID_ULONG(type, idx) KVM_RISCV_REG_ID_U32(type, idx) |
| 72 | #endif |
| 73 | |
| 74 | static uint64_t kvm_encode_reg_size_id(uint64_t id, size_t size_b) |
| 75 | { |
| 76 | uint64_t size_ctz = __builtin_ctz(size_b); |
| 77 | |
| 78 | return id | (size_ctz << KVM_REG_SIZE_SHIFT); |
| 79 | } |
| 80 | |
| 81 | static uint64_t kvm_riscv_vector_reg_id(RISCVCPU *cpu, |
| 82 | uint64_t idx) |
| 83 | { |
| 84 | uint64_t id; |
| 85 | size_t size_b; |
| 86 | |
| 87 | g_assert(idx < 32); |
| 88 | |
| 89 | id = KVM_REG_RISCV | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(idx); |
| 90 | size_b = cpu->cfg.vlenb; |
| 91 | |
| 92 | return kvm_encode_reg_size_id(id, size_b); |
| 93 | } |
| 94 | |
| 95 | #define RISCV_CORE_REG(name) \ |
| 96 | KVM_RISCV_REG_ID_ULONG(KVM_REG_RISCV_CORE, \ |
| 97 | KVM_REG_RISCV_CORE_REG(name)) |
| 98 | |
| 99 | #define RISCV_CSR_REG(name) \ |
| 100 | KVM_RISCV_REG_ID_ULONG(KVM_REG_RISCV_CSR, \ |
| 101 | KVM_REG_RISCV_CSR_REG(name)) |
| 102 | |
| 103 | #define RISCV_CONFIG_REG(name) \ |
| 104 | KVM_RISCV_REG_ID_ULONG(KVM_REG_RISCV_CONFIG, \ |
| 105 | KVM_REG_RISCV_CONFIG_REG(name)) |
| 106 | |
| 107 | #define RISCV_TIMER_REG(name) KVM_RISCV_REG_ID_U64(KVM_REG_RISCV_TIMER, \ |
| 108 | KVM_REG_RISCV_TIMER_REG(name)) |
| 109 | |
| 110 | #define RISCV_FP_F_REG(idx) KVM_RISCV_REG_ID_U32(KVM_REG_RISCV_FP_F, idx) |
| 111 | |
| 112 | #define RISCV_FP_D_REG(idx) KVM_RISCV_REG_ID_U64(KVM_REG_RISCV_FP_D, idx) |
| 113 | |
| 114 | #define RISCV_VECTOR_CSR_REG(name) \ |
| 115 | KVM_RISCV_REG_ID_ULONG(KVM_REG_RISCV_VECTOR, \ |
| 116 | KVM_REG_RISCV_VECTOR_CSR_REG(name)) |
| 117 | |
| 118 | #define KVM_RISCV_GET_TIMER(cs, name, reg) \ |
| 119 | do { \ |
| 120 | int ret = kvm_get_one_reg(cs, RISCV_TIMER_REG(name), ®); \ |
| 121 | if (ret) { \ |
| 122 | abort(); \ |
| 123 | } \ |
| 124 | } while (0) |
| 125 | |
| 126 | #define KVM_RISCV_SET_TIMER(cs, name, reg) \ |
| 127 | do { \ |
| 128 | int ret = kvm_set_one_reg(cs, RISCV_TIMER_REG(name), ®); \ |
| 129 | if (ret) { \ |
| 130 | abort(); \ |
| 131 | } \ |
| 132 | } while (0) |
| 133 | |
| 134 | typedef struct KVMCPUConfig { |
| 135 | const char *name; |
| 136 | const char *description; |
| 137 | target_ulong offset; |
| 138 | uint64_t kvm_reg_id; |
| 139 | uint32_t prop_size; |
| 140 | bool user_set; |
| 141 | bool supported; |
| 142 | } KVMCPUConfig; |
| 143 | |
| 144 | #define KVM_MISA_CFG(_bit, _reg_id) \ |
| 145 | {.offset = _bit, .kvm_reg_id = _reg_id} |
| 146 | |
| 147 | /* KVM ISA extensions */ |
| 148 | static KVMCPUConfig kvm_misa_ext_cfgs[] = { |
| 149 | KVM_MISA_CFG(RVA, KVM_RISCV_ISA_EXT_A), |
| 150 | KVM_MISA_CFG(RVC, KVM_RISCV_ISA_EXT_C), |
| 151 | KVM_MISA_CFG(RVD, KVM_RISCV_ISA_EXT_D), |
| 152 | KVM_MISA_CFG(RVF, KVM_RISCV_ISA_EXT_F), |
| 153 | KVM_MISA_CFG(RVH, KVM_RISCV_ISA_EXT_H), |
| 154 | KVM_MISA_CFG(RVI, KVM_RISCV_ISA_EXT_I), |
| 155 | KVM_MISA_CFG(RVM, KVM_RISCV_ISA_EXT_M), |
| 156 | KVM_MISA_CFG(RVV, KVM_RISCV_ISA_EXT_V), |
| 157 | }; |
| 158 | |
| 159 | static void kvm_cpu_get_misa_ext_cfg(Object *obj, Visitor *v, |
| 160 | const char *name, |
| 161 | void *opaque, Error **errp) |
| 162 | { |
| 163 | KVMCPUConfig *misa_ext_cfg = opaque; |
| 164 | target_ulong misa_bit = misa_ext_cfg->offset; |
| 165 | RISCVCPU *cpu = RISCV_CPU(obj); |
| 166 | CPURISCVState *env = &cpu->env; |
| 167 | bool value = env->misa_ext_mask & misa_bit; |
| 168 | |
| 169 | visit_type_bool(v, name, &value, errp); |
| 170 | } |
| 171 | |
| 172 | static void kvm_cpu_set_misa_ext_cfg(Object *obj, Visitor *v, |
| 173 | const char *name, |
| 174 | void *opaque, Error **errp) |
| 175 | { |
| 176 | KVMCPUConfig *misa_ext_cfg = opaque; |
| 177 | target_ulong misa_bit = misa_ext_cfg->offset; |
| 178 | RISCVCPU *cpu = RISCV_CPU(obj); |
| 179 | CPURISCVState *env = &cpu->env; |
| 180 | bool value, host_bit; |
| 181 | |
| 182 | if (!visit_type_bool(v, name, &value, errp)) { |
| 183 | return; |
| 184 | } |
| 185 | |
| 186 | host_bit = env->misa_ext_mask & misa_bit; |
| 187 | |
| 188 | if (value == host_bit) { |
| 189 | return; |
| 190 | } |
| 191 | |
| 192 | if (!value) { |
| 193 | misa_ext_cfg->user_set = true; |
| 194 | return; |
| 195 | } |
| 196 | |
| 197 | /* |
| 198 | * Forbid users to enable extensions that aren't |
| 199 | * available in the hart. |
| 200 | */ |
| 201 | error_setg(errp, "Enabling MISA bit '%s' is not allowed: it's not " |
| 202 | "enabled in the host", misa_ext_cfg->name); |
| 203 | } |
| 204 | |
| 205 | static void kvm_riscv_update_cpu_misa_ext(RISCVCPU *cpu, CPUState *cs) |
| 206 | { |
| 207 | CPURISCVState *env = &cpu->env; |
| 208 | uint64_t id, reg; |
| 209 | int i, ret; |
| 210 | |
| 211 | for (i = 0; i < ARRAY_SIZE(kvm_misa_ext_cfgs); i++) { |
| 212 | KVMCPUConfig *misa_cfg = &kvm_misa_ext_cfgs[i]; |
| 213 | target_ulong misa_bit = misa_cfg->offset; |
| 214 | |
| 215 | if (!misa_cfg->user_set) { |
| 216 | continue; |
| 217 | } |
| 218 | |
| 219 | /* If we're here we're going to disable the MISA bit */ |
| 220 | reg = 0; |
| 221 | id = KVM_RISCV_REG_ID_ULONG(KVM_REG_RISCV_ISA_EXT, |
| 222 | misa_cfg->kvm_reg_id); |
| 223 | ret = kvm_set_one_reg(cs, id, ®); |
| 224 | if (ret != 0) { |
| 225 | /* |
| 226 | * We're not checking for -EINVAL because if the bit is about |
| 227 | * to be disabled, it means that it was already enabled by |
| 228 | * KVM. We determined that by fetching the 'isa' register |
| 229 | * during init() time. Any error at this point is worth |
| 230 | * aborting. |
| 231 | */ |
| 232 | error_report("Unable to set KVM reg %s, error %d", |
| 233 | misa_cfg->name, ret); |
| 234 | exit(EXIT_FAILURE); |
| 235 | } |
| 236 | env->misa_ext &= ~misa_bit; |
| 237 | } |
| 238 | } |
| 239 | |
| 240 | #define KVM_CSR_CFG(_name, _env_prop, reg_id) \ |
| 241 | {.name = _name, .offset = ENV_CSR_OFFSET(_env_prop), \ |
| 242 | .prop_size = sizeof(((CPURISCVState *)0)->_env_prop), \ |
| 243 | .kvm_reg_id = reg_id} |
| 244 | |
| 245 | static KVMCPUConfig kvm_csr_cfgs[] = { |
| 246 | KVM_CSR_CFG("sstatus", mstatus, RISCV_CSR_REG(sstatus)), |
| 247 | KVM_CSR_CFG("sie", mie, RISCV_CSR_REG(sie)), |
| 248 | KVM_CSR_CFG("stvec", stvec, RISCV_CSR_REG(stvec)), |
| 249 | KVM_CSR_CFG("sscratch", sscratch, RISCV_CSR_REG(sscratch)), |
| 250 | KVM_CSR_CFG("sepc", sepc, RISCV_CSR_REG(sepc)), |
| 251 | KVM_CSR_CFG("scause", scause, RISCV_CSR_REG(scause)), |
| 252 | KVM_CSR_CFG("stval", stval, RISCV_CSR_REG(stval)), |
| 253 | KVM_CSR_CFG("sip", mip, RISCV_CSR_REG(sip)), |
| 254 | KVM_CSR_CFG("satp", satp, RISCV_CSR_REG(satp)), |
| 255 | KVM_CSR_CFG("scounteren", scounteren, RISCV_CSR_REG(scounteren)), |
| 256 | KVM_CSR_CFG("senvcfg", senvcfg, RISCV_CSR_REG(senvcfg)), |
| 257 | }; |
| 258 | |
| 259 | static void *kvmconfig_get_env_addr(RISCVCPU *cpu, KVMCPUConfig *csr_cfg) |
| 260 | { |
| 261 | return (void *)&cpu->env + csr_cfg->offset; |
| 262 | } |
| 263 | |
| 264 | static uint32_t kvm_cpu_csr_get_u32(RISCVCPU *cpu, KVMCPUConfig *csr_cfg) |
| 265 | { |
| 266 | uint32_t *val32 = kvmconfig_get_env_addr(cpu, csr_cfg); |
| 267 | return *val32; |
| 268 | } |
| 269 | |
| 270 | static uint64_t kvm_cpu_csr_get_u64(RISCVCPU *cpu, KVMCPUConfig *csr_cfg) |
| 271 | { |
| 272 | uint64_t *val64 = kvmconfig_get_env_addr(cpu, csr_cfg); |
| 273 | return *val64; |
| 274 | } |
| 275 | |
| 276 | static void kvm_cpu_csr_set_u32(RISCVCPU *cpu, KVMCPUConfig *csr_cfg, |
| 277 | uint32_t val) |
| 278 | { |
| 279 | uint32_t *val32 = kvmconfig_get_env_addr(cpu, csr_cfg); |
| 280 | *val32 = val; |
| 281 | } |
| 282 | |
| 283 | static void kvm_cpu_csr_set_u64(RISCVCPU *cpu, KVMCPUConfig *csr_cfg, |
| 284 | uint64_t val) |
| 285 | { |
| 286 | uint64_t *val64 = kvmconfig_get_env_addr(cpu, csr_cfg); |
| 287 | *val64 = val; |
| 288 | } |
| 289 | |
| 290 | #define KVM_EXT_CFG(_name, _prop, _reg_id) \ |
| 291 | {.name = _name, .offset = CPU_CFG_OFFSET(_prop), \ |
| 292 | .kvm_reg_id = _reg_id} |
| 293 | |
| 294 | static KVMCPUConfig kvm_multi_ext_cfgs[] = { |
| 295 | KVM_EXT_CFG("zicbom", ext_zicbom, KVM_RISCV_ISA_EXT_ZICBOM), |
| 296 | KVM_EXT_CFG("zicbop", ext_zicbop, KVM_RISCV_ISA_EXT_ZICBOP), |
| 297 | KVM_EXT_CFG("zicboz", ext_zicboz, KVM_RISCV_ISA_EXT_ZICBOZ), |
| 298 | KVM_EXT_CFG("ziccrse", ext_ziccrse, KVM_RISCV_ISA_EXT_ZICCRSE), |
| 299 | KVM_EXT_CFG("zicntr", ext_zicntr, KVM_RISCV_ISA_EXT_ZICNTR), |
| 300 | KVM_EXT_CFG("zicond", ext_zicond, KVM_RISCV_ISA_EXT_ZICOND), |
| 301 | KVM_EXT_CFG("zicsr", ext_zicsr, KVM_RISCV_ISA_EXT_ZICSR), |
| 302 | KVM_EXT_CFG("zifencei", ext_zifencei, KVM_RISCV_ISA_EXT_ZIFENCEI), |
| 303 | KVM_EXT_CFG("zihintntl", ext_zihintntl, KVM_RISCV_ISA_EXT_ZIHINTNTL), |
| 304 | KVM_EXT_CFG("zihintpause", ext_zihintpause, KVM_RISCV_ISA_EXT_ZIHINTPAUSE), |
| 305 | KVM_EXT_CFG("zihpm", ext_zihpm, KVM_RISCV_ISA_EXT_ZIHPM), |
| 306 | KVM_EXT_CFG("zilsd", ext_zilsd, KVM_RISCV_ISA_EXT_ZILSD), |
| 307 | KVM_EXT_CFG("zimop", ext_zimop, KVM_RISCV_ISA_EXT_ZIMOP), |
| 308 | KVM_EXT_CFG("zcmop", ext_zcmop, KVM_RISCV_ISA_EXT_ZCMOP), |
| 309 | KVM_EXT_CFG("zclsd", ext_zclsd, KVM_RISCV_ISA_EXT_ZCLSD), |
| 310 | KVM_EXT_CFG("zabha", ext_zabha, KVM_RISCV_ISA_EXT_ZABHA), |
| 311 | KVM_EXT_CFG("zacas", ext_zacas, KVM_RISCV_ISA_EXT_ZACAS), |
| 312 | KVM_EXT_CFG("zalasr", ext_zalasr, KVM_RISCV_ISA_EXT_ZALASR), |
| 313 | KVM_EXT_CFG("zawrs", ext_zawrs, KVM_RISCV_ISA_EXT_ZAWRS), |
| 314 | KVM_EXT_CFG("zfa", ext_zfa, KVM_RISCV_ISA_EXT_ZFA), |
| 315 | KVM_EXT_CFG("zfbfmin", ext_zfbfmin, KVM_RISCV_ISA_EXT_ZFBFMIN), |
| 316 | KVM_EXT_CFG("zfh", ext_zfh, KVM_RISCV_ISA_EXT_ZFH), |
| 317 | KVM_EXT_CFG("zfhmin", ext_zfhmin, KVM_RISCV_ISA_EXT_ZFHMIN), |
| 318 | KVM_EXT_CFG("zba", ext_zba, KVM_RISCV_ISA_EXT_ZBA), |
| 319 | KVM_EXT_CFG("zbb", ext_zbb, KVM_RISCV_ISA_EXT_ZBB), |
| 320 | KVM_EXT_CFG("zbc", ext_zbc, KVM_RISCV_ISA_EXT_ZBC), |
| 321 | KVM_EXT_CFG("zbkb", ext_zbkb, KVM_RISCV_ISA_EXT_ZBKB), |
| 322 | KVM_EXT_CFG("zbkc", ext_zbkc, KVM_RISCV_ISA_EXT_ZBKC), |
| 323 | KVM_EXT_CFG("zbkx", ext_zbkx, KVM_RISCV_ISA_EXT_ZBKX), |
| 324 | KVM_EXT_CFG("zbs", ext_zbs, KVM_RISCV_ISA_EXT_ZBS), |
| 325 | KVM_EXT_CFG("zca", ext_zca, KVM_RISCV_ISA_EXT_ZCA), |
| 326 | KVM_EXT_CFG("zcb", ext_zcb, KVM_RISCV_ISA_EXT_ZCB), |
| 327 | KVM_EXT_CFG("zcd", ext_zcd, KVM_RISCV_ISA_EXT_ZCD), |
| 328 | KVM_EXT_CFG("zcf", ext_zcf, KVM_RISCV_ISA_EXT_ZCF), |
| 329 | KVM_EXT_CFG("zknd", ext_zknd, KVM_RISCV_ISA_EXT_ZKND), |
| 330 | KVM_EXT_CFG("zkne", ext_zkne, KVM_RISCV_ISA_EXT_ZKNE), |
| 331 | KVM_EXT_CFG("zknh", ext_zknh, KVM_RISCV_ISA_EXT_ZKNH), |
| 332 | KVM_EXT_CFG("zkr", ext_zkr, KVM_RISCV_ISA_EXT_ZKR), |
| 333 | KVM_EXT_CFG("zksed", ext_zksed, KVM_RISCV_ISA_EXT_ZKSED), |
| 334 | KVM_EXT_CFG("zksh", ext_zksh, KVM_RISCV_ISA_EXT_ZKSH), |
| 335 | KVM_EXT_CFG("zkt", ext_zkt, KVM_RISCV_ISA_EXT_ZKT), |
| 336 | KVM_EXT_CFG("ztso", ext_ztso, KVM_RISCV_ISA_EXT_ZTSO), |
| 337 | KVM_EXT_CFG("zvbb", ext_zvbb, KVM_RISCV_ISA_EXT_ZVBB), |
| 338 | KVM_EXT_CFG("zvbc", ext_zvbc, KVM_RISCV_ISA_EXT_ZVBC), |
| 339 | KVM_EXT_CFG("zvfh", ext_zvfh, KVM_RISCV_ISA_EXT_ZVFH), |
| 340 | KVM_EXT_CFG("zvfhmin", ext_zvfhmin, KVM_RISCV_ISA_EXT_ZVFHMIN), |
| 341 | KVM_EXT_CFG("zvfbfmin", ext_zvfbfmin, KVM_RISCV_ISA_EXT_ZVFBFMIN), |
| 342 | KVM_EXT_CFG("zvfbfwma", ext_zvfbfwma, KVM_RISCV_ISA_EXT_ZVFBFWMA), |
| 343 | KVM_EXT_CFG("zvkb", ext_zvkb, KVM_RISCV_ISA_EXT_ZVKB), |
| 344 | KVM_EXT_CFG("zvkg", ext_zvkg, KVM_RISCV_ISA_EXT_ZVKG), |
| 345 | KVM_EXT_CFG("zvkned", ext_zvkned, KVM_RISCV_ISA_EXT_ZVKNED), |
| 346 | KVM_EXT_CFG("zvknha", ext_zvknha, KVM_RISCV_ISA_EXT_ZVKNHA), |
| 347 | KVM_EXT_CFG("zvknhb", ext_zvknhb, KVM_RISCV_ISA_EXT_ZVKNHB), |
| 348 | KVM_EXT_CFG("zvksed", ext_zvksed, KVM_RISCV_ISA_EXT_ZVKSED), |
| 349 | KVM_EXT_CFG("zvksh", ext_zvksh, KVM_RISCV_ISA_EXT_ZVKSH), |
| 350 | KVM_EXT_CFG("zvkt", ext_zvkt, KVM_RISCV_ISA_EXT_ZVKT), |
| 351 | KVM_EXT_CFG("smnpm", ext_smnpm, KVM_RISCV_ISA_EXT_SMNPM), |
| 352 | KVM_EXT_CFG("smstateen", ext_smstateen, KVM_RISCV_ISA_EXT_SMSTATEEN), |
| 353 | KVM_EXT_CFG("ssaia", ext_ssaia, KVM_RISCV_ISA_EXT_SSAIA), |
| 354 | KVM_EXT_CFG("sscofpmf", ext_sscofpmf, KVM_RISCV_ISA_EXT_SSCOFPMF), |
| 355 | KVM_EXT_CFG("ssnpm", ext_ssnpm, KVM_RISCV_ISA_EXT_SSNPM), |
| 356 | KVM_EXT_CFG("sstc", ext_sstc, KVM_RISCV_ISA_EXT_SSTC), |
| 357 | KVM_EXT_CFG("svade", ext_svade, KVM_RISCV_ISA_EXT_SVADE), |
| 358 | KVM_EXT_CFG("svadu", ext_svadu, KVM_RISCV_ISA_EXT_SVADU), |
| 359 | KVM_EXT_CFG("svinval", ext_svinval, KVM_RISCV_ISA_EXT_SVINVAL), |
| 360 | KVM_EXT_CFG("svnapot", ext_svnapot, KVM_RISCV_ISA_EXT_SVNAPOT), |
| 361 | KVM_EXT_CFG("svpbmt", ext_svpbmt, KVM_RISCV_ISA_EXT_SVPBMT), |
| 362 | KVM_EXT_CFG("svvptc", ext_svvptc, KVM_RISCV_ISA_EXT_SVVPTC), |
| 363 | }; |
| 364 | |
| 365 | static void *kvmconfig_get_cfg_addr(RISCVCPU *cpu, KVMCPUConfig *kvmcfg) |
| 366 | { |
| 367 | return (void *)&cpu->cfg + kvmcfg->offset; |
| 368 | } |
| 369 | |
| 370 | static void kvm_cpu_cfg_set(RISCVCPU *cpu, KVMCPUConfig *multi_ext, |
| 371 | uint32_t val) |
| 372 | { |
| 373 | bool *ext_enabled = kvmconfig_get_cfg_addr(cpu, multi_ext); |
| 374 | |
| 375 | *ext_enabled = val; |
| 376 | } |
| 377 | |
| 378 | static uint32_t kvm_cpu_cfg_get(RISCVCPU *cpu, |
| 379 | KVMCPUConfig *multi_ext) |
| 380 | { |
| 381 | bool *ext_enabled = kvmconfig_get_cfg_addr(cpu, multi_ext); |
| 382 | |
| 383 | return *ext_enabled; |
| 384 | } |
| 385 | |
| 386 | static void kvm_cpu_get_multi_ext_cfg(Object *obj, Visitor *v, |
| 387 | const char *name, |
| 388 | void *opaque, Error **errp) |
| 389 | { |
| 390 | KVMCPUConfig *multi_ext_cfg = opaque; |
| 391 | RISCVCPU *cpu = RISCV_CPU(obj); |
| 392 | bool value = kvm_cpu_cfg_get(cpu, multi_ext_cfg); |
| 393 | |
| 394 | visit_type_bool(v, name, &value, errp); |
| 395 | } |
| 396 | |
| 397 | static void kvm_cpu_set_multi_ext_cfg(Object *obj, Visitor *v, |
| 398 | const char *name, |
| 399 | void *opaque, Error **errp) |
| 400 | { |
| 401 | KVMCPUConfig *multi_ext_cfg = opaque; |
| 402 | RISCVCPU *cpu = RISCV_CPU(obj); |
| 403 | bool value, host_val; |
| 404 | |
| 405 | if (!visit_type_bool(v, name, &value, errp)) { |
| 406 | return; |
| 407 | } |
| 408 | |
| 409 | host_val = kvm_cpu_cfg_get(cpu, multi_ext_cfg); |
| 410 | |
| 411 | /* |
| 412 | * Ignore if the user is setting the same value |
| 413 | * as the host. |
| 414 | */ |
| 415 | if (value == host_val) { |
| 416 | return; |
| 417 | } |
| 418 | |
| 419 | if (!multi_ext_cfg->supported) { |
| 420 | /* |
| 421 | * Error out if the user is trying to enable an |
| 422 | * extension that KVM doesn't support. Ignore |
| 423 | * option otherwise. |
| 424 | */ |
| 425 | if (value) { |
| 426 | error_setg(errp, "KVM does not support disabling extension %s", |
| 427 | multi_ext_cfg->name); |
| 428 | } |
| 429 | |
| 430 | return; |
| 431 | } |
| 432 | |
| 433 | multi_ext_cfg->user_set = true; |
| 434 | kvm_cpu_cfg_set(cpu, multi_ext_cfg, value); |
| 435 | } |
| 436 | |
| 437 | static KVMCPUConfig kvm_cbom_blocksize = { |
| 438 | .name = "cbom_blocksize", |
| 439 | .offset = CPU_CFG_OFFSET(cbom_blocksize), |
| 440 | .kvm_reg_id = KVM_REG_RISCV_CONFIG_REG(zicbom_block_size) |
| 441 | }; |
| 442 | |
| 443 | static KVMCPUConfig kvm_cboz_blocksize = { |
| 444 | .name = "cboz_blocksize", |
| 445 | .offset = CPU_CFG_OFFSET(cboz_blocksize), |
| 446 | .kvm_reg_id = KVM_REG_RISCV_CONFIG_REG(zicboz_block_size) |
| 447 | }; |
| 448 | |
| 449 | static KVMCPUConfig kvm_cbop_blocksize = { |
| 450 | .name = "cbop_blocksize", |
| 451 | .offset = CPU_CFG_OFFSET(cbop_blocksize), |
| 452 | .kvm_reg_id = KVM_REG_RISCV_CONFIG_REG(zicbop_block_size) |
| 453 | }; |
| 454 | |
| 455 | static KVMCPUConfig kvm_v_vlenb = { |
| 456 | .name = "vlenb", |
| 457 | .offset = CPU_CFG_OFFSET(vlenb), |
| 458 | .kvm_reg_id = KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_VECTOR | |
| 459 | KVM_REG_RISCV_VECTOR_CSR_REG(vlenb) |
| 460 | }; |
| 461 | |
| 462 | static KVMCPUConfig kvm_sbi_dbcn = { |
| 463 | .name = "sbi_dbcn", |
| 464 | .kvm_reg_id = KVM_REG_RISCV | KVM_REG_SIZE_U64 | |
| 465 | KVM_REG_RISCV_SBI_EXT | KVM_RISCV_SBI_EXT_DBCN |
| 466 | }; |
| 467 | |
| 468 | static void kvm_riscv_update_cpu_cfg_isa_ext(RISCVCPU *cpu, CPUState *cs) |
| 469 | { |
| 470 | uint64_t id, reg; |
| 471 | int i, ret; |
| 472 | |
| 473 | for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) { |
| 474 | KVMCPUConfig *multi_ext_cfg = &kvm_multi_ext_cfgs[i]; |
| 475 | |
| 476 | if (!multi_ext_cfg->user_set) { |
| 477 | continue; |
| 478 | } |
| 479 | |
| 480 | id = KVM_RISCV_REG_ID_ULONG(KVM_REG_RISCV_ISA_EXT, |
| 481 | multi_ext_cfg->kvm_reg_id); |
| 482 | reg = kvm_cpu_cfg_get(cpu, multi_ext_cfg); |
| 483 | ret = kvm_set_one_reg(cs, id, ®); |
| 484 | if (ret != 0) { |
| 485 | if (!reg && ret == -EINVAL) { |
| 486 | warn_report("KVM cannot disable extension %s", |
| 487 | multi_ext_cfg->name); |
| 488 | } else { |
| 489 | error_report("Unable to enable extension %s in KVM, error %d", |
| 490 | multi_ext_cfg->name, ret); |
| 491 | exit(EXIT_FAILURE); |
| 492 | } |
| 493 | } |
| 494 | } |
| 495 | } |
| 496 | |
| 497 | static void cpu_get_cfg_unavailable(Object *obj, Visitor *v, |
| 498 | const char *name, |
| 499 | void *opaque, Error **errp) |
| 500 | { |
| 501 | bool value = false; |
| 502 | |
| 503 | visit_type_bool(v, name, &value, errp); |
| 504 | } |
| 505 | |
| 506 | static void cpu_set_cfg_unavailable(Object *obj, Visitor *v, |
| 507 | const char *name, |
| 508 | void *opaque, Error **errp) |
| 509 | { |
| 510 | const char *propname = opaque; |
| 511 | bool value; |
| 512 | |
| 513 | if (!visit_type_bool(v, name, &value, errp)) { |
| 514 | return; |
| 515 | } |
| 516 | |
| 517 | if (value) { |
| 518 | error_setg(errp, "'%s' is not available with KVM", |
| 519 | propname); |
| 520 | } |
| 521 | } |
| 522 | |
| 523 | static void riscv_cpu_add_kvm_unavail_prop(Object *obj, const char *prop_name) |
| 524 | { |
| 525 | /* Check if KVM created the property already */ |
| 526 | if (object_property_find(obj, prop_name)) { |
| 527 | return; |
| 528 | } |
| 529 | |
| 530 | /* |
| 531 | * Set the default to disabled for every extension |
| 532 | * unknown to KVM and error out if the user attempts |
| 533 | * to enable any of them. |
| 534 | */ |
| 535 | object_property_add(obj, prop_name, "bool", |
| 536 | cpu_get_cfg_unavailable, |
| 537 | cpu_set_cfg_unavailable, |
| 538 | NULL, (void *)prop_name); |
| 539 | } |
| 540 | |
| 541 | static void kvm_riscv_add_cpu_user_properties(Object *cpu_obj) |
| 542 | { |
| 543 | const RISCVIsaExtData *edata; |
| 544 | int i; |
| 545 | |
| 546 | riscv_add_satp_mode_properties(cpu_obj); |
| 547 | |
| 548 | for (i = 0; i < ARRAY_SIZE(kvm_misa_ext_cfgs); i++) { |
| 549 | KVMCPUConfig *misa_cfg = &kvm_misa_ext_cfgs[i]; |
| 550 | int bit = misa_cfg->offset; |
| 551 | |
| 552 | misa_cfg->name = riscv_get_misa_ext_name(bit); |
| 553 | misa_cfg->description = riscv_get_misa_ext_description(bit); |
| 554 | |
| 555 | object_property_add(cpu_obj, misa_cfg->name, "bool", |
| 556 | kvm_cpu_get_misa_ext_cfg, |
| 557 | kvm_cpu_set_misa_ext_cfg, |
| 558 | NULL, misa_cfg); |
| 559 | object_property_set_description(cpu_obj, misa_cfg->name, |
| 560 | misa_cfg->description); |
| 561 | } |
| 562 | |
| 563 | for (i = 0; misa_bits[i] != 0; i++) { |
| 564 | const char *ext_name = riscv_get_misa_ext_name(misa_bits[i]); |
| 565 | riscv_cpu_add_kvm_unavail_prop(cpu_obj, ext_name); |
| 566 | } |
| 567 | |
| 568 | for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) { |
| 569 | KVMCPUConfig *multi_cfg = &kvm_multi_ext_cfgs[i]; |
| 570 | |
| 571 | object_property_add(cpu_obj, multi_cfg->name, "bool", |
| 572 | kvm_cpu_get_multi_ext_cfg, |
| 573 | kvm_cpu_set_multi_ext_cfg, |
| 574 | NULL, multi_cfg); |
| 575 | } |
| 576 | |
| 577 | /* |
| 578 | * Mark all isa_edata_arr properties that collides with |
| 579 | * a KVM property as unavailable. |
| 580 | */ |
| 581 | for (edata = isa_edata_arr; edata && edata->name; edata++) { |
| 582 | if (edata->prop_name) { |
| 583 | riscv_cpu_add_kvm_unavail_prop(cpu_obj, edata->prop_name); |
| 584 | } |
| 585 | } |
| 586 | |
| 587 | /* We don't have the needed KVM support for profiles */ |
| 588 | for (i = 0; riscv_profiles[i] != NULL; i++) { |
| 589 | riscv_cpu_add_kvm_unavail_prop(cpu_obj, riscv_profiles[i]->name); |
| 590 | } |
| 591 | } |
| 592 | |
| 593 | static int kvm_riscv_get_regs_core(CPUState *cs) |
| 594 | { |
| 595 | int ret = 0; |
| 596 | int i; |
| 597 | target_ulong reg; |
| 598 | CPURISCVState *env = &RISCV_CPU(cs)->env; |
| 599 | |
| 600 | ret = kvm_get_one_reg(cs, RISCV_CORE_REG(regs.pc), ®); |
| 601 | if (ret) { |
| 602 | return ret; |
| 603 | } |
| 604 | env->pc = reg; |
| 605 | |
| 606 | ret = kvm_get_one_reg(cs, RISCV_CORE_REG(mode), ®); |
| 607 | if (ret) { |
| 608 | return ret; |
| 609 | } |
| 610 | env->priv = reg; |
| 611 | |
| 612 | for (i = 1; i < 32; i++) { |
| 613 | uint64_t id = KVM_RISCV_REG_ID_ULONG(KVM_REG_RISCV_CORE, i); |
| 614 | ret = kvm_get_one_reg(cs, id, ®); |
| 615 | if (ret) { |
| 616 | return ret; |
| 617 | } |
| 618 | env->gpr[i] = reg; |
| 619 | } |
| 620 | |
| 621 | return ret; |
| 622 | } |
| 623 | |
| 624 | static int kvm_riscv_put_regs_core(CPUState *cs) |
| 625 | { |
| 626 | int ret = 0; |
| 627 | int i; |
| 628 | target_ulong reg; |
| 629 | CPURISCVState *env = &RISCV_CPU(cs)->env; |
| 630 | |
| 631 | reg = env->pc; |
| 632 | ret = kvm_set_one_reg(cs, RISCV_CORE_REG(regs.pc), ®); |
| 633 | if (ret) { |
| 634 | return ret; |
| 635 | } |
| 636 | |
| 637 | reg = env->priv; |
| 638 | ret = kvm_set_one_reg(cs, RISCV_CORE_REG(mode), ®); |
| 639 | if (ret) { |
| 640 | return ret; |
| 641 | } |
| 642 | |
| 643 | for (i = 1; i < 32; i++) { |
| 644 | uint64_t id = KVM_RISCV_REG_ID_ULONG(KVM_REG_RISCV_CORE, i); |
| 645 | reg = env->gpr[i]; |
| 646 | ret = kvm_set_one_reg(cs, id, ®); |
| 647 | if (ret) { |
| 648 | return ret; |
| 649 | } |
| 650 | } |
| 651 | |
| 652 | return ret; |
| 653 | } |
| 654 | |
| 655 | static int kvm_riscv_get_regs_csr(CPUState *cs) |
| 656 | { |
| 657 | RISCVCPU *cpu = RISCV_CPU(cs); |
| 658 | uint64_t reg; |
| 659 | int i, ret; |
| 660 | |
| 661 | for (i = 0; i < ARRAY_SIZE(kvm_csr_cfgs); i++) { |
| 662 | KVMCPUConfig *csr_cfg = &kvm_csr_cfgs[i]; |
| 663 | |
| 664 | if (!csr_cfg->supported) { |
| 665 | continue; |
| 666 | } |
| 667 | |
| 668 | ret = kvm_get_one_reg(cs, csr_cfg->kvm_reg_id, ®); |
| 669 | if (ret) { |
| 670 | return ret; |
| 671 | } |
| 672 | |
| 673 | if (csr_cfg->prop_size == sizeof(uint32_t)) { |
| 674 | kvm_cpu_csr_set_u32(cpu, csr_cfg, (uint32_t)reg); |
| 675 | } else if (csr_cfg->prop_size == sizeof(uint64_t)) { |
| 676 | kvm_cpu_csr_set_u64(cpu, csr_cfg, reg); |
| 677 | } else { |
| 678 | g_assert_not_reached(); |
| 679 | } |
| 680 | } |
| 681 | |
| 682 | return 0; |
| 683 | } |
| 684 | |
| 685 | static int kvm_riscv_put_regs_csr(CPUState *cs) |
| 686 | { |
| 687 | RISCVCPU *cpu = RISCV_CPU(cs); |
| 688 | uint64_t reg; |
| 689 | int i, ret; |
| 690 | |
| 691 | for (i = 0; i < ARRAY_SIZE(kvm_csr_cfgs); i++) { |
| 692 | KVMCPUConfig *csr_cfg = &kvm_csr_cfgs[i]; |
| 693 | |
| 694 | if (!csr_cfg->supported) { |
| 695 | continue; |
| 696 | } |
| 697 | |
| 698 | if (csr_cfg->prop_size == sizeof(uint32_t)) { |
| 699 | reg = kvm_cpu_csr_get_u32(cpu, csr_cfg); |
| 700 | } else if (csr_cfg->prop_size == sizeof(uint64_t)) { |
| 701 | reg = kvm_cpu_csr_get_u64(cpu, csr_cfg); |
| 702 | } else { |
| 703 | g_assert_not_reached(); |
| 704 | } |
| 705 | |
| 706 | ret = kvm_set_one_reg(cs, csr_cfg->kvm_reg_id, ®); |
| 707 | if (ret) { |
| 708 | return ret; |
| 709 | } |
| 710 | } |
| 711 | |
| 712 | return 0; |
| 713 | } |
| 714 | |
| 715 | static void kvm_riscv_reset_regs_csr(CPURISCVState *env) |
| 716 | { |
| 717 | env->mstatus = 0; |
| 718 | env->mie = 0; |
| 719 | env->stvec = 0; |
| 720 | env->sscratch = 0; |
| 721 | env->sepc = 0; |
| 722 | env->scause = 0; |
| 723 | env->stval = 0; |
| 724 | env->mip = 0; |
| 725 | env->satp = 0; |
| 726 | env->scounteren = 0; |
| 727 | env->senvcfg = 0; |
| 728 | env->priv = PRV_S; |
| 729 | } |
| 730 | |
| 731 | static int kvm_riscv_get_regs_fp(CPUState *cs) |
| 732 | { |
| 733 | int ret = 0; |
| 734 | int i; |
| 735 | CPURISCVState *env = &RISCV_CPU(cs)->env; |
| 736 | |
| 737 | if (riscv_has_ext(env, RVD)) { |
| 738 | uint64_t reg; |
| 739 | for (i = 0; i < 32; i++) { |
| 740 | ret = kvm_get_one_reg(cs, RISCV_FP_D_REG(i), ®); |
| 741 | if (ret) { |
| 742 | return ret; |
| 743 | } |
| 744 | env->fpr[i] = reg; |
| 745 | } |
| 746 | return ret; |
| 747 | } |
| 748 | |
| 749 | if (riscv_has_ext(env, RVF)) { |
| 750 | uint32_t reg; |
| 751 | for (i = 0; i < 32; i++) { |
| 752 | ret = kvm_get_one_reg(cs, RISCV_FP_F_REG(i), ®); |
| 753 | if (ret) { |
| 754 | return ret; |
| 755 | } |
| 756 | env->fpr[i] = reg; |
| 757 | } |
| 758 | return ret; |
| 759 | } |
| 760 | |
| 761 | return ret; |
| 762 | } |
| 763 | |
| 764 | static int kvm_riscv_put_regs_fp(CPUState *cs) |
| 765 | { |
| 766 | int ret = 0; |
| 767 | int i; |
| 768 | CPURISCVState *env = &RISCV_CPU(cs)->env; |
| 769 | |
| 770 | if (riscv_has_ext(env, RVD)) { |
| 771 | uint64_t reg; |
| 772 | for (i = 0; i < 32; i++) { |
| 773 | reg = env->fpr[i]; |
| 774 | ret = kvm_set_one_reg(cs, RISCV_FP_D_REG(i), ®); |
| 775 | if (ret) { |
| 776 | return ret; |
| 777 | } |
| 778 | } |
| 779 | return ret; |
| 780 | } |
| 781 | |
| 782 | if (riscv_has_ext(env, RVF)) { |
| 783 | uint32_t reg; |
| 784 | for (i = 0; i < 32; i++) { |
| 785 | reg = env->fpr[i]; |
| 786 | ret = kvm_set_one_reg(cs, RISCV_FP_F_REG(i), ®); |
| 787 | if (ret) { |
| 788 | return ret; |
| 789 | } |
| 790 | } |
| 791 | return ret; |
| 792 | } |
| 793 | |
| 794 | return ret; |
| 795 | } |
| 796 | |
| 797 | static void kvm_riscv_get_regs_timer(CPUState *cs) |
| 798 | { |
| 799 | CPURISCVState *env = &RISCV_CPU(cs)->env; |
| 800 | |
| 801 | if (env->kvm_timer_dirty) { |
| 802 | return; |
| 803 | } |
| 804 | |
| 805 | KVM_RISCV_GET_TIMER(cs, time, env->kvm_timer_time); |
| 806 | KVM_RISCV_GET_TIMER(cs, compare, env->kvm_timer_compare); |
| 807 | KVM_RISCV_GET_TIMER(cs, state, env->kvm_timer_state); |
| 808 | KVM_RISCV_GET_TIMER(cs, frequency, env->kvm_timer_frequency); |
| 809 | |
| 810 | env->kvm_timer_dirty = true; |
| 811 | } |
| 812 | |
| 813 | static void kvm_riscv_put_regs_timer(CPUState *cs) |
| 814 | { |
| 815 | uint64_t reg; |
| 816 | CPURISCVState *env = &RISCV_CPU(cs)->env; |
| 817 | |
| 818 | if (!env->kvm_timer_dirty) { |
| 819 | return; |
| 820 | } |
| 821 | |
| 822 | KVM_RISCV_SET_TIMER(cs, time, env->kvm_timer_time); |
| 823 | KVM_RISCV_SET_TIMER(cs, compare, env->kvm_timer_compare); |
| 824 | |
| 825 | /* |
| 826 | * To set register of RISCV_TIMER_REG(state) will occur a error from KVM |
| 827 | * on env->kvm_timer_state == 0, It's better to adapt in KVM, but it |
| 828 | * doesn't matter that adaping in QEMU now. |
| 829 | * TODO If KVM changes, adapt here. |
| 830 | */ |
| 831 | if (env->kvm_timer_state) { |
| 832 | KVM_RISCV_SET_TIMER(cs, state, env->kvm_timer_state); |
| 833 | } |
| 834 | |
| 835 | /* |
| 836 | * For now, migration will not work between Hosts with different timer |
| 837 | * frequency. Therefore, we should check whether they are the same here |
| 838 | * during the migration. |
| 839 | */ |
| 840 | if (migration_is_running()) { |
| 841 | KVM_RISCV_GET_TIMER(cs, frequency, reg); |
| 842 | if (reg != env->kvm_timer_frequency) { |
| 843 | error_report("Dst Hosts timer frequency != Src Hosts"); |
| 844 | } |
| 845 | } |
| 846 | |
| 847 | env->kvm_timer_dirty = false; |
| 848 | } |
| 849 | |
| 850 | uint64_t kvm_riscv_get_timebase_frequency(RISCVCPU *cpu) |
| 851 | { |
| 852 | uint64_t reg; |
| 853 | |
| 854 | KVM_RISCV_GET_TIMER(CPU(cpu), frequency, reg); |
| 855 | |
| 856 | return reg; |
| 857 | } |
| 858 | |
| 859 | static int kvm_riscv_get_regs_vector(CPUState *cs) |
| 860 | { |
| 861 | RISCVCPU *cpu = RISCV_CPU(cs); |
| 862 | CPURISCVState *env = &cpu->env; |
| 863 | target_ulong reg; |
| 864 | uint64_t vreg_id; |
| 865 | int vreg_idx, ret = 0; |
| 866 | |
| 867 | if (!riscv_has_ext(env, RVV)) { |
| 868 | return 0; |
| 869 | } |
| 870 | |
| 871 | ret = kvm_get_one_reg(cs, RISCV_VECTOR_CSR_REG(vstart), ®); |
| 872 | if (ret) { |
| 873 | return ret; |
| 874 | } |
| 875 | env->vstart = reg; |
| 876 | |
| 877 | ret = kvm_get_one_reg(cs, RISCV_VECTOR_CSR_REG(vl), ®); |
| 878 | if (ret) { |
| 879 | return ret; |
| 880 | } |
| 881 | env->vl = reg; |
| 882 | |
| 883 | ret = kvm_get_one_reg(cs, RISCV_VECTOR_CSR_REG(vtype), ®); |
| 884 | if (ret) { |
| 885 | return ret; |
| 886 | } |
| 887 | env->vtype = reg; |
| 888 | |
| 889 | if (kvm_v_vlenb.supported) { |
| 890 | ret = kvm_get_one_reg(cs, RISCV_VECTOR_CSR_REG(vlenb), ®); |
| 891 | if (ret) { |
| 892 | return ret; |
| 893 | } |
| 894 | cpu->cfg.vlenb = reg; |
| 895 | |
| 896 | for (int i = 0; i < 32; i++) { |
| 897 | /* |
| 898 | * vreg[] is statically allocated using RV_VLEN_MAX. |
| 899 | * Use it instead of vlenb to calculate vreg_idx for |
| 900 | * simplicity. |
| 901 | */ |
| 902 | vreg_idx = i * RV_VLEN_MAX / 64; |
| 903 | vreg_id = kvm_riscv_vector_reg_id(cpu, i); |
| 904 | |
| 905 | ret = kvm_get_one_reg(cs, vreg_id, &env->vreg[vreg_idx]); |
| 906 | if (ret) { |
| 907 | return ret; |
| 908 | } |
| 909 | } |
| 910 | } |
| 911 | |
| 912 | return 0; |
| 913 | } |
| 914 | |
| 915 | static int kvm_riscv_put_regs_vector(CPUState *cs) |
| 916 | { |
| 917 | RISCVCPU *cpu = RISCV_CPU(cs); |
| 918 | CPURISCVState *env = &cpu->env; |
| 919 | target_ulong reg; |
| 920 | uint64_t vreg_id; |
| 921 | int vreg_idx, ret = 0; |
| 922 | |
| 923 | if (!riscv_has_ext(env, RVV)) { |
| 924 | return 0; |
| 925 | } |
| 926 | |
| 927 | reg = env->vstart; |
| 928 | ret = kvm_set_one_reg(cs, RISCV_VECTOR_CSR_REG(vstart), ®); |
| 929 | if (ret) { |
| 930 | return ret; |
| 931 | } |
| 932 | |
| 933 | reg = env->vl; |
| 934 | ret = kvm_set_one_reg(cs, RISCV_VECTOR_CSR_REG(vl), ®); |
| 935 | if (ret) { |
| 936 | return ret; |
| 937 | } |
| 938 | |
| 939 | reg = env->vtype; |
| 940 | ret = kvm_set_one_reg(cs, RISCV_VECTOR_CSR_REG(vtype), ®); |
| 941 | if (ret) { |
| 942 | return ret; |
| 943 | } |
| 944 | |
| 945 | if (kvm_v_vlenb.supported) { |
| 946 | reg = cpu->cfg.vlenb; |
| 947 | ret = kvm_set_one_reg(cs, RISCV_VECTOR_CSR_REG(vlenb), ®); |
| 948 | |
| 949 | for (int i = 0; i < 32; i++) { |
| 950 | /* |
| 951 | * vreg[] is statically allocated using RV_VLEN_MAX. |
| 952 | * Use it instead of vlenb to calculate vreg_idx for |
| 953 | * simplicity. |
| 954 | */ |
| 955 | vreg_idx = i * RV_VLEN_MAX / 64; |
| 956 | vreg_id = kvm_riscv_vector_reg_id(cpu, i); |
| 957 | |
| 958 | ret = kvm_set_one_reg(cs, vreg_id, &env->vreg[vreg_idx]); |
| 959 | if (ret) { |
| 960 | return ret; |
| 961 | } |
| 962 | } |
| 963 | } |
| 964 | |
| 965 | return ret; |
| 966 | } |
| 967 | |
| 968 | typedef struct KVMScratchCPU { |
| 969 | int kvmfd; |
| 970 | int vmfd; |
| 971 | int cpufd; |
| 972 | } KVMScratchCPU; |
| 973 | |
| 974 | /* |
| 975 | * Heavily inspired by kvm_arm_create_scratch_host_vcpu() |
| 976 | * from target/arm/kvm.c. |
| 977 | */ |
| 978 | static bool kvm_riscv_create_scratch_vcpu(KVMScratchCPU *scratch) |
| 979 | { |
| 980 | int kvmfd = -1, vmfd = -1, cpufd = -1; |
| 981 | |
| 982 | kvmfd = qemu_open_old("/dev/kvm", O_RDWR); |
| 983 | if (kvmfd < 0) { |
| 984 | goto err; |
| 985 | } |
| 986 | do { |
| 987 | vmfd = ioctl(kvmfd, KVM_CREATE_VM, 0); |
| 988 | } while (vmfd == -1 && errno == EINTR); |
| 989 | if (vmfd < 0) { |
| 990 | goto err; |
| 991 | } |
| 992 | cpufd = ioctl(vmfd, KVM_CREATE_VCPU, 0); |
| 993 | if (cpufd < 0) { |
| 994 | goto err; |
| 995 | } |
| 996 | |
| 997 | scratch->kvmfd = kvmfd; |
| 998 | scratch->vmfd = vmfd; |
| 999 | scratch->cpufd = cpufd; |
| 1000 | |
| 1001 | return true; |
| 1002 | |
| 1003 | err: |
| 1004 | if (cpufd >= 0) { |
| 1005 | close(cpufd); |
| 1006 | } |
| 1007 | if (vmfd >= 0) { |
| 1008 | close(vmfd); |
| 1009 | } |
| 1010 | if (kvmfd >= 0) { |
| 1011 | close(kvmfd); |
| 1012 | } |
| 1013 | |
| 1014 | return false; |
| 1015 | } |
| 1016 | |
| 1017 | static void kvm_riscv_destroy_scratch_vcpu(KVMScratchCPU *scratch) |
| 1018 | { |
| 1019 | close(scratch->cpufd); |
| 1020 | close(scratch->vmfd); |
| 1021 | close(scratch->kvmfd); |
| 1022 | } |
| 1023 | |
| 1024 | static void kvm_riscv_init_max_satp_mode(RISCVCPU *cpu, KVMScratchCPU *kvmcpu) |
| 1025 | { |
| 1026 | struct kvm_one_reg reg; |
| 1027 | int ret; |
| 1028 | |
| 1029 | reg.id = RISCV_CONFIG_REG(satp_mode); |
| 1030 | reg.addr = (uint64_t)&cpu->cfg.max_satp_mode; |
| 1031 | ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); |
| 1032 | if (ret != 0) { |
| 1033 | error_report("Unable to retrieve satp mode from host, error %d", ret); |
| 1034 | } |
| 1035 | } |
| 1036 | |
| 1037 | static void kvm_riscv_init_machine_ids(RISCVCPU *cpu, KVMScratchCPU *kvmcpu) |
| 1038 | { |
| 1039 | struct kvm_one_reg reg; |
| 1040 | int ret; |
| 1041 | |
| 1042 | reg.id = RISCV_CONFIG_REG(mvendorid); |
| 1043 | reg.addr = (uint64_t)&cpu->cfg.mvendorid; |
| 1044 | ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); |
| 1045 | if (ret != 0) { |
| 1046 | error_report("Unable to retrieve mvendorid from host, error %d", ret); |
| 1047 | } |
| 1048 | |
| 1049 | reg.id = RISCV_CONFIG_REG(marchid); |
| 1050 | reg.addr = (uint64_t)&cpu->cfg.marchid; |
| 1051 | ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); |
| 1052 | if (ret != 0) { |
| 1053 | error_report("Unable to retrieve marchid from host, error %d", ret); |
| 1054 | } |
| 1055 | |
| 1056 | reg.id = RISCV_CONFIG_REG(mimpid); |
| 1057 | reg.addr = (uint64_t)&cpu->cfg.mimpid; |
| 1058 | ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); |
| 1059 | if (ret != 0) { |
| 1060 | error_report("Unable to retrieve mimpid from host, error %d", ret); |
| 1061 | } |
| 1062 | } |
| 1063 | |
| 1064 | static void kvm_riscv_init_misa_ext_mask(RISCVCPU *cpu, |
| 1065 | KVMScratchCPU *kvmcpu) |
| 1066 | { |
| 1067 | CPURISCVState *env = &cpu->env; |
| 1068 | struct kvm_one_reg reg; |
| 1069 | int ret; |
| 1070 | |
| 1071 | reg.id = RISCV_CONFIG_REG(isa); |
| 1072 | reg.addr = (uint64_t)&env->misa_ext_mask; |
| 1073 | ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); |
| 1074 | |
| 1075 | if (ret) { |
| 1076 | error_report("Unable to fetch ISA register from KVM, " |
| 1077 | "error %d", ret); |
| 1078 | kvm_riscv_destroy_scratch_vcpu(kvmcpu); |
| 1079 | exit(EXIT_FAILURE); |
| 1080 | } |
| 1081 | |
| 1082 | env->misa_ext = env->misa_ext_mask; |
| 1083 | } |
| 1084 | |
| 1085 | static void kvm_riscv_read_cbomz_blksize(RISCVCPU *cpu, KVMScratchCPU *kvmcpu, |
| 1086 | KVMCPUConfig *cbomz_cfg) |
| 1087 | { |
| 1088 | struct kvm_one_reg reg; |
| 1089 | int ret; |
| 1090 | |
| 1091 | reg.id = KVM_RISCV_REG_ID_ULONG(KVM_REG_RISCV_CONFIG, |
| 1092 | cbomz_cfg->kvm_reg_id); |
| 1093 | reg.addr = (uint64_t)kvmconfig_get_cfg_addr(cpu, cbomz_cfg); |
| 1094 | ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); |
| 1095 | if (ret != 0) { |
| 1096 | error_report("Unable to read KVM reg %s, error %d", |
| 1097 | cbomz_cfg->name, ret); |
| 1098 | exit(EXIT_FAILURE); |
| 1099 | } |
| 1100 | } |
| 1101 | |
| 1102 | static void kvm_riscv_read_multiext_legacy(RISCVCPU *cpu, |
| 1103 | KVMScratchCPU *kvmcpu) |
| 1104 | { |
| 1105 | uint64_t val; |
| 1106 | int i, ret; |
| 1107 | |
| 1108 | for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) { |
| 1109 | KVMCPUConfig *multi_ext_cfg = &kvm_multi_ext_cfgs[i]; |
| 1110 | struct kvm_one_reg reg; |
| 1111 | |
| 1112 | reg.id = KVM_RISCV_REG_ID_ULONG(KVM_REG_RISCV_ISA_EXT, |
| 1113 | multi_ext_cfg->kvm_reg_id); |
| 1114 | reg.addr = (uint64_t)&val; |
| 1115 | ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); |
| 1116 | if (ret != 0) { |
| 1117 | if (errno == EINVAL) { |
| 1118 | /* Silently default to 'false' if KVM does not support it. */ |
| 1119 | multi_ext_cfg->supported = false; |
| 1120 | val = false; |
| 1121 | } else { |
| 1122 | error_report("Unable to read ISA_EXT KVM register %s: %s", |
| 1123 | multi_ext_cfg->name, strerror(errno)); |
| 1124 | exit(EXIT_FAILURE); |
| 1125 | } |
| 1126 | } else { |
| 1127 | multi_ext_cfg->supported = true; |
| 1128 | } |
| 1129 | |
| 1130 | kvm_cpu_cfg_set(cpu, multi_ext_cfg, val); |
| 1131 | } |
| 1132 | |
| 1133 | if (cpu->cfg.ext_zicbom) { |
| 1134 | kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cbom_blocksize); |
| 1135 | } |
| 1136 | |
| 1137 | if (cpu->cfg.ext_zicboz) { |
| 1138 | kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cboz_blocksize); |
| 1139 | } |
| 1140 | } |
| 1141 | |
| 1142 | static void kvm_riscv_read_csr_cfg_legacy(KVMScratchCPU *kvmcpu) |
| 1143 | { |
| 1144 | uint64_t val; |
| 1145 | int i, ret; |
| 1146 | |
| 1147 | for (i = 0; i < ARRAY_SIZE(kvm_csr_cfgs); i++) { |
| 1148 | KVMCPUConfig *csr_cfg = &kvm_csr_cfgs[i]; |
| 1149 | struct kvm_one_reg reg; |
| 1150 | |
| 1151 | reg.id = csr_cfg->kvm_reg_id; |
| 1152 | reg.addr = (uint64_t)&val; |
| 1153 | ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); |
| 1154 | if (ret != 0) { |
| 1155 | if (errno == EINVAL) { |
| 1156 | csr_cfg->supported = false; |
| 1157 | } else { |
| 1158 | error_report("Unable to read KVM CSR %s: %s", |
| 1159 | csr_cfg->name, strerror(errno)); |
| 1160 | exit(EXIT_FAILURE); |
| 1161 | } |
| 1162 | } else { |
| 1163 | csr_cfg->supported = true; |
| 1164 | } |
| 1165 | } |
| 1166 | } |
| 1167 | |
| 1168 | static int uint64_cmp(const void *a, const void *b) |
| 1169 | { |
| 1170 | uint64_t val1 = *(const uint64_t *)a; |
| 1171 | uint64_t val2 = *(const uint64_t *)b; |
| 1172 | |
| 1173 | if (val1 < val2) { |
| 1174 | return -1; |
| 1175 | } |
| 1176 | |
| 1177 | if (val1 > val2) { |
| 1178 | return 1; |
| 1179 | } |
| 1180 | |
| 1181 | return 0; |
| 1182 | } |
| 1183 | |
| 1184 | static void kvm_riscv_check_sbi_dbcn_support(RISCVCPU *cpu, |
| 1185 | struct kvm_reg_list *reglist) |
| 1186 | { |
| 1187 | struct kvm_reg_list *reg_search; |
| 1188 | |
| 1189 | reg_search = bsearch(&kvm_sbi_dbcn.kvm_reg_id, reglist->reg, reglist->n, |
| 1190 | sizeof(uint64_t), uint64_cmp); |
| 1191 | |
| 1192 | if (reg_search) { |
| 1193 | kvm_sbi_dbcn.supported = true; |
| 1194 | } |
| 1195 | } |
| 1196 | |
| 1197 | static void kvm_riscv_read_vlenb(RISCVCPU *cpu, KVMScratchCPU *kvmcpu, |
| 1198 | struct kvm_reg_list *reglist) |
| 1199 | { |
| 1200 | struct kvm_one_reg reg; |
| 1201 | struct kvm_reg_list *reg_search; |
| 1202 | uint64_t val; |
| 1203 | int ret; |
| 1204 | |
| 1205 | reg_search = bsearch(&kvm_v_vlenb.kvm_reg_id, reglist->reg, reglist->n, |
| 1206 | sizeof(uint64_t), uint64_cmp); |
| 1207 | |
| 1208 | if (reg_search) { |
| 1209 | reg.id = kvm_v_vlenb.kvm_reg_id; |
| 1210 | reg.addr = (uint64_t)&val; |
| 1211 | |
| 1212 | ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); |
| 1213 | if (ret != 0) { |
| 1214 | error_report("Unable to read vlenb register, error code: %d", |
| 1215 | errno); |
| 1216 | exit(EXIT_FAILURE); |
| 1217 | } |
| 1218 | |
| 1219 | kvm_v_vlenb.supported = true; |
| 1220 | cpu->cfg.vlenb = val; |
| 1221 | } |
| 1222 | } |
| 1223 | |
| 1224 | static void kvm_riscv_read_csr_cfg(struct kvm_reg_list *reglist) |
| 1225 | { |
| 1226 | struct kvm_reg_list *reg_search; |
| 1227 | uint64_t reg_id; |
| 1228 | |
| 1229 | for (int i = 0; i < ARRAY_SIZE(kvm_csr_cfgs); i++) { |
| 1230 | KVMCPUConfig *csr_cfg = &kvm_csr_cfgs[i]; |
| 1231 | |
| 1232 | reg_id = csr_cfg->kvm_reg_id; |
| 1233 | reg_search = bsearch(®_id, reglist->reg, reglist->n, |
| 1234 | sizeof(uint64_t), uint64_cmp); |
| 1235 | if (!reg_search) { |
| 1236 | continue; |
| 1237 | } |
| 1238 | |
| 1239 | csr_cfg->supported = true; |
| 1240 | } |
| 1241 | } |
| 1242 | |
| 1243 | static void kvm_riscv_init_cfg(RISCVCPU *cpu, KVMScratchCPU *kvmcpu) |
| 1244 | { |
| 1245 | g_autofree struct kvm_reg_list *reglist = NULL; |
| 1246 | KVMCPUConfig *multi_ext_cfg; |
| 1247 | struct kvm_one_reg reg; |
| 1248 | struct kvm_reg_list rl_struct; |
| 1249 | uint64_t val, reg_id, *reg_search; |
| 1250 | int i, ret; |
| 1251 | |
| 1252 | rl_struct.n = 0; |
| 1253 | ret = ioctl(kvmcpu->cpufd, KVM_GET_REG_LIST, &rl_struct); |
| 1254 | |
| 1255 | /* |
| 1256 | * If KVM_GET_REG_LIST isn't supported we'll get errno 22 |
| 1257 | * (EINVAL). Use read_legacy() in this case. |
| 1258 | */ |
| 1259 | if (errno == EINVAL) { |
| 1260 | kvm_riscv_read_multiext_legacy(cpu, kvmcpu); |
| 1261 | kvm_riscv_read_csr_cfg_legacy(kvmcpu); |
| 1262 | return; |
| 1263 | } else if (errno != E2BIG) { |
| 1264 | /* |
| 1265 | * E2BIG is an expected error message for the API since we |
| 1266 | * don't know the number of registers. The right amount will |
| 1267 | * be written in rl_struct.n. |
| 1268 | * |
| 1269 | * Error out if we get any other errno. |
| 1270 | */ |
| 1271 | error_report("Error when accessing get-reg-list: %s", |
| 1272 | strerror(errno)); |
| 1273 | exit(EXIT_FAILURE); |
| 1274 | } |
| 1275 | |
| 1276 | reglist = g_malloc(sizeof(struct kvm_reg_list) + |
| 1277 | rl_struct.n * sizeof(uint64_t)); |
| 1278 | reglist->n = rl_struct.n; |
| 1279 | ret = ioctl(kvmcpu->cpufd, KVM_GET_REG_LIST, reglist); |
| 1280 | if (ret) { |
| 1281 | error_report("Error when reading KVM_GET_REG_LIST: %s", |
| 1282 | strerror(errno)); |
| 1283 | exit(EXIT_FAILURE); |
| 1284 | } |
| 1285 | |
| 1286 | /* sort reglist to use bsearch() */ |
| 1287 | qsort(®list->reg, reglist->n, sizeof(uint64_t), uint64_cmp); |
| 1288 | |
| 1289 | for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) { |
| 1290 | multi_ext_cfg = &kvm_multi_ext_cfgs[i]; |
| 1291 | reg_id = KVM_RISCV_REG_ID_ULONG(KVM_REG_RISCV_ISA_EXT, |
| 1292 | multi_ext_cfg->kvm_reg_id); |
| 1293 | reg_search = bsearch(®_id, reglist->reg, reglist->n, |
| 1294 | sizeof(uint64_t), uint64_cmp); |
| 1295 | if (!reg_search) { |
| 1296 | continue; |
| 1297 | } |
| 1298 | |
| 1299 | reg.id = reg_id; |
| 1300 | reg.addr = (uint64_t)&val; |
| 1301 | ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); |
| 1302 | if (ret != 0) { |
| 1303 | error_report("Unable to read ISA_EXT KVM register %s: %s", |
| 1304 | multi_ext_cfg->name, strerror(errno)); |
| 1305 | exit(EXIT_FAILURE); |
| 1306 | } |
| 1307 | |
| 1308 | multi_ext_cfg->supported = true; |
| 1309 | kvm_cpu_cfg_set(cpu, multi_ext_cfg, val); |
| 1310 | } |
| 1311 | |
| 1312 | if (cpu->cfg.ext_zicbom) { |
| 1313 | kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cbom_blocksize); |
| 1314 | } |
| 1315 | |
| 1316 | if (cpu->cfg.ext_zicbop) { |
| 1317 | kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cbop_blocksize); |
| 1318 | } |
| 1319 | |
| 1320 | if (cpu->cfg.ext_zicboz) { |
| 1321 | kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cboz_blocksize); |
| 1322 | } |
| 1323 | |
| 1324 | if (riscv_has_ext(&cpu->env, RVV)) { |
| 1325 | kvm_riscv_read_vlenb(cpu, kvmcpu, reglist); |
| 1326 | } |
| 1327 | |
| 1328 | kvm_riscv_check_sbi_dbcn_support(cpu, reglist); |
| 1329 | kvm_riscv_read_csr_cfg(reglist); |
| 1330 | } |
| 1331 | |
| 1332 | static void riscv_init_kvm_registers(Object *cpu_obj) |
| 1333 | { |
| 1334 | RISCVCPU *cpu = RISCV_CPU(cpu_obj); |
| 1335 | KVMScratchCPU kvmcpu; |
| 1336 | |
| 1337 | if (!kvm_riscv_create_scratch_vcpu(&kvmcpu)) { |
| 1338 | return; |
| 1339 | } |
| 1340 | |
| 1341 | kvm_riscv_init_machine_ids(cpu, &kvmcpu); |
| 1342 | kvm_riscv_init_misa_ext_mask(cpu, &kvmcpu); |
| 1343 | kvm_riscv_init_cfg(cpu, &kvmcpu); |
| 1344 | kvm_riscv_init_max_satp_mode(cpu, &kvmcpu); |
| 1345 | |
| 1346 | kvm_riscv_destroy_scratch_vcpu(&kvmcpu); |
| 1347 | } |
| 1348 | |
| 1349 | const KVMCapabilityInfo kvm_arch_required_capabilities[] = { |
| 1350 | KVM_CAP_LAST_INFO |
| 1351 | }; |
| 1352 | |
| 1353 | int kvm_arch_get_registers(CPUState *cs, Error **errp) |
| 1354 | { |
| 1355 | int ret = 0; |
| 1356 | |
| 1357 | ret = kvm_riscv_get_regs_core(cs); |
| 1358 | if (ret) { |
| 1359 | return ret; |
| 1360 | } |
| 1361 | |
| 1362 | ret = kvm_riscv_get_regs_csr(cs); |
| 1363 | if (ret) { |
| 1364 | return ret; |
| 1365 | } |
| 1366 | |
| 1367 | ret = kvm_riscv_get_regs_fp(cs); |
| 1368 | if (ret) { |
| 1369 | return ret; |
| 1370 | } |
| 1371 | |
| 1372 | ret = kvm_riscv_get_regs_vector(cs); |
| 1373 | if (ret) { |
| 1374 | return ret; |
| 1375 | } |
| 1376 | |
| 1377 | if (cap_has_mp_state) { |
| 1378 | struct kvm_mp_state mp_state; |
| 1379 | |
| 1380 | ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state); |
| 1381 | if (ret) { |
| 1382 | return ret; |
| 1383 | } |
| 1384 | RISCV_CPU(cs)->env.kvm_mp_state = mp_state.mp_state; |
| 1385 | } |
| 1386 | |
| 1387 | return ret; |
| 1388 | } |
| 1389 | |
| 1390 | bool kvm_riscv_has_mp_state(void) |
| 1391 | { |
| 1392 | return cap_has_mp_state; |
| 1393 | } |
| 1394 | |
| 1395 | static int kvm_riscv_put_mp_state(CPUState *cs) |
| 1396 | { |
| 1397 | struct kvm_mp_state mp_state = { |
| 1398 | .mp_state = RISCV_CPU(cs)->env.kvm_mp_state, |
| 1399 | }; |
| 1400 | |
| 1401 | if (!cap_has_mp_state) { |
| 1402 | return 0; |
| 1403 | } |
| 1404 | |
| 1405 | return kvm_vcpu_ioctl(cs, KVM_SET_MP_STATE, &mp_state); |
| 1406 | } |
| 1407 | |
| 1408 | int kvm_arch_put_registers(CPUState *cs, KvmPutState level, Error **errp) |
| 1409 | { |
| 1410 | int ret = 0; |
| 1411 | |
| 1412 | ret = kvm_riscv_put_regs_core(cs); |
| 1413 | if (ret) { |
| 1414 | return ret; |
| 1415 | } |
| 1416 | |
| 1417 | ret = kvm_riscv_put_regs_csr(cs); |
| 1418 | if (ret) { |
| 1419 | return ret; |
| 1420 | } |
| 1421 | |
| 1422 | /* |
| 1423 | * For RUNTIME_STATE, KVM already has the correct FP and Vector state |
| 1424 | * from the preceding KVM_RUN exit. QEMU never modifies these registers |
| 1425 | * during exit handling, so re-syncing is unnecessary. This saves ~68 |
| 1426 | * KVM_SET_ONE_REG ioctls per vCPU exit. See also s390x which uses |
| 1427 | * the same pattern. |
| 1428 | */ |
| 1429 | if (KVM_PUT_RUNTIME_STATE == level) { |
| 1430 | return ret; |
| 1431 | } |
| 1432 | |
| 1433 | ret = kvm_riscv_put_regs_fp(cs); |
| 1434 | if (ret) { |
| 1435 | return ret; |
| 1436 | } |
| 1437 | |
| 1438 | ret = kvm_riscv_put_regs_vector(cs); |
| 1439 | if (ret) { |
| 1440 | return ret; |
| 1441 | } |
| 1442 | |
| 1443 | if (KVM_PUT_RESET_STATE == level) { |
| 1444 | CPURISCVState *env = &RISCV_CPU(cs)->env; |
| 1445 | |
| 1446 | env->kvm_mp_state = cs->cpu_index == 0 ? KVM_MP_STATE_RUNNABLE |
| 1447 | : KVM_MP_STATE_STOPPED; |
| 1448 | env->kvm_mp_state_loaded = false; |
| 1449 | ret = kvm_riscv_put_mp_state(cs); |
| 1450 | if (ret) { |
| 1451 | return ret; |
| 1452 | } |
| 1453 | } else if (KVM_PUT_FULL_STATE == level && |
| 1454 | RISCV_CPU(cs)->env.kvm_mp_state_loaded) { |
| 1455 | ret = kvm_riscv_put_mp_state(cs); |
| 1456 | if (ret) { |
| 1457 | return ret; |
| 1458 | } |
| 1459 | } |
| 1460 | |
| 1461 | return ret; |
| 1462 | } |
| 1463 | |
| 1464 | int kvm_arch_release_virq_post(int virq) |
| 1465 | { |
| 1466 | return 0; |
| 1467 | } |
| 1468 | |
| 1469 | int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route, |
| 1470 | uint64_t address, uint32_t data, PCIDevice *dev) |
| 1471 | { |
| 1472 | return 0; |
| 1473 | } |
| 1474 | |
| 1475 | int kvm_arch_destroy_vcpu(CPUState *cs) |
| 1476 | { |
| 1477 | return 0; |
| 1478 | } |
| 1479 | |
| 1480 | unsigned long kvm_arch_vcpu_id(CPUState *cpu) |
| 1481 | { |
| 1482 | return cpu->cpu_index; |
| 1483 | } |
| 1484 | |
| 1485 | static void kvm_riscv_vm_state_change(void *opaque, bool running, |
| 1486 | RunState state) |
| 1487 | { |
| 1488 | CPUState *cs = opaque; |
| 1489 | |
| 1490 | if (running) { |
| 1491 | kvm_riscv_put_regs_timer(cs); |
| 1492 | } else { |
| 1493 | kvm_riscv_get_regs_timer(cs); |
| 1494 | } |
| 1495 | } |
| 1496 | |
| 1497 | void kvm_arch_init_irq_routing(KVMState *s) |
| 1498 | { |
| 1499 | } |
| 1500 | |
| 1501 | static int kvm_vcpu_set_machine_ids(RISCVCPU *cpu, CPUState *cs) |
| 1502 | { |
| 1503 | target_ulong reg; |
| 1504 | uint64_t id; |
| 1505 | int ret; |
| 1506 | |
| 1507 | id = RISCV_CONFIG_REG(mvendorid); |
| 1508 | /* |
| 1509 | * cfg.mvendorid is an uint32 but a target_ulong will |
| 1510 | * be written. Assign it to a target_ulong var to avoid |
| 1511 | * writing pieces of other cpu->cfg fields in the reg. |
| 1512 | */ |
| 1513 | reg = cpu->cfg.mvendorid; |
| 1514 | ret = kvm_set_one_reg(cs, id, ®); |
| 1515 | if (ret != 0) { |
| 1516 | return ret; |
| 1517 | } |
| 1518 | |
| 1519 | id = RISCV_CONFIG_REG(marchid); |
| 1520 | ret = kvm_set_one_reg(cs, id, &cpu->cfg.marchid); |
| 1521 | if (ret != 0) { |
| 1522 | return ret; |
| 1523 | } |
| 1524 | |
| 1525 | id = RISCV_CONFIG_REG(mimpid); |
| 1526 | ret = kvm_set_one_reg(cs, id, &cpu->cfg.mimpid); |
| 1527 | |
| 1528 | return ret; |
| 1529 | } |
| 1530 | |
| 1531 | static int kvm_vcpu_enable_sbi_dbcn(RISCVCPU *cpu, CPUState *cs) |
| 1532 | { |
| 1533 | target_ulong reg = 1; |
| 1534 | |
| 1535 | if (!kvm_sbi_dbcn.supported) { |
| 1536 | return 0; |
| 1537 | } |
| 1538 | |
| 1539 | return kvm_set_one_reg(cs, kvm_sbi_dbcn.kvm_reg_id, ®); |
| 1540 | } |
| 1541 | |
| 1542 | int kvm_arch_pre_create_vcpu(CPUState *cpu, Error **errp) |
| 1543 | { |
| 1544 | return 0; |
| 1545 | } |
| 1546 | |
| 1547 | int kvm_arch_init_vcpu(CPUState *cs) |
| 1548 | { |
| 1549 | int ret = 0; |
| 1550 | RISCVCPU *cpu = RISCV_CPU(cs); |
| 1551 | |
| 1552 | qemu_add_vm_change_state_handler(kvm_riscv_vm_state_change, cs); |
| 1553 | |
| 1554 | if (!object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_CPU_HOST)) { |
| 1555 | ret = kvm_vcpu_set_machine_ids(cpu, cs); |
| 1556 | if (ret != 0) { |
| 1557 | return ret; |
| 1558 | } |
| 1559 | } |
| 1560 | |
| 1561 | kvm_riscv_update_cpu_misa_ext(cpu, cs); |
| 1562 | kvm_riscv_update_cpu_cfg_isa_ext(cpu, cs); |
| 1563 | |
| 1564 | ret = kvm_vcpu_enable_sbi_dbcn(cpu, cs); |
| 1565 | |
| 1566 | return ret; |
| 1567 | } |
| 1568 | |
| 1569 | int kvm_arch_msi_data_to_gsi(uint32_t data) |
| 1570 | { |
| 1571 | abort(); |
| 1572 | } |
| 1573 | |
| 1574 | int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route, |
| 1575 | int vector, PCIDevice *dev) |
| 1576 | { |
| 1577 | return 0; |
| 1578 | } |
| 1579 | |
| 1580 | int kvm_arch_get_default_type(MachineState *ms) |
| 1581 | { |
| 1582 | return 0; |
| 1583 | } |
| 1584 | |
| 1585 | int kvm_arch_init(MachineState *ms, KVMState *s) |
| 1586 | { |
| 1587 | cap_has_mp_state = kvm_check_extension(s, KVM_CAP_MP_STATE); |
| 1588 | return 0; |
| 1589 | } |
| 1590 | |
| 1591 | int kvm_arch_irqchip_create(KVMState *s) |
| 1592 | { |
| 1593 | /* |
| 1594 | * We can create the VAIA using the newer device control API. |
| 1595 | */ |
| 1596 | return kvm_check_extension(s, KVM_CAP_DEVICE_CTRL); |
| 1597 | } |
| 1598 | |
| 1599 | int kvm_arch_process_async_events(CPUState *cs) |
| 1600 | { |
| 1601 | return 0; |
| 1602 | } |
| 1603 | |
| 1604 | void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run) |
| 1605 | { |
| 1606 | } |
| 1607 | |
| 1608 | MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run) |
| 1609 | { |
| 1610 | return MEMTXATTRS_UNSPECIFIED; |
| 1611 | } |
| 1612 | |
| 1613 | bool kvm_arch_stop_on_emulation_error(CPUState *cs) |
| 1614 | { |
| 1615 | return true; |
| 1616 | } |
| 1617 | |
| 1618 | static void kvm_riscv_handle_sbi_dbcn(CPUState *cs, struct kvm_run *run) |
| 1619 | { |
| 1620 | const MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED; |
| 1621 | g_autofree uint8_t *buf = NULL; |
| 1622 | RISCVCPU *cpu = RISCV_CPU(cs); |
| 1623 | target_ulong num_bytes; |
| 1624 | uint64_t addr; |
| 1625 | unsigned char ch; |
| 1626 | int ret; |
| 1627 | |
| 1628 | switch (run->riscv_sbi.function_id) { |
| 1629 | case SBI_EXT_DBCN_CONSOLE_READ: |
| 1630 | case SBI_EXT_DBCN_CONSOLE_WRITE: |
| 1631 | num_bytes = run->riscv_sbi.args[0]; |
| 1632 | |
| 1633 | if (num_bytes == 0) { |
| 1634 | run->riscv_sbi.ret[0] = SBI_SUCCESS; |
| 1635 | run->riscv_sbi.ret[1] = 0; |
| 1636 | break; |
| 1637 | } |
| 1638 | |
| 1639 | addr = run->riscv_sbi.args[1]; |
| 1640 | |
| 1641 | /* |
| 1642 | * Handle the case where a 32 bit CPU is running in a |
| 1643 | * 64 bit addressing env. |
| 1644 | */ |
| 1645 | if (riscv_cpu_is_32bit(cpu)) { |
| 1646 | addr |= (uint64_t)run->riscv_sbi.args[2] << 32; |
| 1647 | } |
| 1648 | |
| 1649 | buf = g_malloc0(num_bytes); |
| 1650 | |
| 1651 | if (run->riscv_sbi.function_id == SBI_EXT_DBCN_CONSOLE_READ) { |
| 1652 | ret = qemu_chr_fe_read_all(serial_hd(0)->fe, buf, num_bytes); |
| 1653 | if (ret < 0) { |
| 1654 | error_report("SBI_EXT_DBCN_CONSOLE_READ: error when " |
| 1655 | "reading chardev"); |
| 1656 | exit(1); |
| 1657 | } |
| 1658 | |
| 1659 | address_space_write(cs->as, addr, attrs, buf, ret); |
| 1660 | } else { |
| 1661 | address_space_read(cs->as, addr, attrs, buf, num_bytes); |
| 1662 | |
| 1663 | ret = qemu_chr_fe_write_all(serial_hd(0)->fe, buf, num_bytes); |
| 1664 | if (ret < 0) { |
| 1665 | error_report("SBI_EXT_DBCN_CONSOLE_WRITE: error when " |
| 1666 | "writing chardev"); |
| 1667 | exit(1); |
| 1668 | } |
| 1669 | } |
| 1670 | |
| 1671 | run->riscv_sbi.ret[0] = SBI_SUCCESS; |
| 1672 | run->riscv_sbi.ret[1] = ret; |
| 1673 | break; |
| 1674 | case SBI_EXT_DBCN_CONSOLE_WRITE_BYTE: |
| 1675 | ch = run->riscv_sbi.args[0]; |
| 1676 | ret = qemu_chr_fe_write_all(serial_hd(0)->fe, &ch, sizeof(ch)); |
| 1677 | |
| 1678 | if (ret < 0) { |
| 1679 | error_report("SBI_EXT_DBCN_CONSOLE_WRITE_BYTE: error when " |
| 1680 | "writing chardev"); |
| 1681 | exit(1); |
| 1682 | } |
| 1683 | |
| 1684 | run->riscv_sbi.ret[0] = SBI_SUCCESS; |
| 1685 | run->riscv_sbi.ret[1] = 0; |
| 1686 | break; |
| 1687 | default: |
| 1688 | run->riscv_sbi.ret[0] = SBI_ERR_NOT_SUPPORTED; |
| 1689 | } |
| 1690 | } |
| 1691 | |
| 1692 | static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run) |
| 1693 | { |
| 1694 | int ret = 0; |
| 1695 | unsigned char ch; |
| 1696 | switch (run->riscv_sbi.extension_id) { |
| 1697 | case SBI_EXT_0_1_CONSOLE_PUTCHAR: |
| 1698 | ch = run->riscv_sbi.args[0]; |
| 1699 | qemu_chr_fe_write(serial_hd(0)->fe, &ch, sizeof(ch)); |
| 1700 | break; |
| 1701 | case SBI_EXT_0_1_CONSOLE_GETCHAR: |
| 1702 | ret = qemu_chr_fe_read_all(serial_hd(0)->fe, &ch, sizeof(ch)); |
| 1703 | if (ret == sizeof(ch)) { |
| 1704 | run->riscv_sbi.ret[0] = ch; |
| 1705 | } else { |
| 1706 | run->riscv_sbi.ret[0] = -1; |
| 1707 | } |
| 1708 | ret = 0; |
| 1709 | break; |
| 1710 | case SBI_EXT_DBCN: |
| 1711 | kvm_riscv_handle_sbi_dbcn(cs, run); |
| 1712 | break; |
| 1713 | default: |
| 1714 | qemu_log_mask(LOG_UNIMP, |
| 1715 | "%s: un-handled SBI EXIT, specific reasons is %lu\n", |
| 1716 | __func__, run->riscv_sbi.extension_id); |
| 1717 | ret = -1; |
| 1718 | break; |
| 1719 | } |
| 1720 | return ret; |
| 1721 | } |
| 1722 | |
| 1723 | static int kvm_riscv_handle_csr(CPUState *cs, struct kvm_run *run) |
| 1724 | { |
| 1725 | target_ulong csr_num = run->riscv_csr.csr_num; |
| 1726 | target_ulong new_value = run->riscv_csr.new_value; |
| 1727 | target_ulong write_mask = run->riscv_csr.write_mask; |
| 1728 | int ret = 0; |
| 1729 | |
| 1730 | switch (csr_num) { |
| 1731 | case CSR_SEED: |
| 1732 | run->riscv_csr.ret_value = riscv_new_csr_seed(new_value, write_mask); |
| 1733 | break; |
| 1734 | default: |
| 1735 | qemu_log_mask(LOG_UNIMP, |
| 1736 | "%s: un-handled CSR EXIT for CSR %lx\n", |
| 1737 | __func__, csr_num); |
| 1738 | ret = -1; |
| 1739 | break; |
| 1740 | } |
| 1741 | |
| 1742 | return ret; |
| 1743 | } |
| 1744 | |
| 1745 | static bool kvm_riscv_handle_debug(CPUState *cs) |
| 1746 | { |
| 1747 | RISCVCPU *cpu = RISCV_CPU(cs); |
| 1748 | CPURISCVState *env = &cpu->env; |
| 1749 | |
| 1750 | /* Ensure PC is synchronised */ |
| 1751 | kvm_cpu_synchronize_state(cs); |
| 1752 | |
| 1753 | if (kvm_find_sw_breakpoint(cs, env->pc)) { |
| 1754 | return true; |
| 1755 | } |
| 1756 | |
| 1757 | return false; |
| 1758 | } |
| 1759 | |
| 1760 | int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run) |
| 1761 | { |
| 1762 | int ret = 0; |
| 1763 | switch (run->exit_reason) { |
| 1764 | case KVM_EXIT_RISCV_SBI: |
| 1765 | ret = kvm_riscv_handle_sbi(cs, run); |
| 1766 | break; |
| 1767 | case KVM_EXIT_RISCV_CSR: |
| 1768 | ret = kvm_riscv_handle_csr(cs, run); |
| 1769 | break; |
| 1770 | case KVM_EXIT_DEBUG: |
| 1771 | if (kvm_riscv_handle_debug(cs)) { |
| 1772 | ret = EXCP_DEBUG; |
| 1773 | } |
| 1774 | break; |
| 1775 | default: |
| 1776 | qemu_log_mask(LOG_UNIMP, "%s: un-handled exit reason %d\n", |
| 1777 | __func__, run->exit_reason); |
| 1778 | ret = -1; |
| 1779 | break; |
| 1780 | } |
| 1781 | return ret; |
| 1782 | } |
| 1783 | |
| 1784 | void kvm_riscv_reset_vcpu(RISCVCPU *cpu) |
| 1785 | { |
| 1786 | CPURISCVState *env = &cpu->env; |
| 1787 | int i; |
| 1788 | |
| 1789 | for (i = 0; i < 32; i++) { |
| 1790 | env->gpr[i] = 0; |
| 1791 | } |
| 1792 | env->pc = cpu->env.kernel_addr; |
| 1793 | env->gpr[10] = kvm_arch_vcpu_id(CPU(cpu)); /* a0 */ |
| 1794 | env->gpr[11] = cpu->env.fdt_addr; /* a1 */ |
| 1795 | |
| 1796 | kvm_riscv_reset_regs_csr(env); |
| 1797 | } |
| 1798 | |
| 1799 | void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level) |
| 1800 | { |
| 1801 | int ret; |
| 1802 | unsigned virq = level ? KVM_INTERRUPT_SET : KVM_INTERRUPT_UNSET; |
| 1803 | |
| 1804 | if (irq != IRQ_S_EXT) { |
| 1805 | perror("kvm riscv set irq != IRQ_S_EXT\n"); |
| 1806 | abort(); |
| 1807 | } |
| 1808 | |
| 1809 | ret = kvm_vcpu_ioctl(CPU(cpu), KVM_INTERRUPT, &virq); |
| 1810 | if (ret < 0) { |
| 1811 | perror("Set irq failed"); |
| 1812 | abort(); |
| 1813 | } |
| 1814 | } |
| 1815 | |
| 1816 | static int aia_mode; |
| 1817 | |
| 1818 | static const char *kvm_aia_mode_str(uint64_t mode) |
| 1819 | { |
| 1820 | switch (mode) { |
| 1821 | case KVM_DEV_RISCV_AIA_MODE_EMUL: |
| 1822 | return "emul"; |
| 1823 | case KVM_DEV_RISCV_AIA_MODE_HWACCEL: |
| 1824 | return "hwaccel"; |
| 1825 | case KVM_DEV_RISCV_AIA_MODE_AUTO: |
| 1826 | default: |
| 1827 | return "auto"; |
| 1828 | }; |
| 1829 | } |
| 1830 | |
| 1831 | static char *riscv_get_kvm_aia(Object *obj, Error **errp) |
| 1832 | { |
| 1833 | return g_strdup(kvm_aia_mode_str(aia_mode)); |
| 1834 | } |
| 1835 | |
| 1836 | static void riscv_set_kvm_aia(Object *obj, const char *val, Error **errp) |
| 1837 | { |
| 1838 | if (!strcmp(val, "emul")) { |
| 1839 | aia_mode = KVM_DEV_RISCV_AIA_MODE_EMUL; |
| 1840 | } else if (!strcmp(val, "hwaccel")) { |
| 1841 | aia_mode = KVM_DEV_RISCV_AIA_MODE_HWACCEL; |
| 1842 | } else if (!strcmp(val, "auto")) { |
| 1843 | aia_mode = KVM_DEV_RISCV_AIA_MODE_AUTO; |
| 1844 | } else { |
| 1845 | error_setg(errp, "Invalid KVM AIA mode"); |
| 1846 | error_append_hint(errp, "Valid values are emul, hwaccel, and auto.\n"); |
| 1847 | } |
| 1848 | } |
| 1849 | |
| 1850 | void kvm_arch_accel_class_init(ObjectClass *oc) |
| 1851 | { |
| 1852 | object_class_property_add_str(oc, "riscv-aia", riscv_get_kvm_aia, |
| 1853 | riscv_set_kvm_aia); |
| 1854 | object_class_property_set_description(oc, "riscv-aia", |
| 1855 | "Set KVM AIA mode. Valid values are 'emul', 'hwaccel' and 'auto'. " |
| 1856 | "Changing KVM AIA modes relies on host support. Defaults to 'auto' " |
| 1857 | "if the host supports it"); |
| 1858 | object_property_set_default_str(object_class_property_find(oc, "riscv-aia"), |
| 1859 | "auto"); |
| 1860 | } |
| 1861 | |
| 1862 | void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift, |
| 1863 | uint64_t aia_irq_num, uint64_t aia_msi_num, |
| 1864 | uint64_t aplic_base, uint64_t imsic_base, |
| 1865 | uint64_t guest_num) |
| 1866 | { |
| 1867 | int ret, i; |
| 1868 | int aia_fd = -1; |
| 1869 | uint64_t default_aia_mode; |
| 1870 | uint64_t socket_count = riscv_socket_count(machine); |
| 1871 | uint64_t max_hart_per_socket = 0; |
| 1872 | uint64_t socket, base_hart, hart_count, socket_imsic_base, imsic_addr; |
| 1873 | uint64_t socket_bits, hart_bits, guest_bits; |
| 1874 | uint64_t max_group_id; |
| 1875 | |
| 1876 | aia_fd = kvm_create_device(kvm_state, KVM_DEV_TYPE_RISCV_AIA, false); |
| 1877 | |
| 1878 | if (aia_fd < 0) { |
| 1879 | error_report("Unable to create in-kernel irqchip"); |
| 1880 | exit(1); |
| 1881 | } |
| 1882 | |
| 1883 | ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, |
| 1884 | KVM_DEV_RISCV_AIA_CONFIG_MODE, |
| 1885 | &default_aia_mode, false, NULL); |
| 1886 | if (ret < 0) { |
| 1887 | error_report("KVM AIA: failed to get current KVM AIA mode"); |
| 1888 | exit(1); |
| 1889 | } |
| 1890 | |
| 1891 | if (default_aia_mode != aia_mode) { |
| 1892 | ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, |
| 1893 | KVM_DEV_RISCV_AIA_CONFIG_MODE, |
| 1894 | &aia_mode, true, NULL); |
| 1895 | if (ret < 0) { |
| 1896 | warn_report("KVM AIA: failed to set KVM AIA mode '%s', using " |
| 1897 | "default host mode '%s'", |
| 1898 | kvm_aia_mode_str(aia_mode), |
| 1899 | kvm_aia_mode_str(default_aia_mode)); |
| 1900 | |
| 1901 | /* failed to change AIA mode, use default */ |
| 1902 | aia_mode = default_aia_mode; |
| 1903 | } |
| 1904 | } |
| 1905 | |
| 1906 | /* |
| 1907 | * Skip APLIC creation in KVM if we're running split mode. |
| 1908 | * This is done by leaving KVM_DEV_RISCV_AIA_CONFIG_SRCS |
| 1909 | * unset. We can also skip KVM_DEV_RISCV_AIA_ADDR_APLIC |
| 1910 | * since KVM won't be using it. |
| 1911 | */ |
| 1912 | if (!kvm_kernel_irqchip_split()) { |
| 1913 | ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, |
| 1914 | KVM_DEV_RISCV_AIA_CONFIG_SRCS, |
| 1915 | &aia_irq_num, true, NULL); |
| 1916 | if (ret < 0) { |
| 1917 | error_report("KVM AIA: failed to set number of input irq lines"); |
| 1918 | exit(1); |
| 1919 | } |
| 1920 | |
| 1921 | ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_ADDR, |
| 1922 | KVM_DEV_RISCV_AIA_ADDR_APLIC, |
| 1923 | &aplic_base, true, NULL); |
| 1924 | if (ret < 0) { |
| 1925 | error_report("KVM AIA: failed to set the base address of APLIC"); |
| 1926 | exit(1); |
| 1927 | } |
| 1928 | } |
| 1929 | |
| 1930 | ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, |
| 1931 | KVM_DEV_RISCV_AIA_CONFIG_IDS, |
| 1932 | &aia_msi_num, true, NULL); |
| 1933 | if (ret < 0) { |
| 1934 | error_report("KVM AIA: failed to set number of msi"); |
| 1935 | exit(1); |
| 1936 | } |
| 1937 | |
| 1938 | |
| 1939 | if (socket_count > 1) { |
| 1940 | max_group_id = socket_count - 1; |
| 1941 | socket_bits = find_last_bit(&max_group_id, BITS_PER_LONG) + 1; |
| 1942 | ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, |
| 1943 | KVM_DEV_RISCV_AIA_CONFIG_GROUP_BITS, |
| 1944 | &socket_bits, true, NULL); |
| 1945 | if (ret < 0) { |
| 1946 | error_report("KVM AIA: failed to set group_bits"); |
| 1947 | exit(1); |
| 1948 | } |
| 1949 | |
| 1950 | ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, |
| 1951 | KVM_DEV_RISCV_AIA_CONFIG_GROUP_SHIFT, |
| 1952 | &group_shift, true, NULL); |
| 1953 | if (ret < 0) { |
| 1954 | error_report("KVM AIA: failed to set group_shift"); |
| 1955 | exit(1); |
| 1956 | } |
| 1957 | } |
| 1958 | |
| 1959 | guest_bits = guest_num == 0 ? 0 : |
| 1960 | find_last_bit(&guest_num, BITS_PER_LONG) + 1; |
| 1961 | ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, |
| 1962 | KVM_DEV_RISCV_AIA_CONFIG_GUEST_BITS, |
| 1963 | &guest_bits, true, NULL); |
| 1964 | if (ret < 0) { |
| 1965 | error_report("KVM AIA: failed to set guest_bits"); |
| 1966 | exit(1); |
| 1967 | } |
| 1968 | |
| 1969 | for (socket = 0; socket < socket_count; socket++) { |
| 1970 | socket_imsic_base = imsic_base + socket * (1U << group_shift); |
| 1971 | hart_count = riscv_socket_hart_count(machine, socket); |
| 1972 | base_hart = riscv_socket_first_hartid(machine, socket); |
| 1973 | |
| 1974 | if (max_hart_per_socket < hart_count) { |
| 1975 | max_hart_per_socket = hart_count; |
| 1976 | } |
| 1977 | |
| 1978 | for (i = 0; i < hart_count; i++) { |
| 1979 | imsic_addr = socket_imsic_base + i * IMSIC_HART_SIZE(guest_bits); |
| 1980 | ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_ADDR, |
| 1981 | KVM_DEV_RISCV_AIA_ADDR_IMSIC(i + base_hart), |
| 1982 | &imsic_addr, true, NULL); |
| 1983 | if (ret < 0) { |
| 1984 | error_report("KVM AIA: failed to set the IMSIC address for hart %d", i); |
| 1985 | exit(1); |
| 1986 | } |
| 1987 | } |
| 1988 | } |
| 1989 | |
| 1990 | |
| 1991 | if (max_hart_per_socket > 1) { |
| 1992 | max_hart_per_socket--; |
| 1993 | hart_bits = find_last_bit(&max_hart_per_socket, BITS_PER_LONG) + 1; |
| 1994 | } else { |
| 1995 | hart_bits = 0; |
| 1996 | } |
| 1997 | |
| 1998 | ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, |
| 1999 | KVM_DEV_RISCV_AIA_CONFIG_HART_BITS, |
| 2000 | &hart_bits, true, NULL); |
| 2001 | if (ret < 0) { |
| 2002 | error_report("KVM AIA: failed to set hart_bits"); |
| 2003 | exit(1); |
| 2004 | } |
| 2005 | |
| 2006 | if (kvm_has_gsi_routing()) { |
| 2007 | for (uint64_t idx = 0; idx < aia_irq_num + 1; ++idx) { |
| 2008 | /* KVM AIA only has one APLIC instance */ |
| 2009 | kvm_irqchip_add_irq_route(kvm_state, idx, 0, idx); |
| 2010 | } |
| 2011 | kvm_gsi_routing_allowed = true; |
| 2012 | kvm_irqchip_commit_routes(kvm_state); |
| 2013 | } |
| 2014 | |
| 2015 | ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CTRL, |
| 2016 | KVM_DEV_RISCV_AIA_CTRL_INIT, |
| 2017 | NULL, true, NULL); |
| 2018 | if (ret < 0) { |
| 2019 | error_report("KVM AIA: initialized fail"); |
| 2020 | exit(1); |
| 2021 | } |
| 2022 | |
| 2023 | kvm_msi_via_irqfd_allowed = true; |
| 2024 | } |
| 2025 | |
| 2026 | static void kvm_cpu_instance_init(CPUState *cs) |
| 2027 | { |
| 2028 | Object *obj = OBJECT(RISCV_CPU(cs)); |
| 2029 | |
| 2030 | riscv_init_kvm_registers(obj); |
| 2031 | |
| 2032 | kvm_riscv_add_cpu_user_properties(obj); |
| 2033 | } |
| 2034 | |
| 2035 | /* |
| 2036 | * We'll get here via the following path: |
| 2037 | * |
| 2038 | * riscv_cpu_realize() |
| 2039 | * -> cpu_common_realize() |
| 2040 | * -> kvm_cpu_realize() (via accel_cpu_common_realize()) |
| 2041 | */ |
| 2042 | static bool kvm_cpu_realize(CPUState *cs, Error **errp) |
| 2043 | { |
| 2044 | RISCVCPU *cpu = RISCV_CPU(cs); |
| 2045 | int ret; |
| 2046 | |
| 2047 | if (riscv_has_ext(&cpu->env, RVV)) { |
| 2048 | ret = prctl(PR_RISCV_V_SET_CONTROL, PR_RISCV_V_VSTATE_CTRL_ON); |
| 2049 | if (ret) { |
| 2050 | error_setg_errno(errp, errno, |
| 2051 | "Error in prctl PR_RISCV_V_SET_CONTROL"); |
| 2052 | return false; |
| 2053 | } |
| 2054 | } |
| 2055 | |
| 2056 | return true; |
| 2057 | } |
| 2058 | |
| 2059 | void riscv_kvm_cpu_finalize_features(RISCVCPU *cpu, Error **errp) |
| 2060 | { |
| 2061 | CPURISCVState *env = &cpu->env; |
| 2062 | KVMScratchCPU kvmcpu; |
| 2063 | struct kvm_one_reg reg; |
| 2064 | uint64_t val; |
| 2065 | int ret; |
| 2066 | |
| 2067 | /* short-circuit without spinning the scratch CPU */ |
| 2068 | if (!cpu->cfg.ext_zicbom && !cpu->cfg.ext_zicbop && |
| 2069 | !cpu->cfg.ext_zicboz && !riscv_has_ext(env, RVV)) { |
| 2070 | return; |
| 2071 | } |
| 2072 | |
| 2073 | if (!kvm_riscv_create_scratch_vcpu(&kvmcpu)) { |
| 2074 | error_setg(errp, "Unable to create scratch KVM cpu"); |
| 2075 | return; |
| 2076 | } |
| 2077 | |
| 2078 | if (cpu->cfg.ext_zicbom && |
| 2079 | riscv_cpu_option_set(cpu, kvm_cbom_blocksize.name)) { |
| 2080 | |
| 2081 | reg.id = KVM_RISCV_REG_ID_ULONG(KVM_REG_RISCV_CONFIG, |
| 2082 | kvm_cbom_blocksize.kvm_reg_id); |
| 2083 | reg.addr = (uint64_t)&val; |
| 2084 | ret = ioctl(kvmcpu.cpufd, KVM_GET_ONE_REG, ®); |
| 2085 | if (ret != 0) { |
| 2086 | error_setg_errno(errp, errno, "Unable to read cbom_blocksize"); |
| 2087 | return; |
| 2088 | } |
| 2089 | |
| 2090 | if (cpu->cfg.cbom_blocksize != val) { |
| 2091 | error_setg(errp, "Unable to set cbom_blocksize to a different " |
| 2092 | "value than the host (%lu)", val); |
| 2093 | return; |
| 2094 | } |
| 2095 | } |
| 2096 | |
| 2097 | if (cpu->cfg.ext_zicboz && |
| 2098 | riscv_cpu_option_set(cpu, kvm_cboz_blocksize.name)) { |
| 2099 | |
| 2100 | reg.id = KVM_RISCV_REG_ID_ULONG(KVM_REG_RISCV_CONFIG, |
| 2101 | kvm_cboz_blocksize.kvm_reg_id); |
| 2102 | reg.addr = (uint64_t)&val; |
| 2103 | ret = ioctl(kvmcpu.cpufd, KVM_GET_ONE_REG, ®); |
| 2104 | if (ret != 0) { |
| 2105 | error_setg_errno(errp, errno, "Unable to read cboz_blocksize"); |
| 2106 | return; |
| 2107 | } |
| 2108 | |
| 2109 | if (cpu->cfg.cboz_blocksize != val) { |
| 2110 | error_setg(errp, "Unable to set cboz_blocksize to a different " |
| 2111 | "value than the host (%lu)", val); |
| 2112 | return; |
| 2113 | } |
| 2114 | } |
| 2115 | |
| 2116 | if (cpu->cfg.ext_zicbop && |
| 2117 | riscv_cpu_option_set(cpu, kvm_cbop_blocksize.name)) { |
| 2118 | |
| 2119 | reg.id = KVM_RISCV_REG_ID_ULONG(KVM_REG_RISCV_CONFIG, |
| 2120 | kvm_cbop_blocksize.kvm_reg_id); |
| 2121 | reg.addr = (uint64_t)&val; |
| 2122 | ret = ioctl(kvmcpu.cpufd, KVM_GET_ONE_REG, ®); |
| 2123 | if (ret != 0) { |
| 2124 | error_setg_errno(errp, errno, "Unable to read cbop_blocksize"); |
| 2125 | return; |
| 2126 | } |
| 2127 | |
| 2128 | if (cpu->cfg.cbop_blocksize != val) { |
| 2129 | error_setg(errp, "Unable to set cbop_blocksize to a different " |
| 2130 | "value than the host (%lu)", val); |
| 2131 | return; |
| 2132 | } |
| 2133 | } |
| 2134 | |
| 2135 | /* Users are setting vlen, not vlenb */ |
| 2136 | if (riscv_has_ext(env, RVV) && riscv_cpu_option_set(cpu, "vlen")) { |
| 2137 | if (!kvm_v_vlenb.supported) { |
| 2138 | error_setg(errp, "Unable to set 'vlenb': register not supported"); |
| 2139 | return; |
| 2140 | } |
| 2141 | |
| 2142 | reg.id = kvm_v_vlenb.kvm_reg_id; |
| 2143 | reg.addr = (uint64_t)&val; |
| 2144 | ret = ioctl(kvmcpu.cpufd, KVM_GET_ONE_REG, ®); |
| 2145 | if (ret != 0) { |
| 2146 | error_setg_errno(errp, errno, "Unable to read vlenb register"); |
| 2147 | return; |
| 2148 | } |
| 2149 | |
| 2150 | if (cpu->cfg.vlenb != val) { |
| 2151 | error_setg(errp, "Unable to set 'vlen' to a different " |
| 2152 | "value than the host (%lu)", val * 8); |
| 2153 | return; |
| 2154 | } |
| 2155 | } |
| 2156 | |
| 2157 | kvm_riscv_destroy_scratch_vcpu(&kvmcpu); |
| 2158 | } |
| 2159 | |
| 2160 | static void kvm_cpu_accel_class_init(ObjectClass *oc, const void *data) |
| 2161 | { |
| 2162 | AccelCPUClass *acc = ACCEL_CPU_CLASS(oc); |
| 2163 | |
| 2164 | acc->cpu_instance_init = kvm_cpu_instance_init; |
| 2165 | acc->cpu_target_realize = kvm_cpu_realize; |
| 2166 | } |
| 2167 | |
| 2168 | static const TypeInfo kvm_cpu_accel_type_info = { |
| 2169 | .name = ACCEL_CPU_NAME("kvm"), |
| 2170 | |
| 2171 | .parent = TYPE_ACCEL_CPU, |
| 2172 | .class_init = kvm_cpu_accel_class_init, |
| 2173 | .abstract = true, |
| 2174 | }; |
| 2175 | static void kvm_cpu_accel_register_types(void) |
| 2176 | { |
| 2177 | type_register_static(&kvm_cpu_accel_type_info); |
| 2178 | } |
| 2179 | type_init(kvm_cpu_accel_register_types); |
| 2180 | |
| 2181 | static const TypeInfo riscv_kvm_cpu_type_infos[] = { |
| 2182 | { |
| 2183 | .name = TYPE_RISCV_CPU_HOST, |
| 2184 | .parent = TYPE_RISCV_CPU, |
| 2185 | #if defined(TARGET_RISCV32) |
| 2186 | .class_data = &(const RISCVCPUDef) { |
| 2187 | .misa_mxl_max = MXL_RV32, |
| 2188 | .priv_spec = RISCV_PROFILE_ATTR_UNUSED, |
| 2189 | .vext_spec = RISCV_PROFILE_ATTR_UNUSED, |
| 2190 | .cfg.max_satp_mode = -1, |
| 2191 | }, |
| 2192 | #elif defined(TARGET_RISCV64) |
| 2193 | .class_data = &(const RISCVCPUDef) { |
| 2194 | .misa_mxl_max = MXL_RV64, |
| 2195 | .priv_spec = RISCV_PROFILE_ATTR_UNUSED, |
| 2196 | .vext_spec = RISCV_PROFILE_ATTR_UNUSED, |
| 2197 | .cfg.max_satp_mode = -1, |
| 2198 | }, |
| 2199 | #endif |
| 2200 | } |
| 2201 | }; |
| 2202 | |
| 2203 | DEFINE_TYPES(riscv_kvm_cpu_type_infos) |
| 2204 | |
| 2205 | static const uint32_t ebreak_insn = 0x00100073; |
| 2206 | static const uint16_t c_ebreak_insn = 0x9002; |
| 2207 | |
| 2208 | int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp) |
| 2209 | { |
| 2210 | if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 2, 0)) { |
| 2211 | return -EINVAL; |
| 2212 | } |
| 2213 | |
| 2214 | if ((bp->saved_insn & 0x3) == 0x3) { |
| 2215 | if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 4, 0) |
| 2216 | || cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&ebreak_insn, 4, 1)) { |
| 2217 | return -EINVAL; |
| 2218 | } |
| 2219 | } else { |
| 2220 | if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&c_ebreak_insn, 2, 1)) { |
| 2221 | return -EINVAL; |
| 2222 | } |
| 2223 | } |
| 2224 | |
| 2225 | return 0; |
| 2226 | } |
| 2227 | |
| 2228 | int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp) |
| 2229 | { |
| 2230 | uint32_t ebreak; |
| 2231 | uint16_t c_ebreak; |
| 2232 | |
| 2233 | if ((bp->saved_insn & 0x3) == 0x3) { |
| 2234 | if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&ebreak, 4, 0) || |
| 2235 | ebreak != ebreak_insn || |
| 2236 | cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 4, 1)) { |
| 2237 | return -EINVAL; |
| 2238 | } |
| 2239 | } else { |
| 2240 | if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&c_ebreak, 2, 0) || |
| 2241 | c_ebreak != c_ebreak_insn || |
| 2242 | cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 2, 1)) { |
| 2243 | return -EINVAL; |
| 2244 | } |
| 2245 | } |
| 2246 | |
| 2247 | return 0; |
| 2248 | } |
| 2249 | |
| 2250 | int kvm_arch_insert_gdbstub_hw_breakpoint(vaddr addr, vaddr len, |
| 2251 | GdbBreakpointType type) |
| 2252 | { |
| 2253 | /* TODO; To be implemented later. */ |
| 2254 | return -EINVAL; |
| 2255 | } |
| 2256 | |
| 2257 | int kvm_arch_remove_gdbstub_hw_breakpoint(vaddr addr, vaddr len, |
| 2258 | GdbBreakpointType type) |
| 2259 | { |
| 2260 | /* TODO; To be implemented later. */ |
| 2261 | return -EINVAL; |
| 2262 | } |
| 2263 | |
| 2264 | void kvm_arch_remove_all_gdbstub_hw_breakpoints(void) |
| 2265 | { |
| 2266 | /* TODO; To be implemented later. */ |
| 2267 | } |
| 2268 | |
| 2269 | void kvm_arch_update_guest_debug(CPUState *cs, struct kvm_guest_debug *dbg) |
| 2270 | { |
| 2271 | if (kvm_sw_breakpoints_active(cs)) { |
| 2272 | dbg->control |= KVM_GUESTDBG_ENABLE; |
| 2273 | } |
| 2274 | } |