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1 /*
2 * RISC-V Control and Status Registers.
3 *
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2017-2018 SiFive, Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2 or later, as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "qemu/log.h"
22 #include "qemu/timer.h"
23 #include "cpu.h"
24 #include "target/riscv/tcg/csr.h"
25 #include "tcg/tcg-cpu.h"
26 #include "pmu.h"
27 #include "time_helper.h"
28 #include "exec/cputlb.h"
29 #include "exec/icount.h"
30 #include "accel/tcg/cpu-loop.h"
31 #include "accel/tcg/getpc.h"
32 #include "qapi/error.h"
33 #include "tcg/insn-start-words.h"
34 #include "internals.h"
35 #if !defined(CONFIG_USER_ONLY)
36 #include "target/riscv/tcg/debug.h"
37 #endif
38
39 /* CSR function table public API */
40 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops)
41 {
42 *ops = csr_ops[csrno & (CSR_TABLE_SIZE - 1)];
43 }
44
45 void riscv_set_csr_ops(int csrno, const riscv_csr_operations *ops)
46 {
47 csr_ops[csrno & (CSR_TABLE_SIZE - 1)] = *ops;
48 }
49
50 /* Predicates */
51 #if !defined(CONFIG_USER_ONLY)
52 RISCVException smstateen_acc_ok(CPURISCVState *env, int index, uint64_t bit)
53 {
54 bool virt = env->virt_enabled;
55
56 if (env->priv == PRV_M || !riscv_cpu_cfg(env)->ext_smstateen) {
57 return RISCV_EXCP_NONE;
58 }
59
60 if (!(env->mstateen[index] & bit)) {
61 return RISCV_EXCP_ILLEGAL_INST;
62 }
63
64 if (virt) {
65 if (!(env->hstateen[index] & bit)) {
66 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
67 }
68
69 if (env->priv == PRV_U && !(env->sstateen[index] & bit)) {
70 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
71 }
72 }
73
74 if (env->priv == PRV_U && riscv_has_ext(env, RVS)) {
75 if (!(env->sstateen[index] & bit)) {
76 return RISCV_EXCP_ILLEGAL_INST;
77 }
78 }
79
80 return RISCV_EXCP_NONE;
81 }
82 #endif
83
84 static RISCVException fs(CPURISCVState *env, int csrno)
85 {
86 #if !defined(CONFIG_USER_ONLY)
87 if (!env->debugger && !riscv_cpu_fp_enabled(env) &&
88 !riscv_cpu_cfg(env)->ext_zfinx) {
89 return RISCV_EXCP_ILLEGAL_INST;
90 }
91
92 if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
93 return smstateen_acc_ok(env, 0, SMSTATEEN0_FCSR);
94 }
95 #endif
96 return RISCV_EXCP_NONE;
97 }
98
99 static RISCVException vs(CPURISCVState *env, int csrno)
100 {
101 if (riscv_cpu_cfg(env)->ext_zve32x) {
102 #if !defined(CONFIG_USER_ONLY)
103 if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
104 return RISCV_EXCP_ILLEGAL_INST;
105 }
106 #endif
107 return RISCV_EXCP_NONE;
108 }
109 return RISCV_EXCP_ILLEGAL_INST;
110 }
111
112 static RISCVException ctr(CPURISCVState *env, int csrno)
113 {
114 #if !defined(CONFIG_USER_ONLY)
115 RISCVCPU *cpu = env_archcpu(env);
116 int ctr_index;
117 target_ulong ctr_mask;
118 int base_csrno = CSR_CYCLE;
119 bool rv32 = riscv_cpu_mxl(env) == MXL_RV32 ? true : false;
120
121 if (rv32 && csrno >= CSR_CYCLEH) {
122 /* Offset for RV32 hpmcounternh counters */
123 base_csrno += 0x80;
124 }
125 ctr_index = csrno - base_csrno;
126 ctr_mask = BIT(ctr_index);
127
128 if ((csrno >= CSR_CYCLE && csrno <= CSR_INSTRET) ||
129 (csrno >= CSR_CYCLEH && csrno <= CSR_INSTRETH)) {
130 if (!riscv_cpu_cfg(env)->ext_zicntr) {
131 return RISCV_EXCP_ILLEGAL_INST;
132 }
133
134 goto skip_ext_pmu_check;
135 }
136
137 if (!(cpu->pmu_avail_ctrs & ctr_mask)) {
138 /* No counter is enabled in PMU or the counter is out of range */
139 return RISCV_EXCP_ILLEGAL_INST;
140 }
141
142 skip_ext_pmu_check:
143
144 if (env->debugger) {
145 return RISCV_EXCP_NONE;
146 }
147
148 if (env->priv < PRV_M && !get_field(env->mcounteren, ctr_mask)) {
149 return RISCV_EXCP_ILLEGAL_INST;
150 }
151
152 if (env->virt_enabled) {
153 if (!get_field(env->hcounteren, ctr_mask) ||
154 (env->priv == PRV_U && !get_field(env->scounteren, ctr_mask))) {
155 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
156 }
157 }
158
159 if (riscv_has_ext(env, RVS) && env->priv == PRV_U &&
160 !get_field(env->scounteren, ctr_mask)) {
161 return RISCV_EXCP_ILLEGAL_INST;
162 }
163
164 #endif
165 return RISCV_EXCP_NONE;
166 }
167
168 static RISCVException ctr32(CPURISCVState *env, int csrno)
169 {
170 if (riscv_cpu_mxl(env) != MXL_RV32) {
171 return RISCV_EXCP_ILLEGAL_INST;
172 }
173
174 return ctr(env, csrno);
175 }
176
177 static RISCVException zcmt(CPURISCVState *env, int csrno)
178 {
179 if (!riscv_cpu_cfg(env)->ext_zcmt) {
180 return RISCV_EXCP_ILLEGAL_INST;
181 }
182
183 #if !defined(CONFIG_USER_ONLY)
184 RISCVException ret = smstateen_acc_ok(env, 0, SMSTATEEN0_JVT);
185 if (ret != RISCV_EXCP_NONE) {
186 return ret;
187 }
188 #endif
189
190 return RISCV_EXCP_NONE;
191 }
192
193 static RISCVException cfi_ss(CPURISCVState *env, int csrno)
194 {
195 if (!env_archcpu(env)->cfg.ext_zicfiss) {
196 return RISCV_EXCP_ILLEGAL_INST;
197 }
198
199 /* If ext implemented, M-mode always have access to SSP CSR */
200 if (env->priv == PRV_M) {
201 return RISCV_EXCP_NONE;
202 }
203
204 /* if bcfi not active for current env, access to csr is illegal */
205 if (!cpu_get_bcfien(env)) {
206 #if !defined(CONFIG_USER_ONLY)
207 if (env->debugger) {
208 return RISCV_EXCP_NONE;
209 } else if (env->virt_enabled) {
210 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
211 }
212 #endif
213 return RISCV_EXCP_ILLEGAL_INST;
214 }
215
216 return RISCV_EXCP_NONE;
217 }
218
219 #if !defined(CONFIG_USER_ONLY)
220 static RISCVException mctr(CPURISCVState *env, int csrno)
221 {
222 RISCVCPU *cpu = env_archcpu(env);
223 uint32_t pmu_avail_ctrs = cpu->pmu_avail_ctrs;
224 int ctr_index;
225 int base_csrno = CSR_MHPMCOUNTER3;
226
227 if ((riscv_cpu_mxl(env) == MXL_RV32) && csrno >= CSR_MCYCLEH) {
228 /* Offset for RV32 mhpmcounternh counters */
229 csrno -= 0x80;
230 }
231
232 g_assert(csrno >= CSR_MHPMCOUNTER3 && csrno <= CSR_MHPMCOUNTER31);
233
234 ctr_index = csrno - base_csrno;
235 if ((BIT(ctr_index) & pmu_avail_ctrs >> 3) == 0) {
236 /* The PMU is not enabled or counter is out of range */
237 return RISCV_EXCP_ILLEGAL_INST;
238 }
239
240 return RISCV_EXCP_NONE;
241 }
242
243 static RISCVException mctr32(CPURISCVState *env, int csrno)
244 {
245 if (riscv_cpu_mxl(env) != MXL_RV32) {
246 return RISCV_EXCP_ILLEGAL_INST;
247 }
248
249 return mctr(env, csrno);
250 }
251
252 static RISCVException sscofpmf(CPURISCVState *env, int csrno)
253 {
254 if (!riscv_cpu_cfg(env)->ext_sscofpmf) {
255 return RISCV_EXCP_ILLEGAL_INST;
256 }
257
258 return RISCV_EXCP_NONE;
259 }
260
261 static RISCVException sscofpmf_32(CPURISCVState *env, int csrno)
262 {
263 if (riscv_cpu_mxl(env) != MXL_RV32) {
264 return RISCV_EXCP_ILLEGAL_INST;
265 }
266
267 return sscofpmf(env, csrno);
268 }
269
270 static RISCVException smcntrpmf(CPURISCVState *env, int csrno)
271 {
272 if (!riscv_cpu_cfg(env)->ext_smcntrpmf) {
273 return RISCV_EXCP_ILLEGAL_INST;
274 }
275
276 return RISCV_EXCP_NONE;
277 }
278
279 static RISCVException smcntrpmf_32(CPURISCVState *env, int csrno)
280 {
281 if (riscv_cpu_mxl(env) != MXL_RV32) {
282 return RISCV_EXCP_ILLEGAL_INST;
283 }
284
285 return smcntrpmf(env, csrno);
286 }
287
288 static RISCVException any(CPURISCVState *env, int csrno)
289 {
290 return RISCV_EXCP_NONE;
291 }
292
293 static RISCVException any32(CPURISCVState *env, int csrno)
294 {
295 if (riscv_cpu_mxl(env) != MXL_RV32) {
296 return RISCV_EXCP_ILLEGAL_INST;
297 }
298
299 return any(env, csrno);
300
301 }
302
303 static RISCVException aia_any(CPURISCVState *env, int csrno)
304 {
305 if (!riscv_cpu_cfg(env)->ext_smaia) {
306 return RISCV_EXCP_ILLEGAL_INST;
307 }
308
309 return any(env, csrno);
310 }
311
312 static RISCVException aia_any32(CPURISCVState *env, int csrno)
313 {
314 if (!riscv_cpu_cfg(env)->ext_smaia) {
315 return RISCV_EXCP_ILLEGAL_INST;
316 }
317
318 return any32(env, csrno);
319 }
320
321 static RISCVException csrind_any(CPURISCVState *env, int csrno)
322 {
323 if (!riscv_cpu_cfg(env)->ext_smcsrind) {
324 return RISCV_EXCP_ILLEGAL_INST;
325 }
326
327 return RISCV_EXCP_NONE;
328 }
329
330 static RISCVException csrind_or_aia_any(CPURISCVState *env, int csrno)
331 {
332 if (!riscv_cpu_cfg(env)->ext_smaia && !riscv_cpu_cfg(env)->ext_smcsrind) {
333 return RISCV_EXCP_ILLEGAL_INST;
334 }
335
336 return any(env, csrno);
337 }
338
339 static RISCVException smode(CPURISCVState *env, int csrno)
340 {
341 if (riscv_has_ext(env, RVS)) {
342 return RISCV_EXCP_NONE;
343 }
344
345 return RISCV_EXCP_ILLEGAL_INST;
346 }
347
348 static RISCVException smode32(CPURISCVState *env, int csrno)
349 {
350 if (riscv_cpu_mxl(env) != MXL_RV32) {
351 return RISCV_EXCP_ILLEGAL_INST;
352 }
353
354 return smode(env, csrno);
355 }
356
357 static RISCVException aia_smode(CPURISCVState *env, int csrno)
358 {
359 int ret;
360
361 if (!riscv_cpu_cfg(env)->ext_ssaia) {
362 return RISCV_EXCP_ILLEGAL_INST;
363 }
364
365 if (csrno == CSR_STOPEI) {
366 ret = smstateen_acc_ok(env, 0, SMSTATEEN0_IMSIC);
367 } else {
368 ret = smstateen_acc_ok(env, 0, SMSTATEEN0_AIA);
369 }
370
371 if (ret != RISCV_EXCP_NONE) {
372 return ret;
373 }
374
375 return smode(env, csrno);
376 }
377
378 static RISCVException aia_smode32(CPURISCVState *env, int csrno)
379 {
380 int ret;
381 privilege_mode_t csr_priv = get_field(csrno, 0x300);
382
383 if (csr_priv == PRV_M && !riscv_cpu_cfg(env)->ext_smaia) {
384 return RISCV_EXCP_ILLEGAL_INST;
385 } else if (!riscv_cpu_cfg(env)->ext_ssaia) {
386 return RISCV_EXCP_ILLEGAL_INST;
387 }
388
389 ret = smstateen_acc_ok(env, 0, SMSTATEEN0_AIA);
390 if (ret != RISCV_EXCP_NONE) {
391 return ret;
392 }
393
394 return smode32(env, csrno);
395 }
396
397 static RISCVException scountinhibit_pred(CPURISCVState *env, int csrno)
398 {
399 RISCVCPU *cpu = env_archcpu(env);
400
401 if (!cpu->cfg.ext_ssccfg || !cpu->cfg.ext_smcdeleg) {
402 return RISCV_EXCP_ILLEGAL_INST;
403 }
404
405 if (!get_field(env->menvcfg, MENVCFG_CDE)) {
406 return RISCV_EXCP_ILLEGAL_INST;
407 }
408
409 if (env->virt_enabled) {
410 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
411 }
412
413 return smode(env, csrno);
414 }
415
416 static bool csrind_extensions_present(CPURISCVState *env)
417 {
418 return riscv_cpu_cfg(env)->ext_smcsrind || riscv_cpu_cfg(env)->ext_sscsrind;
419 }
420
421 static bool aia_extensions_present(CPURISCVState *env)
422 {
423 return riscv_cpu_cfg(env)->ext_smaia || riscv_cpu_cfg(env)->ext_ssaia;
424 }
425
426 static bool csrind_or_aia_extensions_present(CPURISCVState *env)
427 {
428 return csrind_extensions_present(env) || aia_extensions_present(env);
429 }
430
431 static RISCVException csrind_smode(CPURISCVState *env, int csrno)
432 {
433 if (!csrind_extensions_present(env)) {
434 return RISCV_EXCP_ILLEGAL_INST;
435 }
436
437 return smode(env, csrno);
438 }
439
440 static RISCVException csrind_or_aia_smode(CPURISCVState *env, int csrno)
441 {
442 if (!csrind_or_aia_extensions_present(env)) {
443 return RISCV_EXCP_ILLEGAL_INST;
444 }
445
446 return smode(env, csrno);
447 }
448
449 static RISCVException hmode(CPURISCVState *env, int csrno)
450 {
451 if (riscv_has_ext(env, RVH)) {
452 return RISCV_EXCP_NONE;
453 }
454
455 return RISCV_EXCP_ILLEGAL_INST;
456 }
457
458 static RISCVException hmode32(CPURISCVState *env, int csrno)
459 {
460 if (riscv_cpu_mxl(env) != MXL_RV32) {
461 return RISCV_EXCP_ILLEGAL_INST;
462 }
463
464 return hmode(env, csrno);
465
466 }
467
468 static RISCVException csrind_hmode(CPURISCVState *env, int csrno)
469 {
470 if (!csrind_extensions_present(env)) {
471 return RISCV_EXCP_ILLEGAL_INST;
472 }
473
474 return hmode(env, csrno);
475 }
476
477 static RISCVException csrind_or_aia_hmode(CPURISCVState *env, int csrno)
478 {
479 if (!csrind_or_aia_extensions_present(env)) {
480 return RISCV_EXCP_ILLEGAL_INST;
481 }
482
483 return hmode(env, csrno);
484 }
485
486 static RISCVException umode(CPURISCVState *env, int csrno)
487 {
488 if (riscv_has_ext(env, RVU)) {
489 return RISCV_EXCP_NONE;
490 }
491
492 return RISCV_EXCP_ILLEGAL_INST;
493 }
494
495 static RISCVException umode32(CPURISCVState *env, int csrno)
496 {
497 if (riscv_cpu_mxl(env) != MXL_RV32) {
498 return RISCV_EXCP_ILLEGAL_INST;
499 }
500
501 return umode(env, csrno);
502 }
503
504 static RISCVException mstateen(CPURISCVState *env, int csrno)
505 {
506 if (!riscv_cpu_cfg(env)->ext_smstateen) {
507 return RISCV_EXCP_ILLEGAL_INST;
508 }
509
510 return any(env, csrno);
511 }
512
513 static RISCVException mstateen_32(CPURISCVState *env, int csrno)
514 {
515 if (riscv_cpu_mxl(env) != MXL_RV32) {
516 return RISCV_EXCP_ILLEGAL_INST;
517 }
518
519 return mstateen(env, csrno);
520 }
521
522 static RISCVException hstateen_pred(CPURISCVState *env, int csrno, int base)
523 {
524 if (!riscv_cpu_cfg(env)->ext_smstateen) {
525 return RISCV_EXCP_ILLEGAL_INST;
526 }
527
528 RISCVException ret = hmode(env, csrno);
529 if (ret != RISCV_EXCP_NONE) {
530 return ret;
531 }
532
533 if (env->debugger) {
534 return RISCV_EXCP_NONE;
535 }
536
537 if (env->priv < PRV_M) {
538 if (!(env->mstateen[csrno - base] & SMSTATEEN_STATEEN)) {
539 return RISCV_EXCP_ILLEGAL_INST;
540 }
541 }
542
543 return RISCV_EXCP_NONE;
544 }
545
546 static RISCVException hstateen(CPURISCVState *env, int csrno)
547 {
548 return hstateen_pred(env, csrno, CSR_HSTATEEN0);
549 }
550
551 static RISCVException hstateenh(CPURISCVState *env, int csrno)
552 {
553 if (riscv_cpu_mxl(env) != MXL_RV32) {
554 return RISCV_EXCP_ILLEGAL_INST;
555 }
556
557 return hstateen_pred(env, csrno, CSR_HSTATEEN0H);
558 }
559
560 static RISCVException sstateen(CPURISCVState *env, int csrno)
561 {
562 bool virt = env->virt_enabled;
563 int index = csrno - CSR_SSTATEEN0;
564
565 if (!riscv_cpu_cfg(env)->ext_smstateen) {
566 return RISCV_EXCP_ILLEGAL_INST;
567 }
568
569 RISCVException ret = smode(env, csrno);
570 if (ret != RISCV_EXCP_NONE) {
571 return ret;
572 }
573
574 if (env->debugger) {
575 return RISCV_EXCP_NONE;
576 }
577
578 if (env->priv < PRV_M) {
579 if (!(env->mstateen[index] & SMSTATEEN_STATEEN)) {
580 return RISCV_EXCP_ILLEGAL_INST;
581 }
582
583 if (virt) {
584 if (!(env->hstateen[index] & SMSTATEEN_STATEEN)) {
585 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
586 }
587 }
588 }
589
590 return RISCV_EXCP_NONE;
591 }
592
593 static RISCVException sstc(CPURISCVState *env, int csrno)
594 {
595 bool hmode_check = false;
596
597 if (!riscv_cpu_cfg(env)->ext_sstc) {
598 return RISCV_EXCP_ILLEGAL_INST;
599 }
600
601 if ((csrno == CSR_VSTIMECMP) || (csrno == CSR_VSTIMECMPH)) {
602 hmode_check = true;
603 }
604
605 RISCVException ret = hmode_check ? hmode(env, csrno) : smode(env, csrno);
606 if (ret != RISCV_EXCP_NONE) {
607 return ret;
608 }
609
610 if (env->debugger) {
611 return RISCV_EXCP_NONE;
612 }
613
614 if (!env->rdtime_fn) {
615 return RISCV_EXCP_ILLEGAL_INST;
616 }
617
618 if (env->priv == PRV_M) {
619 return RISCV_EXCP_NONE;
620 }
621
622 /*
623 * No need of separate function for rv32 as menvcfg stores both menvcfg
624 * menvcfgh for RV32.
625 */
626 if (!(get_field(env->mcounteren, COUNTEREN_TM) &&
627 get_field(env->menvcfg, MENVCFG_STCE))) {
628 return RISCV_EXCP_ILLEGAL_INST;
629 }
630
631 if (env->virt_enabled) {
632 if (!(get_field(env->hcounteren, COUNTEREN_TM) &&
633 get_field(env->henvcfg, HENVCFG_STCE))) {
634 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
635 }
636 }
637
638 return RISCV_EXCP_NONE;
639 }
640
641 static RISCVException sstc_32(CPURISCVState *env, int csrno)
642 {
643 if (riscv_cpu_mxl(env) != MXL_RV32) {
644 return RISCV_EXCP_ILLEGAL_INST;
645 }
646
647 return sstc(env, csrno);
648 }
649
650 static RISCVException satp(CPURISCVState *env, int csrno)
651 {
652 if (env->priv == PRV_S && !env->virt_enabled &&
653 get_field(env->mstatus, MSTATUS_TVM)) {
654 return RISCV_EXCP_ILLEGAL_INST;
655 }
656 if (env->priv == PRV_S && env->virt_enabled &&
657 get_field(env->hstatus, HSTATUS_VTVM)) {
658 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
659 }
660
661 return smode(env, csrno);
662 }
663
664 static RISCVException hgatp(CPURISCVState *env, int csrno)
665 {
666 if (env->priv == PRV_S && !env->virt_enabled &&
667 get_field(env->mstatus, MSTATUS_TVM)) {
668 return RISCV_EXCP_ILLEGAL_INST;
669 }
670
671 return hmode(env, csrno);
672 }
673
674 /*
675 * M-mode:
676 * Without ext_smctr raise illegal inst excep.
677 * Otherwise everything is accessible to m-mode.
678 *
679 * S-mode:
680 * Without ext_ssctr or mstateen.ctr raise illegal inst excep.
681 * Otherwise everything other than mctrctl is accessible.
682 *
683 * VS-mode:
684 * Without ext_ssctr or mstateen.ctr raise illegal inst excep.
685 * Without hstateen.ctr raise virtual illegal inst excep.
686 * Otherwise allow sctrctl (vsctrctl), sctrstatus, 0x200-0x2ff entry range.
687 * Always raise illegal instruction exception for sctrdepth.
688 */
689 static RISCVException ctr_mmode(CPURISCVState *env, int csrno)
690 {
691 /* Check if smctr-ext is present */
692 if (riscv_cpu_cfg(env)->ext_smctr) {
693 return RISCV_EXCP_NONE;
694 }
695
696 return RISCV_EXCP_ILLEGAL_INST;
697 }
698
699 static RISCVException ctr_smode(CPURISCVState *env, int csrno)
700 {
701 const RISCVCPUConfig *cfg = riscv_cpu_cfg(env);
702
703 if (!cfg->ext_smctr && !cfg->ext_ssctr) {
704 return RISCV_EXCP_ILLEGAL_INST;
705 }
706
707 RISCVException ret = smstateen_acc_ok(env, 0, SMSTATEEN0_CTR);
708 if (ret == RISCV_EXCP_NONE && csrno == CSR_SCTRDEPTH &&
709 env->virt_enabled) {
710 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
711 }
712
713 return ret;
714 }
715
716 static RISCVException aia_hmode(CPURISCVState *env, int csrno)
717 {
718 int ret;
719
720 if (!riscv_cpu_cfg(env)->ext_ssaia) {
721 return RISCV_EXCP_ILLEGAL_INST;
722 }
723
724 if (csrno == CSR_VSTOPEI) {
725 ret = smstateen_acc_ok(env, 0, SMSTATEEN0_IMSIC);
726 } else {
727 ret = smstateen_acc_ok(env, 0, SMSTATEEN0_AIA);
728 }
729
730 if (ret != RISCV_EXCP_NONE) {
731 return ret;
732 }
733
734 return hmode(env, csrno);
735 }
736
737 static RISCVException aia_hmode32(CPURISCVState *env, int csrno)
738 {
739 int ret;
740
741 if (!riscv_cpu_cfg(env)->ext_ssaia) {
742 return RISCV_EXCP_ILLEGAL_INST;
743 }
744
745 ret = smstateen_acc_ok(env, 0, SMSTATEEN0_AIA);
746 if (ret != RISCV_EXCP_NONE) {
747 return ret;
748 }
749
750 if (!riscv_cpu_cfg(env)->ext_ssaia) {
751 return RISCV_EXCP_ILLEGAL_INST;
752 }
753
754 return hmode32(env, csrno);
755 }
756
757 static RISCVException dbltrp_hmode(CPURISCVState *env, int csrno)
758 {
759 if (riscv_cpu_cfg(env)->ext_ssdbltrp) {
760 return RISCV_EXCP_NONE;
761 }
762
763 return hmode(env, csrno);
764 }
765
766 static RISCVException pmp(CPURISCVState *env, int csrno)
767 {
768 if (riscv_cpu_cfg(env)->pmp) {
769 int max_pmpcfg = (env->priv_ver >= PRIV_VERSION_1_12_0) ?
770 + CSR_PMPCFG15 : CSR_PMPCFG3;
771
772 if (csrno <= max_pmpcfg) {
773 uint32_t reg_index = csrno - CSR_PMPCFG0;
774
775 /* TODO: RV128 restriction check */
776 if ((reg_index & 1) && (riscv_cpu_mxl(env) == MXL_RV64)) {
777 return RISCV_EXCP_ILLEGAL_INST;
778 }
779 }
780
781 return RISCV_EXCP_NONE;
782 }
783
784 return RISCV_EXCP_ILLEGAL_INST;
785 }
786
787 static RISCVException have_mseccfg(CPURISCVState *env, int csrno)
788 {
789 if (riscv_cpu_cfg(env)->ext_smepmp) {
790 return RISCV_EXCP_NONE;
791 }
792 if (riscv_cpu_cfg(env)->ext_zkr) {
793 return RISCV_EXCP_NONE;
794 }
795 if (riscv_cpu_cfg(env)->ext_smmpm) {
796 return RISCV_EXCP_NONE;
797 }
798 if (riscv_cpu_cfg(env)->ext_zicfilp) {
799 return RISCV_EXCP_NONE;
800 }
801
802 return RISCV_EXCP_ILLEGAL_INST;
803 }
804
805 static RISCVException debug(CPURISCVState *env, int csrno)
806 {
807 if (riscv_cpu_cfg(env)->debug) {
808 return RISCV_EXCP_NONE;
809 }
810
811 return RISCV_EXCP_ILLEGAL_INST;
812 }
813
814 static RISCVException rnmi(CPURISCVState *env, int csrno)
815 {
816 RISCVCPU *cpu = env_archcpu(env);
817
818 if (cpu->cfg.ext_smrnmi) {
819 return RISCV_EXCP_NONE;
820 }
821
822 return RISCV_EXCP_ILLEGAL_INST;
823 }
824 #endif
825
826 static RISCVException seed(CPURISCVState *env, int csrno)
827 {
828 if (!riscv_cpu_cfg(env)->ext_zkr) {
829 return RISCV_EXCP_ILLEGAL_INST;
830 }
831
832 #if !defined(CONFIG_USER_ONLY)
833 if (env->debugger) {
834 return RISCV_EXCP_NONE;
835 }
836
837 /*
838 * With a CSR read-write instruction:
839 * 1) The seed CSR is always available in machine mode as normal.
840 * 2) Attempted access to seed from virtual modes VS and VU always raises
841 * an exception(virtual instruction exception only if mseccfg.sseed=1).
842 * 3) Without the corresponding access control bit set to 1, any attempted
843 * access to seed from U, S or HS modes will raise an illegal instruction
844 * exception.
845 */
846 if (env->priv == PRV_M) {
847 return RISCV_EXCP_NONE;
848 } else if (env->virt_enabled) {
849 if (env->mseccfg & MSECCFG_SSEED) {
850 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
851 } else {
852 return RISCV_EXCP_ILLEGAL_INST;
853 }
854 } else {
855 if (env->priv == PRV_S && (env->mseccfg & MSECCFG_SSEED)) {
856 return RISCV_EXCP_NONE;
857 } else if (env->priv == PRV_U && (env->mseccfg & MSECCFG_USEED)) {
858 return RISCV_EXCP_NONE;
859 } else {
860 return RISCV_EXCP_ILLEGAL_INST;
861 }
862 }
863 #else
864 return RISCV_EXCP_NONE;
865 #endif
866 }
867
868 /* zicfiss CSR_SSP read and write */
869 static RISCVException read_ssp(CPURISCVState *env, int csrno,
870 target_ulong *val)
871 {
872 *val = env->ssp;
873 return RISCV_EXCP_NONE;
874 }
875
876 static RISCVException write_ssp(CPURISCVState *env, int csrno,
877 target_ulong val, uintptr_t ra)
878 {
879 env->ssp = val;
880 return RISCV_EXCP_NONE;
881 }
882
883 /* User Floating-Point CSRs */
884 static RISCVException read_fflags(CPURISCVState *env, int csrno,
885 target_ulong *val)
886 {
887 *val = riscv_cpu_get_fflags(env);
888 return RISCV_EXCP_NONE;
889 }
890
891 static RISCVException write_fflags(CPURISCVState *env, int csrno,
892 target_ulong val, uintptr_t ra)
893 {
894 #if !defined(CONFIG_USER_ONLY)
895 if (riscv_has_ext(env, RVF)) {
896 env->mstatus |= MSTATUS_FS;
897 }
898 #endif
899 riscv_cpu_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT));
900 return RISCV_EXCP_NONE;
901 }
902
903 static RISCVException read_frm(CPURISCVState *env, int csrno,
904 target_ulong *val)
905 {
906 *val = env->frm;
907 return RISCV_EXCP_NONE;
908 }
909
910 static RISCVException write_frm(CPURISCVState *env, int csrno,
911 target_ulong val, uintptr_t ra)
912 {
913 #if !defined(CONFIG_USER_ONLY)
914 if (riscv_has_ext(env, RVF)) {
915 env->mstatus |= MSTATUS_FS;
916 }
917 #endif
918 env->frm = val & (FSR_RD >> FSR_RD_SHIFT);
919 return RISCV_EXCP_NONE;
920 }
921
922 static RISCVException read_fcsr(CPURISCVState *env, int csrno,
923 target_ulong *val)
924 {
925 /*
926 * This is an 8-bit operation, fflags make up the lower 5 bits and
927 * frm the upper 3 bits of fcsr.
928 */
929 *val = (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT)
930 | (env->frm << FSR_RD_SHIFT);
931 return RISCV_EXCP_NONE;
932 }
933
934 static RISCVException write_fcsr(CPURISCVState *env, int csrno,
935 target_ulong val, uintptr_t ra)
936 {
937 #if !defined(CONFIG_USER_ONLY)
938 if (riscv_has_ext(env, RVF)) {
939 env->mstatus |= MSTATUS_FS;
940 }
941 #endif
942 env->frm = (val & FSR_RD) >> FSR_RD_SHIFT;
943 riscv_cpu_set_fflags(env, (val & FSR_AEXC) >> FSR_AEXC_SHIFT);
944 return RISCV_EXCP_NONE;
945 }
946
947 static RISCVException read_vtype(CPURISCVState *env, int csrno,
948 target_ulong *val)
949 {
950 uint64_t vill;
951 int xl = env->xl;
952 /*
953 * TCG plugins can read registers before env->xl is initialized.
954 * Fall back to the CPU's maximum XLEN in that early-init case.
955 */
956 if (xl == 0) {
957 xl = riscv_cpu_mxl(env);
958 }
959
960 switch (xl) {
961 case MXL_RV32:
962 vill = (uint32_t)env->vill << 31;
963 break;
964 case MXL_RV64:
965 vill = (uint64_t)env->vill << 63;
966 break;
967 default:
968 g_assert_not_reached();
969 }
970 *val = (target_ulong)vill | env->vtype;
971 return RISCV_EXCP_NONE;
972 }
973
974 static RISCVException read_vl(CPURISCVState *env, int csrno,
975 target_ulong *val)
976 {
977 *val = env->vl;
978 return RISCV_EXCP_NONE;
979 }
980
981 static RISCVException read_vlenb(CPURISCVState *env, int csrno,
982 target_ulong *val)
983 {
984 *val = riscv_cpu_cfg(env)->vlenb;
985 return RISCV_EXCP_NONE;
986 }
987
988 static RISCVException read_vxrm(CPURISCVState *env, int csrno,
989 target_ulong *val)
990 {
991 *val = env->vxrm;
992 return RISCV_EXCP_NONE;
993 }
994
995 static RISCVException write_vxrm(CPURISCVState *env, int csrno,
996 target_ulong val, uintptr_t ra)
997 {
998 #if !defined(CONFIG_USER_ONLY)
999 env->mstatus |= MSTATUS_VS;
1000 #endif
1001 env->vxrm = val & (VCSR_VXRM >> VCSR_VXRM_SHIFT);
1002 return RISCV_EXCP_NONE;
1003 }
1004
1005 static RISCVException read_vxsat(CPURISCVState *env, int csrno,
1006 target_ulong *val)
1007 {
1008 *val = env->vxsat & BIT(0);
1009 return RISCV_EXCP_NONE;
1010 }
1011
1012 static RISCVException write_vxsat(CPURISCVState *env, int csrno,
1013 target_ulong val, uintptr_t ra)
1014 {
1015 #if !defined(CONFIG_USER_ONLY)
1016 env->mstatus |= MSTATUS_VS;
1017 #endif
1018 env->vxsat = val & BIT(0);
1019 return RISCV_EXCP_NONE;
1020 }
1021
1022 static RISCVException read_vstart(CPURISCVState *env, int csrno,
1023 target_ulong *val)
1024 {
1025 *val = env->vstart;
1026 return RISCV_EXCP_NONE;
1027 }
1028
1029 static RISCVException write_vstart(CPURISCVState *env, int csrno,
1030 target_ulong val, uintptr_t ra)
1031 {
1032 #if !defined(CONFIG_USER_ONLY)
1033 env->mstatus |= MSTATUS_VS;
1034 #endif
1035 /*
1036 * The vstart CSR is defined to have only enough writable bits
1037 * to hold the largest element index, i.e. lg2(VLEN) bits.
1038 */
1039 env->vstart = val & ~(~0ULL << ctzl(riscv_cpu_cfg(env)->vlenb << 3));
1040 return RISCV_EXCP_NONE;
1041 }
1042
1043 static RISCVException read_vcsr(CPURISCVState *env, int csrno,
1044 target_ulong *val)
1045 {
1046 *val = (env->vxrm << VCSR_VXRM_SHIFT) | (env->vxsat << VCSR_VXSAT_SHIFT);
1047 return RISCV_EXCP_NONE;
1048 }
1049
1050 static RISCVException write_vcsr(CPURISCVState *env, int csrno,
1051 target_ulong val, uintptr_t ra)
1052 {
1053 #if !defined(CONFIG_USER_ONLY)
1054 env->mstatus |= MSTATUS_VS;
1055 #endif
1056 env->vxrm = (val & VCSR_VXRM) >> VCSR_VXRM_SHIFT;
1057 env->vxsat = (val & VCSR_VXSAT) >> VCSR_VXSAT_SHIFT;
1058 return RISCV_EXCP_NONE;
1059 }
1060
1061 #if defined(CONFIG_USER_ONLY)
1062 /* User Timers and Counters */
1063 static target_ulong get_ticks(bool shift)
1064 {
1065 int64_t val = cpu_get_host_ticks();
1066 target_ulong result = shift ? val >> 32 : val;
1067
1068 return result;
1069 }
1070
1071 static RISCVException read_time(CPURISCVState *env, int csrno,
1072 target_ulong *val)
1073 {
1074 *val = cpu_get_host_ticks();
1075 return RISCV_EXCP_NONE;
1076 }
1077
1078 static RISCVException read_timeh(CPURISCVState *env, int csrno,
1079 target_ulong *val)
1080 {
1081 *val = cpu_get_host_ticks() >> 32;
1082 return RISCV_EXCP_NONE;
1083 }
1084
1085 static RISCVException read_hpmcounter(CPURISCVState *env, int csrno,
1086 target_ulong *val)
1087 {
1088 *val = get_ticks(false);
1089 return RISCV_EXCP_NONE;
1090 }
1091
1092 static RISCVException read_hpmcounterh(CPURISCVState *env, int csrno,
1093 target_ulong *val)
1094 {
1095 *val = get_ticks(true);
1096 return RISCV_EXCP_NONE;
1097 }
1098
1099 #else /* CONFIG_USER_ONLY */
1100
1101 static RISCVException read_mcyclecfg(CPURISCVState *env, int csrno,
1102 target_ulong *val)
1103 {
1104 bool rv32 = riscv_cpu_mxl(env) == MXL_RV32;
1105 *val = extract64(env->mcyclecfg, 0, rv32 ? 32 : 64);
1106 return RISCV_EXCP_NONE;
1107 }
1108
1109 static RISCVException write_mcyclecfg(CPURISCVState *env, int csrno,
1110 target_ulong val, uintptr_t ra)
1111 {
1112 uint64_t inh_avail_mask;
1113
1114 if (riscv_cpu_mxl(env) == MXL_RV32) {
1115 env->mcyclecfg = deposit64(env->mcyclecfg, 0, 32, val);
1116 } else {
1117 /* Set xINH fields if priv mode supported */
1118 inh_avail_mask = ~MHPMEVENT_FILTER_MASK | MCYCLECFG_BIT_MINH;
1119 inh_avail_mask |= riscv_has_ext(env, RVU) ? MCYCLECFG_BIT_UINH : 0;
1120 inh_avail_mask |= riscv_has_ext(env, RVS) ? MCYCLECFG_BIT_SINH : 0;
1121 inh_avail_mask |= (riscv_has_ext(env, RVH) &&
1122 riscv_has_ext(env, RVU)) ? MCYCLECFG_BIT_VUINH : 0;
1123 inh_avail_mask |= (riscv_has_ext(env, RVH) &&
1124 riscv_has_ext(env, RVS)) ? MCYCLECFG_BIT_VSINH : 0;
1125 env->mcyclecfg = val & inh_avail_mask;
1126 }
1127
1128 return RISCV_EXCP_NONE;
1129 }
1130
1131 static RISCVException read_mcyclecfgh(CPURISCVState *env, int csrno,
1132 target_ulong *val)
1133 {
1134 *val = extract64(env->mcyclecfg, 32, 32);
1135 return RISCV_EXCP_NONE;
1136 }
1137
1138 static RISCVException write_mcyclecfgh(CPURISCVState *env, int csrno,
1139 target_ulong val, uintptr_t ra)
1140 {
1141 target_ulong inh_avail_mask = (target_ulong)(~MHPMEVENTH_FILTER_MASK |
1142 MCYCLECFGH_BIT_MINH);
1143
1144 /* Set xINH fields if priv mode supported */
1145 inh_avail_mask |= riscv_has_ext(env, RVU) ? MCYCLECFGH_BIT_UINH : 0;
1146 inh_avail_mask |= riscv_has_ext(env, RVS) ? MCYCLECFGH_BIT_SINH : 0;
1147 inh_avail_mask |= (riscv_has_ext(env, RVH) &&
1148 riscv_has_ext(env, RVU)) ? MCYCLECFGH_BIT_VUINH : 0;
1149 inh_avail_mask |= (riscv_has_ext(env, RVH) &&
1150 riscv_has_ext(env, RVS)) ? MCYCLECFGH_BIT_VSINH : 0;
1151
1152 env->mcyclecfg = deposit64(env->mcyclecfg, 32, 32, val & inh_avail_mask);
1153 return RISCV_EXCP_NONE;
1154 }
1155
1156 static RISCVException read_minstretcfg(CPURISCVState *env, int csrno,
1157 target_ulong *val)
1158 {
1159 bool rv32 = riscv_cpu_mxl(env) == MXL_RV32;
1160 *val = extract64(env->minstretcfg, 0, rv32 ? 32 : 64);
1161 return RISCV_EXCP_NONE;
1162 }
1163
1164 static RISCVException write_minstretcfg(CPURISCVState *env, int csrno,
1165 target_ulong val, uintptr_t ra)
1166 {
1167 uint64_t inh_avail_mask;
1168
1169 if (riscv_cpu_mxl(env) == MXL_RV32) {
1170 env->minstretcfg = val;
1171 } else {
1172 inh_avail_mask = ~MHPMEVENT_FILTER_MASK | MINSTRETCFG_BIT_MINH;
1173 inh_avail_mask |= riscv_has_ext(env, RVU) ? MINSTRETCFG_BIT_UINH : 0;
1174 inh_avail_mask |= riscv_has_ext(env, RVS) ? MINSTRETCFG_BIT_SINH : 0;
1175 inh_avail_mask |= (riscv_has_ext(env, RVH) &&
1176 riscv_has_ext(env, RVU)) ? MINSTRETCFG_BIT_VUINH : 0;
1177 inh_avail_mask |= (riscv_has_ext(env, RVH) &&
1178 riscv_has_ext(env, RVS)) ? MINSTRETCFG_BIT_VSINH : 0;
1179 env->minstretcfg = val & inh_avail_mask;
1180 }
1181 return RISCV_EXCP_NONE;
1182 }
1183
1184 static RISCVException read_minstretcfgh(CPURISCVState *env, int csrno,
1185 target_ulong *val)
1186 {
1187 *val = extract64(env->minstretcfg, 32, 32);
1188 return RISCV_EXCP_NONE;
1189 }
1190
1191 static RISCVException write_minstretcfgh(CPURISCVState *env, int csrno,
1192 target_ulong val, uintptr_t ra)
1193 {
1194 target_ulong inh_avail_mask = (target_ulong)(~MHPMEVENTH_FILTER_MASK |
1195 MINSTRETCFGH_BIT_MINH);
1196
1197 inh_avail_mask |= riscv_has_ext(env, RVU) ? MINSTRETCFGH_BIT_UINH : 0;
1198 inh_avail_mask |= riscv_has_ext(env, RVS) ? MINSTRETCFGH_BIT_SINH : 0;
1199 inh_avail_mask |= (riscv_has_ext(env, RVH) &&
1200 riscv_has_ext(env, RVU)) ? MINSTRETCFGH_BIT_VUINH : 0;
1201 inh_avail_mask |= (riscv_has_ext(env, RVH) &&
1202 riscv_has_ext(env, RVS)) ? MINSTRETCFGH_BIT_VSINH : 0;
1203
1204 env->minstretcfg = deposit64(env->minstretcfg, 32, 32,
1205 val & inh_avail_mask);
1206 return RISCV_EXCP_NONE;
1207 }
1208
1209 static RISCVException read_mhpmevent(CPURISCVState *env, int csrno,
1210 target_ulong *val)
1211 {
1212 int evt_index = csrno - CSR_MCOUNTINHIBIT;
1213 bool rv32 = riscv_cpu_mxl(env) == MXL_RV32;
1214
1215 *val = extract64(env->mhpmevent_val[evt_index], 0, rv32 ? 32 : 64);
1216
1217 return RISCV_EXCP_NONE;
1218 }
1219
1220 static RISCVException write_mhpmevent(CPURISCVState *env, int csrno,
1221 target_ulong val, uintptr_t ra)
1222 {
1223 int evt_index = csrno - CSR_MCOUNTINHIBIT;
1224 uint64_t mhpmevt_val;
1225 uint64_t inh_avail_mask;
1226
1227 if (riscv_cpu_mxl(env) == MXL_RV32) {
1228 mhpmevt_val = deposit64(env->mhpmevent_val[evt_index], 0, 32, val);
1229 } else {
1230 inh_avail_mask = ~MHPMEVENT_FILTER_MASK | MHPMEVENT_BIT_MINH;
1231 inh_avail_mask |= riscv_has_ext(env, RVU) ? MHPMEVENT_BIT_UINH : 0;
1232 inh_avail_mask |= riscv_has_ext(env, RVS) ? MHPMEVENT_BIT_SINH : 0;
1233 inh_avail_mask |= (riscv_has_ext(env, RVH) &&
1234 riscv_has_ext(env, RVU)) ? MHPMEVENT_BIT_VUINH : 0;
1235 inh_avail_mask |= (riscv_has_ext(env, RVH) &&
1236 riscv_has_ext(env, RVS)) ? MHPMEVENT_BIT_VSINH : 0;
1237 mhpmevt_val = val & inh_avail_mask;
1238 }
1239
1240 env->mhpmevent_val[evt_index] = mhpmevt_val;
1241 riscv_pmu_update_event_map(env, mhpmevt_val, evt_index);
1242
1243 return RISCV_EXCP_NONE;
1244 }
1245
1246 static RISCVException read_mhpmeventh(CPURISCVState *env, int csrno,
1247 target_ulong *val)
1248 {
1249 int evt_index = csrno - CSR_MHPMEVENT3H + 3;
1250
1251 *val = extract64(env->mhpmevent_val[evt_index], 32, 32);
1252
1253 return RISCV_EXCP_NONE;
1254 }
1255
1256 static RISCVException write_mhpmeventh(CPURISCVState *env, int csrno,
1257 target_ulong val, uintptr_t ra)
1258 {
1259 int evt_index = csrno - CSR_MHPMEVENT3H + 3;
1260 target_ulong inh_avail_mask = (target_ulong)(~MHPMEVENTH_FILTER_MASK |
1261 MHPMEVENTH_BIT_MINH);
1262
1263 inh_avail_mask |= riscv_has_ext(env, RVU) ? MHPMEVENTH_BIT_UINH : 0;
1264 inh_avail_mask |= riscv_has_ext(env, RVS) ? MHPMEVENTH_BIT_SINH : 0;
1265 inh_avail_mask |= (riscv_has_ext(env, RVH) &&
1266 riscv_has_ext(env, RVU)) ? MHPMEVENTH_BIT_VUINH : 0;
1267 inh_avail_mask |= (riscv_has_ext(env, RVH) &&
1268 riscv_has_ext(env, RVS)) ? MHPMEVENTH_BIT_VSINH : 0;
1269
1270 env->mhpmevent_val[evt_index] = deposit64(env->mhpmevent_val[evt_index],
1271 32, 32, val & inh_avail_mask);
1272
1273 riscv_pmu_update_event_map(env, env->mhpmevent_val[evt_index], evt_index);
1274
1275 return RISCV_EXCP_NONE;
1276 }
1277
1278 static uint64_t riscv_pmu_ctr_get_fixed_counters_val(CPURISCVState *env,
1279 int counter_idx)
1280 {
1281 int inst = riscv_pmu_ctr_monitor_instructions(env, counter_idx);
1282 uint64_t *counter_arr_virt = env->pmu_fixed_ctrs[inst].counter_virt;
1283 uint64_t *counter_arr = env->pmu_fixed_ctrs[inst].counter;
1284 uint64_t curr_val = 0;
1285 uint64_t cfg_val = 0;
1286
1287 if (counter_idx == 0) {
1288 cfg_val = env->mcyclecfg;
1289 } else if (counter_idx == 2) {
1290 cfg_val = env->minstretcfg;
1291 } else {
1292 cfg_val = env->mhpmevent_val[counter_idx];
1293 cfg_val &= MHPMEVENT_FILTER_MASK;
1294 }
1295
1296 if (!cfg_val) {
1297 if (icount_enabled()) {
1298 curr_val = inst ? icount_get_raw() : icount_get();
1299 } else {
1300 curr_val = cpu_get_host_ticks();
1301 }
1302
1303 return curr_val;
1304 }
1305
1306 /* Update counter before reading. */
1307 riscv_pmu_update_fixed_ctrs(env, env->priv, env->virt_enabled);
1308
1309 if (!(cfg_val & MCYCLECFG_BIT_MINH)) {
1310 curr_val += counter_arr[PRV_M];
1311 }
1312
1313 if (!(cfg_val & MCYCLECFG_BIT_SINH)) {
1314 curr_val += counter_arr[PRV_S];
1315 }
1316
1317 if (!(cfg_val & MCYCLECFG_BIT_UINH)) {
1318 curr_val += counter_arr[PRV_U];
1319 }
1320
1321 if (!(cfg_val & MCYCLECFG_BIT_VSINH)) {
1322 curr_val += counter_arr_virt[PRV_S];
1323 }
1324
1325 if (!(cfg_val & MCYCLECFG_BIT_VUINH)) {
1326 curr_val += counter_arr_virt[PRV_U];
1327 }
1328
1329 return curr_val;
1330 }
1331
1332 static RISCVException riscv_pmu_write_ctr(CPURISCVState *env, target_ulong val,
1333 uint32_t ctr_idx)
1334 {
1335 PMUCTRState *counter = &env->pmu_ctrs[ctr_idx];
1336 bool rv32 = riscv_cpu_mxl(env) == MXL_RV32;
1337 int deposit_size = rv32 ? 32 : 64;
1338 uint64_t ctr;
1339
1340 counter->mhpmcounter_val = deposit64(counter->mhpmcounter_val,
1341 0, deposit_size, val);
1342
1343 if (!get_field(env->mcountinhibit, BIT(ctr_idx)) &&
1344 (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) ||
1345 riscv_pmu_ctr_monitor_instructions(env, ctr_idx))) {
1346 ctr = riscv_pmu_ctr_get_fixed_counters_val(env, ctr_idx);
1347 counter->mhpmcounter_prev = deposit64(counter->mhpmcounter_prev,
1348 0, deposit_size, ctr);
1349 if (ctr_idx > 2) {
1350 riscv_pmu_setup_timer(env, counter->mhpmcounter_val, ctr_idx);
1351 }
1352 } else {
1353 /* Other counters can keep incrementing from the given value */
1354 counter->mhpmcounter_prev = deposit64(counter->mhpmcounter_prev,
1355 0, deposit_size, val);
1356
1357 }
1358
1359 return RISCV_EXCP_NONE;
1360 }
1361
1362 static RISCVException riscv_pmu_write_ctrh(CPURISCVState *env, target_ulong val,
1363 uint32_t ctr_idx)
1364 {
1365 PMUCTRState *counter = &env->pmu_ctrs[ctr_idx];
1366 uint64_t ctrh;
1367
1368 counter->mhpmcounter_val = deposit64(counter->mhpmcounter_val,
1369 32, 32, val);
1370 if (!get_field(env->mcountinhibit, BIT(ctr_idx)) &&
1371 (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) ||
1372 riscv_pmu_ctr_monitor_instructions(env, ctr_idx))) {
1373 ctrh = riscv_pmu_ctr_get_fixed_counters_val(env, ctr_idx);
1374 counter->mhpmcounter_prev = deposit64(counter->mhpmcounter_prev,
1375 32, 32, ctrh);
1376 if (ctr_idx > 2) {
1377 riscv_pmu_setup_timer(env, counter->mhpmcounter_val, ctr_idx);
1378 }
1379 } else {
1380 counter->mhpmcounter_prev = deposit64(counter->mhpmcounter_prev,
1381 32, 32, val);
1382 }
1383
1384 return RISCV_EXCP_NONE;
1385 }
1386
1387 static RISCVException write_mhpmcounter(CPURISCVState *env, int csrno,
1388 target_ulong val, uintptr_t ra)
1389 {
1390 int ctr_idx = csrno - CSR_MCYCLE;
1391
1392 return riscv_pmu_write_ctr(env, val, ctr_idx);
1393 }
1394
1395 static RISCVException write_mhpmcounterh(CPURISCVState *env, int csrno,
1396 target_ulong val, uintptr_t ra)
1397 {
1398 int ctr_idx = csrno - CSR_MCYCLEH;
1399
1400 return riscv_pmu_write_ctrh(env, val, ctr_idx);
1401 }
1402
1403 RISCVException riscv_pmu_read_ctr(CPURISCVState *env, target_ulong *val,
1404 bool upper_half, uint32_t ctr_idx)
1405 {
1406 PMUCTRState *counter = &env->pmu_ctrs[ctr_idx];
1407 bool rv32 = riscv_cpu_mxl(env) == MXL_RV32;
1408 int start = upper_half ? 32 : 0;
1409 int length = rv32 ? 32 : 64;
1410 uint64_t ctr_prev, ctr_val;
1411
1412 /* Ensure upper_half is only set for XLEN == 32 */
1413 g_assert(rv32 || !upper_half);
1414
1415 ctr_prev = extract64(counter->mhpmcounter_prev, start, length);
1416 ctr_val = extract64(counter->mhpmcounter_val, start, length);
1417
1418 if (get_field(env->mcountinhibit, BIT(ctr_idx))) {
1419 /*
1420 * Counter should not increment if inhibit bit is set. Just return the
1421 * current counter value.
1422 */
1423 *val = ctr_val;
1424 return RISCV_EXCP_NONE;
1425 }
1426
1427 /*
1428 * The kernel computes the perf delta by subtracting the current value from
1429 * the value it initialized previously (ctr_val).
1430 */
1431 if (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) ||
1432 riscv_pmu_ctr_monitor_instructions(env, ctr_idx)) {
1433 uint64_t cntr = riscv_pmu_ctr_get_fixed_counters_val(env, ctr_idx) -
1434 ctr_prev + ctr_val;
1435 *val = extract64(cntr, start, length);
1436 } else {
1437 *val = ctr_val;
1438 }
1439
1440 return RISCV_EXCP_NONE;
1441 }
1442
1443 static RISCVException read_hpmcounter(CPURISCVState *env, int csrno,
1444 target_ulong *val)
1445 {
1446 uint16_t ctr_index;
1447
1448 if (csrno >= CSR_MCYCLE && csrno <= CSR_MHPMCOUNTER31) {
1449 ctr_index = csrno - CSR_MCYCLE;
1450 } else if (csrno >= CSR_CYCLE && csrno <= CSR_HPMCOUNTER31) {
1451 ctr_index = csrno - CSR_CYCLE;
1452 } else {
1453 return RISCV_EXCP_ILLEGAL_INST;
1454 }
1455
1456 return riscv_pmu_read_ctr(env, val, false, ctr_index);
1457 }
1458
1459 static RISCVException read_hpmcounterh(CPURISCVState *env, int csrno,
1460 target_ulong *val)
1461 {
1462 uint16_t ctr_index;
1463
1464 if (csrno >= CSR_MCYCLEH && csrno <= CSR_MHPMCOUNTER31H) {
1465 ctr_index = csrno - CSR_MCYCLEH;
1466 } else if (csrno >= CSR_CYCLEH && csrno <= CSR_HPMCOUNTER31H) {
1467 ctr_index = csrno - CSR_CYCLEH;
1468 } else {
1469 return RISCV_EXCP_ILLEGAL_INST;
1470 }
1471
1472 return riscv_pmu_read_ctr(env, val, true, ctr_index);
1473 }
1474
1475 static int rmw_cd_mhpmcounter(CPURISCVState *env, int ctr_idx,
1476 target_ulong *val, target_ulong new_val,
1477 target_ulong wr_mask)
1478 {
1479 if (wr_mask != 0 && wr_mask != -1) {
1480 return -EINVAL;
1481 }
1482
1483 if (!wr_mask && val) {
1484 riscv_pmu_read_ctr(env, val, false, ctr_idx);
1485 } else if (wr_mask) {
1486 riscv_pmu_write_ctr(env, new_val, ctr_idx);
1487 } else {
1488 return -EINVAL;
1489 }
1490
1491 return 0;
1492 }
1493
1494 static int rmw_cd_mhpmcounterh(CPURISCVState *env, int ctr_idx,
1495 target_ulong *val, target_ulong new_val,
1496 target_ulong wr_mask)
1497 {
1498 if (wr_mask != 0 && wr_mask != -1) {
1499 return -EINVAL;
1500 }
1501
1502 if (!wr_mask && val) {
1503 riscv_pmu_read_ctr(env, val, true, ctr_idx);
1504 } else if (wr_mask) {
1505 riscv_pmu_write_ctrh(env, new_val, ctr_idx);
1506 } else {
1507 return -EINVAL;
1508 }
1509
1510 return 0;
1511 }
1512
1513 static int rmw_cd_mhpmevent(CPURISCVState *env, int evt_index,
1514 target_ulong *val, target_ulong new_val,
1515 uint64_t wr_mask)
1516 {
1517 uint64_t mhpmevt_val = env->mhpmevent_val[evt_index];
1518
1519 if (wr_mask != 0 && wr_mask != -1) {
1520 return -EINVAL;
1521 }
1522
1523 if (!wr_mask && val) {
1524 *val = mhpmevt_val;
1525 if (riscv_cpu_cfg(env)->ext_sscofpmf) {
1526 *val &= ~MHPMEVENT_BIT_MINH;
1527 }
1528 } else if (wr_mask) {
1529 wr_mask &= ~MHPMEVENT_BIT_MINH;
1530 /* wr_mask is 64-bit so upper 32 bits of mhpmevt_val are retained */
1531 mhpmevt_val = (new_val & wr_mask) | (mhpmevt_val & ~wr_mask);
1532 env->mhpmevent_val[evt_index] = mhpmevt_val;
1533 riscv_pmu_update_event_map(env, mhpmevt_val, evt_index);
1534 } else {
1535 return -EINVAL;
1536 }
1537
1538 return 0;
1539 }
1540
1541 static int rmw_cd_mhpmeventh(CPURISCVState *env, int evt_index,
1542 target_ulong *val, target_ulong new_val,
1543 target_ulong wr_mask)
1544 {
1545 uint64_t mhpmevt_val = env->mhpmevent_val[evt_index];
1546 uint32_t mhpmevth_val = extract64(mhpmevt_val, 32, 32);
1547
1548 if (wr_mask != 0 && wr_mask != -1) {
1549 return -EINVAL;
1550 }
1551
1552 if (!wr_mask && val) {
1553 *val = mhpmevth_val;
1554 if (riscv_cpu_cfg(env)->ext_sscofpmf) {
1555 *val &= ~MHPMEVENTH_BIT_MINH;
1556 }
1557 } else if (wr_mask) {
1558 wr_mask &= ~MHPMEVENTH_BIT_MINH;
1559 mhpmevth_val = (new_val & wr_mask) | (mhpmevth_val & ~wr_mask);
1560 mhpmevt_val = deposit64(mhpmevt_val, 32, 32, mhpmevth_val);
1561 env->mhpmevent_val[evt_index] = mhpmevt_val;
1562 riscv_pmu_update_event_map(env, mhpmevt_val, evt_index);
1563 } else {
1564 return -EINVAL;
1565 }
1566
1567 return 0;
1568 }
1569
1570 static int rmw_cd_ctr_cfg(CPURISCVState *env, int cfg_index, target_ulong *val,
1571 target_ulong new_val, uint64_t wr_mask)
1572 {
1573 /*
1574 * wr_mask is 64-bit so upper 32 bits of mcyclecfg and minstretcfg
1575 * are retained.
1576 */
1577 switch (cfg_index) {
1578 case 0: /* CYCLECFG */
1579 if (wr_mask) {
1580 wr_mask &= ~MCYCLECFG_BIT_MINH;
1581 env->mcyclecfg = (new_val & wr_mask) | (env->mcyclecfg & ~wr_mask);
1582 } else {
1583 *val = env->mcyclecfg &= ~MHPMEVENT_BIT_MINH;
1584 }
1585 break;
1586 case 2: /* INSTRETCFG */
1587 if (wr_mask) {
1588 wr_mask &= ~MINSTRETCFG_BIT_MINH;
1589 env->minstretcfg = (new_val & wr_mask) |
1590 (env->minstretcfg & ~wr_mask);
1591 } else {
1592 *val = env->minstretcfg &= ~MHPMEVENT_BIT_MINH;
1593 }
1594 break;
1595 default:
1596 return -EINVAL;
1597 }
1598 return 0;
1599 }
1600
1601 static int rmw_cd_ctr_cfgh(CPURISCVState *env, int cfg_index, target_ulong *val,
1602 target_ulong new_val, target_ulong wr_mask)
1603 {
1604 uint64_t cfgh;
1605
1606 if (riscv_cpu_mxl(env) != MXL_RV32) {
1607 return RISCV_EXCP_ILLEGAL_INST;
1608 }
1609
1610 switch (cfg_index) {
1611 case 0: /* CYCLECFGH */
1612 cfgh = extract64(env->mcyclecfg, 32, 32);
1613 if (wr_mask) {
1614 wr_mask &= ~MCYCLECFGH_BIT_MINH;
1615 cfgh = (new_val & wr_mask) | (cfgh & ~wr_mask);
1616 env->mcyclecfg = deposit64(env->mcyclecfg, 32, 32, cfgh);
1617 } else {
1618 *val = cfgh;
1619 }
1620 break;
1621 case 2: /* INSTRETCFGH */
1622 cfgh = extract64(env->minstretcfg, 32, 32);
1623 if (wr_mask) {
1624 wr_mask &= ~MINSTRETCFGH_BIT_MINH;
1625 cfgh = (new_val & wr_mask) | (cfgh & ~wr_mask);
1626 env->minstretcfg = deposit64(env->minstretcfg, 32, 32, cfgh);
1627 } else {
1628 *val = cfgh;
1629 }
1630 break;
1631 default:
1632 return -EINVAL;
1633 }
1634 return 0;
1635 }
1636
1637
1638 static RISCVException read_scountovf(CPURISCVState *env, int csrno,
1639 target_ulong *val)
1640 {
1641 int mhpmevt_start = CSR_MHPMEVENT3 - CSR_MCOUNTINHIBIT;
1642 int i;
1643 *val = 0;
1644 bool virt = env->virt_enabled;
1645
1646 /* Virtualize scountovf for counter delegation */
1647 if (riscv_cpu_cfg(env)->ext_sscofpmf &&
1648 riscv_cpu_cfg(env)->ext_ssccfg &&
1649 get_field(env->menvcfg, MENVCFG_CDE) &&
1650 env->virt_enabled) {
1651 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
1652 }
1653
1654 for (i = mhpmevt_start; i < RV_MAX_MHPMEVENTS; i++) {
1655 if (env->priv < PRV_M) {
1656 if (!get_field(env->mcounteren, BIT(i))) {
1657 /* no mcounteren in S/HS-mode */
1658 continue;
1659 }
1660
1661 if (virt && !get_field(env->hcounteren, BIT(i))) {
1662 /* no hcounteren in VS-mode */
1663 continue;
1664 }
1665 }
1666
1667 if (env->mhpmevent_val[i] & MHPMEVENT_BIT_OF) {
1668 *val |= BIT(i);
1669 }
1670 }
1671
1672 return RISCV_EXCP_NONE;
1673 }
1674
1675 static RISCVException read_time(CPURISCVState *env, int csrno,
1676 target_ulong *val)
1677 {
1678 uint64_t delta = env->virt_enabled ? env->htimedelta : 0;
1679
1680 if (!env->rdtime_fn) {
1681 return RISCV_EXCP_ILLEGAL_INST;
1682 }
1683
1684 *val = env->rdtime_fn(env->rdtime_fn_arg) + delta;
1685 return RISCV_EXCP_NONE;
1686 }
1687
1688 static RISCVException read_timeh(CPURISCVState *env, int csrno,
1689 target_ulong *val)
1690 {
1691 uint64_t delta = env->virt_enabled ? env->htimedelta : 0;
1692
1693 if (!env->rdtime_fn) {
1694 return RISCV_EXCP_ILLEGAL_INST;
1695 }
1696
1697 *val = (env->rdtime_fn(env->rdtime_fn_arg) + delta) >> 32;
1698 return RISCV_EXCP_NONE;
1699 }
1700
1701 static RISCVException read_vstimecmp(CPURISCVState *env, int csrno,
1702 target_ulong *val)
1703 {
1704 *val = env->vstimecmp;
1705
1706 return RISCV_EXCP_NONE;
1707 }
1708
1709 static RISCVException read_vstimecmph(CPURISCVState *env, int csrno,
1710 target_ulong *val)
1711 {
1712 *val = env->vstimecmp >> 32;
1713
1714 return RISCV_EXCP_NONE;
1715 }
1716
1717 static RISCVException write_vstimecmp(CPURISCVState *env, int csrno,
1718 target_ulong val, uintptr_t ra)
1719 {
1720 if (riscv_cpu_mxl(env) == MXL_RV32) {
1721 env->vstimecmp = deposit64(env->vstimecmp, 0, 32, (uint64_t)val);
1722 } else {
1723 env->vstimecmp = val;
1724 }
1725
1726 riscv_timer_write_timecmp(env, env->vstimer, env->vstimecmp,
1727 env->htimedelta, MIP_VSTIP);
1728
1729 return RISCV_EXCP_NONE;
1730 }
1731
1732 static RISCVException write_vstimecmph(CPURISCVState *env, int csrno,
1733 target_ulong val, uintptr_t ra)
1734 {
1735 env->vstimecmp = deposit64(env->vstimecmp, 32, 32, (uint64_t)val);
1736 riscv_timer_write_timecmp(env, env->vstimer, env->vstimecmp,
1737 env->htimedelta, MIP_VSTIP);
1738
1739 return RISCV_EXCP_NONE;
1740 }
1741
1742 static RISCVException read_stimecmp(CPURISCVState *env, int csrno,
1743 target_ulong *val)
1744 {
1745 if (env->virt_enabled) {
1746 *val = env->vstimecmp;
1747 } else {
1748 *val = env->stimecmp;
1749 }
1750
1751 return RISCV_EXCP_NONE;
1752 }
1753
1754 static RISCVException read_stimecmph(CPURISCVState *env, int csrno,
1755 target_ulong *val)
1756 {
1757 if (env->virt_enabled) {
1758 *val = env->vstimecmp >> 32;
1759 } else {
1760 *val = env->stimecmp >> 32;
1761 }
1762
1763 return RISCV_EXCP_NONE;
1764 }
1765
1766 static RISCVException write_stimecmp(CPURISCVState *env, int csrno,
1767 target_ulong val, uintptr_t ra)
1768 {
1769 if (env->virt_enabled) {
1770 if (env->hvictl & HVICTL_VTI) {
1771 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
1772 }
1773 return write_vstimecmp(env, csrno, val, ra);
1774 }
1775
1776 if (riscv_cpu_mxl(env) == MXL_RV32) {
1777 env->stimecmp = deposit64(env->stimecmp, 0, 32, (uint64_t)val);
1778 } else {
1779 env->stimecmp = val;
1780 }
1781
1782 riscv_timer_write_timecmp(env, env->stimer, env->stimecmp, 0, MIP_STIP);
1783
1784 return RISCV_EXCP_NONE;
1785 }
1786
1787 static RISCVException write_stimecmph(CPURISCVState *env, int csrno,
1788 target_ulong val, uintptr_t ra)
1789 {
1790 if (env->virt_enabled) {
1791 if (env->hvictl & HVICTL_VTI) {
1792 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
1793 }
1794 return write_vstimecmph(env, csrno, val, ra);
1795 }
1796
1797 env->stimecmp = deposit64(env->stimecmp, 32, 32, (uint64_t)val);
1798 riscv_timer_write_timecmp(env, env->stimer, env->stimecmp, 0, MIP_STIP);
1799
1800 return RISCV_EXCP_NONE;
1801 }
1802
1803 #define VSTOPI_NUM_SRCS 5
1804
1805 /*
1806 * All core local interrupts except the fixed ones 0:15. This macro is for
1807 * virtual interrupts logic so please don't change this to avoid messing up
1808 * the whole support, For reference see AIA spec: `5.3 Interrupt filtering and
1809 * virtual interrupts for supervisor level` and `6.3.2 Virtual interrupts for
1810 * VS level`.
1811 */
1812 #define LOCAL_INTERRUPTS (~0xFFFFULL)
1813
1814 static const uint64_t delegable_ints =
1815 S_MODE_INTERRUPTS | VS_MODE_INTERRUPTS | MIP_LCOFIP;
1816 static const uint64_t vs_delegable_ints =
1817 (VS_MODE_INTERRUPTS | LOCAL_INTERRUPTS) & ~MIP_LCOFIP;
1818 static const uint64_t all_ints = M_MODE_INTERRUPTS | S_MODE_INTERRUPTS |
1819 HS_MODE_INTERRUPTS | LOCAL_INTERRUPTS;
1820 #define DELEGABLE_EXCPS ((1ULL << (RISCV_EXCP_INST_ADDR_MIS)) | \
1821 (1ULL << (RISCV_EXCP_INST_ACCESS_FAULT)) | \
1822 (1ULL << (RISCV_EXCP_ILLEGAL_INST)) | \
1823 (1ULL << (RISCV_EXCP_BREAKPOINT)) | \
1824 (1ULL << (RISCV_EXCP_LOAD_ADDR_MIS)) | \
1825 (1ULL << (RISCV_EXCP_LOAD_ACCESS_FAULT)) | \
1826 (1ULL << (RISCV_EXCP_STORE_AMO_ADDR_MIS)) | \
1827 (1ULL << (RISCV_EXCP_STORE_AMO_ACCESS_FAULT)) | \
1828 (1ULL << (RISCV_EXCP_U_ECALL)) | \
1829 (1ULL << (RISCV_EXCP_S_ECALL)) | \
1830 (1ULL << (RISCV_EXCP_VS_ECALL)) | \
1831 (1ULL << (RISCV_EXCP_INST_PAGE_FAULT)) | \
1832 (1ULL << (RISCV_EXCP_LOAD_PAGE_FAULT)) | \
1833 (1ULL << (RISCV_EXCP_STORE_PAGE_FAULT)) | \
1834 (1ULL << (RISCV_EXCP_SW_CHECK)) | \
1835 (1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) | \
1836 (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) | \
1837 (1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) | \
1838 (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT)))
1839 static const target_ulong vs_delegable_excps = DELEGABLE_EXCPS &
1840 ~((1ULL << (RISCV_EXCP_S_ECALL)) |
1841 (1ULL << (RISCV_EXCP_VS_ECALL)) |
1842 (1ULL << (RISCV_EXCP_M_ECALL)) |
1843 (1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) |
1844 (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) |
1845 (1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) |
1846 (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT)));
1847 static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE |
1848 SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS |
1849 SSTATUS_SUM | SSTATUS_MXR | SSTATUS_VS;
1850
1851 /*
1852 * Spec allows for bits 13:63 to be either read-only or writable.
1853 * So far we have interrupt LCOFIP in that region which is writable.
1854 *
1855 * Also, spec allows to inject virtual interrupts in this region even
1856 * without any hardware interrupts for that interrupt number.
1857 *
1858 * For now interrupt in 13:63 region are all kept writable. 13 being
1859 * LCOFIP and 14:63 being virtual only. Change this in future if we
1860 * introduce more interrupts that are not writable.
1861 */
1862
1863 /* Bit STIP can be an alias of mip.STIP that's why it's writable in mvip. */
1864 static const uint64_t mvip_writable_mask = MIP_SSIP | MIP_STIP | MIP_SEIP |
1865 LOCAL_INTERRUPTS;
1866 static const uint64_t mvien_writable_mask = MIP_SSIP | MIP_SEIP |
1867 LOCAL_INTERRUPTS;
1868
1869 static const uint64_t sip_writable_mask = SIP_SSIP | LOCAL_INTERRUPTS;
1870 static const uint64_t hip_writable_mask = MIP_VSSIP;
1871 static const uint64_t hvip_writable_mask = MIP_VSSIP | MIP_VSTIP |
1872 MIP_VSEIP | LOCAL_INTERRUPTS;
1873 static const uint64_t hvien_writable_mask = LOCAL_INTERRUPTS;
1874
1875 static const uint64_t vsip_writable_mask = MIP_VSSIP | LOCAL_INTERRUPTS;
1876
1877 /* Machine Information Registers */
1878 static RISCVException read_zero(CPURISCVState *env, int csrno,
1879 target_ulong *val)
1880 {
1881 *val = 0;
1882 return RISCV_EXCP_NONE;
1883 }
1884
1885 static RISCVException write_ignore(CPURISCVState *env, int csrno,
1886 target_ulong val, uintptr_t ra)
1887 {
1888 return RISCV_EXCP_NONE;
1889 }
1890
1891 static RISCVException read_mvendorid(CPURISCVState *env, int csrno,
1892 target_ulong *val)
1893 {
1894 *val = riscv_cpu_cfg(env)->mvendorid;
1895 return RISCV_EXCP_NONE;
1896 }
1897
1898 static RISCVException read_marchid(CPURISCVState *env, int csrno,
1899 target_ulong *val)
1900 {
1901 *val = riscv_cpu_cfg(env)->marchid;
1902 return RISCV_EXCP_NONE;
1903 }
1904
1905 static RISCVException read_mimpid(CPURISCVState *env, int csrno,
1906 target_ulong *val)
1907 {
1908 *val = riscv_cpu_cfg(env)->mimpid;
1909 return RISCV_EXCP_NONE;
1910 }
1911
1912 static RISCVException read_mhartid(CPURISCVState *env, int csrno,
1913 target_ulong *val)
1914 {
1915 *val = env->mhartid;
1916 return RISCV_EXCP_NONE;
1917 }
1918
1919 /* Machine Trap Setup */
1920
1921 /* We do not store SD explicitly, only compute it on demand. */
1922 static uint64_t add_status_sd(RISCVMXL xl, uint64_t status)
1923 {
1924 if ((status & MSTATUS_FS) == MSTATUS_FS ||
1925 (status & MSTATUS_VS) == MSTATUS_VS ||
1926 (status & MSTATUS_XS) == MSTATUS_XS) {
1927 switch (xl) {
1928 case MXL_RV32:
1929 return status | MSTATUS32_SD;
1930 case MXL_RV64:
1931 return status | MSTATUS64_SD;
1932 case MXL_RV128:
1933 return MSTATUSH128_SD;
1934 default:
1935 g_assert_not_reached();
1936 }
1937 }
1938 return status;
1939 }
1940
1941 static RISCVException read_mstatus(CPURISCVState *env, int csrno,
1942 target_ulong *val)
1943 {
1944 *val = add_status_sd(riscv_cpu_mxl(env), env->mstatus);
1945 return RISCV_EXCP_NONE;
1946 }
1947
1948 static bool validate_vm(CPURISCVState *env, target_ulong vm)
1949 {
1950 bool rv32 = riscv_cpu_mxl(env) == MXL_RV32;
1951 RISCVCPU *cpu = env_archcpu(env);
1952 int satp_mode_supported_max = cpu->cfg.max_satp_mode;
1953 const bool *valid_vm = rv32 ? valid_vm_1_10_32 : valid_vm_1_10_64;
1954
1955 assert(satp_mode_supported_max >= 0);
1956 return vm <= satp_mode_supported_max && valid_vm[vm];
1957 }
1958
1959 static target_ulong legalize_xatp(CPURISCVState *env, target_ulong old_xatp,
1960 target_ulong val)
1961 {
1962 target_ulong mask;
1963 bool vm;
1964 if (riscv_cpu_mxl(env) == MXL_RV32) {
1965 vm = validate_vm(env, get_field(val, SATP32_MODE));
1966 mask = (val ^ old_xatp) & (SATP32_MODE | SATP32_ASID | SATP32_PPN);
1967 } else {
1968 vm = validate_vm(env, get_field(val, SATP64_MODE));
1969 mask = (val ^ old_xatp) & (SATP64_MODE | SATP64_ASID | SATP64_PPN);
1970 }
1971
1972 if (vm && mask) {
1973 /*
1974 * The ISA defines SATP.MODE=Bare as "no translation", but we still
1975 * pass these through QEMU's TLB emulation as it improves
1976 * performance. Flushing the TLB on SATP writes with paging
1977 * enabled avoids leaking those invalid cached mappings.
1978 */
1979 tlb_flush(env_cpu(env));
1980 return val;
1981 }
1982 return old_xatp;
1983 }
1984
1985 static target_ulong legalize_mpp(CPURISCVState *env, target_ulong old_mpp,
1986 target_ulong val)
1987 {
1988 bool valid = false;
1989 target_ulong new_mpp = get_field(val, MSTATUS_MPP);
1990
1991 switch (new_mpp) {
1992 case PRV_M:
1993 valid = true;
1994 break;
1995 case PRV_S:
1996 valid = riscv_has_ext(env, RVS);
1997 break;
1998 case PRV_U:
1999 valid = riscv_has_ext(env, RVU);
2000 break;
2001 }
2002
2003 /* Remain field unchanged if new_mpp value is invalid */
2004 if (!valid) {
2005 val = set_field(val, MSTATUS_MPP, old_mpp);
2006 }
2007
2008 return val;
2009 }
2010
2011 static uint64_t riscv_write_uxl(CPURISCVState *env, uint64_t val,
2012 uint64_t field)
2013 {
2014 RISCVMXL xl = riscv_cpu_mxl(env);
2015 uint64_t uxl = get_field(val, field);
2016
2017 if (xl != MXL_RV128 && uxl == MXL_RV128) {
2018 uxl = xl;
2019 val = set_field(val, field, uxl);
2020 }
2021
2022 return val;
2023 }
2024
2025 static RISCVException write_mstatus(CPURISCVState *env, int csrno,
2026 target_ulong val, uintptr_t ra)
2027 {
2028 uint64_t mstatus = env->mstatus;
2029 uint64_t mask = 0;
2030 RISCVMXL xl = riscv_cpu_mxl(env);
2031
2032 /*
2033 * MPP field have been made WARL since priv version 1.11. However,
2034 * legalization for it will not break any software running on 1.10.
2035 */
2036 val = legalize_mpp(env, get_field(mstatus, MSTATUS_MPP), val);
2037
2038 /* flush tlb on mstatus fields that affect VM */
2039 if ((val ^ mstatus) & MSTATUS_MXR) {
2040 tlb_flush(env_cpu(env));
2041 }
2042 mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE |
2043 MSTATUS_SPP | MSTATUS_MPRV | MSTATUS_SUM |
2044 MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR |
2045 MSTATUS_TW;
2046
2047 if (riscv_has_ext(env, RVF)) {
2048 mask |= MSTATUS_FS;
2049 }
2050
2051 if (riscv_cpu_cfg(env)->ext_zve32x) {
2052 mask |= MSTATUS_VS;
2053 }
2054
2055 if (riscv_env_smode_dbltrp_enabled(env, env->virt_enabled)) {
2056 mask |= MSTATUS_SDT;
2057 if ((val & MSTATUS_SDT) != 0) {
2058 val &= ~MSTATUS_SIE;
2059 }
2060 }
2061
2062 if (riscv_cpu_cfg(env)->ext_smdbltrp) {
2063 mask |= MSTATUS_MDT;
2064 if ((val & MSTATUS_MDT) != 0) {
2065 val &= ~MSTATUS_MIE;
2066 }
2067 }
2068
2069 if (xl != MXL_RV32 || env->debugger) {
2070 if ((val & MSTATUS64_SXL) != 0) {
2071 mask |= MSTATUS64_SXL;
2072 val = riscv_write_uxl(env, val, MSTATUS64_SXL);
2073 }
2074
2075 if ((val & MSTATUS64_UXL) != 0) {
2076 mask |= MSTATUS64_UXL;
2077 val = riscv_write_uxl(env, val, MSTATUS64_UXL);
2078 }
2079 }
2080
2081 /* If cfi lp extension is available, then apply cfi lp mask */
2082 if (env_archcpu(env)->cfg.ext_zicfilp) {
2083 mask |= (MSTATUS_MPELP | MSTATUS_SPELP);
2084 }
2085
2086 mstatus = (mstatus & ~mask) | (val & mask);
2087
2088 env->mstatus = mstatus;
2089
2090 /*
2091 * Except in debug mode, UXL/SXL can only be modified by higher
2092 * privilege mode. So xl will not be changed in normal mode.
2093 */
2094 if (env->debugger) {
2095 env->xl = cpu_recompute_xl(env);
2096 }
2097
2098 return RISCV_EXCP_NONE;
2099 }
2100
2101 static RISCVException read_mstatush(CPURISCVState *env, int csrno,
2102 target_ulong *val)
2103 {
2104 *val = env->mstatus >> 32;
2105 return RISCV_EXCP_NONE;
2106 }
2107
2108 static RISCVException write_mstatush(CPURISCVState *env, int csrno,
2109 target_ulong val, uintptr_t ra)
2110 {
2111 uint64_t valh = (uint64_t)val << 32;
2112 uint64_t mask = 0;
2113
2114 if (riscv_cpu_cfg(env)->ext_smdbltrp) {
2115 mask |= MSTATUS_MDT;
2116 if ((valh & MSTATUS_MDT) != 0) {
2117 mask |= MSTATUS_MIE;
2118 }
2119 }
2120 env->mstatus = (env->mstatus & ~mask) | (valh & mask);
2121
2122 return RISCV_EXCP_NONE;
2123 }
2124
2125 static RISCVException read_mstatus_i128(CPURISCVState *env, int csrno,
2126 Int128 *val)
2127 {
2128 *val = int128_make128(env->mstatus, add_status_sd(MXL_RV128,
2129 env->mstatus));
2130 return RISCV_EXCP_NONE;
2131 }
2132
2133 static RISCVException read_misa_i128(CPURISCVState *env, int csrno,
2134 Int128 *val)
2135 {
2136 *val = int128_make128(env->misa_ext, (uint64_t)MXL_RV128 << 62);
2137 return RISCV_EXCP_NONE;
2138 }
2139
2140 static RISCVException read_misa(CPURISCVState *env, int csrno,
2141 target_ulong *val)
2142 {
2143 target_ulong misa;
2144
2145 switch (env->misa_mxl) {
2146 case MXL_RV32:
2147 misa = (target_ulong)MXL_RV32 << 30;
2148 break;
2149 #ifdef TARGET_RISCV64
2150 case MXL_RV64:
2151 misa = (target_ulong)MXL_RV64 << 62;
2152 break;
2153 #endif
2154 default:
2155 g_assert_not_reached();
2156 }
2157
2158 *val = misa | env->misa_ext;
2159 return RISCV_EXCP_NONE;
2160 }
2161
2162 static target_ulong get_next_pc(CPURISCVState *env, uintptr_t ra)
2163 {
2164 uint64_t data[INSN_START_WORDS];
2165
2166 /* Outside of a running cpu, env contains the next pc. */
2167 if (ra == 0 || !cpu_unwind_state_data(env_cpu(env), ra, data)) {
2168 return env->pc;
2169 }
2170
2171 /* Within unwind data, [0] is pc and [1] is the opcode. */
2172 return data[0] + insn_len(data[1]);
2173 }
2174
2175 static RISCVException write_misa(CPURISCVState *env, int csrno,
2176 target_ulong val, uintptr_t ra)
2177 {
2178 RISCVCPU *cpu = env_archcpu(env);
2179 uint32_t orig_misa_ext = env->misa_ext;
2180 Error *local_err = NULL;
2181
2182 if (!riscv_cpu_cfg(env)->misa_w) {
2183 /* drop write to misa */
2184 return RISCV_EXCP_NONE;
2185 }
2186
2187 /* Mask extensions that are not supported by this hart */
2188 val &= env->misa_ext_mask;
2189
2190 /* drop write if RVC is cleared and next instruction is not aligned */
2191 if ((env->misa_ext & RVC) && !(val & RVC) &&
2192 (get_next_pc(env, ra) & 3) != 0) {
2193 qemu_log_mask(LOG_GUEST_ERROR, "Unable to write MISA ext value "
2194 "0x%x, MISA.C disable failed\n", env->misa_ext);
2195
2196 return RISCV_EXCP_NONE;
2197 }
2198
2199 /* Disable RVG if any of its dependencies are disabled */
2200 if (!(val & RVI && val & RVM && val & RVA &&
2201 val & RVF && val & RVD)) {
2202 val &= ~RVG;
2203 }
2204
2205 /* If nothing changed, do nothing. */
2206 if (val == env->misa_ext) {
2207 return RISCV_EXCP_NONE;
2208 }
2209
2210 env->misa_ext = val;
2211 riscv_cpu_validate_set_extensions(cpu, &local_err);
2212 if (local_err != NULL) {
2213 /* Rollback on validation error */
2214 qemu_log_mask(LOG_GUEST_ERROR, "Unable to write MISA ext value "
2215 "0x%x, keeping existing MISA ext 0x%x\n",
2216 env->misa_ext, orig_misa_ext);
2217
2218 env->misa_ext = orig_misa_ext;
2219
2220 return RISCV_EXCP_NONE;
2221 }
2222
2223 if (!(env->misa_ext & RVF)) {
2224 env->mstatus &= ~MSTATUS_FS;
2225 }
2226
2227 env->xl = riscv_cpu_mxl(env);
2228 return RISCV_EXCP_NONE;
2229 }
2230
2231 static RISCVException read_medeleg(CPURISCVState *env, int csrno,
2232 target_ulong *val)
2233 {
2234 *val = env->medeleg;
2235 return RISCV_EXCP_NONE;
2236 }
2237
2238 static RISCVException write_medeleg(CPURISCVState *env, int csrno,
2239 target_ulong val, uintptr_t ra)
2240 {
2241 env->medeleg = (env->medeleg & ~DELEGABLE_EXCPS) | (val & DELEGABLE_EXCPS);
2242 return RISCV_EXCP_NONE;
2243 }
2244
2245 static RISCVException rmw_mideleg64(CPURISCVState *env, int csrno,
2246 uint64_t *ret_val,
2247 uint64_t new_val, uint64_t wr_mask)
2248 {
2249 uint64_t mask = wr_mask & delegable_ints;
2250
2251 if (ret_val) {
2252 *ret_val = env->mideleg;
2253 }
2254
2255 env->mideleg = (env->mideleg & ~mask) | (new_val & mask);
2256
2257 if (riscv_has_ext(env, RVH)) {
2258 env->mideleg |= HS_MODE_INTERRUPTS;
2259 }
2260
2261 return RISCV_EXCP_NONE;
2262 }
2263
2264 static RISCVException rmw_mideleg(CPURISCVState *env, int csrno,
2265 target_ulong *ret_val,
2266 target_ulong new_val, target_ulong wr_mask)
2267 {
2268 uint64_t rval;
2269 RISCVException ret;
2270
2271 ret = rmw_mideleg64(env, csrno, &rval, new_val, wr_mask);
2272 if (ret_val) {
2273 *ret_val = rval;
2274 }
2275
2276 return ret;
2277 }
2278
2279 static RISCVException rmw_midelegh(CPURISCVState *env, int csrno,
2280 target_ulong *ret_val,
2281 target_ulong new_val,
2282 target_ulong wr_mask)
2283 {
2284 uint64_t rval;
2285 RISCVException ret;
2286
2287 ret = rmw_mideleg64(env, csrno, &rval,
2288 ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32);
2289 if (ret_val) {
2290 *ret_val = rval >> 32;
2291 }
2292
2293 return ret;
2294 }
2295
2296 static RISCVException rmw_mie64(CPURISCVState *env, int csrno,
2297 uint64_t *ret_val,
2298 uint64_t new_val, uint64_t wr_mask)
2299 {
2300 uint64_t mask = wr_mask & all_ints;
2301
2302 if (ret_val) {
2303 *ret_val = env->mie;
2304 }
2305
2306 env->mie = (env->mie & ~mask) | (new_val & mask);
2307
2308 if (!riscv_has_ext(env, RVH)) {
2309 env->mie &= ~((uint64_t)HS_MODE_INTERRUPTS);
2310 }
2311
2312 return RISCV_EXCP_NONE;
2313 }
2314
2315 static RISCVException rmw_mie(CPURISCVState *env, int csrno,
2316 target_ulong *ret_val,
2317 target_ulong new_val, target_ulong wr_mask)
2318 {
2319 uint64_t rval;
2320 RISCVException ret;
2321
2322 ret = rmw_mie64(env, csrno, &rval, new_val, wr_mask);
2323 if (ret_val) {
2324 *ret_val = rval;
2325 }
2326
2327 return ret;
2328 }
2329
2330 static RISCVException rmw_mieh(CPURISCVState *env, int csrno,
2331 target_ulong *ret_val,
2332 target_ulong new_val, target_ulong wr_mask)
2333 {
2334 uint64_t rval;
2335 RISCVException ret;
2336
2337 ret = rmw_mie64(env, csrno, &rval,
2338 ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32);
2339 if (ret_val) {
2340 *ret_val = rval >> 32;
2341 }
2342
2343 return ret;
2344 }
2345
2346 static RISCVException rmw_mvien64(CPURISCVState *env, int csrno,
2347 uint64_t *ret_val,
2348 uint64_t new_val, uint64_t wr_mask)
2349 {
2350 uint64_t mask = wr_mask & mvien_writable_mask;
2351
2352 if (ret_val) {
2353 *ret_val = env->mvien;
2354 }
2355
2356 env->mvien = (env->mvien & ~mask) | (new_val & mask);
2357
2358 return RISCV_EXCP_NONE;
2359 }
2360
2361 static RISCVException rmw_mvien(CPURISCVState *env, int csrno,
2362 target_ulong *ret_val,
2363 target_ulong new_val, target_ulong wr_mask)
2364 {
2365 uint64_t rval;
2366 RISCVException ret;
2367
2368 ret = rmw_mvien64(env, csrno, &rval, new_val, wr_mask);
2369 if (ret_val) {
2370 *ret_val = rval;
2371 }
2372
2373 return ret;
2374 }
2375
2376 static RISCVException rmw_mvienh(CPURISCVState *env, int csrno,
2377 target_ulong *ret_val,
2378 target_ulong new_val, target_ulong wr_mask)
2379 {
2380 uint64_t rval;
2381 RISCVException ret;
2382
2383 ret = rmw_mvien64(env, csrno, &rval,
2384 ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32);
2385 if (ret_val) {
2386 *ret_val = rval >> 32;
2387 }
2388
2389 return ret;
2390 }
2391
2392 static RISCVException read_mtopi(CPURISCVState *env, int csrno,
2393 target_ulong *val)
2394 {
2395 int irq;
2396 uint8_t iprio;
2397
2398 irq = riscv_cpu_mirq_pending(env);
2399 if (irq <= 0 || irq > 63) {
2400 *val = 0;
2401 } else {
2402 iprio = env->miprio[irq];
2403 if (!iprio) {
2404 if (riscv_cpu_default_priority(irq) > IPRIO_DEFAULT_M) {
2405 iprio = IPRIO_MMAXIPRIO;
2406 }
2407 }
2408 *val = (irq & TOPI_IID_MASK) << TOPI_IID_SHIFT;
2409 *val |= iprio;
2410 }
2411
2412 return RISCV_EXCP_NONE;
2413 }
2414
2415 static int aia_xlate_vs_csrno(CPURISCVState *env, int csrno)
2416 {
2417 if (!env->virt_enabled) {
2418 return csrno;
2419 }
2420
2421 switch (csrno) {
2422 case CSR_SISELECT:
2423 return CSR_VSISELECT;
2424 case CSR_SIREG:
2425 return CSR_VSIREG;
2426 case CSR_STOPEI:
2427 return CSR_VSTOPEI;
2428 default:
2429 return csrno;
2430 };
2431 }
2432
2433 static int csrind_xlate_vs_csrno(CPURISCVState *env, int csrno)
2434 {
2435 if (!env->virt_enabled) {
2436 return csrno;
2437 }
2438
2439 switch (csrno) {
2440 case CSR_SISELECT:
2441 return CSR_VSISELECT;
2442 case CSR_SIREG:
2443 case CSR_SIREG2:
2444 case CSR_SIREG3:
2445 case CSR_SIREG4:
2446 case CSR_SIREG5:
2447 case CSR_SIREG6:
2448 return CSR_VSIREG + (csrno - CSR_SIREG);
2449 default:
2450 return csrno;
2451 };
2452 }
2453
2454 static RISCVException rmw_xiselect(CPURISCVState *env, int csrno,
2455 target_ulong *val, target_ulong new_val,
2456 target_ulong wr_mask)
2457 {
2458 uint16_t *iselect;
2459 int ret;
2460
2461 ret = smstateen_acc_ok(env, 0, SMSTATEEN0_SVSLCT);
2462 if (ret != RISCV_EXCP_NONE) {
2463 return ret;
2464 }
2465
2466 /* Translate CSR number for VS-mode */
2467 csrno = csrind_xlate_vs_csrno(env, csrno);
2468
2469 /* Find the iselect CSR based on CSR number */
2470 switch (csrno) {
2471 case CSR_MISELECT:
2472 iselect = &env->miselect;
2473 break;
2474 case CSR_SISELECT:
2475 iselect = &env->siselect;
2476 break;
2477 case CSR_VSISELECT:
2478 iselect = &env->vsiselect;
2479 break;
2480 default:
2481 return RISCV_EXCP_ILLEGAL_INST;
2482 };
2483
2484 if (val) {
2485 *val = *iselect;
2486 }
2487
2488 if (riscv_cpu_cfg(env)->ext_smcsrind || riscv_cpu_cfg(env)->ext_sscsrind) {
2489 wr_mask &= ISELECT_MASK_SXCSRIND;
2490 } else {
2491 wr_mask &= ISELECT_MASK_AIA;
2492 }
2493
2494 if (wr_mask) {
2495 *iselect = (*iselect & ~wr_mask) | (new_val & wr_mask);
2496 }
2497
2498 return RISCV_EXCP_NONE;
2499 }
2500
2501 static bool xiselect_aia_range(uint16_t isel)
2502 {
2503 return (ISELECT_IPRIO0 <= isel && isel <= ISELECT_IPRIO15) ||
2504 (ISELECT_IMSIC_FIRST <= isel && isel <= ISELECT_IMSIC_LAST);
2505 }
2506
2507 static bool xiselect_cd_range(uint16_t isel)
2508 {
2509 return (ISELECT_CD_FIRST <= isel && isel <= ISELECT_CD_LAST);
2510 }
2511
2512 static bool xiselect_ctr_range(int csrno, uint16_t isel)
2513 {
2514 /* MIREG-MIREG6 for the range 0x200-0x2ff are not used by CTR. */
2515 return CTR_ENTRIES_FIRST <= isel && isel <= CTR_ENTRIES_LAST &&
2516 csrno < CSR_MIREG;
2517 }
2518
2519 static int rmw_iprio(target_ulong xlen,
2520 uint16_t iselect, uint8_t *iprio,
2521 target_ulong *val, target_ulong new_val,
2522 target_ulong wr_mask, int ext_irq_no)
2523 {
2524 int i, firq, nirqs;
2525 target_ulong old_val;
2526
2527 if (iselect < ISELECT_IPRIO0 || ISELECT_IPRIO15 < iselect) {
2528 return -EINVAL;
2529 }
2530 if (xlen != 32 && iselect & 0x1) {
2531 return -EINVAL;
2532 }
2533
2534 nirqs = 4 * (xlen / 32);
2535 firq = ((iselect - ISELECT_IPRIO0) / (xlen / 32)) * (nirqs);
2536
2537 old_val = 0;
2538 for (i = 0; i < nirqs; i++) {
2539 old_val |= ((target_ulong)iprio[firq + i]) << (IPRIO_IRQ_BITS * i);
2540 }
2541
2542 if (val) {
2543 *val = old_val;
2544 }
2545
2546 if (wr_mask) {
2547 new_val = (old_val & ~wr_mask) | (new_val & wr_mask);
2548 for (i = 0; i < nirqs; i++) {
2549 /*
2550 * M-level and S-level external IRQ priority always read-only
2551 * zero. This means default priority order is always preferred
2552 * for M-level and S-level external IRQs.
2553 */
2554 if ((firq + i) == ext_irq_no) {
2555 continue;
2556 }
2557 iprio[firq + i] = (new_val >> (IPRIO_IRQ_BITS * i)) & 0xff;
2558 }
2559 }
2560
2561 return 0;
2562 }
2563
2564 static int rmw_ctrsource(CPURISCVState *env, uint16_t isel, target_ulong *val,
2565 target_ulong new_val, target_ulong wr_mask)
2566 {
2567 /*
2568 * CTR arrays are treated as circular buffers and TOS always points to next
2569 * empty slot, keeping TOS - 1 always pointing to latest entry. Given entry
2570 * 0 is always the latest one, traversal is a bit different here. See the
2571 * below example.
2572 *
2573 * Depth = 16.
2574 *
2575 * idx [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [A] [B] [C] [D] [E] [F]
2576 * TOS H
2577 * entry 6 5 4 3 2 1 0 F E D C B A 9 8 7
2578 */
2579 const uint64_t entry = isel - CTR_ENTRIES_FIRST;
2580 const uint64_t depth = 16 << get_field(env->sctrdepth, SCTRDEPTH_MASK);
2581 uint64_t idx;
2582
2583 /* Entry greater than depth-1 is read-only zero */
2584 if (entry >= depth) {
2585 if (val) {
2586 *val = 0;
2587 }
2588 return 0;
2589 }
2590
2591 idx = get_field(env->sctrstatus, SCTRSTATUS_WRPTR_MASK);
2592 idx = (idx - entry - 1) & (depth - 1);
2593
2594 if (val) {
2595 *val = env->ctr_src[idx];
2596 }
2597
2598 env->ctr_src[idx] = (env->ctr_src[idx] & ~wr_mask) | (new_val & wr_mask);
2599
2600 return 0;
2601 }
2602
2603 static int rmw_ctrtarget(CPURISCVState *env, uint16_t isel, target_ulong *val,
2604 target_ulong new_val, target_ulong wr_mask)
2605 {
2606 /*
2607 * CTR arrays are treated as circular buffers and TOS always points to next
2608 * empty slot, keeping TOS - 1 always pointing to latest entry. Given entry
2609 * 0 is always the latest one, traversal is a bit different here. See the
2610 * below example.
2611 *
2612 * Depth = 16.
2613 *
2614 * idx [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [A] [B] [C] [D] [E] [F]
2615 * head H
2616 * entry 6 5 4 3 2 1 0 F E D C B A 9 8 7
2617 */
2618 const uint64_t entry = isel - CTR_ENTRIES_FIRST;
2619 const uint64_t depth = 16 << get_field(env->sctrdepth, SCTRDEPTH_MASK);
2620 uint64_t idx;
2621
2622 /* Entry greater than depth-1 is read-only zero */
2623 if (entry >= depth) {
2624 if (val) {
2625 *val = 0;
2626 }
2627 return 0;
2628 }
2629
2630 idx = get_field(env->sctrstatus, SCTRSTATUS_WRPTR_MASK);
2631 idx = (idx - entry - 1) & (depth - 1);
2632
2633 if (val) {
2634 *val = env->ctr_dst[idx];
2635 }
2636
2637 env->ctr_dst[idx] = (env->ctr_dst[idx] & ~wr_mask) | (new_val & wr_mask);
2638
2639 return 0;
2640 }
2641
2642 static int rmw_ctrdata(CPURISCVState *env, uint16_t isel, target_ulong *val,
2643 target_ulong new_val, target_ulong wr_mask)
2644 {
2645 /*
2646 * CTR arrays are treated as circular buffers and TOS always points to next
2647 * empty slot, keeping TOS - 1 always pointing to latest entry. Given entry
2648 * 0 is always the latest one, traversal is a bit different here. See the
2649 * below example.
2650 *
2651 * Depth = 16.
2652 *
2653 * idx [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [A] [B] [C] [D] [E] [F]
2654 * head H
2655 * entry 6 5 4 3 2 1 0 F E D C B A 9 8 7
2656 */
2657 const uint64_t entry = isel - CTR_ENTRIES_FIRST;
2658 const uint64_t mask = wr_mask & CTRDATA_MASK;
2659 const uint64_t depth = 16 << get_field(env->sctrdepth, SCTRDEPTH_MASK);
2660 uint64_t idx;
2661
2662 /* Entry greater than depth-1 is read-only zero */
2663 if (entry >= depth) {
2664 if (val) {
2665 *val = 0;
2666 }
2667 return 0;
2668 }
2669
2670 idx = get_field(env->sctrstatus, SCTRSTATUS_WRPTR_MASK);
2671 idx = (idx - entry - 1) & (depth - 1);
2672
2673 if (val) {
2674 *val = env->ctr_data[idx];
2675 }
2676
2677 env->ctr_data[idx] = (env->ctr_data[idx] & ~mask) | (new_val & mask);
2678
2679 return 0;
2680 }
2681
2682 static RISCVException rmw_xireg_aia(CPURISCVState *env, int csrno,
2683 uint16_t isel, target_ulong *val,
2684 target_ulong new_val, target_ulong wr_mask)
2685 {
2686 bool virt = false, isel_reserved = false;
2687 int ret = -EINVAL;
2688 uint8_t *iprio;
2689 privilege_mode_t priv;
2690 uint32_t vgein;
2691 uint64_t wide_val;
2692
2693 /* VS-mode CSR number passed in has already been translated */
2694 switch (csrno) {
2695 case CSR_MIREG:
2696 if (!riscv_cpu_cfg(env)->ext_smaia) {
2697 goto done;
2698 }
2699 iprio = env->miprio;
2700 priv = PRV_M;
2701 break;
2702 case CSR_SIREG:
2703 if (!riscv_cpu_cfg(env)->ext_ssaia ||
2704 (env->priv == PRV_S && env->mvien & MIP_SEIP &&
2705 env->siselect >= ISELECT_IMSIC_EIDELIVERY &&
2706 env->siselect <= ISELECT_IMSIC_EIE63)) {
2707 goto done;
2708 }
2709 iprio = env->siprio;
2710 priv = PRV_S;
2711 break;
2712 case CSR_VSIREG:
2713 if (!riscv_cpu_cfg(env)->ext_ssaia) {
2714 goto done;
2715 }
2716 iprio = env->hviprio;
2717 priv = PRV_S;
2718 virt = true;
2719 break;
2720 default:
2721 goto done;
2722 };
2723
2724 /* Find the selected guest interrupt file */
2725 vgein = (virt) ? get_field(env->hstatus, HSTATUS_VGEIN) : 0;
2726
2727 if (ISELECT_IPRIO0 <= isel && isel <= ISELECT_IPRIO15) {
2728 /* Local interrupt priority registers not available for VS-mode */
2729 if (!virt) {
2730 ret = rmw_iprio(riscv_cpu_mxl_bits(env),
2731 isel, iprio, val, new_val, wr_mask,
2732 (priv == PRV_M) ? IRQ_M_EXT : IRQ_S_EXT);
2733 }
2734 } else if (ISELECT_IMSIC_FIRST <= isel && isel <= ISELECT_IMSIC_LAST) {
2735 /* IMSIC registers only available when machine implements it. */
2736 if (env->aia_ireg_rmw_cb[priv]) {
2737 /* Selected guest interrupt file should not be zero */
2738 if (virt && (!vgein || env->geilen < vgein)) {
2739 goto done;
2740 }
2741 /* Call machine specific IMSIC register emulation */
2742 ret = env->aia_ireg_rmw_cb[priv](env->aia_ireg_rmw_cb_arg[priv],
2743 AIA_MAKE_IREG(isel, priv, virt, vgein,
2744 riscv_cpu_mxl_bits(env)),
2745 &wide_val, new_val, wr_mask);
2746 if (val) {
2747 *val = wide_val;
2748 }
2749 }
2750 } else {
2751 isel_reserved = true;
2752 }
2753
2754 done:
2755 /*
2756 * If AIA is not enabled, illegal instruction exception is always
2757 * returned regardless of whether we are in VS-mode or not
2758 */
2759 if (ret) {
2760 return (env->virt_enabled && virt && !isel_reserved) ?
2761 RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST;
2762 }
2763
2764 return RISCV_EXCP_NONE;
2765 }
2766
2767 static int rmw_xireg_cd(CPURISCVState *env, int csrno,
2768 uint16_t isel, target_ulong *val,
2769 target_ulong new_val, target_ulong wr_mask)
2770 {
2771 int ret = -EINVAL;
2772 uint16_t ctr_index = isel - ISELECT_CD_FIRST;
2773 uint16_t isel_hpm_start = ISELECT_CD_FIRST + 3;
2774
2775 if (!riscv_cpu_cfg(env)->ext_smcdeleg || !riscv_cpu_cfg(env)->ext_ssccfg) {
2776 ret = RISCV_EXCP_ILLEGAL_INST;
2777 goto done;
2778 }
2779
2780 /* Invalid siselect value for reserved */
2781 if (ctr_index == 1) {
2782 goto done;
2783 }
2784
2785 /* sireg4 and sireg5 provides access RV32 only CSRs */
2786 if (((csrno == CSR_SIREG5) || (csrno == CSR_SIREG4)) &&
2787 (riscv_cpu_mxl(env) != MXL_RV32)) {
2788 ret = RISCV_EXCP_ILLEGAL_INST;
2789 goto done;
2790 }
2791
2792 /* Check Sscofpmf dependancy */
2793 if (!riscv_cpu_cfg(env)->ext_sscofpmf && csrno == CSR_SIREG5 &&
2794 (isel_hpm_start <= isel && isel <= ISELECT_CD_LAST)) {
2795 goto done;
2796 }
2797
2798 /* Check smcntrpmf dependancy */
2799 if (!riscv_cpu_cfg(env)->ext_smcntrpmf &&
2800 (csrno == CSR_SIREG2 || csrno == CSR_SIREG5) &&
2801 (ISELECT_CD_FIRST <= isel && isel < isel_hpm_start)) {
2802 goto done;
2803 }
2804
2805 if (!get_field(env->mcounteren, BIT(ctr_index)) ||
2806 !get_field(env->menvcfg, MENVCFG_CDE)) {
2807 goto done;
2808 }
2809
2810 switch (csrno) {
2811 case CSR_SIREG:
2812 ret = rmw_cd_mhpmcounter(env, ctr_index, val, new_val, wr_mask);
2813 break;
2814 case CSR_SIREG4:
2815 ret = rmw_cd_mhpmcounterh(env, ctr_index, val, new_val, wr_mask);
2816 break;
2817 case CSR_SIREG2:
2818 if (ctr_index <= 2) {
2819 ret = rmw_cd_ctr_cfg(env, ctr_index, val, new_val, wr_mask);
2820 } else {
2821 ret = rmw_cd_mhpmevent(env, ctr_index, val, new_val, wr_mask);
2822 }
2823 break;
2824 case CSR_SIREG5:
2825 if (ctr_index <= 2) {
2826 ret = rmw_cd_ctr_cfgh(env, ctr_index, val, new_val, wr_mask);
2827 } else {
2828 ret = rmw_cd_mhpmeventh(env, ctr_index, val, new_val, wr_mask);
2829 }
2830 break;
2831 default:
2832 goto done;
2833 }
2834
2835 done:
2836 return ret;
2837 }
2838
2839 static int rmw_xireg_ctr(CPURISCVState *env, int csrno,
2840 uint16_t isel, target_ulong *val,
2841 target_ulong new_val, target_ulong wr_mask)
2842 {
2843 if (!riscv_cpu_cfg(env)->ext_smctr && !riscv_cpu_cfg(env)->ext_ssctr) {
2844 return -EINVAL;
2845 }
2846
2847 if (csrno == CSR_SIREG || csrno == CSR_VSIREG) {
2848 return rmw_ctrsource(env, isel, val, new_val, wr_mask);
2849 } else if (csrno == CSR_SIREG2 || csrno == CSR_VSIREG2) {
2850 return rmw_ctrtarget(env, isel, val, new_val, wr_mask);
2851 } else if (csrno == CSR_SIREG3 || csrno == CSR_VSIREG3) {
2852 return rmw_ctrdata(env, isel, val, new_val, wr_mask);
2853 } else if (val) {
2854 *val = 0;
2855 }
2856
2857 return 0;
2858 }
2859
2860 /*
2861 * rmw_xireg_csrind: Perform indirect access to xireg and xireg2-xireg6
2862 *
2863 * Perform indirect access to xireg and xireg2-xireg6.
2864 * This is a generic interface for all xireg CSRs. Apart from AIA, all other
2865 * extension using csrind should be implemented here.
2866 */
2867 static int rmw_xireg_csrind(CPURISCVState *env, int csrno,
2868 uint16_t isel, target_ulong *val,
2869 target_ulong new_val, target_ulong wr_mask)
2870 {
2871 bool virt = csrno == CSR_VSIREG ? true : false;
2872 int ret = -EINVAL;
2873
2874 if (xiselect_cd_range(isel)) {
2875 ret = rmw_xireg_cd(env, csrno, isel, val, new_val, wr_mask);
2876 } else if (xiselect_ctr_range(csrno, isel)) {
2877 ret = rmw_xireg_ctr(env, csrno, isel, val, new_val, wr_mask);
2878 } else {
2879 /*
2880 * As per the specification, access to unimplented region is undefined
2881 * but recommendation is to raise illegal instruction exception.
2882 */
2883 return RISCV_EXCP_ILLEGAL_INST;
2884 }
2885
2886 if (ret) {
2887 return (env->virt_enabled && virt) ?
2888 RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST;
2889 }
2890
2891 return RISCV_EXCP_NONE;
2892 }
2893
2894 static int rmw_xiregi(CPURISCVState *env, int csrno, target_ulong *val,
2895 target_ulong new_val, target_ulong wr_mask)
2896 {
2897 int ret = -EINVAL;
2898 uint16_t isel;
2899
2900 ret = smstateen_acc_ok(env, 0, SMSTATEEN0_SVSLCT);
2901 if (ret != RISCV_EXCP_NONE) {
2902 return ret;
2903 }
2904
2905 /* Translate CSR number for VS-mode */
2906 csrno = csrind_xlate_vs_csrno(env, csrno);
2907
2908 if (CSR_MIREG <= csrno && csrno <= CSR_MIREG6 &&
2909 csrno != CSR_MIREG4 - 1) {
2910 isel = env->miselect;
2911 } else if (CSR_SIREG <= csrno && csrno <= CSR_SIREG6 &&
2912 csrno != CSR_SIREG4 - 1) {
2913 isel = env->siselect;
2914 } else if (CSR_VSIREG <= csrno && csrno <= CSR_VSIREG6 &&
2915 csrno != CSR_VSIREG4 - 1) {
2916 isel = env->vsiselect;
2917 } else {
2918 return RISCV_EXCP_ILLEGAL_INST;
2919 }
2920
2921 return rmw_xireg_csrind(env, csrno, isel, val, new_val, wr_mask);
2922 }
2923
2924 static RISCVException rmw_xireg(CPURISCVState *env, int csrno,
2925 target_ulong *val, target_ulong new_val,
2926 target_ulong wr_mask)
2927 {
2928 int ret = -EINVAL;
2929 uint16_t isel;
2930
2931 ret = smstateen_acc_ok(env, 0, SMSTATEEN0_SVSLCT);
2932 if (ret != RISCV_EXCP_NONE) {
2933 return ret;
2934 }
2935
2936 /* Translate CSR number for VS-mode */
2937 csrno = csrind_xlate_vs_csrno(env, csrno);
2938
2939 /* Decode register details from CSR number */
2940 switch (csrno) {
2941 case CSR_MIREG:
2942 isel = env->miselect;
2943 break;
2944 case CSR_SIREG:
2945 isel = env->siselect;
2946 break;
2947 case CSR_VSIREG:
2948 isel = env->vsiselect;
2949 break;
2950 default:
2951 goto done;
2952 };
2953
2954 /*
2955 * Use the xiselect range to determine actual op on xireg.
2956 *
2957 * Since we only checked the existence of AIA or Indirect Access in the
2958 * predicate, we should check the existence of the exact extension when
2959 * we get to a specific range and return illegal instruction exception even
2960 * in VS-mode.
2961 */
2962 if (xiselect_aia_range(isel)) {
2963 return rmw_xireg_aia(env, csrno, isel, val, new_val, wr_mask);
2964 } else if (riscv_cpu_cfg(env)->ext_smcsrind ||
2965 riscv_cpu_cfg(env)->ext_sscsrind) {
2966 return rmw_xireg_csrind(env, csrno, isel, val, new_val, wr_mask);
2967 }
2968
2969 done:
2970 return RISCV_EXCP_ILLEGAL_INST;
2971 }
2972
2973 static RISCVException rmw_xtopei(CPURISCVState *env, int csrno,
2974 target_ulong *val, target_ulong new_val,
2975 target_ulong wr_mask)
2976 {
2977 bool virt;
2978 int ret = -EINVAL;
2979 privilege_mode_t priv;
2980 uint32_t vgein;
2981 uint64_t wide_val;
2982
2983 /* Translate CSR number for VS-mode */
2984 csrno = aia_xlate_vs_csrno(env, csrno);
2985
2986 /* Decode register details from CSR number */
2987 virt = false;
2988 switch (csrno) {
2989 case CSR_MTOPEI:
2990 priv = PRV_M;
2991 break;
2992 case CSR_STOPEI:
2993 if (env->mvien & MIP_SEIP && env->priv == PRV_S) {
2994 goto done;
2995 }
2996 priv = PRV_S;
2997 break;
2998 case CSR_VSTOPEI:
2999 priv = PRV_S;
3000 virt = true;
3001 break;
3002 default:
3003 goto done;
3004 };
3005
3006 /* IMSIC CSRs only available when machine implements IMSIC. */
3007 if (!env->aia_ireg_rmw_cb[priv]) {
3008 goto done;
3009 }
3010
3011 /* Find the selected guest interrupt file */
3012 vgein = (virt) ? get_field(env->hstatus, HSTATUS_VGEIN) : 0;
3013
3014 /* Selected guest interrupt file should be valid */
3015 if (virt && (!vgein || env->geilen < vgein)) {
3016 goto done;
3017 }
3018
3019 /* Call machine specific IMSIC register emulation for TOPEI */
3020 ret = env->aia_ireg_rmw_cb[priv](env->aia_ireg_rmw_cb_arg[priv],
3021 AIA_MAKE_IREG(ISELECT_IMSIC_TOPEI, priv, virt, vgein,
3022 riscv_cpu_mxl_bits(env)),
3023 &wide_val, new_val, wr_mask);
3024 if (val) {
3025 *val = wide_val;
3026 }
3027
3028 done:
3029 if (ret) {
3030 return (env->virt_enabled && virt) ?
3031 RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST;
3032 }
3033 return RISCV_EXCP_NONE;
3034 }
3035
3036 static RISCVException read_mtvec(CPURISCVState *env, int csrno,
3037 target_ulong *val)
3038 {
3039 *val = env->mtvec;
3040 return RISCV_EXCP_NONE;
3041 }
3042
3043 static RISCVException write_mtvec(CPURISCVState *env, int csrno,
3044 target_ulong val, uintptr_t ra)
3045 {
3046 /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */
3047 if ((val & 3) < 2) {
3048 env->mtvec = val;
3049 } else {
3050 qemu_log_mask(LOG_UNIMP, "CSR_MTVEC: reserved mode not supported\n");
3051 }
3052 return RISCV_EXCP_NONE;
3053 }
3054
3055 static RISCVException read_mcountinhibit(CPURISCVState *env, int csrno,
3056 target_ulong *val)
3057 {
3058 *val = env->mcountinhibit;
3059 return RISCV_EXCP_NONE;
3060 }
3061
3062 static RISCVException write_mcountinhibit(CPURISCVState *env, int csrno,
3063 target_ulong val, uintptr_t ra)
3064 {
3065 int cidx;
3066 PMUCTRState *counter;
3067 RISCVCPU *cpu = env_archcpu(env);
3068 uint32_t present_ctrs = cpu->pmu_avail_ctrs | COUNTEREN_CY | COUNTEREN_IR;
3069 target_ulong updated_ctrs = (env->mcountinhibit ^ val) & present_ctrs;
3070 uint64_t mhpmctr_val, prev_count, curr_count;
3071
3072 /* WARL register - disable unavailable counters; TM bit is always 0 */
3073 env->mcountinhibit = val & present_ctrs;
3074
3075 /* Check if any other counter is also monitoring cycles/instructions */
3076 for (cidx = 0; cidx < RV_MAX_MHPMCOUNTERS; cidx++) {
3077 if (!(updated_ctrs & BIT(cidx)) ||
3078 (!riscv_pmu_ctr_monitor_cycles(env, cidx) &&
3079 !riscv_pmu_ctr_monitor_instructions(env, cidx))) {
3080 continue;
3081 }
3082
3083 counter = &env->pmu_ctrs[cidx];
3084
3085 if (!get_field(env->mcountinhibit, BIT(cidx))) {
3086 counter->mhpmcounter_prev = riscv_pmu_ctr_get_fixed_counters_val(env, cidx);
3087
3088 if (cidx > 2) {
3089 riscv_pmu_setup_timer(env, counter->mhpmcounter_val, cidx);
3090 }
3091 } else {
3092 curr_count = riscv_pmu_ctr_get_fixed_counters_val(env, cidx);
3093
3094 mhpmctr_val = counter->mhpmcounter_val;
3095 prev_count = counter->mhpmcounter_prev;
3096
3097 /* Adjust the counter for later reads. */
3098 mhpmctr_val = curr_count - prev_count + mhpmctr_val;
3099 counter->mhpmcounter_val = mhpmctr_val;
3100 }
3101 }
3102
3103 return RISCV_EXCP_NONE;
3104 }
3105
3106 static RISCVException read_scountinhibit(CPURISCVState *env, int csrno,
3107 target_ulong *val)
3108 {
3109 /* S-mode can only access the bits delegated by M-mode */
3110 *val = env->mcountinhibit & env->mcounteren;
3111 return RISCV_EXCP_NONE;
3112 }
3113
3114 static RISCVException write_scountinhibit(CPURISCVState *env, int csrno,
3115 target_ulong val, uintptr_t ra)
3116 {
3117 return write_mcountinhibit(env, csrno, val & env->mcounteren, ra);
3118 }
3119
3120 static RISCVException read_mcounteren(CPURISCVState *env, int csrno,
3121 target_ulong *val)
3122 {
3123 *val = env->mcounteren;
3124 return RISCV_EXCP_NONE;
3125 }
3126
3127 static RISCVException write_mcounteren(CPURISCVState *env, int csrno,
3128 target_ulong val, uintptr_t ra)
3129 {
3130 RISCVCPU *cpu = env_archcpu(env);
3131
3132 /* WARL register - disable unavailable counters */
3133 env->mcounteren = val & (cpu->pmu_avail_ctrs | COUNTEREN_CY | COUNTEREN_TM |
3134 COUNTEREN_IR);
3135 return RISCV_EXCP_NONE;
3136 }
3137
3138 /* Machine Trap Handling */
3139 static RISCVException read_mscratch_i128(CPURISCVState *env, int csrno,
3140 Int128 *val)
3141 {
3142 *val = int128_make128(env->mscratch, env->mscratchh);
3143 return RISCV_EXCP_NONE;
3144 }
3145
3146 static RISCVException write_mscratch_i128(CPURISCVState *env, int csrno,
3147 Int128 val)
3148 {
3149 env->mscratch = int128_getlo(val);
3150 env->mscratchh = int128_gethi(val);
3151 return RISCV_EXCP_NONE;
3152 }
3153
3154 static RISCVException read_mscratch(CPURISCVState *env, int csrno,
3155 target_ulong *val)
3156 {
3157 *val = env->mscratch;
3158 return RISCV_EXCP_NONE;
3159 }
3160
3161 static RISCVException write_mscratch(CPURISCVState *env, int csrno,
3162 target_ulong val, uintptr_t ra)
3163 {
3164 env->mscratch = val;
3165 return RISCV_EXCP_NONE;
3166 }
3167
3168 static RISCVException read_mepc(CPURISCVState *env, int csrno,
3169 target_ulong *val)
3170 {
3171 *val = env->mepc & get_xepc_mask(env);
3172 return RISCV_EXCP_NONE;
3173 }
3174
3175 static RISCVException write_mepc(CPURISCVState *env, int csrno,
3176 target_ulong val, uintptr_t ra)
3177 {
3178 env->mepc = val & get_xepc_mask(env);
3179 return RISCV_EXCP_NONE;
3180 }
3181
3182 static RISCVException read_mcause(CPURISCVState *env, int csrno,
3183 target_ulong *val)
3184 {
3185 *val = env->mcause;
3186 return RISCV_EXCP_NONE;
3187 }
3188
3189 static RISCVException write_mcause(CPURISCVState *env, int csrno,
3190 target_ulong val, uintptr_t ra)
3191 {
3192 env->mcause = val;
3193 return RISCV_EXCP_NONE;
3194 }
3195
3196 static RISCVException read_mtval(CPURISCVState *env, int csrno,
3197 target_ulong *val)
3198 {
3199 *val = env->mtval;
3200 return RISCV_EXCP_NONE;
3201 }
3202
3203 static RISCVException write_mtval(CPURISCVState *env, int csrno,
3204 target_ulong val, uintptr_t ra)
3205 {
3206 env->mtval = val;
3207 return RISCV_EXCP_NONE;
3208 }
3209
3210 /* Execution environment configuration setup */
3211 static RISCVException read_menvcfg(CPURISCVState *env, int csrno,
3212 target_ulong *val)
3213 {
3214 *val = env->menvcfg;
3215 return RISCV_EXCP_NONE;
3216 }
3217
3218 static RISCVException write_henvcfg(CPURISCVState *env, int csrno,
3219 target_ulong val, uintptr_t ra);
3220 static RISCVException write_menvcfg(CPURISCVState *env, int csrno,
3221 target_ulong val, uintptr_t ra)
3222 {
3223 const RISCVCPUConfig *cfg = riscv_cpu_cfg(env);
3224 uint64_t mask = MENVCFG_FIOM | MENVCFG_CBIE | MENVCFG_CBCFE |
3225 MENVCFG_CBZE;
3226 bool stce_changed = false;
3227
3228 /*
3229 * menvcfg.LPE (Zicfilp) and menvcfg.SSE (Zicfiss) reside in the low
3230 * 32 bits and are defined for both RV32 and RV64, so they must be
3231 * writable regardless of MXLEN.
3232 */
3233 if (cfg->ext_zicfilp) {
3234 mask |= MENVCFG_LPE;
3235 }
3236
3237 if (cfg->ext_zicfiss) {
3238 mask |= MENVCFG_SSE;
3239 }
3240
3241 if (riscv_cpu_mxl(env) == MXL_RV64) {
3242 mask |= (cfg->ext_svpbmt ? MENVCFG_PBMTE : 0) |
3243 (cfg->ext_sstc ? MENVCFG_STCE : 0) |
3244 (cfg->ext_smcdeleg ? MENVCFG_CDE : 0) |
3245 (cfg->ext_svadu ? MENVCFG_ADUE : 0) |
3246 (cfg->ext_ssdbltrp ? MENVCFG_DTE : 0);
3247
3248 /* Update PMM field only if the value is valid according to Zjpm v1.0 */
3249 if (env_archcpu(env)->cfg.ext_smnpm &&
3250 get_field(val, MENVCFG_PMM) != PMM_FIELD_RESERVED) {
3251 mask |= MENVCFG_PMM;
3252 }
3253
3254 if ((val & MENVCFG_DTE) == 0) {
3255 env->mstatus &= ~MSTATUS_SDT;
3256 }
3257
3258 if (cfg->ext_sstc &&
3259 ((env->menvcfg & MENVCFG_STCE) != (val & MENVCFG_STCE))) {
3260 stce_changed = true;
3261 }
3262 }
3263 env->menvcfg = (env->menvcfg & ~mask) | (val & mask);
3264
3265 if (stce_changed) {
3266 riscv_timer_stce_changed(env, true, !!(val & MENVCFG_STCE));
3267 }
3268
3269 return write_henvcfg(env, CSR_HENVCFG, env->henvcfg, ra);
3270 }
3271
3272 static RISCVException read_menvcfgh(CPURISCVState *env, int csrno,
3273 target_ulong *val)
3274 {
3275 *val = env->menvcfg >> 32;
3276 return RISCV_EXCP_NONE;
3277 }
3278
3279 static RISCVException write_henvcfgh(CPURISCVState *env, int csrno,
3280 target_ulong val, uintptr_t ra);
3281 static RISCVException write_menvcfgh(CPURISCVState *env, int csrno,
3282 target_ulong val, uintptr_t ra)
3283 {
3284 const RISCVCPUConfig *cfg = riscv_cpu_cfg(env);
3285 uint64_t mask = (cfg->ext_svpbmt ? MENVCFG_PBMTE : 0) |
3286 (cfg->ext_sstc ? MENVCFG_STCE : 0) |
3287 (cfg->ext_svadu ? MENVCFG_ADUE : 0) |
3288 (cfg->ext_smcdeleg ? MENVCFG_CDE : 0) |
3289 (cfg->ext_ssdbltrp ? MENVCFG_DTE : 0);
3290 uint64_t valh = (uint64_t)val << 32;
3291 bool stce_changed = false;
3292
3293 if (cfg->ext_sstc &&
3294 ((env->menvcfg & MENVCFG_STCE) != (valh & MENVCFG_STCE))) {
3295 stce_changed = true;
3296 }
3297
3298 if ((valh & MENVCFG_DTE) == 0) {
3299 env->mstatus &= ~MSTATUS_SDT;
3300 }
3301
3302 env->menvcfg = (env->menvcfg & ~mask) | (valh & mask);
3303
3304 if (stce_changed) {
3305 riscv_timer_stce_changed(env, true, !!(valh & MENVCFG_STCE));
3306 }
3307
3308 return write_henvcfgh(env, CSR_HENVCFGH, env->henvcfg >> 32, ra);
3309 }
3310
3311 static RISCVException read_senvcfg(CPURISCVState *env, int csrno,
3312 target_ulong *val)
3313 {
3314 RISCVException ret;
3315
3316 ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG);
3317 if (ret != RISCV_EXCP_NONE) {
3318 return ret;
3319 }
3320
3321 *val = env->senvcfg;
3322 return RISCV_EXCP_NONE;
3323 }
3324
3325 static RISCVException write_senvcfg(CPURISCVState *env, int csrno,
3326 target_ulong val, uintptr_t ra)
3327 {
3328 uint64_t mask = SENVCFG_FIOM | SENVCFG_CBIE | SENVCFG_CBCFE | SENVCFG_CBZE;
3329 RISCVException ret;
3330 /* Update PMM field only if the value is valid according to Zjpm v1.0 */
3331 if (env_archcpu(env)->cfg.ext_ssnpm &&
3332 riscv_cpu_mxl(env) == MXL_RV64 &&
3333 get_field(val, SENVCFG_PMM) != PMM_FIELD_RESERVED) {
3334 mask |= SENVCFG_PMM;
3335 }
3336
3337 ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG);
3338 if (ret != RISCV_EXCP_NONE) {
3339 return ret;
3340 }
3341
3342 if (env_archcpu(env)->cfg.ext_zicfilp) {
3343 mask |= SENVCFG_LPE;
3344 }
3345
3346 /* Higher mode SSE must be ON for next-less mode SSE to be ON */
3347 if (env_archcpu(env)->cfg.ext_zicfiss &&
3348 get_field(env->menvcfg, MENVCFG_SSE) &&
3349 (env->virt_enabled ? get_field(env->henvcfg, HENVCFG_SSE) : true)) {
3350 mask |= SENVCFG_SSE;
3351 }
3352
3353 if (env_archcpu(env)->cfg.ext_svukte) {
3354 mask |= SENVCFG_UKTE;
3355 }
3356
3357 env->senvcfg = (env->senvcfg & ~mask) | (val & mask);
3358 return RISCV_EXCP_NONE;
3359 }
3360
3361 static RISCVException read_henvcfg(CPURISCVState *env, int csrno,
3362 target_ulong *val)
3363 {
3364 RISCVException ret;
3365
3366 ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG);
3367 if (ret != RISCV_EXCP_NONE) {
3368 return ret;
3369 }
3370
3371 /*
3372 * henvcfg.pbmte is read_only 0 when menvcfg.pbmte = 0
3373 * henvcfg.stce is read_only 0 when menvcfg.stce = 0
3374 * henvcfg.adue is read_only 0 when menvcfg.adue = 0
3375 * henvcfg.dte is read_only 0 when menvcfg.dte = 0
3376 */
3377 *val = env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_ADUE |
3378 HENVCFG_DTE) | env->menvcfg);
3379 return RISCV_EXCP_NONE;
3380 }
3381
3382 static RISCVException write_henvcfg(CPURISCVState *env, int csrno,
3383 target_ulong val, uintptr_t ra)
3384 {
3385 const RISCVCPUConfig *cfg = riscv_cpu_cfg(env);
3386 uint64_t mask = HENVCFG_FIOM | HENVCFG_CBIE | HENVCFG_CBCFE | HENVCFG_CBZE;
3387 RISCVException ret;
3388 bool stce_changed = false;
3389
3390 ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG);
3391 if (ret != RISCV_EXCP_NONE) {
3392 return ret;
3393 }
3394
3395 /*
3396 * henvcfg.LPE (Zicfilp) and henvcfg.SSE (Zicfiss) reside in the low
3397 * 32 bits and are defined for both RV32 and RV64, so they must be
3398 * writable regardless of MXLEN.
3399 */
3400 if (cfg->ext_zicfilp) {
3401 mask |= HENVCFG_LPE;
3402 }
3403
3404 /* H can light up SSE for VS only if HS had it from menvcfg */
3405 if (cfg->ext_zicfiss && get_field(env->menvcfg, MENVCFG_SSE)) {
3406 mask |= HENVCFG_SSE;
3407 }
3408
3409 if (riscv_cpu_mxl(env) == MXL_RV64) {
3410 mask |= env->menvcfg & (HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_ADUE |
3411 HENVCFG_DTE);
3412
3413 /* Update PMM field only if the value is valid according to Zjpm v1.0 */
3414 if (env_archcpu(env)->cfg.ext_ssnpm &&
3415 get_field(val, HENVCFG_PMM) != PMM_FIELD_RESERVED) {
3416 mask |= HENVCFG_PMM;
3417 }
3418
3419 if (cfg->ext_sstc &&
3420 ((env->henvcfg & HENVCFG_STCE) != (val & HENVCFG_STCE))) {
3421 stce_changed = true;
3422 }
3423 }
3424
3425 if (riscv_cpu_mxl(env) == MXL_RV32) {
3426 /*
3427 * RV32 stores STCE/ADUE/PBMTE/DTE in henvcfgh, so a low-half henvcfg
3428 * write must not clobber the upper 32 bits.
3429 */
3430 env->henvcfg = (env->henvcfg & ~0xFFFFFFFFULL) | (val & mask);
3431 } else {
3432 env->henvcfg = val & mask;
3433 }
3434 if ((env->henvcfg & HENVCFG_DTE) == 0) {
3435 env->vsstatus &= ~MSTATUS_SDT;
3436 }
3437
3438 if (stce_changed) {
3439 riscv_timer_stce_changed(env, false, !!(val & HENVCFG_STCE));
3440 }
3441
3442 return RISCV_EXCP_NONE;
3443 }
3444
3445 static RISCVException read_henvcfgh(CPURISCVState *env, int csrno,
3446 target_ulong *val)
3447 {
3448 RISCVException ret;
3449
3450 ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG);
3451 if (ret != RISCV_EXCP_NONE) {
3452 return ret;
3453 }
3454
3455 *val = (env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_ADUE |
3456 HENVCFG_DTE) | env->menvcfg)) >> 32;
3457 return RISCV_EXCP_NONE;
3458 }
3459
3460 static RISCVException write_henvcfgh(CPURISCVState *env, int csrno,
3461 target_ulong val, uintptr_t ra)
3462 {
3463 const RISCVCPUConfig *cfg = riscv_cpu_cfg(env);
3464 uint64_t mask = env->menvcfg & (HENVCFG_PBMTE | HENVCFG_STCE |
3465 HENVCFG_ADUE | HENVCFG_DTE);
3466 uint64_t valh = (uint64_t)val << 32;
3467 RISCVException ret;
3468 bool stce_changed = false;
3469
3470 ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG);
3471 if (ret != RISCV_EXCP_NONE) {
3472 return ret;
3473 }
3474
3475 if (cfg->ext_sstc &&
3476 ((env->henvcfg & HENVCFG_STCE) != (valh & HENVCFG_STCE))) {
3477 stce_changed = true;
3478 }
3479
3480 env->henvcfg = (env->henvcfg & 0xFFFFFFFF) | (valh & mask);
3481 if ((env->henvcfg & HENVCFG_DTE) == 0) {
3482 env->vsstatus &= ~MSTATUS_SDT;
3483 }
3484
3485 if (stce_changed) {
3486 riscv_timer_stce_changed(env, false, !!(val & HENVCFG_STCE));
3487 }
3488
3489 return RISCV_EXCP_NONE;
3490 }
3491
3492 static RISCVException read_mstateen(CPURISCVState *env, int csrno,
3493 target_ulong *val)
3494 {
3495 *val = env->mstateen[csrno - CSR_MSTATEEN0];
3496
3497 return RISCV_EXCP_NONE;
3498 }
3499
3500 static RISCVException write_mstateen(CPURISCVState *env, int csrno,
3501 uint64_t wr_mask, target_ulong new_val)
3502 {
3503 uint64_t *reg;
3504
3505 reg = &env->mstateen[csrno - CSR_MSTATEEN0];
3506 *reg = (*reg & ~wr_mask) | (new_val & wr_mask);
3507
3508 return RISCV_EXCP_NONE;
3509 }
3510
3511 static RISCVException write_mstateen0(CPURISCVState *env, int csrno,
3512 target_ulong new_val, uintptr_t ra)
3513 {
3514 uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG;
3515 if (!riscv_has_ext(env, RVF)) {
3516 wr_mask |= SMSTATEEN0_FCSR;
3517 }
3518
3519 if (riscv_cpu_mxl(env) == MXL_RV64) {
3520 if (env->priv_ver >= PRIV_VERSION_1_13_0) {
3521 wr_mask |= SMSTATEEN0_P1P13;
3522 }
3523
3524 if (riscv_cpu_cfg(env)->ext_smaia ||
3525 riscv_cpu_cfg(env)->ext_smcsrind) {
3526 wr_mask |= SMSTATEEN0_SVSLCT;
3527 }
3528
3529 /*
3530 * As per the AIA specification, SMSTATEEN0_IMSIC is valid
3531 * only if IMSIC is implemented. However, that information is
3532 * with MachineState and we can't figure that out in csr.c.
3533 * Just enable if Smaia is available.
3534 */
3535 if (riscv_cpu_cfg(env)->ext_smaia) {
3536 wr_mask |= (SMSTATEEN0_AIA | SMSTATEEN0_IMSIC);
3537 }
3538
3539 if (riscv_cpu_cfg(env)->ext_ssctr) {
3540 wr_mask |= SMSTATEEN0_CTR;
3541 }
3542 }
3543
3544 return write_mstateen(env, csrno, wr_mask, new_val);
3545 }
3546
3547 static RISCVException write_mstateen_1_3(CPURISCVState *env, int csrno,
3548 target_ulong new_val, uintptr_t ra)
3549 {
3550 return write_mstateen(env, csrno, SMSTATEEN_STATEEN, new_val);
3551 }
3552
3553 static RISCVException read_mstateenh(CPURISCVState *env, int csrno,
3554 target_ulong *val)
3555 {
3556 *val = env->mstateen[csrno - CSR_MSTATEEN0H] >> 32;
3557
3558 return RISCV_EXCP_NONE;
3559 }
3560
3561 static RISCVException write_mstateenh(CPURISCVState *env, int csrno,
3562 uint64_t wr_mask, target_ulong new_val)
3563 {
3564 uint64_t *reg, val;
3565
3566 reg = &env->mstateen[csrno - CSR_MSTATEEN0H];
3567 val = (uint64_t)new_val << 32;
3568 val |= *reg & 0xFFFFFFFF;
3569 *reg = (*reg & ~wr_mask) | (val & wr_mask);
3570
3571 return RISCV_EXCP_NONE;
3572 }
3573
3574 static RISCVException write_mstateen0h(CPURISCVState *env, int csrno,
3575 target_ulong new_val, uintptr_t ra)
3576 {
3577 uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG;
3578
3579 if (env->priv_ver >= PRIV_VERSION_1_13_0) {
3580 wr_mask |= SMSTATEEN0_P1P13;
3581 }
3582
3583 if (riscv_cpu_cfg(env)->ext_smaia || riscv_cpu_cfg(env)->ext_smcsrind) {
3584 wr_mask |= SMSTATEEN0_SVSLCT;
3585 }
3586
3587 /*
3588 * As per the AIA specification, SMSTATEEN0_IMSIC is valid only if
3589 * IMSIC is implemented. However, that information is with
3590 * MachineState and we can't figure that out in csr.c. Just enable
3591 * if Smaia is available.
3592 */
3593 if (riscv_cpu_cfg(env)->ext_smaia) {
3594 wr_mask |= (SMSTATEEN0_AIA | SMSTATEEN0_IMSIC);
3595 }
3596
3597 if (riscv_cpu_cfg(env)->ext_ssctr) {
3598 wr_mask |= SMSTATEEN0_CTR;
3599 }
3600
3601 return write_mstateenh(env, csrno, wr_mask, new_val);
3602 }
3603
3604 static RISCVException write_mstateenh_1_3(CPURISCVState *env, int csrno,
3605 target_ulong new_val, uintptr_t ra)
3606 {
3607 return write_mstateenh(env, csrno, SMSTATEEN_STATEEN, new_val);
3608 }
3609
3610 static RISCVException read_hstateen(CPURISCVState *env, int csrno,
3611 target_ulong *val)
3612 {
3613 int index = csrno - CSR_HSTATEEN0;
3614
3615 *val = env->hstateen[index] & env->mstateen[index];
3616
3617 return RISCV_EXCP_NONE;
3618 }
3619
3620 static RISCVException write_hstateen(CPURISCVState *env, int csrno,
3621 uint64_t mask, target_ulong new_val)
3622 {
3623 int index = csrno - CSR_HSTATEEN0;
3624 uint64_t *reg, wr_mask;
3625
3626 reg = &env->hstateen[index];
3627 wr_mask = env->mstateen[index] & mask;
3628 *reg = (*reg & ~wr_mask) | (new_val & wr_mask);
3629
3630 return RISCV_EXCP_NONE;
3631 }
3632
3633 static RISCVException write_hstateen0(CPURISCVState *env, int csrno,
3634 target_ulong new_val, uintptr_t ra)
3635 {
3636 uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG;
3637
3638 if (!riscv_has_ext(env, RVF)) {
3639 wr_mask |= SMSTATEEN0_FCSR;
3640 }
3641
3642 if (riscv_cpu_mxl(env) == MXL_RV64) {
3643 if (riscv_cpu_cfg(env)->ext_ssaia ||
3644 riscv_cpu_cfg(env)->ext_sscsrind) {
3645 wr_mask |= SMSTATEEN0_SVSLCT;
3646 }
3647
3648 /*
3649 * As per the AIA specification, SMSTATEEN0_IMSIC is valid
3650 * only if IMSIC is implemented. However, that information is
3651 * with MachineState and we can't figure that out in csr.c.
3652 * Just enable if Ssaia is available.
3653 */
3654 if (riscv_cpu_cfg(env)->ext_ssaia) {
3655 wr_mask |= (SMSTATEEN0_AIA | SMSTATEEN0_IMSIC);
3656 }
3657
3658 if (riscv_cpu_cfg(env)->ext_ssctr) {
3659 wr_mask |= SMSTATEEN0_CTR;
3660 }
3661 }
3662
3663 return write_hstateen(env, csrno, wr_mask, new_val);
3664 }
3665
3666 static RISCVException write_hstateen_1_3(CPURISCVState *env, int csrno,
3667 target_ulong new_val, uintptr_t ra)
3668 {
3669 return write_hstateen(env, csrno, SMSTATEEN_STATEEN, new_val);
3670 }
3671
3672 static RISCVException read_hstateenh(CPURISCVState *env, int csrno,
3673 target_ulong *val)
3674 {
3675 int index = csrno - CSR_HSTATEEN0H;
3676
3677 *val = (env->hstateen[index] >> 32) & (env->mstateen[index] >> 32);
3678
3679 return RISCV_EXCP_NONE;
3680 }
3681
3682 static RISCVException write_hstateenh(CPURISCVState *env, int csrno,
3683 uint64_t mask, target_ulong new_val)
3684 {
3685 int index = csrno - CSR_HSTATEEN0H;
3686 uint64_t *reg, wr_mask, val;
3687
3688 reg = &env->hstateen[index];
3689 val = (uint64_t)new_val << 32;
3690 val |= *reg & 0xFFFFFFFF;
3691 wr_mask = env->mstateen[index] & mask;
3692 *reg = (*reg & ~wr_mask) | (val & wr_mask);
3693
3694 return RISCV_EXCP_NONE;
3695 }
3696
3697 static RISCVException write_hstateen0h(CPURISCVState *env, int csrno,
3698 target_ulong new_val, uintptr_t ra)
3699 {
3700 uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG;
3701
3702 if (riscv_cpu_cfg(env)->ext_ssaia || riscv_cpu_cfg(env)->ext_sscsrind) {
3703 wr_mask |= SMSTATEEN0_SVSLCT;
3704 }
3705
3706 /*
3707 * As per the AIA specification, SMSTATEEN0_IMSIC is valid only if
3708 * IMSIC is implemented. However, that information is with
3709 * MachineState and we can't figure that out in csr.c. Just enable
3710 * if Ssaia is available.
3711 */
3712 if (riscv_cpu_cfg(env)->ext_ssaia) {
3713 wr_mask |= (SMSTATEEN0_AIA | SMSTATEEN0_IMSIC);
3714 }
3715
3716 if (riscv_cpu_cfg(env)->ext_ssctr) {
3717 wr_mask |= SMSTATEEN0_CTR;
3718 }
3719
3720 return write_hstateenh(env, csrno, wr_mask, new_val);
3721 }
3722
3723 static RISCVException write_hstateenh_1_3(CPURISCVState *env, int csrno,
3724 target_ulong new_val, uintptr_t ra)
3725 {
3726 return write_hstateenh(env, csrno, SMSTATEEN_STATEEN, new_val);
3727 }
3728
3729 static RISCVException read_sstateen(CPURISCVState *env, int csrno,
3730 target_ulong *val)
3731 {
3732 bool virt = env->virt_enabled;
3733 int index = csrno - CSR_SSTATEEN0;
3734
3735 *val = env->sstateen[index] & env->mstateen[index];
3736 if (virt) {
3737 *val &= env->hstateen[index];
3738 }
3739
3740 return RISCV_EXCP_NONE;
3741 }
3742
3743 static RISCVException write_sstateen(CPURISCVState *env, int csrno,
3744 uint64_t mask, target_ulong new_val)
3745 {
3746 bool virt = env->virt_enabled;
3747 int index = csrno - CSR_SSTATEEN0;
3748 uint64_t wr_mask;
3749 uint64_t *reg;
3750
3751 wr_mask = env->mstateen[index] & mask;
3752 if (virt) {
3753 wr_mask &= env->hstateen[index];
3754 }
3755
3756 reg = &env->sstateen[index];
3757 *reg = (*reg & ~wr_mask) | (new_val & wr_mask);
3758
3759 return RISCV_EXCP_NONE;
3760 }
3761
3762 static RISCVException write_sstateen0(CPURISCVState *env, int csrno,
3763 target_ulong new_val, uintptr_t ra)
3764 {
3765 uint64_t wr_mask = 0;
3766
3767 if (!riscv_has_ext(env, RVF)) {
3768 wr_mask |= SMSTATEEN0_FCSR;
3769 }
3770
3771 return write_sstateen(env, csrno, wr_mask, new_val);
3772 }
3773
3774 static RISCVException write_sstateen_1_3(CPURISCVState *env, int csrno,
3775 target_ulong new_val, uintptr_t ra)
3776 {
3777 return write_sstateen(env, csrno, SMSTATEEN_STATEEN, new_val);
3778 }
3779
3780 static RISCVException rmw_mip64(CPURISCVState *env, int csrno,
3781 uint64_t *ret_val,
3782 uint64_t new_val, uint64_t wr_mask)
3783 {
3784 uint64_t old_mip, mask = wr_mask & delegable_ints;
3785 uint32_t gin;
3786
3787 /*
3788 * When mvien[9]=1, mip.SEIP is read-only and reflects only
3789 * the external interrupt signal from the interrupt controller.
3790 */
3791 if (env->mvien & MIP_SEIP) {
3792 mask &= ~MIP_SEIP;
3793 }
3794
3795 if (mask & MIP_SEIP) {
3796 env->software_seip = new_val & MIP_SEIP;
3797 new_val |= env->external_seip * MIP_SEIP;
3798 }
3799
3800 if (riscv_cpu_cfg(env)->ext_sstc && (env->priv == PRV_M) &&
3801 get_field(env->menvcfg, MENVCFG_STCE)) {
3802 /* sstc extension forbids STIP & VSTIP to be writeable in mip */
3803
3804 /* STIP is not writable when menvcfg.STCE is enabled. */
3805 mask = mask & ~MIP_STIP;
3806
3807 /* VSTIP is not writable when both [mh]envcfg.STCE are enabled. */
3808 if (get_field(env->henvcfg, HENVCFG_STCE)) {
3809 mask = mask & ~MIP_VSTIP;
3810 }
3811 }
3812
3813 if (mask) {
3814 old_mip = riscv_cpu_update_mip(env, mask, (new_val & mask));
3815 } else {
3816 old_mip = env->mip;
3817 }
3818
3819 if (csrno != CSR_HVIP) {
3820 gin = get_field(env->hstatus, HSTATUS_VGEIN);
3821 old_mip |= (env->hgeip & (1ULL << gin)) ? MIP_VSEIP : 0;
3822 old_mip |= env->vstime_irq ? MIP_VSTIP : 0;
3823 }
3824
3825 if (ret_val) {
3826 *ret_val = old_mip;
3827 }
3828
3829 return RISCV_EXCP_NONE;
3830 }
3831
3832 static RISCVException rmw_mip(CPURISCVState *env, int csrno,
3833 target_ulong *ret_val,
3834 target_ulong new_val, target_ulong wr_mask)
3835 {
3836 uint64_t rval;
3837 RISCVException ret;
3838
3839 ret = rmw_mip64(env, csrno, &rval, new_val, wr_mask);
3840 if (ret_val) {
3841 *ret_val = rval;
3842 }
3843
3844 return ret;
3845 }
3846
3847 static RISCVException rmw_miph(CPURISCVState *env, int csrno,
3848 target_ulong *ret_val,
3849 target_ulong new_val, target_ulong wr_mask)
3850 {
3851 uint64_t rval;
3852 RISCVException ret;
3853
3854 ret = rmw_mip64(env, csrno, &rval,
3855 ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32);
3856 if (ret_val) {
3857 *ret_val = rval >> 32;
3858 }
3859
3860 return ret;
3861 }
3862
3863 /*
3864 * The function is written for two use-cases:
3865 * 1- To access mvip csr as is for m-mode access.
3866 * 2- To access sip as a combination of mip and mvip for s-mode.
3867 *
3868 * Both report bits 1, 5, 9 and 13:63 but with the exception of
3869 * STIP being read-only zero in case of mvip when sstc extension
3870 * is present.
3871 * Also, sip needs to be read-only zero when both mideleg[i] and
3872 * mvien[i] are zero but mvip needs to be an alias of mip.
3873 */
3874 static RISCVException rmw_mvip64(CPURISCVState *env, int csrno,
3875 uint64_t *ret_val,
3876 uint64_t new_val, uint64_t wr_mask)
3877 {
3878 RISCVCPU *cpu = env_archcpu(env);
3879 target_ulong ret_mip = 0;
3880 RISCVException ret;
3881 uint64_t old_mvip;
3882
3883 /*
3884 * mideleg[i] mvien[i]
3885 * 0 0 No delegation. mvip[i] is alias of mip[i].
3886 * 0 1 mvip[i] becomes source of interrupt, mip bypassed.
3887 * 1 X mip[i] is source of interrupt and mvip[i] aliases
3888 * mip[i].
3889 *
3890 * So alias condition would be for bits:
3891 * ((S_MODE_INTERRUPTS | LOCAL_INTERRUPTS) & (mideleg | ~mvien)) |
3892 * (!sstc & MIP_STIP)
3893 *
3894 * Non-alias condition will be for bits:
3895 * (S_MODE_INTERRUPTS | LOCAL_INTERRUPTS) & (~mideleg & mvien)
3896 *
3897 * alias_mask denotes the bits that come from mip nalias_mask denotes bits
3898 * that come from hvip.
3899 */
3900 uint64_t alias_mask = ((S_MODE_INTERRUPTS | LOCAL_INTERRUPTS) &
3901 (env->mideleg | ~env->mvien)) | MIP_STIP;
3902 uint64_t nalias_mask = (S_MODE_INTERRUPTS | LOCAL_INTERRUPTS) &
3903 (~env->mideleg & env->mvien);
3904 uint64_t wr_mask_mvip;
3905 uint64_t wr_mask_mip;
3906
3907 /*
3908 * mideleg[i] mvien[i]
3909 * 0 0 sip[i] read-only zero.
3910 * 0 1 sip[i] alias of mvip[i].
3911 * 1 X sip[i] alias of mip[i].
3912 *
3913 * Both alias and non-alias mask remain same for sip except for bits
3914 * which are zero in both mideleg and mvien.
3915 */
3916 if (csrno == CSR_SIP) {
3917 /* Remove bits that are zero in both mideleg and mvien. */
3918 alias_mask &= (env->mideleg | env->mvien);
3919 nalias_mask &= (env->mideleg | env->mvien);
3920 }
3921
3922 /*
3923 * If sstc is present, mvip.STIP is not an alias of mip.STIP so clear
3924 * that our in mip returned value.
3925 */
3926 if (cpu->cfg.ext_sstc && (env->priv == PRV_M) &&
3927 get_field(env->menvcfg, MENVCFG_STCE)) {
3928 alias_mask &= ~MIP_STIP;
3929 }
3930
3931 wr_mask_mip = wr_mask & alias_mask & mvip_writable_mask;
3932 wr_mask_mvip = wr_mask & nalias_mask & mvip_writable_mask;
3933
3934 /*
3935 * For bits set in alias_mask, mvip needs to be alias of mip, so forward
3936 * this to rmw_mip.
3937 */
3938 ret = rmw_mip(env, CSR_MIP, &ret_mip, new_val, wr_mask_mip);
3939 if (ret != RISCV_EXCP_NONE) {
3940 return ret;
3941 }
3942
3943 old_mvip = env->mvip;
3944
3945 /*
3946 * Write to mvip. Update only non-alias bits. Alias bits were updated
3947 * in mip in rmw_mip above.
3948 */
3949 if (wr_mask_mvip) {
3950 env->mvip = (env->mvip & ~wr_mask_mvip) | (new_val & wr_mask_mvip);
3951
3952 /*
3953 * Given mvip is separate source from mip, we need to trigger interrupt
3954 * from here separately. Normally this happen from riscv_cpu_update_mip.
3955 */
3956 riscv_cpu_interrupt(env);
3957 }
3958
3959 if (ret_val) {
3960 ret_mip &= alias_mask;
3961 old_mvip &= nalias_mask;
3962
3963 *ret_val = old_mvip | ret_mip;
3964 }
3965
3966 return RISCV_EXCP_NONE;
3967 }
3968
3969 static RISCVException rmw_mvip(CPURISCVState *env, int csrno,
3970 target_ulong *ret_val,
3971 target_ulong new_val, target_ulong wr_mask)
3972 {
3973 uint64_t rval;
3974 RISCVException ret;
3975
3976 ret = rmw_mvip64(env, csrno, &rval, new_val, wr_mask);
3977 if (ret_val) {
3978 *ret_val = rval;
3979 }
3980
3981 return ret;
3982 }
3983
3984 static RISCVException rmw_mviph(CPURISCVState *env, int csrno,
3985 target_ulong *ret_val,
3986 target_ulong new_val, target_ulong wr_mask)
3987 {
3988 uint64_t rval;
3989 RISCVException ret;
3990
3991 ret = rmw_mvip64(env, csrno, &rval,
3992 ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32);
3993 if (ret_val) {
3994 *ret_val = rval >> 32;
3995 }
3996
3997 return ret;
3998 }
3999
4000 /* Supervisor Trap Setup */
4001 static RISCVException read_sstatus_i128(CPURISCVState *env, int csrno,
4002 Int128 *val)
4003 {
4004 uint64_t mask = sstatus_v1_10_mask;
4005 uint64_t sstatus;
4006 if (env->xl != MXL_RV32 || env->debugger) {
4007 mask |= SSTATUS64_UXL;
4008 }
4009 if (riscv_cpu_cfg(env)->ext_ssdbltrp) {
4010 mask |= SSTATUS_SDT;
4011 }
4012
4013 if (env_archcpu(env)->cfg.ext_zicfilp) {
4014 mask |= SSTATUS_SPELP;
4015 }
4016 sstatus = env->mstatus & mask;
4017 *val = int128_make128(sstatus, add_status_sd(MXL_RV128, sstatus));
4018 return RISCV_EXCP_NONE;
4019 }
4020
4021 static RISCVException read_sstatus(CPURISCVState *env, int csrno,
4022 target_ulong *val)
4023 {
4024 target_ulong mask = (sstatus_v1_10_mask);
4025 if (env->xl != MXL_RV32 || env->debugger) {
4026 mask |= SSTATUS64_UXL;
4027 }
4028
4029 if (env_archcpu(env)->cfg.ext_zicfilp) {
4030 mask |= SSTATUS_SPELP;
4031 }
4032 if (riscv_cpu_cfg(env)->ext_ssdbltrp) {
4033 mask |= SSTATUS_SDT;
4034 }
4035
4036 *val = add_status_sd(riscv_cpu_sxl(env), env->mstatus & mask);
4037 return RISCV_EXCP_NONE;
4038 }
4039
4040 static RISCVException write_sstatus(CPURISCVState *env, int csrno,
4041 target_ulong val, uintptr_t ra)
4042 {
4043 target_ulong mask = (sstatus_v1_10_mask);
4044
4045 if (env->xl != MXL_RV32 || env->debugger) {
4046 if ((val & SSTATUS64_UXL) != 0) {
4047 mask |= SSTATUS64_UXL;
4048 }
4049 }
4050
4051 if (env_archcpu(env)->cfg.ext_zicfilp) {
4052 mask |= SSTATUS_SPELP;
4053 }
4054 if (riscv_cpu_cfg(env)->ext_ssdbltrp) {
4055 mask |= SSTATUS_SDT;
4056 }
4057 target_ulong newval = (env->mstatus & ~mask) | (val & mask);
4058 return write_mstatus(env, CSR_MSTATUS, newval, ra);
4059 }
4060
4061 static RISCVException rmw_vsie64(CPURISCVState *env, int csrno,
4062 uint64_t *ret_val,
4063 uint64_t new_val, uint64_t wr_mask)
4064 {
4065 uint64_t alias_mask = (LOCAL_INTERRUPTS | VS_MODE_INTERRUPTS) &
4066 env->hideleg;
4067 uint64_t nalias_mask = LOCAL_INTERRUPTS & (~env->hideleg & env->hvien);
4068 uint64_t rval, rval_vs, vsbits;
4069 uint64_t wr_mask_vsie;
4070 uint64_t wr_mask_mie;
4071 RISCVException ret;
4072
4073 /* Bring VS-level bits to correct position */
4074 vsbits = new_val & (VS_MODE_INTERRUPTS >> 1);
4075 new_val &= ~(VS_MODE_INTERRUPTS >> 1);
4076 new_val |= vsbits << 1;
4077
4078 vsbits = wr_mask & (VS_MODE_INTERRUPTS >> 1);
4079 wr_mask &= ~(VS_MODE_INTERRUPTS >> 1);
4080 wr_mask |= vsbits << 1;
4081
4082 wr_mask_mie = wr_mask & alias_mask;
4083 wr_mask_vsie = wr_mask & nalias_mask;
4084
4085 ret = rmw_mie64(env, csrno, &rval, new_val, wr_mask_mie);
4086
4087 rval_vs = env->vsie & nalias_mask;
4088 env->vsie = (env->vsie & ~wr_mask_vsie) | (new_val & wr_mask_vsie);
4089
4090 if (ret_val) {
4091 rval &= alias_mask;
4092 vsbits = rval & VS_MODE_INTERRUPTS;
4093 rval &= ~VS_MODE_INTERRUPTS;
4094 *ret_val = rval | (vsbits >> 1) | rval_vs;
4095 }
4096
4097 return ret;
4098 }
4099
4100 static RISCVException rmw_vsie(CPURISCVState *env, int csrno,
4101 target_ulong *ret_val,
4102 target_ulong new_val, target_ulong wr_mask)
4103 {
4104 uint64_t rval;
4105 RISCVException ret;
4106
4107 ret = rmw_vsie64(env, csrno, &rval, new_val, wr_mask);
4108 if (ret_val) {
4109 *ret_val = rval;
4110 }
4111
4112 return ret;
4113 }
4114
4115 static RISCVException rmw_vsieh(CPURISCVState *env, int csrno,
4116 target_ulong *ret_val,
4117 target_ulong new_val, target_ulong wr_mask)
4118 {
4119 uint64_t rval;
4120 RISCVException ret;
4121
4122 ret = rmw_vsie64(env, csrno, &rval,
4123 ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32);
4124 if (ret_val) {
4125 *ret_val = rval >> 32;
4126 }
4127
4128 return ret;
4129 }
4130
4131 static RISCVException rmw_sie64(CPURISCVState *env, int csrno,
4132 uint64_t *ret_val,
4133 uint64_t new_val, uint64_t wr_mask)
4134 {
4135 uint64_t nalias_mask = (S_MODE_INTERRUPTS | LOCAL_INTERRUPTS) &
4136 (~env->mideleg & env->mvien);
4137 uint64_t alias_mask = (S_MODE_INTERRUPTS | LOCAL_INTERRUPTS) & env->mideleg;
4138 uint64_t sie_mask = wr_mask & nalias_mask;
4139 RISCVException ret;
4140
4141 /*
4142 * mideleg[i] mvien[i]
4143 * 0 0 sie[i] read-only zero.
4144 * 0 1 sie[i] is a separate writable bit.
4145 * 1 X sie[i] alias of mie[i].
4146 *
4147 * Both alias and non-alias mask remain same for sip except for bits
4148 * which are zero in both mideleg and mvien.
4149 */
4150 if (env->virt_enabled) {
4151 if (env->hvictl & HVICTL_VTI) {
4152 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
4153 }
4154 ret = rmw_vsie64(env, CSR_VSIE, ret_val, new_val, wr_mask);
4155 if (ret_val) {
4156 *ret_val &= alias_mask;
4157 }
4158 } else {
4159 ret = rmw_mie64(env, csrno, ret_val, new_val, wr_mask & alias_mask);
4160 if (ret_val) {
4161 *ret_val &= alias_mask;
4162 *ret_val |= env->sie & nalias_mask;
4163 }
4164
4165 env->sie = (env->sie & ~sie_mask) | (new_val & sie_mask);
4166 }
4167
4168 return ret;
4169 }
4170
4171 static RISCVException rmw_sie(CPURISCVState *env, int csrno,
4172 target_ulong *ret_val,
4173 target_ulong new_val, target_ulong wr_mask)
4174 {
4175 uint64_t rval;
4176 RISCVException ret;
4177
4178 ret = rmw_sie64(env, csrno, &rval, new_val, wr_mask);
4179 if (ret == RISCV_EXCP_NONE && ret_val) {
4180 *ret_val = rval;
4181 }
4182
4183 return ret;
4184 }
4185
4186 static RISCVException rmw_sieh(CPURISCVState *env, int csrno,
4187 target_ulong *ret_val,
4188 target_ulong new_val, target_ulong wr_mask)
4189 {
4190 uint64_t rval;
4191 RISCVException ret;
4192
4193 ret = rmw_sie64(env, csrno, &rval,
4194 ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32);
4195 if (ret_val) {
4196 *ret_val = rval >> 32;
4197 }
4198
4199 return ret;
4200 }
4201
4202 static RISCVException read_stvec(CPURISCVState *env, int csrno,
4203 target_ulong *val)
4204 {
4205 *val = env->stvec;
4206 return RISCV_EXCP_NONE;
4207 }
4208
4209 static RISCVException write_stvec(CPURISCVState *env, int csrno,
4210 target_ulong val, uintptr_t ra)
4211 {
4212 /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */
4213 if ((val & 3) < 2) {
4214 env->stvec = val;
4215 } else {
4216 qemu_log_mask(LOG_UNIMP, "CSR_STVEC: reserved mode not supported\n");
4217 }
4218 return RISCV_EXCP_NONE;
4219 }
4220
4221 static RISCVException read_scounteren(CPURISCVState *env, int csrno,
4222 target_ulong *val)
4223 {
4224 *val = env->scounteren;
4225 return RISCV_EXCP_NONE;
4226 }
4227
4228 static RISCVException write_scounteren(CPURISCVState *env, int csrno,
4229 target_ulong val, uintptr_t ra)
4230 {
4231 RISCVCPU *cpu = env_archcpu(env);
4232
4233 /* WARL register - disable unavailable counters */
4234 env->scounteren = val & (cpu->pmu_avail_ctrs | COUNTEREN_CY | COUNTEREN_TM |
4235 COUNTEREN_IR);
4236 return RISCV_EXCP_NONE;
4237 }
4238
4239 /* Supervisor Trap Handling */
4240 static RISCVException read_sscratch_i128(CPURISCVState *env, int csrno,
4241 Int128 *val)
4242 {
4243 *val = int128_make128(env->sscratch, env->sscratchh);
4244 return RISCV_EXCP_NONE;
4245 }
4246
4247 static RISCVException write_sscratch_i128(CPURISCVState *env, int csrno,
4248 Int128 val)
4249 {
4250 env->sscratch = int128_getlo(val);
4251 env->sscratchh = int128_gethi(val);
4252 return RISCV_EXCP_NONE;
4253 }
4254
4255 static RISCVException read_sscratch(CPURISCVState *env, int csrno,
4256 target_ulong *val)
4257 {
4258 *val = env->sscratch;
4259 return RISCV_EXCP_NONE;
4260 }
4261
4262 static RISCVException write_sscratch(CPURISCVState *env, int csrno,
4263 target_ulong val, uintptr_t ra)
4264 {
4265 env->sscratch = val;
4266 return RISCV_EXCP_NONE;
4267 }
4268
4269 static RISCVException read_sepc(CPURISCVState *env, int csrno,
4270 target_ulong *val)
4271 {
4272 *val = env->sepc & get_xepc_mask(env);
4273 return RISCV_EXCP_NONE;
4274 }
4275
4276 static RISCVException write_sepc(CPURISCVState *env, int csrno,
4277 target_ulong val, uintptr_t ra)
4278 {
4279 env->sepc = val & get_xepc_mask(env);
4280 return RISCV_EXCP_NONE;
4281 }
4282
4283 static RISCVException read_scause(CPURISCVState *env, int csrno,
4284 target_ulong *val)
4285 {
4286 *val = env->scause;
4287 return RISCV_EXCP_NONE;
4288 }
4289
4290 static RISCVException write_scause(CPURISCVState *env, int csrno,
4291 target_ulong val, uintptr_t ra)
4292 {
4293 env->scause = val;
4294 return RISCV_EXCP_NONE;
4295 }
4296
4297 static RISCVException read_stval(CPURISCVState *env, int csrno,
4298 target_ulong *val)
4299 {
4300 *val = env->stval;
4301 return RISCV_EXCP_NONE;
4302 }
4303
4304 static RISCVException write_stval(CPURISCVState *env, int csrno,
4305 target_ulong val, uintptr_t ra)
4306 {
4307 env->stval = val;
4308 return RISCV_EXCP_NONE;
4309 }
4310
4311 static RISCVException rmw_hvip64(CPURISCVState *env, int csrno,
4312 uint64_t *ret_val,
4313 uint64_t new_val, uint64_t wr_mask);
4314
4315 static RISCVException rmw_vsip64(CPURISCVState *env, int csrno,
4316 uint64_t *ret_val,
4317 uint64_t new_val, uint64_t wr_mask)
4318 {
4319 RISCVException ret;
4320 uint64_t rval, mask = env->hideleg & VS_MODE_INTERRUPTS;
4321 uint64_t vsbits;
4322
4323 /* Add virtualized bits into vsip mask. */
4324 mask |= env->hvien & ~env->hideleg;
4325
4326 /* Bring VS-level bits to correct position */
4327 vsbits = new_val & (VS_MODE_INTERRUPTS >> 1);
4328 new_val &= ~(VS_MODE_INTERRUPTS >> 1);
4329 new_val |= vsbits << 1;
4330 vsbits = wr_mask & (VS_MODE_INTERRUPTS >> 1);
4331 wr_mask &= ~(VS_MODE_INTERRUPTS >> 1);
4332 wr_mask |= vsbits << 1;
4333
4334 ret = rmw_hvip64(env, csrno, &rval, new_val,
4335 wr_mask & mask & vsip_writable_mask);
4336 if (ret_val) {
4337 rval &= mask;
4338 vsbits = rval & VS_MODE_INTERRUPTS;
4339 rval &= ~VS_MODE_INTERRUPTS;
4340 *ret_val = rval | (vsbits >> 1);
4341 }
4342
4343 return ret;
4344 }
4345
4346 static RISCVException rmw_vsip(CPURISCVState *env, int csrno,
4347 target_ulong *ret_val,
4348 target_ulong new_val, target_ulong wr_mask)
4349 {
4350 uint64_t rval;
4351 RISCVException ret;
4352
4353 ret = rmw_vsip64(env, csrno, &rval, new_val, wr_mask);
4354 if (ret_val) {
4355 *ret_val = rval;
4356 }
4357
4358 return ret;
4359 }
4360
4361 static RISCVException rmw_vsiph(CPURISCVState *env, int csrno,
4362 target_ulong *ret_val,
4363 target_ulong new_val, target_ulong wr_mask)
4364 {
4365 uint64_t rval;
4366 RISCVException ret;
4367
4368 ret = rmw_vsip64(env, csrno, &rval,
4369 ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32);
4370 if (ret_val) {
4371 *ret_val = rval >> 32;
4372 }
4373
4374 return ret;
4375 }
4376
4377 static RISCVException rmw_sip64(CPURISCVState *env, int csrno,
4378 uint64_t *ret_val,
4379 uint64_t new_val, uint64_t wr_mask)
4380 {
4381 RISCVException ret;
4382 uint64_t mask = (env->mideleg | env->mvien) & sip_writable_mask;
4383
4384 if (env->virt_enabled) {
4385 if (env->hvictl & HVICTL_VTI) {
4386 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
4387 }
4388 ret = rmw_vsip64(env, CSR_VSIP, ret_val, new_val, wr_mask);
4389 } else {
4390 ret = rmw_mvip64(env, csrno, ret_val, new_val, wr_mask & mask);
4391 }
4392
4393 if (ret_val) {
4394 *ret_val &= (env->mideleg | env->mvien) &
4395 (S_MODE_INTERRUPTS | LOCAL_INTERRUPTS);
4396 }
4397
4398 return ret;
4399 }
4400
4401 static RISCVException rmw_sip(CPURISCVState *env, int csrno,
4402 target_ulong *ret_val,
4403 target_ulong new_val, target_ulong wr_mask)
4404 {
4405 uint64_t rval;
4406 RISCVException ret;
4407
4408 ret = rmw_sip64(env, csrno, &rval, new_val, wr_mask);
4409 if (ret_val) {
4410 *ret_val = rval;
4411 }
4412
4413 return ret;
4414 }
4415
4416 static RISCVException rmw_siph(CPURISCVState *env, int csrno,
4417 target_ulong *ret_val,
4418 target_ulong new_val, target_ulong wr_mask)
4419 {
4420 uint64_t rval;
4421 RISCVException ret;
4422
4423 ret = rmw_sip64(env, csrno, &rval,
4424 ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32);
4425 if (ret_val) {
4426 *ret_val = rval >> 32;
4427 }
4428
4429 return ret;
4430 }
4431
4432 /* Supervisor Protection and Translation */
4433 static RISCVException read_satp(CPURISCVState *env, int csrno,
4434 target_ulong *val)
4435 {
4436 if (!riscv_cpu_cfg(env)->mmu) {
4437 *val = 0;
4438 return RISCV_EXCP_NONE;
4439 }
4440 *val = env->satp;
4441 return RISCV_EXCP_NONE;
4442 }
4443
4444 static RISCVException write_satp(CPURISCVState *env, int csrno,
4445 target_ulong val, uintptr_t ra)
4446 {
4447 if (!riscv_cpu_cfg(env)->mmu) {
4448 return RISCV_EXCP_NONE;
4449 }
4450
4451 env->satp = legalize_xatp(env, env->satp, val);
4452 return RISCV_EXCP_NONE;
4453 }
4454
4455 static RISCVException rmw_sctrdepth(CPURISCVState *env, int csrno,
4456 target_ulong *ret_val,
4457 target_ulong new_val, target_ulong wr_mask)
4458 {
4459 uint64_t mask = wr_mask & SCTRDEPTH_MASK;
4460
4461 if (ret_val) {
4462 *ret_val = env->sctrdepth;
4463 }
4464
4465 env->sctrdepth = (env->sctrdepth & ~mask) | (new_val & mask);
4466
4467 /* Correct depth. */
4468 if (mask) {
4469 uint64_t depth = get_field(env->sctrdepth, SCTRDEPTH_MASK);
4470
4471 if (depth > SCTRDEPTH_MAX) {
4472 depth = SCTRDEPTH_MAX;
4473 env->sctrdepth = set_field(env->sctrdepth, SCTRDEPTH_MASK, depth);
4474 }
4475
4476 /* Update sctrstatus.WRPTR with a legal value */
4477 depth = 16ULL << depth;
4478 env->sctrstatus =
4479 env->sctrstatus & (~SCTRSTATUS_WRPTR_MASK | (depth - 1));
4480 }
4481
4482 return RISCV_EXCP_NONE;
4483 }
4484
4485 static RISCVException rmw_sctrstatus(CPURISCVState *env, int csrno,
4486 target_ulong *ret_val,
4487 target_ulong new_val, target_ulong wr_mask)
4488 {
4489 uint32_t depth = 16 << get_field(env->sctrdepth, SCTRDEPTH_MASK);
4490 uint32_t mask = wr_mask & SCTRSTATUS_MASK;
4491
4492 if (ret_val) {
4493 *ret_val = env->sctrstatus;
4494 }
4495
4496 env->sctrstatus = (env->sctrstatus & ~mask) | (new_val & mask);
4497
4498 /* Update sctrstatus.WRPTR with a legal value */
4499 env->sctrstatus = env->sctrstatus & (~SCTRSTATUS_WRPTR_MASK | (depth - 1));
4500
4501 return RISCV_EXCP_NONE;
4502 }
4503
4504 static RISCVException rmw_xctrctl(CPURISCVState *env, int csrno,
4505 target_ulong *ret_val,
4506 target_ulong new_val, target_ulong wr_mask)
4507 {
4508 uint64_t csr_mask, mask = wr_mask;
4509 uint64_t *ctl_ptr = &env->mctrctl;
4510
4511 if (csrno == CSR_MCTRCTL) {
4512 csr_mask = MCTRCTL_MASK;
4513 } else if (csrno == CSR_SCTRCTL && !env->virt_enabled) {
4514 csr_mask = SCTRCTL_MASK;
4515 } else {
4516 /*
4517 * This is for csrno == CSR_SCTRCTL and env->virt_enabled == true
4518 * or csrno == CSR_VSCTRCTL.
4519 */
4520 csr_mask = VSCTRCTL_MASK;
4521 ctl_ptr = &env->vsctrctl;
4522 }
4523
4524 mask &= csr_mask;
4525
4526 if (ret_val) {
4527 *ret_val = *ctl_ptr & csr_mask;
4528 }
4529
4530 *ctl_ptr = (*ctl_ptr & ~mask) | (new_val & mask);
4531
4532 return RISCV_EXCP_NONE;
4533 }
4534
4535 static RISCVException read_vstopi(CPURISCVState *env, int csrno,
4536 target_ulong *val)
4537 {
4538 int irq, ret;
4539 uint64_t topei = 0;
4540 uint64_t vseip, vsgein;
4541 uint32_t iid, iprio, hviid, hviprio, gein;
4542 uint32_t s, scount = 0, siid[VSTOPI_NUM_SRCS], siprio[VSTOPI_NUM_SRCS];
4543
4544 gein = get_field(env->hstatus, HSTATUS_VGEIN);
4545 hviid = get_field(env->hvictl, HVICTL_IID);
4546 hviprio = get_field(env->hvictl, HVICTL_IPRIO);
4547
4548 if (gein) {
4549 vsgein = (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0;
4550 vseip = env->mie & (env->mip | vsgein) & MIP_VSEIP;
4551 if (gein <= env->geilen && vseip) {
4552 siid[scount] = IRQ_S_EXT;
4553 siprio[scount] = IPRIO_MMAXIPRIO + 1;
4554 if (env->aia_ireg_rmw_cb[PRV_S]) {
4555 /*
4556 * Call machine specific IMSIC register emulation for
4557 * reading TOPEI.
4558 */
4559 ret = env->aia_ireg_rmw_cb[PRV_S](
4560 env->aia_ireg_rmw_cb_arg[PRV_S],
4561 AIA_MAKE_IREG(ISELECT_IMSIC_TOPEI, PRV_S, true, gein,
4562 riscv_cpu_mxl_bits(env)),
4563 &topei, 0, 0);
4564 if (!ret && topei) {
4565 siprio[scount] = topei & IMSIC_TOPEI_IPRIO_MASK;
4566 }
4567 }
4568 scount++;
4569 }
4570 } else {
4571 if (hviid == IRQ_S_EXT && hviprio) {
4572 siid[scount] = IRQ_S_EXT;
4573 siprio[scount] = hviprio;
4574 scount++;
4575 }
4576 }
4577
4578 if (env->hvictl & HVICTL_VTI) {
4579 if (hviid != IRQ_S_EXT) {
4580 siid[scount] = hviid;
4581 siprio[scount] = hviprio;
4582 scount++;
4583 }
4584 } else {
4585 irq = riscv_cpu_vsirq_pending(env);
4586 if (irq != IRQ_S_EXT && 0 < irq && irq <= 63) {
4587 siid[scount] = irq;
4588 siprio[scount] = env->hviprio[irq];
4589 scount++;
4590 }
4591 }
4592
4593 iid = 0;
4594 iprio = UINT_MAX;
4595 for (s = 0; s < scount; s++) {
4596 if (siprio[s] < iprio) {
4597 iid = siid[s];
4598 iprio = siprio[s];
4599 }
4600 }
4601
4602 if (iid) {
4603 if (env->hvictl & HVICTL_IPRIOM) {
4604 if (iprio > IPRIO_MMAXIPRIO) {
4605 iprio = IPRIO_MMAXIPRIO;
4606 }
4607 if (!iprio) {
4608 if (riscv_cpu_default_priority(iid) > IPRIO_DEFAULT_S) {
4609 iprio = IPRIO_MMAXIPRIO;
4610 }
4611 }
4612 } else {
4613 iprio = 1;
4614 }
4615 } else {
4616 iprio = 0;
4617 }
4618
4619 *val = (iid & TOPI_IID_MASK) << TOPI_IID_SHIFT;
4620 *val |= iprio;
4621
4622 return RISCV_EXCP_NONE;
4623 }
4624
4625 static RISCVException read_stopi(CPURISCVState *env, int csrno,
4626 target_ulong *val)
4627 {
4628 int irq;
4629 uint8_t iprio;
4630
4631 if (env->virt_enabled) {
4632 return read_vstopi(env, CSR_VSTOPI, val);
4633 }
4634
4635 irq = riscv_cpu_sirq_pending(env);
4636 if (irq <= 0 || irq > 63) {
4637 *val = 0;
4638 } else {
4639 iprio = env->siprio[irq];
4640 if (!iprio) {
4641 if (riscv_cpu_default_priority(irq) > IPRIO_DEFAULT_S) {
4642 iprio = IPRIO_MMAXIPRIO;
4643 }
4644 }
4645 *val = (irq & TOPI_IID_MASK) << TOPI_IID_SHIFT;
4646 *val |= iprio;
4647 }
4648
4649 return RISCV_EXCP_NONE;
4650 }
4651
4652 /* Hypervisor Extensions */
4653 static RISCVException read_hstatus(CPURISCVState *env, int csrno,
4654 target_ulong *val)
4655 {
4656 *val = env->hstatus;
4657 if (riscv_cpu_mxl(env) != MXL_RV32) {
4658 /* We only support 64-bit VSXL */
4659 *val = set_field(*val, HSTATUS_VSXL, 2);
4660 }
4661 /* We only support little endian */
4662 *val = set_field(*val, HSTATUS_VSBE, 0);
4663 return RISCV_EXCP_NONE;
4664 }
4665
4666 static RISCVException write_hstatus(CPURISCVState *env, int csrno,
4667 target_ulong val, uintptr_t ra)
4668 {
4669 uint64_t mask = (target_ulong)-1;
4670 if (!env_archcpu(env)->cfg.ext_svukte) {
4671 mask &= ~HSTATUS_HUKTE;
4672 }
4673 /* Update PMM field only if the value is valid according to Zjpm v1.0 */
4674 if (!env_archcpu(env)->cfg.ext_ssnpm ||
4675 riscv_cpu_mxl(env) != MXL_RV64 ||
4676 get_field(val, HSTATUS_HUPMM) == PMM_FIELD_RESERVED) {
4677 mask &= ~HSTATUS_HUPMM;
4678 }
4679 env->hstatus = (env->hstatus & ~mask) | (val & mask);
4680
4681 if (riscv_cpu_mxl(env) != MXL_RV32 && get_field(val, HSTATUS_VSXL) != 2) {
4682 qemu_log_mask(LOG_UNIMP,
4683 "QEMU does not support mixed HSXLEN options.");
4684 }
4685 if (get_field(val, HSTATUS_VSBE) != 0) {
4686 qemu_log_mask(LOG_UNIMP, "QEMU does not support big endian guests.");
4687 }
4688 return RISCV_EXCP_NONE;
4689 }
4690
4691 static RISCVException read_hedeleg(CPURISCVState *env, int csrno,
4692 target_ulong *val)
4693 {
4694 *val = env->hedeleg;
4695 return RISCV_EXCP_NONE;
4696 }
4697
4698 static RISCVException write_hedeleg(CPURISCVState *env, int csrno,
4699 target_ulong val, uintptr_t ra)
4700 {
4701 env->hedeleg = val & vs_delegable_excps;
4702 return RISCV_EXCP_NONE;
4703 }
4704
4705 static RISCVException read_hedelegh(CPURISCVState *env, int csrno,
4706 target_ulong *val)
4707 {
4708 RISCVException ret;
4709 ret = smstateen_acc_ok(env, 0, SMSTATEEN0_P1P13);
4710 if (ret != RISCV_EXCP_NONE) {
4711 return ret;
4712 }
4713
4714 /* Reserved, now read zero */
4715 *val = 0;
4716 return RISCV_EXCP_NONE;
4717 }
4718
4719 static RISCVException write_hedelegh(CPURISCVState *env, int csrno,
4720 target_ulong val, uintptr_t ra)
4721 {
4722 RISCVException ret;
4723 ret = smstateen_acc_ok(env, 0, SMSTATEEN0_P1P13);
4724 if (ret != RISCV_EXCP_NONE) {
4725 return ret;
4726 }
4727
4728 /* Reserved, now write ignore */
4729 return RISCV_EXCP_NONE;
4730 }
4731
4732 static RISCVException rmw_hvien64(CPURISCVState *env, int csrno,
4733 uint64_t *ret_val,
4734 uint64_t new_val, uint64_t wr_mask)
4735 {
4736 uint64_t mask = wr_mask & hvien_writable_mask;
4737
4738 if (ret_val) {
4739 *ret_val = env->hvien;
4740 }
4741
4742 env->hvien = (env->hvien & ~mask) | (new_val & mask);
4743
4744 return RISCV_EXCP_NONE;
4745 }
4746
4747 static RISCVException rmw_hvien(CPURISCVState *env, int csrno,
4748 target_ulong *ret_val,
4749 target_ulong new_val, target_ulong wr_mask)
4750 {
4751 uint64_t rval;
4752 RISCVException ret;
4753
4754 ret = rmw_hvien64(env, csrno, &rval, new_val, wr_mask);
4755 if (ret_val) {
4756 *ret_val = rval;
4757 }
4758
4759 return ret;
4760 }
4761
4762 static RISCVException rmw_hvienh(CPURISCVState *env, int csrno,
4763 target_ulong *ret_val,
4764 target_ulong new_val, target_ulong wr_mask)
4765 {
4766 uint64_t rval;
4767 RISCVException ret;
4768
4769 ret = rmw_hvien64(env, csrno, &rval,
4770 ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32);
4771 if (ret_val) {
4772 *ret_val = rval >> 32;
4773 }
4774
4775 return ret;
4776 }
4777
4778 static RISCVException rmw_hideleg64(CPURISCVState *env, int csrno,
4779 uint64_t *ret_val,
4780 uint64_t new_val, uint64_t wr_mask)
4781 {
4782 uint64_t mask = wr_mask & vs_delegable_ints;
4783
4784 if (ret_val) {
4785 *ret_val = env->hideleg & vs_delegable_ints;
4786 }
4787
4788 env->hideleg = (env->hideleg & ~mask) | (new_val & mask);
4789 return RISCV_EXCP_NONE;
4790 }
4791
4792 static RISCVException rmw_hideleg(CPURISCVState *env, int csrno,
4793 target_ulong *ret_val,
4794 target_ulong new_val, target_ulong wr_mask)
4795 {
4796 uint64_t rval;
4797 RISCVException ret;
4798
4799 ret = rmw_hideleg64(env, csrno, &rval, new_val, wr_mask);
4800 if (ret_val) {
4801 *ret_val = rval;
4802 }
4803
4804 return ret;
4805 }
4806
4807 static RISCVException rmw_hidelegh(CPURISCVState *env, int csrno,
4808 target_ulong *ret_val,
4809 target_ulong new_val, target_ulong wr_mask)
4810 {
4811 uint64_t rval;
4812 RISCVException ret;
4813
4814 ret = rmw_hideleg64(env, csrno, &rval,
4815 ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32);
4816 if (ret_val) {
4817 *ret_val = rval >> 32;
4818 }
4819
4820 return ret;
4821 }
4822
4823 /*
4824 * The function is written for two use-cases:
4825 * 1- To access hvip csr as is for HS-mode access.
4826 * 2- To access vsip as a combination of hvip, and mip for vs-mode.
4827 *
4828 * Both report bits 2, 6, 10 and 13:63.
4829 * vsip needs to be read-only zero when both hideleg[i] and
4830 * hvien[i] are zero.
4831 */
4832 static RISCVException rmw_hvip64(CPURISCVState *env, int csrno,
4833 uint64_t *ret_val,
4834 uint64_t new_val, uint64_t wr_mask)
4835 {
4836 RISCVException ret;
4837 uint64_t old_hvip;
4838 uint64_t ret_mip;
4839
4840 /*
4841 * For bits 10, 6 and 2, vsip[i] is an alias of hip[i]. These bits are
4842 * present in hip, hvip and mip. Where mip[i] is alias of hip[i] and hvip[i]
4843 * is OR'ed in hip[i] to inject virtual interrupts from hypervisor. These
4844 * bits are actually being maintained in mip so we read them from there.
4845 * This way we have a single source of truth and allows for easier
4846 * implementation.
4847 *
4848 * For bits 13:63 we have:
4849 *
4850 * hideleg[i] hvien[i]
4851 * 0 0 No delegation. vsip[i] readonly zero.
4852 * 0 1 vsip[i] is alias of hvip[i], sip bypassed.
4853 * 1 X vsip[i] is alias of sip[i], hvip bypassed.
4854 *
4855 * alias_mask denotes the bits that come from sip (mip here given we
4856 * maintain all bits there). nalias_mask denotes bits that come from
4857 * hvip.
4858 */
4859 uint64_t alias_mask = (env->hideleg | ~env->hvien) | VS_MODE_INTERRUPTS;
4860 uint64_t nalias_mask = (~env->hideleg & env->hvien);
4861 uint64_t wr_mask_hvip;
4862 uint64_t wr_mask_mip;
4863
4864 /*
4865 * Both alias and non-alias mask remain same for vsip except:
4866 * 1- For VS* bits if they are zero in hideleg.
4867 * 2- For 13:63 bits if they are zero in both hideleg and hvien.
4868 */
4869 if (csrno == CSR_VSIP) {
4870 /* zero-out VS* bits that are not delegated to VS mode. */
4871 alias_mask &= (env->hideleg | ~VS_MODE_INTERRUPTS);
4872
4873 /*
4874 * zero-out 13:63 bits that are zero in both hideleg and hvien.
4875 * nalias_mask mask can not contain any VS* bits so only second
4876 * condition applies on it.
4877 */
4878 nalias_mask &= (env->hideleg | env->hvien);
4879 alias_mask &= (env->hideleg | env->hvien);
4880 }
4881
4882 wr_mask_hvip = wr_mask & nalias_mask & hvip_writable_mask;
4883 wr_mask_mip = wr_mask & alias_mask & hvip_writable_mask;
4884
4885 /* Aliased bits, bits 10, 6, 2 need to come from mip. */
4886 ret = rmw_mip64(env, csrno, &ret_mip, new_val, wr_mask_mip);
4887 if (ret != RISCV_EXCP_NONE) {
4888 return ret;
4889 }
4890
4891 old_hvip = env->hvip;
4892
4893 if (wr_mask_hvip) {
4894 env->hvip = (env->hvip & ~wr_mask_hvip) | (new_val & wr_mask_hvip);
4895
4896 /*
4897 * Given hvip is separate source from mip, we need to trigger interrupt
4898 * from here separately. Normally this happen from riscv_cpu_update_mip.
4899 */
4900 riscv_cpu_interrupt(env);
4901 }
4902
4903 if (ret_val) {
4904 /* Only take VS* bits from mip. */
4905 ret_mip &= alias_mask;
4906
4907 /* Take in non-delegated 13:63 bits from hvip. */
4908 old_hvip &= nalias_mask;
4909
4910 *ret_val = ret_mip | old_hvip;
4911 }
4912
4913 return ret;
4914 }
4915
4916 static RISCVException rmw_hvip(CPURISCVState *env, int csrno,
4917 target_ulong *ret_val,
4918 target_ulong new_val, target_ulong wr_mask)
4919 {
4920 uint64_t rval;
4921 RISCVException ret;
4922
4923 ret = rmw_hvip64(env, csrno, &rval, new_val, wr_mask);
4924 if (ret_val) {
4925 *ret_val = rval;
4926 }
4927
4928 return ret;
4929 }
4930
4931 static RISCVException rmw_hviph(CPURISCVState *env, int csrno,
4932 target_ulong *ret_val,
4933 target_ulong new_val, target_ulong wr_mask)
4934 {
4935 uint64_t rval;
4936 RISCVException ret;
4937
4938 ret = rmw_hvip64(env, csrno, &rval,
4939 ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32);
4940 if (ret_val) {
4941 *ret_val = rval >> 32;
4942 }
4943
4944 return ret;
4945 }
4946
4947 static RISCVException rmw_hip(CPURISCVState *env, int csrno,
4948 target_ulong *ret_value,
4949 target_ulong new_value, target_ulong write_mask)
4950 {
4951 int ret = rmw_mip(env, csrno, ret_value, new_value,
4952 write_mask & hip_writable_mask);
4953
4954 if (ret_value) {
4955 *ret_value &= HS_MODE_INTERRUPTS;
4956 }
4957 return ret;
4958 }
4959
4960 static RISCVException rmw_hie(CPURISCVState *env, int csrno,
4961 target_ulong *ret_val,
4962 target_ulong new_val, target_ulong wr_mask)
4963 {
4964 uint64_t rval;
4965 RISCVException ret;
4966
4967 ret = rmw_mie64(env, csrno, &rval, new_val, wr_mask & HS_MODE_INTERRUPTS);
4968 if (ret_val) {
4969 *ret_val = rval & HS_MODE_INTERRUPTS;
4970 }
4971
4972 return ret;
4973 }
4974
4975 static RISCVException read_hcounteren(CPURISCVState *env, int csrno,
4976 target_ulong *val)
4977 {
4978 *val = env->hcounteren;
4979 return RISCV_EXCP_NONE;
4980 }
4981
4982 static RISCVException write_hcounteren(CPURISCVState *env, int csrno,
4983 target_ulong val, uintptr_t ra)
4984 {
4985 RISCVCPU *cpu = env_archcpu(env);
4986
4987 /* WARL register - disable unavailable counters */
4988 env->hcounteren = val & (cpu->pmu_avail_ctrs | COUNTEREN_CY | COUNTEREN_TM |
4989 COUNTEREN_IR);
4990 return RISCV_EXCP_NONE;
4991 }
4992
4993 static RISCVException read_hgeie(CPURISCVState *env, int csrno,
4994 target_ulong *val)
4995 {
4996 if (val) {
4997 *val = env->hgeie;
4998 }
4999 return RISCV_EXCP_NONE;
5000 }
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