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1 /*
2 * QEMU RISC-V CSRs
3 *
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2017-2018 SiFive, Inc.
6 * SPDX-License-Identifier: GPL-2.0-or-later
7 */
8
9 #ifndef RISCV_CSR_H
10 #define RISCV_CSR_H
11
12 #include "exec/target_long.h"
13 #include "cpu_bits.h"
14
15 RISCVException riscv_csrr(CPURISCVState *env, int csrno,
16 target_ulong *ret_value);
17
18 RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
19 target_ulong *ret_value, target_ulong new_value,
20 target_ulong write_mask, uintptr_t ra);
21 RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno,
22 target_ulong *ret_value,
23 target_ulong new_value,
24 target_ulong write_mask);
25
26 typedef RISCVException (*riscv_csr_predicate_fn)(CPURISCVState *env,
27 int csrno);
28 typedef RISCVException (*riscv_csr_read_fn)(CPURISCVState *env, int csrno,
29 target_ulong *ret_value);
30 typedef RISCVException (*riscv_csr_write_fn)(CPURISCVState *env, int csrno,
31 target_ulong new_value,
32 uintptr_t ra);
33 typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno,
34 target_ulong *ret_value,
35 target_ulong new_value,
36 target_ulong write_mask);
37
38 RISCVException riscv_csrr_i128(CPURISCVState *env, int csrno,
39 Int128 *ret_value);
40 RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno,
41 Int128 *ret_value, Int128 new_value,
42 Int128 write_mask, uintptr_t ra);
43
44 typedef RISCVException (*riscv_csr_read128_fn)(CPURISCVState *env, int csrno,
45 Int128 *ret_value);
46 typedef RISCVException (*riscv_csr_write128_fn)(CPURISCVState *env, int csrno,
47 Int128 new_value);
48
49 typedef struct {
50 const char *name;
51 riscv_csr_predicate_fn predicate;
52 riscv_csr_read_fn read;
53 riscv_csr_write_fn write;
54 riscv_csr_op_fn op;
55 riscv_csr_read128_fn read128;
56 riscv_csr_write128_fn write128;
57 /* The default priv spec version should be PRIV_VERSION_1_10_0 (i.e 0) */
58 uint32_t min_priv_ver;
59 } riscv_csr_operations;
60
61 struct RISCVCSR {
62 int csrno;
63 bool (*insertion_test)(RISCVCPU *cpu);
64 riscv_csr_operations csr_ops;
65 };
66
67 /* CSR function table constants */
68 enum {
69 CSR_TABLE_SIZE = 0x1000
70 };
71
72 /* valid_vm_* arrays are shared with KVM via cpu.c */
73 extern const bool valid_vm_1_10_32[], valid_vm_1_10_64[];
74
75 /* CSR function table */
76 extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE];
77
78 bool riscv_csr_is_fpu(int csrno);
79 bool riscv_csr_is_vpu(int csrno);
80
81 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops);
82 void riscv_set_csr_ops(int csrno, const riscv_csr_operations *ops);
83
84 /* In th_csr.c */
85 extern const RISCVCSR th_csr_list[];
86
87 /* Implemented in mips_csr.c */
88 extern const RISCVCSR mips_csr_list[];
89
90 /* PMP CSRs, defined in pmp.c */
91 void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index,
92 target_ulong val);
93 target_ulong pmpcfg_csr_read(CPURISCVState *env, uint32_t reg_index);
94
95 void mseccfg_csr_write(CPURISCVState *env, uint64_t val);
96 uint64_t mseccfg_csr_read(CPURISCVState *env);
97
98 void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index,
99 target_ulong val);
100 target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index);
101
102 #endif /* RISCV_CSR_H */