| 1 | /* |
| 2 | * QEMU RISC-V Native Debug Support |
| 3 | * |
| 4 | * Copyright (c) 2022 Wind River Systems, Inc. |
| 5 | * |
| 6 | * Author: |
| 7 | * Bin Meng <bin.meng@windriver.com> |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify it |
| 10 | * under the terms and conditions of the GNU General Public License, |
| 11 | * version 2 or later, as published by the Free Software Foundation. |
| 12 | * |
| 13 | * This program is distributed in the hope it will be useful, but WITHOUT |
| 14 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 15 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 16 | * more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License along with |
| 19 | * this program. If not, see <http://www.gnu.org/licenses/>. |
| 20 | */ |
| 21 | |
| 22 | #ifndef RISCV_DEBUG_H |
| 23 | #define RISCV_DEBUG_H |
| 24 | |
| 25 | #include "exec/breakpoint.h" |
| 26 | #include "exec/target_long.h" |
| 27 | |
| 28 | /* register index of tdata CSRs */ |
| 29 | enum { |
| 30 | TDATA1 = 0, |
| 31 | TDATA2, |
| 32 | TDATA3, |
| 33 | TDATA_NUM |
| 34 | }; |
| 35 | |
| 36 | typedef enum { |
| 37 | TRIGGER_TYPE_NO_EXIST = 0, /* trigger does not exist */ |
| 38 | TRIGGER_TYPE_AD_MATCH = 2, /* address/data match trigger */ |
| 39 | TRIGGER_TYPE_INST_CNT = 3, /* instruction count trigger */ |
| 40 | TRIGGER_TYPE_INT = 4, /* interrupt trigger */ |
| 41 | TRIGGER_TYPE_EXCP = 5, /* exception trigger */ |
| 42 | TRIGGER_TYPE_AD_MATCH6 = 6, /* new address/data match trigger */ |
| 43 | TRIGGER_TYPE_EXT_SRC = 7, /* external source trigger */ |
| 44 | TRIGGER_TYPE_UNAVAIL = 15, /* trigger exists, but unavailable */ |
| 45 | TRIGGER_TYPE_NUM |
| 46 | } trigger_type_t; |
| 47 | |
| 48 | /* actions */ |
| 49 | typedef enum { |
| 50 | DBG_ACTION_NONE = -1, /* sentinel value */ |
| 51 | DBG_ACTION_BP = 0, |
| 52 | DBG_ACTION_DBG_MODE, |
| 53 | DBG_ACTION_TRACE0, |
| 54 | DBG_ACTION_TRACE1, |
| 55 | DBG_ACTION_TRACE2, |
| 56 | DBG_ACTION_TRACE3, |
| 57 | DBG_ACTION_EXT_DBG0 = 8, |
| 58 | DBG_ACTION_EXT_DBG1 |
| 59 | } trigger_action_t; |
| 60 | |
| 61 | /* tdata1 field masks */ |
| 62 | |
| 63 | #define RV32_TYPE(t) ((uint32_t)(t) << 28) |
| 64 | #define RV32_TYPE_MASK (0xf << 28) |
| 65 | #define RV32_DMODE BIT(27) |
| 66 | #define RV32_DATA_MASK 0x7ffffff |
| 67 | #define RV64_TYPE(t) ((uint64_t)(t) << 60) |
| 68 | #define RV64_TYPE_MASK (0xfULL << 60) |
| 69 | #define RV64_DMODE BIT_ULL(59) |
| 70 | #define RV64_DATA_MASK 0x7ffffffffffffff |
| 71 | |
| 72 | /* mcontrol field masks */ |
| 73 | |
| 74 | #define TYPE2_LOAD BIT(0) |
| 75 | #define TYPE2_STORE BIT(1) |
| 76 | #define TYPE2_EXEC BIT(2) |
| 77 | #define TYPE2_U BIT(3) |
| 78 | #define TYPE2_S BIT(4) |
| 79 | #define TYPE2_M BIT(6) |
| 80 | #define TYPE2_MATCH (0xf << 7) |
| 81 | #define TYPE2_CHAIN BIT(11) |
| 82 | #define TYPE2_ACTION (0xf << 12) |
| 83 | #define TYPE2_SIZELO (0x3 << 16) |
| 84 | #define TYPE2_TIMING BIT(18) |
| 85 | #define TYPE2_SELECT BIT(19) |
| 86 | #define TYPE2_HIT BIT(20) |
| 87 | #define TYPE2_SIZEHI (0x3 << 21) /* RV64 only */ |
| 88 | |
| 89 | /* mcontrol6 field masks */ |
| 90 | |
| 91 | #define TYPE6_LOAD BIT(0) |
| 92 | #define TYPE6_STORE BIT(1) |
| 93 | #define TYPE6_EXEC BIT(2) |
| 94 | #define TYPE6_U BIT(3) |
| 95 | #define TYPE6_S BIT(4) |
| 96 | #define TYPE6_M BIT(6) |
| 97 | #define TYPE6_MATCH (0xf << 7) |
| 98 | #define TYPE6_CHAIN BIT(11) |
| 99 | #define TYPE6_ACTION (0xf << 12) |
| 100 | #define TYPE6_SIZE (0xf << 16) |
| 101 | #define TYPE6_TIMING BIT(20) |
| 102 | #define TYPE6_SELECT BIT(21) |
| 103 | #define TYPE6_HIT BIT(22) |
| 104 | #define TYPE6_VU BIT(23) |
| 105 | #define TYPE6_VS BIT(24) |
| 106 | |
| 107 | /* access size */ |
| 108 | enum { |
| 109 | SIZE_ANY = 0, |
| 110 | SIZE_1B, |
| 111 | SIZE_2B, |
| 112 | SIZE_4B, |
| 113 | SIZE_6B, |
| 114 | SIZE_8B, |
| 115 | SIZE_10B, |
| 116 | SIZE_12B, |
| 117 | SIZE_14B, |
| 118 | SIZE_16B, |
| 119 | SIZE_NUM = 16 |
| 120 | }; |
| 121 | |
| 122 | /* itrigger filed masks */ |
| 123 | #define ITRIGGER_ACTION 0x3f |
| 124 | #define ITRIGGER_U BIT(6) |
| 125 | #define ITRIGGER_S BIT(7) |
| 126 | #define ITRIGGER_PENDING BIT(8) |
| 127 | #define ITRIGGER_M BIT(9) |
| 128 | #define ITRIGGER_COUNT (0x3fff << 10) |
| 129 | #define ITRIGGER_HIT BIT(24) |
| 130 | #define ITRIGGER_VU BIT(25) |
| 131 | #define ITRIGGER_VS BIT(26) |
| 132 | |
| 133 | #define MHSELECT_IGNORE 0 |
| 134 | #define MHSELECT_MCONTEXT 4 |
| 135 | |
| 136 | bool tdata_available(CPURISCVState *env, int tdata_index); |
| 137 | |
| 138 | target_ulong tselect_csr_read(CPURISCVState *env); |
| 139 | void tselect_csr_write(CPURISCVState *env, target_ulong val); |
| 140 | |
| 141 | target_ulong tdata_csr_read(CPURISCVState *env, int tdata_index); |
| 142 | void tdata_csr_write(CPURISCVState *env, int tdata_index, target_ulong val); |
| 143 | |
| 144 | target_ulong tinfo_csr_read(CPURISCVState *env); |
| 145 | |
| 146 | void riscv_cpu_debug_excp_handler(CPUState *cs); |
| 147 | bool riscv_cpu_debug_check_breakpoint(CPUState *cs); |
| 148 | bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp); |
| 149 | |
| 150 | void riscv_trigger_realize(CPURISCVState *env); |
| 151 | void riscv_trigger_unrealize(CPURISCVState *env); |
| 152 | void riscv_trigger_reset_hold(CPURISCVState *env); |
| 153 | |
| 154 | bool riscv_itrigger_enabled(CPURISCVState *env); |
| 155 | void riscv_itrigger_update_priv(CPURISCVState *env); |
| 156 | #endif /* RISCV_DEBUG_H */ |