@samitouri / QOSamiQemu
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1 /*
2 * RISC-V translation routines for the RV64A Standard Extension.
3 *
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
6 * Bastian Koppelmann, kbastian@mail.uni-paderborn.de
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2 or later, as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program. If not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #define REQUIRE_A_OR_ZAAMO(ctx) do { \
22 if (!ctx->cfg_ptr->ext_zaamo && !has_ext(ctx, RVA)) { \
23 return false; \
24 } \
25 } while (0)
26
27 #define REQUIRE_A_OR_ZALRSC(ctx) do { \
28 if (!ctx->cfg_ptr->ext_zalrsc && !has_ext(ctx, RVA)) { \
29 return false; \
30 } \
31 } while (0)
32
33 static bool gen_lr(DisasContext *ctx, arg_atomic *a, MemOp mop)
34 {
35 TCGv src1;
36
37 mop |= MO_ALIGN;
38 mop |= ctx->mo_endianness;
39
40 decode_save_opc(ctx, 0);
41 src1 = get_address(ctx, a->rs1, 0);
42 if (a->rl) {
43 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
44 }
45 tcg_gen_qemu_ld_tl(load_val, src1, ctx->mem_idx, mop);
46 /*
47 * TSO defines AMOs as acquire+release-RCsc, but does not define LR/SC as
48 * AMOs. Instead treat them like loads.
49 */
50 if (a->aq || ctx->ztso) {
51 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
52 }
53
54 /* Put addr in load_res, data in load_val. */
55 tcg_gen_mov_tl(load_res, src1);
56 gen_set_gpr(ctx, a->rd, load_val);
57
58 return true;
59 }
60
61 static bool gen_sc(DisasContext *ctx, arg_atomic *a, MemOp mop)
62 {
63 TCGv dest, src1, src2;
64 TCGLabel *l1 = gen_new_label();
65 TCGLabel *l2 = gen_new_label();
66
67 mop |= MO_ALIGN;
68 mop |= ctx->mo_endianness;
69
70 decode_save_opc(ctx, 0);
71 src1 = get_address(ctx, a->rs1, 0);
72 tcg_gen_brcond_tl(TCG_COND_NE, load_res, src1, l1);
73
74 /*
75 * Note that the TCG atomic primitives are SC,
76 * so we can ignore AQ/RL along this path.
77 */
78 dest = dest_gpr(ctx, a->rd);
79 src2 = get_gpr(ctx, a->rs2, EXT_NONE);
80 tcg_gen_atomic_cmpxchg_tl(dest, load_res, load_val, src2,
81 ctx->mem_idx, mop);
82 tcg_gen_setcond_tl(TCG_COND_NE, dest, dest, load_val);
83 gen_set_gpr(ctx, a->rd, dest);
84 tcg_gen_br(l2);
85
86 gen_set_label(l1);
87 /*
88 * Address comparison failure. However, we still need to
89 * provide the memory barrier implied by AQ/RL/TSO.
90 */
91 TCGBar bar_strl = (ctx->ztso || a->rl) ? TCG_BAR_STRL : 0;
92 tcg_gen_mb(TCG_MO_ALL + a->aq * TCG_BAR_LDAQ + bar_strl);
93 /*
94 * "For the purposes of memory protection, a failed SC.W may be treated
95 * like a store." so let's check the write access permissions
96 */
97 gen_helper_sc_probe_write(tcg_env, src1,
98 tcg_constant_tl(memop_size(mop)));
99 gen_set_gpr(ctx, a->rd, tcg_constant_tl(1));
100
101 gen_set_label(l2);
102 /*
103 * Clear the load reservation, since an SC must fail if there is
104 * an SC to any address, in between an LR and SC pair.
105 */
106 tcg_gen_movi_tl(load_res, -1);
107
108 return true;
109 }
110
111 static bool trans_lr_w(DisasContext *ctx, arg_lr_w *a)
112 {
113 REQUIRE_A_OR_ZALRSC(ctx);
114 return gen_lr(ctx, a, MO_SL);
115 }
116
117 static bool trans_sc_w(DisasContext *ctx, arg_sc_w *a)
118 {
119 REQUIRE_A_OR_ZALRSC(ctx);
120 return gen_sc(ctx, a, MO_SL);
121 }
122
123 static bool trans_amoswap_w(DisasContext *ctx, arg_amoswap_w *a)
124 {
125 REQUIRE_A_OR_ZAAMO(ctx);
126 return gen_amo(ctx, a, &tcg_gen_atomic_xchg_tl, MO_SL);
127 }
128
129 static bool trans_amoadd_w(DisasContext *ctx, arg_amoadd_w *a)
130 {
131 REQUIRE_A_OR_ZAAMO(ctx);
132 return gen_amo(ctx, a, &tcg_gen_atomic_fetch_add_tl, MO_SL);
133 }
134
135 static bool trans_amoxor_w(DisasContext *ctx, arg_amoxor_w *a)
136 {
137 REQUIRE_A_OR_ZAAMO(ctx);
138 return gen_amo(ctx, a, &tcg_gen_atomic_fetch_xor_tl, MO_SL);
139 }
140
141 static bool trans_amoand_w(DisasContext *ctx, arg_amoand_w *a)
142 {
143 REQUIRE_A_OR_ZAAMO(ctx);
144 return gen_amo(ctx, a, &tcg_gen_atomic_fetch_and_tl, MO_SL);
145 }
146
147 static bool trans_amoor_w(DisasContext *ctx, arg_amoor_w *a)
148 {
149 REQUIRE_A_OR_ZAAMO(ctx);
150 return gen_amo(ctx, a, &tcg_gen_atomic_fetch_or_tl, MO_SL);
151 }
152
153 static bool trans_amomin_w(DisasContext *ctx, arg_amomin_w *a)
154 {
155 REQUIRE_A_OR_ZAAMO(ctx);
156 return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smin_tl, MO_SL);
157 }
158
159 static bool trans_amomax_w(DisasContext *ctx, arg_amomax_w *a)
160 {
161 REQUIRE_A_OR_ZAAMO(ctx);
162 return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smax_tl, MO_SL);
163 }
164
165 static bool trans_amominu_w(DisasContext *ctx, arg_amominu_w *a)
166 {
167 REQUIRE_A_OR_ZAAMO(ctx);
168 return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umin_tl, MO_SL);
169 }
170
171 static bool trans_amomaxu_w(DisasContext *ctx, arg_amomaxu_w *a)
172 {
173 REQUIRE_A_OR_ZAAMO(ctx);
174 return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umax_tl, MO_SL);
175 }
176
177 static bool trans_lr_d(DisasContext *ctx, arg_lr_d *a)
178 {
179 REQUIRE_64BIT(ctx);
180 REQUIRE_A_OR_ZALRSC(ctx);
181 return gen_lr(ctx, a, MO_UQ);
182 }
183
184 static bool trans_sc_d(DisasContext *ctx, arg_sc_d *a)
185 {
186 REQUIRE_64BIT(ctx);
187 REQUIRE_A_OR_ZALRSC(ctx);
188 return gen_sc(ctx, a, MO_UQ);
189 }
190
191 static bool trans_amoswap_d(DisasContext *ctx, arg_amoswap_d *a)
192 {
193 REQUIRE_64BIT(ctx);
194 REQUIRE_A_OR_ZAAMO(ctx);
195 return gen_amo(ctx, a, &tcg_gen_atomic_xchg_tl, MO_UQ);
196 }
197
198 static bool trans_amoadd_d(DisasContext *ctx, arg_amoadd_d *a)
199 {
200 REQUIRE_64BIT(ctx);
201 REQUIRE_A_OR_ZAAMO(ctx);
202 return gen_amo(ctx, a, &tcg_gen_atomic_fetch_add_tl, MO_UQ);
203 }
204
205 static bool trans_amoxor_d(DisasContext *ctx, arg_amoxor_d *a)
206 {
207 REQUIRE_64BIT(ctx);
208 REQUIRE_A_OR_ZAAMO(ctx);
209 return gen_amo(ctx, a, &tcg_gen_atomic_fetch_xor_tl, MO_UQ);
210 }
211
212 static bool trans_amoand_d(DisasContext *ctx, arg_amoand_d *a)
213 {
214 REQUIRE_64BIT(ctx);
215 REQUIRE_A_OR_ZAAMO(ctx);
216 return gen_amo(ctx, a, &tcg_gen_atomic_fetch_and_tl, MO_UQ);
217 }
218
219 static bool trans_amoor_d(DisasContext *ctx, arg_amoor_d *a)
220 {
221 REQUIRE_64BIT(ctx);
222 REQUIRE_A_OR_ZAAMO(ctx);
223 return gen_amo(ctx, a, &tcg_gen_atomic_fetch_or_tl, MO_UQ);
224 }
225
226 static bool trans_amomin_d(DisasContext *ctx, arg_amomin_d *a)
227 {
228 REQUIRE_64BIT(ctx);
229 REQUIRE_A_OR_ZAAMO(ctx);
230 return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smin_tl, MO_UQ);
231 }
232
233 static bool trans_amomax_d(DisasContext *ctx, arg_amomax_d *a)
234 {
235 REQUIRE_64BIT(ctx);
236 REQUIRE_A_OR_ZAAMO(ctx);
237 return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smax_tl, MO_UQ);
238 }
239
240 static bool trans_amominu_d(DisasContext *ctx, arg_amominu_d *a)
241 {
242 REQUIRE_64BIT(ctx);
243 REQUIRE_A_OR_ZAAMO(ctx);
244 return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umin_tl, MO_UQ);
245 }
246
247 static bool trans_amomaxu_d(DisasContext *ctx, arg_amomaxu_d *a)
248 {
249 REQUIRE_64BIT(ctx);
250 REQUIRE_A_OR_ZAAMO(ctx);
251 return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umax_tl, MO_UQ);
252 }